[gcc(refs/users/meissner/heads/work186-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:350977a1094aab16e43144c56a13a2b1d10cf309

commit 350977a1094aab16e43144c56a13a2b1d10cf309
Author: Michael Meissner 
Date:   Thu Nov 14 12:08:51 2024 -0500

Add ChangeLog.vpair and update REVISION.

2024-11-14  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 5 +
 gcc/REVISION| 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..8af0e6edb0ea
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,5 @@
+ Branch work186-vpair, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index fd4265608fe8..b4bf4f245200 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work186 branch
+work186-vpair branch

[gcc(refs/users/meissner/heads/work186-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:043761f295c0b26a027e53267c3c2ee62b94c2fc

commit 043761f295c0b26a027e53267c3c2ee62b94c2fc
Author: Michael Meissner 
Date:   Thu Nov 14 12:09:49 2024 -0500

Add ChangeLog.bugs and update REVISION.

2024-11-14  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..3577ed4dfece
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,5 @@
+ Branch work186-bugs, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index fd4265608fe8..9e8c59c5ea16 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work186 branch
+work186-bugs branch

[gcc] Created branch 'meissner/heads/work186-bugs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work186-bugs' was created in namespace 'refs/users' 
pointing to:

 8ceea75b6208... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work186-vpair' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work186-vpair' was created in namespace 'refs/users' 
pointing to:

 8ceea75b6208... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work186-libs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work186-libs' was created in namespace 'refs/users' 
pointing to:

 8ceea75b6208... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work186-libs)] Add ChangeLog.libs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3779b9490f5761f6f370c65a3ff70b2ec3a9854c

commit 3779b9490f5761f6f370c65a3ff70b2ec3a9854c
Author: Michael Meissner 
Date:   Thu Nov 14 12:10:52 2024 -0500

Add ChangeLog.libs and update REVISION.

2024-11-14  Michael Meissner  

gcc/

* ChangeLog.libs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.libs | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.libs b/gcc/ChangeLog.libs
new file mode 100644
index ..3e6ddfa7fb4a
--- /dev/null
+++ b/gcc/ChangeLog.libs
@@ -0,0 +1,5 @@
+ Branch work186-libs, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index fd4265608fe8..5f0c1d79da92 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work186 branch
+work186-libs branch

[gcc] Created branch 'meissner/heads/work185-dmf' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work185-dmf' was created in namespace 'refs/users' 
pointing to:

 1c686b511ed6... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work186-sha' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work186-sha' was created in namespace 'refs/users' 
pointing to:

 8ceea75b6208... Add ChangeLog.meissner and REVISION.

[gcc r15-5260] aarch64: Add __builtin_aarch64_chkfeat

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:42e8d1a7e8d1b2d38081ef9afbb0e9eb696055e1

commit r15-5260-g42e8d1a7e8d1b2d38081ef9afbb0e9eb696055e1
Author: Szabolcs Nagy 
Date:   Thu Nov 14 16:15:05 2024 +

aarch64: Add __builtin_aarch64_chkfeat

Builtin for chkfeat: the input argument is used to initialize x16 then
execute chkfeat and return the updated x16.

Note: the ACLE __chkfeat(x) will flip the bits to be more intuitive
(xor the input to output), but for the builtin that seems unnecessary
complication.

gcc/ChangeLog:

* config/aarch64/aarch64-builtins.cc (enum aarch64_builtins):
Define AARCH64_BUILTIN_CHKFEAT.
(aarch64_general_init_builtins): Handle chkfeat.
(aarch64_general_expand_builtin): Handle chkfeat.
Co-authored-by: Richard Sandiford 

Diff:
---
 gcc/config/aarch64/aarch64-builtins.cc | 17 +
 1 file changed, 17 insertions(+)

diff --git a/gcc/config/aarch64/aarch64-builtins.cc 
b/gcc/config/aarch64/aarch64-builtins.cc
index 97bde7c15d3b..e693a14f4f3c 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -876,6 +876,8 @@ enum aarch64_builtins
   AARCH64_PLDX,
   AARCH64_PLI,
   AARCH64_PLIX,
+  /* Armv8.9-A / Armv9.4-A builtins.  */
+  AARCH64_BUILTIN_CHKFEAT,
   AARCH64_BUILTIN_MAX
 };
 
@@ -2279,6 +2281,12 @@ aarch64_general_init_builtins (void)
   if (!TARGET_ILP32)
 aarch64_init_pauth_hint_builtins ();
 
+  tree ftype_chkfeat
+= build_function_type_list (uint64_type_node, uint64_type_node, NULL);
+  aarch64_builtin_decls[AARCH64_BUILTIN_CHKFEAT]
+= aarch64_general_add_builtin ("__builtin_aarch64_chkfeat", ftype_chkfeat,
+  AARCH64_BUILTIN_CHKFEAT);
+
   if (in_lto_p)
 handle_arm_acle_h ();
 }
@@ -3498,6 +3506,15 @@ aarch64_general_expand_builtin (unsigned int fcode, tree 
exp, rtx target,
 case AARCH64_PLIX:
   aarch64_expand_prefetch_builtin (exp, fcode);
   return target;
+
+case AARCH64_BUILTIN_CHKFEAT:
+  {
+   rtx x16_reg = gen_rtx_REG (DImode, R16_REGNUM);
+   op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+   emit_move_insn (x16_reg, op0);
+   expand_insn (CODE_FOR_aarch64_chkfeat, 0, 0);
+   return copy_to_reg (x16_reg);
+  }
 }
 
   if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX)

[gcc(refs/users/meissner/heads/work186-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:46f25932b727b0a2f96457edb1cd554dcddbc2ad

commit 46f25932b727b0a2f96457edb1cd554dcddbc2ad
Author: Michael Meissner 
Date:   Thu Nov 14 12:12:40 2024 -0500

Add ChangeLog.test and update REVISION.

2024-11-14  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 5 +
 gcc/REVISION   | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..8d8705b58947
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,5 @@
+ Branch work186-test, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index fd4265608fe8..bc9b462921e8 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work186 branch
+work186-test branch

[gcc] Created branch 'meissner/heads/work186-test' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work186-test' was created in namespace 'refs/users' 
pointing to:

 8ceea75b6208... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work186-sha)] Add ChangeLog.sha and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:55a53162c0f559c29f2e193807b0d6db5f517b39

commit 55a53162c0f559c29f2e193807b0d6db5f517b39
Author: Michael Meissner 
Date:   Thu Nov 14 12:11:43 2024 -0500

Add ChangeLog.sha and update REVISION.

2024-11-14  Michael Meissner  

gcc/

* ChangeLog.sha: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.sha | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha
new file mode 100644
index ..b9e6f67c691f
--- /dev/null
+++ b/gcc/ChangeLog.sha
@@ -0,0 +1,5 @@
+ Branch work186-sha, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index fd4265608fe8..f385fbb7907e 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work186 branch
+work186-sha branch

[gcc r15-5286] libstdc++: Make _GLIBCXX_NODISCARD work for C++11 and C++14

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:e627a941dc463db08f68d94f5ade74665b3070d4

commit r15-5286-ge627a941dc463db08f68d94f5ade74665b3070d4
Author: Jonathan Wakely 
Date:   Mon Feb 26 11:40:46 2024 +

libstdc++: Make _GLIBCXX_NODISCARD work for C++11 and C++14

The _GLIBCXX_NODISCARD macro only expands to [[__nodiscard__]] for C++17
and later, but all supported compilers will allow us to use that for
C++11 and C++14 too. Enable it for those older standards, to give
improved diagnostics for users of those older standards.

libstdc++-v3/ChangeLog:

* include/bits/c++config (_GLIBCXX_NODISCARD): Expand for C++11
and C++14.
* testsuite/22_locale/locale/cons/12438.cc: Adjust dg-warning to
expect nodiscard warnings for C++11 and C++14 as well.
* testsuite/22_locale/locale/operations/2.cc: Likewise.
* testsuite/25_algorithms/equal/debug/1_neg.cc: Likewise.
* testsuite/25_algorithms/equal/debug/2_neg.cc: Likewise.
* testsuite/25_algorithms/equal/debug/3_neg.cc: Likewise.
* testsuite/25_algorithms/find_first_of/concept_check_1.cc:
Likewise.
* testsuite/25_algorithms/is_permutation/2.cc: Likewise.
* testsuite/25_algorithms/lexicographical_compare/71545.cc:
Likewise.
* testsuite/25_algorithms/lower_bound/33613.cc: Likewise.
* testsuite/25_algorithms/lower_bound/debug/irreflexive.cc:
Likewise.
* testsuite/25_algorithms/lower_bound/debug/partitioned_neg.cc:
Likewise.
* 
testsuite/25_algorithms/lower_bound/debug/partitioned_pred_neg.cc: Likewise.
* testsuite/25_algorithms/minmax/3.cc: Likewise.
* testsuite/25_algorithms/search/78346.cc: Likewise.
* testsuite/25_algorithms/search_n/58358.cc: Likewise.
* testsuite/25_algorithms/unique/1.cc: Likewise.
* testsuite/25_algorithms/unique/11480.cc: Likewise.
* testsuite/25_algorithms/upper_bound/33613.cc: Likewise.
* testsuite/25_algorithms/upper_bound/debug/partitioned_neg.cc:
Likewise.
* 
testsuite/25_algorithms/upper_bound/debug/partitioned_pred_neg.cc: Likewise.
* testsuite/27_io/ios_base/types/fmtflags/bitmask_operators.cc:
Likewise.
* testsuite/27_io/ios_base/types/iostate/bitmask_operators.cc:
Likewise.
* testsuite/27_io/ios_base/types/openmode/bitmask_operators.cc:
Likewise.
* testsuite/ext/concept_checks.cc: Likewise.
* testsuite/ext/is_heap/47709.cc: Likewise.
* testsuite/ext/is_sorted/cxx0x.cc: Likewise.

Diff:
---
 libstdc++-v3/include/bits/c++config   | 2 +-
 libstdc++-v3/testsuite/22_locale/locale/cons/12438.cc | 2 +-
 libstdc++-v3/testsuite/22_locale/locale/operations/2.cc   | 2 +-
 libstdc++-v3/testsuite/25_algorithms/equal/debug/1_neg.cc | 2 +-
 libstdc++-v3/testsuite/25_algorithms/equal/debug/2_neg.cc | 2 +-
 libstdc++-v3/testsuite/25_algorithms/equal/debug/3_neg.cc | 2 +-
 .../testsuite/25_algorithms/find_first_of/concept_check_1.cc  | 2 +-
 libstdc++-v3/testsuite/25_algorithms/is_permutation/2.cc  | 2 +-
 .../testsuite/25_algorithms/lexicographical_compare/71545.cc  | 2 +-
 libstdc++-v3/testsuite/25_algorithms/lower_bound/33613.cc | 2 +-
 .../testsuite/25_algorithms/lower_bound/debug/irreflexive.cc  | 2 +-
 .../testsuite/25_algorithms/lower_bound/debug/partitioned_neg.cc  | 2 +-
 .../25_algorithms/lower_bound/debug/partitioned_pred_neg.cc   | 2 +-
 libstdc++-v3/testsuite/25_algorithms/minmax/3.cc  | 2 +-
 libstdc++-v3/testsuite/25_algorithms/search/78346.cc  | 2 +-
 libstdc++-v3/testsuite/25_algorithms/search_n/58358.cc| 2 +-
 libstdc++-v3/testsuite/25_algorithms/unique/1.cc  | 2 +-
 libstdc++-v3/testsuite/25_algorithms/unique/11480.cc  | 2 +-
 libstdc++-v3/testsuite/25_algorithms/upper_bound/33613.cc | 2 +-
 .../testsuite/25_algorithms/upper_bound/debug/partitioned_neg.cc  | 2 +-
 .../25_algorithms/upper_bound/debug/partitioned_pred_neg.cc   | 2 +-
 .../testsuite/27_io/ios_base/types/fmtflags/bitmask_operators.cc  | 8 
 .../testsuite/27_io/ios_base/types/iostate/bitmask_operators.cc   | 8 
 .../testsuite/27_io/ios_base/types/openmode/bitmask_operators.cc  | 8 
 libstdc++-v3/testsuite/ext/concept_checks.cc  | 8 
 libstdc++-v3/testsuite/ext/is_heap/47709.cc   | 3 +--
 libstdc++-v3/testsuite/ext/is_sorted/cxx0x.cc | 3 +--
 27 files changed, 39 insertions(+), 41 deletions(-)

diff --git a/libstdc++-v3/include/bits/c++config 
b/libstdc++-v3/include/bits/c++config
index 1076803a8655..236906d2f79f 100644
--- a/libstdc++-v3/include/bits/

[gcc(refs/users/meissner/heads/work186)] Add ChangeLog.meissner and REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8ceea75b62086870d662cde6b43780eb34c0e10e

commit 8ceea75b62086870d662cde6b43780eb34c0e10e
Author: Michael Meissner 
Date:   Thu Nov 14 12:07:01 2024 -0500

Add ChangeLog.meissner and REVISION.

2024-11-14  Michael Meissner  

gcc/

* REVISION: New file for branch.
* ChangeLog.meissner: New file.

gcc/c-family/

* ChangeLog.meissner: New file.

gcc/c/

* ChangeLog.meissner: New file.

gcc/cp/

* ChangeLog.meissner: New file.

gcc/fortran/

* ChangeLog.meissner: New file.

gcc/testsuite/

* ChangeLog.meissner: New file.

libgcc/

* ChangeLog.meissner: New file.

Diff:
---
 gcc/ChangeLog.meissner   | 5 +
 gcc/REVISION | 1 +
 gcc/c-family/ChangeLog.meissner  | 5 +
 gcc/c/ChangeLog.meissner | 5 +
 gcc/cp/ChangeLog.meissner| 5 +
 gcc/fortran/ChangeLog.meissner   | 5 +
 gcc/testsuite/ChangeLog.meissner | 5 +
 libgcc/ChangeLog.meissner| 5 +
 libstdc++-v3/ChangeLog.meissner  | 5 +
 9 files changed, 41 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
new file mode 100644
index ..81b644bdeb4f
--- /dev/null
+++ b/gcc/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work186, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..fd4265608fe8
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work186 branch
diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner
new file mode 100644
index ..81b644bdeb4f
--- /dev/null
+++ b/gcc/c-family/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work186, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner
new file mode 100644
index ..81b644bdeb4f
--- /dev/null
+++ b/gcc/c/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work186, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner
new file mode 100644
index ..81b644bdeb4f
--- /dev/null
+++ b/gcc/cp/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work186, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner
new file mode 100644
index ..81b644bdeb4f
--- /dev/null
+++ b/gcc/fortran/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work186, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
new file mode 100644
index ..81b644bdeb4f
--- /dev/null
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work186, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
new file mode 100644
index ..81b644bdeb4f
--- /dev/null
+++ b/libgcc/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work186, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner
new file mode 100644
index ..81b644bdeb4f
--- /dev/null
+++ b/libstdc++-v3/ChangeLog.meissner
@@ -0,0 +1,5 @@
+ Branch work186, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch

[gcc] Created branch 'meissner/heads/work186-orig' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work186-orig' was created in namespace 'refs/users' 
pointing to:

 e627a941dc46... libstdc++: Make _GLIBCXX_NODISCARD work for C++11 and C++14

[gcc r15-5262] aarch64: Add __builtin_aarch64_chkfeat and __chkfeat tests

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:8e3ee22346c86d0199d32eb80538b55a0b1469ea

commit r15-5262-g8e3ee22346c86d0199d32eb80538b55a0b1469ea
Author: Szabolcs Nagy 
Date:   Thu Nov 14 16:15:06 2024 +

aarch64: Add __builtin_aarch64_chkfeat and __chkfeat tests

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/acle/chkfeat-1.c: New test.
* gcc.target/aarch64/chkfeat-1.c: New test.
* gcc.target/aarch64/chkfeat-2.c: New test.

Co-authored-by: Yury Khrustalev 
Co-authored-by: Richard Sandiford 

Diff:
---
 gcc/testsuite/gcc.target/aarch64/acle/chkfeat-1.c | 20 ++
 gcc/testsuite/gcc.target/aarch64/chkfeat-1.c  | 75 +++
 gcc/testsuite/gcc.target/aarch64/chkfeat-2.c  | 30 +
 3 files changed, 125 insertions(+)

diff --git a/gcc/testsuite/gcc.target/aarch64/acle/chkfeat-1.c 
b/gcc/testsuite/gcc.target/aarch64/acle/chkfeat-1.c
new file mode 100644
index ..d8393fd3fbd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/chkfeat-1.c
@@ -0,0 +1,20 @@
+/* Test the __chkfeat ACLE intrinsic.  */
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include 
+
+/*
+** test_chkfeat:
+** ...
+** mov x16, 1
+** hint40 // chkfeat x16
+** eor x0, x16, 1
+** ret
+*/
+uint64_t
+test_chkfeat ()
+{
+  return __chkfeat (1);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/chkfeat-1.c 
b/gcc/testsuite/gcc.target/aarch64/chkfeat-1.c
new file mode 100644
index ..2fae81e740fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/chkfeat-1.c
@@ -0,0 +1,75 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbranch-protection=none" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+**foo1:
+** mov x16, 1
+** hint40 // chkfeat x16
+** mov x0, x16
+** ret
+*/
+unsigned long long
+foo1 (void)
+{
+  return __builtin_aarch64_chkfeat (1);
+}
+
+/*
+**foo2:
+** mov x16, 1
+** movkx16, 0x5678, lsl 32
+** movkx16, 0x1234, lsl 48
+** hint40 // chkfeat x16
+** mov x0, x16
+** ret
+*/
+unsigned long long
+foo2 (void)
+{
+  return __builtin_aarch64_chkfeat (0x123456780001);
+}
+
+/*
+**foo3:
+** mov x16, x0
+** hint40 // chkfeat x16
+** mov x0, x16
+** ret
+*/
+unsigned long long
+foo3 (unsigned long long x)
+{
+  return __builtin_aarch64_chkfeat (x);
+}
+
+/*
+**foo4:
+** ldr x16, \[x0\]
+** hint40 // chkfeat x16
+** str x16, \[x0\]
+** ret
+*/
+void
+foo4 (unsigned long long *p)
+{
+  *p = __builtin_aarch64_chkfeat (*p);
+}
+
+/*
+**foo5:
+** mov x16, 1
+** hint40 // chkfeat x16
+** cmp x16, 0
+**(
+** cselw0, w1, w0, eq
+**|
+** cselw0, w0, w1, ne
+**)
+** ret
+*/
+int
+foo5 (int x, int y)
+{
+  return __builtin_aarch64_chkfeat (1) ? x : y;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/chkfeat-2.c 
b/gcc/testsuite/gcc.target/aarch64/chkfeat-2.c
new file mode 100644
index ..f98d7096ffdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/chkfeat-2.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+void bar (void);
+
+/* Extern call may change enabled HW features.  */
+
+/*
+** foo:
+** ...
+** mov x16, 1
+** ...
+** hint40 // chkfeat x16
+** ...
+** bl  bar
+** ...
+** mov x16, 1
+** ...
+** hint40 // chkfeat x16
+** ...
+*/
+unsigned long long
+foo (void)
+{
+  unsigned long long a = __builtin_aarch64_chkfeat (1);
+  bar ();
+  unsigned long long b = __builtin_aarch64_chkfeat (1);
+  return a + b;
+}

[gcc] Created branch 'meissner/heads/work186-dmf' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work186-dmf' was created in namespace 'refs/users' 
pointing to:

 8ceea75b6208... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work186-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cfa79cf5422d2480a18abbff311d421842d96ef1

commit cfa79cf5422d2480a18abbff311d421842d96ef1
Author: Michael Meissner 
Date:   Thu Nov 14 12:07:59 2024 -0500

Add ChangeLog.dmf and update REVISION.

2024-11-14  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 5 +
 gcc/REVISION  | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..8bcb32538b01
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,5 @@
+ Branch work186-dmf, baseline 
+
+2024-11-14   Michael Meissner  
+
+   Clone branch
diff --git a/gcc/REVISION b/gcc/REVISION
index fd4265608fe8..6e3a391b129f 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work186 branch
+work186-dmf branch

[gcc(refs/users/meissner/heads/work186-orig)] Add REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:4635be12b4ee88b75613b56769b60f7a036054a6

commit 4635be12b4ee88b75613b56769b60f7a036054a6
Author: Michael Meissner 
Date:   Thu Nov 14 12:13:48 2024 -0500

Add REVISION.

2024-11-14  Michael Meissner  

gcc/

* REVISION: New file for branch.

Diff:
---
 gcc/REVISION | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..a1341f1937e9
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work186-orig branch

[gcc r15-5287] contrib: Add another ignored commit

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:e5d6e857af903604a526507cffec9c8b8c989d4f

commit r15-5287-ge5d6e857af903604a526507cffec9c8b8c989d4f
Author: Jeff Law 
Date:   Thu Nov 14 10:14:53 2024 -0700

contrib: Add another ignored commit

* gcc-changelog/git_update_version.py (ignored_commits): Add
another ignored commit.

Diff:
---
 contrib/gcc-changelog/git_update_version.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/contrib/gcc-changelog/git_update_version.py 
b/contrib/gcc-changelog/git_update_version.py
index fa2009f6b057..ceed859b4587 100755
--- a/contrib/gcc-changelog/git_update_version.py
+++ b/contrib/gcc-changelog/git_update_version.py
@@ -46,6 +46,7 @@ ignored_commits = {
 '8e6a25b01becf449d54154b7e83de5f4955cba37',
 '72677e1119dc40aa680755d009e079ad49446c46',
 '10d76b7f1e5b63ad6d2b92940c39007913ced037',
+'de3b277247ce98d189f121155b75f490725a42f6',
 '13cf22eb557eb5e3d796822247d8d4957bdb25da'}
 
 FORMAT = '%(asctime)s:%(levelname)s:%(name)s:%(message)s'

[gcc] Created branch 'meissner/heads/work186' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work186' was created in namespace 'refs/users' 
pointing to:

 e627a941dc46... libstdc++: Make _GLIBCXX_NODISCARD work for C++11 and C++14

[gcc r15-5289] libstdc++: Fix get<0> constraint for lvalue ranges::subrange (LWG 3589)

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:4a3a0be34f723df192361e43bb48b9292dfe3a54

commit r15-5289-g4a3a0be34f723df192361e43bb48b9292dfe3a54
Author: Jonathan Wakely 
Date:   Thu Nov 14 17:31:43 2024 +

libstdc++: Fix get<0> constraint for lvalue ranges::subrange (LWG 3589)

Apprived at October 2021 plenary.

libstdc++-v3/ChangeLog:

* include/bits/ranges_util.h (subrange::begin): Fix constraint,
as per LWG 3589.
* testsuite/std/ranges/subrange/lwg3589.cc: New test.

Diff:
---
 libstdc++-v3/include/bits/ranges_util.h|  5 +++-
 .../testsuite/std/ranges/subrange/lwg3589.cc   | 30 ++
 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/bits/ranges_util.h 
b/libstdc++-v3/include/bits/ranges_util.h
index 3f191e6d446a..7be76e07899b 100644
--- a/libstdc++-v3/include/bits/ranges_util.h
+++ b/libstdc++-v3/include/bits/ranges_util.h
@@ -439,8 +439,11 @@ namespace ranges
 __detail::__make_unsigned_like_t>)
   -> subrange, sentinel_t<_Rng>, subrange_kind::sized>;
 
+  // _GLIBCXX_RESOLVE_LIB_DEFECTS
+  // 3589. The const lvalue reference overload of get for subrange does not
+  // constrain I to be copyable when N == 0
   template
-requires (_Num < 2)
+requires ((_Num == 0 && copyable<_It>) || _Num == 1)
 constexpr auto
 get(const subrange<_It, _Sent, _Kind>& __r)
 {
diff --git a/libstdc++-v3/testsuite/std/ranges/subrange/lwg3589.cc 
b/libstdc++-v3/testsuite/std/ranges/subrange/lwg3589.cc
new file mode 100644
index ..1ccc52d81f8a
--- /dev/null
+++ b/libstdc++-v3/testsuite/std/ranges/subrange/lwg3589.cc
@@ -0,0 +1,30 @@
+// { dg-do compile { target c++20 } }
+
+// LWG 3589. The const lvalue reference overload of get for subrange does not
+// constrain I to be copyable when N == 0
+
+#include 
+#include 
+
+void
+test_lwg3589()
+{
+  int a[2]{};
+  __gnu_test::test_range r(a);
+
+  // Use a generic lambda so we have a dependent context.
+  auto test = [](auto& x)
+{
+  // This was wrong before the LWG 3589 change:
+  if constexpr (requires { std::ranges::get<0>(x); })
+   (void) std::ranges::get<0>(x);
+
+  // These always worked unconditionally:
+  (void) std::ranges::get<1>(x);
+  (void) std::ranges::get<0>(std::move(x));
+  (void) std::ranges::get<1>(std::move(x));
+};
+
+  std::ranges::subrange sr(r.begin(), r.end());
+  test(sr);
+}

[gcc(refs/users/meissner/heads/work186)] Change TARGET_POPCNTB to TARGET_POWER5.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:f02415dc2edcdea220c4b7bd8af8a8ad7b0f

commit f02415dc2edcdea220c4b7bd8af8a8ad7b0f
Author: Michael Meissner 
Date:   Thu Nov 14 12:52:59 2024 -0500

Change TARGET_POPCNTB to TARGET_POWER5.

This patch changes TARGET_POPCNTB to TARGET_POWER5 and OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.  The -mpopcntb switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 2.2 
(Power5).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_POPCNTB to TARGET_POWER5.  Change OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_2_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power5 cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_emit_popcount): Update comment.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Change TARGET_POPCNTB to TARGET_POWER5.  Change
OPTION_MASK_POPCNTB to OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount2): Likewise.
(popcntb): Likewise.
(popcntd): Likewise.
(parity2): Likewise.
* gcc/config/rs6000/rs6000.md (-mpopcntb): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 18 +-
 gcc/config/rs6000/rs6000.cc | 10 +-
 gcc/config/rs6000/rs6000.h  |  8 
 gcc/config/rs6000/rs6000.md | 12 ++--
 gcc/config/rs6000/rs6000.opt|  6 --
 7 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 4dc80e598fa4..da3a9c2d8406 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,7 +422,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((flags & OPTION_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..d600f123d6a7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,7 +21,7 @@
 /* ISA masks.  */
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
 #define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
@@ -143,7 +143,7 @@
 | OPTION_MASK_P9_VECTOR\
 | OPTION_MASK_PCREL\
 | OPTION_MASK_PCREL_OPT\
-| OPTION_MASK_POPCNTB  \
+| OPTION_MASK_POWER5   \
 | OPTION_MASK_POPCNTD  \
 | OPTION_MASK_POWERPC64\
 | OPTION_MASK_PPC_GFXOPT   \
@@ -184,11 +184,11 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS

[gcc(refs/users/meissner/heads/work186)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c9284341b3d7f4dfcbfc5619ba0f1b925f1b1bc8

commit c9284341b3d7f4dfcbfc5619ba0f1b925f1b1bc8
Author: Michael Meissner 
Date:   Thu Nov 14 12:55:55 2024 -0500

Revert changes

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 18 +-
 gcc/config/rs6000/rs6000.cc | 10 +-
 gcc/config/rs6000/rs6000.h  |  8 
 gcc/config/rs6000/rs6000.md | 12 ++--
 gcc/config/rs6000/rs6000.opt|  6 ++
 7 files changed, 28 insertions(+), 30 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..9bdbae1ecf94 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POWER5;
+  return TARGET_POPCNTB;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index da3a9c2d8406..4dc80e598fa4 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,7 +422,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POWER5) != 0)
+  if ((flags & OPTION_MASK_POPCNTB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index d600f123d6a7..84fac8bdac1d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,7 +21,7 @@
 /* ISA masks.  */
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
+#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
 #define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
@@ -143,7 +143,7 @@
 | OPTION_MASK_P9_VECTOR\
 | OPTION_MASK_PCREL\
 | OPTION_MASK_PCREL_OPT\
-| OPTION_MASK_POWER5   \
+| OPTION_MASK_POPCNTB  \
 | OPTION_MASK_POPCNTD  \
 | OPTION_MASK_POWERPC64\
 | OPTION_MASK_PPC_GFXOPT   \
@@ -184,11 +184,11 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
-   | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
+   | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
| OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
 RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
-   | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_FPRND
+   | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND
| OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
 RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
@@ -209,7 +209,7 @@ RS6000_CPU ("823", PROCESSOR_MPCCORE, 
OPTION_MASK_SOFT_FLOAT)
 RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
 RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
 RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64
-   | OPTION_MASK_POWER5 | OPTION_MASK_CMPB
+   | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB
| OPTION_MASK_NO_UPDATE)
 RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT)
 RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
@@ -236,16 +236,16 @@ RS6000_CPU ("power3", PROCESSOR_PPC630, 
OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
 RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF)
 RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
-   | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5)
+   | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB)
 RS6000_CPU ("power5+"

[gcc(refs/users/meissner/heads/work186)] Change TARGET_CMPB to TARGET_POWER6.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b20db1b133ae74b8410f87ac2c2eb81f38e45436

commit b20db1b133ae74b8410f87ac2c2eb81f38e45436
Author: Michael Meissner 
Date:   Thu Nov 14 22:26:35 2024 -0500

Change TARGET_CMPB to TARGET_POWER6.

This patch changes TARGET_CMPB to TARGET_POWER6.  The -mcmpb switch is not 
being
changed, just the name of the macros used to determine if the PowerPC 
processor
supports ISA 2.5 (Power6).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_POWER6): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Change TARGET_CMPB to TARGET_POWER6.  Eliminate
redundant TARGET_POWER5 test.
(cmpb3): Change TARGET_CMPB to TARGET_POWER6.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc |  8 
 gcc/config/rs6000/rs6000.h  |  7 ---
 gcc/config/rs6000/rs6000.md | 16 
 4 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f23991af6feb..3e673c54729b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3920,7 +3920,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_DFP)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
+  else if (TARGET_POWER6)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
@@ -4796,7 +4796,7 @@ rs6000_option_override_internal (bool global_init_p)
  DERAT mispredict penalty.  However the LVE and STVE altivec instructions
  need indexed accesses and the type used is the scalar type of the element
  being loaded or stored.  */
-TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
+TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6
  && !TARGET_ALTIVEC);
 
   /* Set the -mrecip options.  */
@@ -22435,7 +22435,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int 
outer_code,
   return false;
 
 case PARITY:
-  *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
+  *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6);
   return false;
 
 case NOT:
@@ -23262,7 +23262,7 @@ rs6000_emit_parity (rtx dst, rtx src)
   tmp = gen_reg_rtx (mode);
 
   /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can.  */
-  if (TARGET_CMPB)
+  if (TARGET_POWER6)
 {
   if (mode == SImode)
{
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8573b8594052..1b10802a87f4 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,12 +449,12 @@ extern int rs6000_vector_align[];
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
 || TARGET_POWER5   /* ISA 2.02 */  \
-|| TARGET_CMPB /* ISA 2.05 */  \
+|| TARGET_POWER6   /* ISA 2.05 */  \
 || TARGET_POPCNTD) /* ISA 2.06 */
 
 #define TARGET_FCTIDZ  TARGET_FCFID
 #define TARGET_STFIWX  TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX  TARGET_CMPB
+#define TARGET_LFIWAX  TARGET_POWER6
 #define TARGET_LFIWZX  TARGET_POPCNTD
 #define TARGET_FCFIDS  TARGET_POPCNTD
 #define TARGET_FCFIDU  TARGET_POPCNTD
@@ -504,6 +504,7 @@ extern int rs6000_vector_align[];
 /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
 #define TARGET

[gcc(refs/users/meissner/heads/work186)] Change TARGET_FPRND to TARGET_POWER5X.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:9c262ae8e2d3ebfdf01ba7f06d072558a89b78fe

commit 9c262ae8e2d3ebfdf01ba7f06d072558a89b78fe
Author: Michael Meissner 
Date:   Thu Nov 14 22:15:18 2024 -0500

Change TARGET_FPRND to TARGET_POWER5X.

This patch changes TARGET_POWER5X to TARGET_POWER5 and OPTION_MASK_POWER5X 
to
OPTION_MASK_POWER5.  The -mfprnd switch is not being changed, just the name 
of
the macros used to determine if the PowerPC processor supports ISA 2.4 
(Power5x).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Change TARGET_FPRND to TARGET_POWER5X.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro.
* gcc/config/rs6000/rs6000.md (fmod3): Change TARGET_FPRND to
TARGET_POWER5X.
(remainder3): Likewise.
(fctiwuz_): Likewise.
(ceil2): Likewise.
(floor2): Likewise.
(round2): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  1 +
 gcc/config/rs6000/rs6000.md | 14 +++---
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 551676681f22..f23991af6feb 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3922,7 +3922,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_CMPB)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
+  else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POWER5)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
@@ -3949,7 +3949,7 @@ rs6000_option_override_internal (bool global_init_p)
   rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
 }
 
-  if (!TARGET_FPRND && TARGET_VSX)
+  if (!TARGET_POWER5X && TARGET_VSX)
 {
   if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
/* TARGET_VSX = 1 implies Power 7 and newer */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 80d954e1178c..8573b8594052 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -503,6 +503,7 @@ extern int rs6000_vector_align[];
 
 /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
 #define TARGET_POWER5  TARGET_POPCNTB
+#define TARGET_POWER5X TARGET_FPRND
 
 /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_.  The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 266bb9abb203..c3f2e8d4a3c9 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -6687,7 +6687,7 @@
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"]
-  "TARGET_HARD_FLOAT && TARGET_FPRND
+  "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
friz %0,%1
@@ -6815,7 +6815,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIZ))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6825,7 +6825,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIP))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6835,7 +6835,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIM))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6846,7 +6846,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
 UNSPEC_FRIN))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "frin %0,%1"
   [(set_att

[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:f79eae4896f752e695fe555c911791da5cb9bec1

commit f79eae4896f752e695fe555c911791da5cb9bec1
Author: Michael Meissner 
Date:   Thu Nov 14 23:47:43 2024 -0500

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 20 +---
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 4c21bfdabe10..b119fcae6a40 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -4,7 +4,7 @@ Add -mcpu=future tuning support.
 
 This patch makes -mtune=future use the same tuning decision as -mtune=power11.
 
-2024-11-14  Michael Meissner  
+2024-11-15  Michael Meissner  
 
 gcc/
 
@@ -18,7 +18,7 @@ Add support for -mcpu=future
 This patch adds the support that can be used in developing GCC support for
 future PowerPC processors.
 
-2024-11-14  Michael Meissner  
+2024-11-15  Michael Meissner  
 
* config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future.
@@ -69,7 +69,7 @@ I updated the 2 tests that used -mvsx to raise the cpu to 
power7.
 
 Can I install this patch on the GCC 15 trunk?
 
-2024-11-14  Michael Meissner  
+2024-11-15  Michael Meissner  
 
 gcc/
 
@@ -79,8 +79,6 @@ gcc/
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.
 
-2024-11-06  Michael Meissner  
-
 gcc/testsuite/
 
* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
@@ -113,7 +111,7 @@ were no regressions.
 
 Can I install this patch on the GCC 15 trunk?
 
-2024-11-14  Michael Meissner  
+2024-11-15  Michael Meissner  
 
 gcc/
 
@@ -220,7 +218,7 @@ This patch changes TARGET_MODULO to TARGET_POWER9.  The 
-mmodulo switch is not
 being changed, just the name of the macros used to determine if the PowerPC
 processor supports ISA 3.0 (Power9).
 
-2024-11-14  Michael Meissner  
+2024-11-15  Michael Meissner  
 
 gcc/
 
@@ -246,7 +244,7 @@ This patch changes TARGET_POPCNTD to TARGET_POWER7.  The 
-mpopcntd switch is not
 being changed, just the name of the macros used to determine if the PowerPC
 processor supports ISA 2.6 (Power7).
 
-2024-11-14  Michael Meissner  
+2024-11-15  Michael Meissner  
 
 gcc/
 
@@ -293,7 +291,7 @@ This patch changes TARGET_CMPB to TARGET_POWER6.  The 
-mcmpb switch is not being
 changed, just the name of the macros used to determine if the PowerPC processor
 supports ISA 2.5 (Power6).
 
-2024-11-14  Michael Meissner  
+2024-11-15  Michael Meissner  
 
 gcc/
 
@@ -324,7 +322,7 @@ This patch changes TARGET_POWER5X to TARGET_POWER5.  The 
-mfprnd switch is not
 being changed, just the name of the macros used to determine if the PowerPC
 processor supports ISA 2.4 (Power5x).
 
-2024-11-14  Michael Meissner  
+2024-11-15  Michael Meissner  
 
 gcc/
 
@@ -348,7 +346,7 @@ This patch changes TARGET_POPCNTB to TARGET_POWER5.  The 
-mpopcntb switch is not
 being changed in this patch, just the name of the macros used to determine if
 the PowerPC processor supports ISA 2.2 (Power5).
 
-2024-11-14  Michael Meissner  
+2024-11-15  Michael Meissner  
 
 gcc/

[gcc r15-5302] rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p4

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:2e22882f3ec88f540c2255ddce4fb69ac69911b7

commit r15-5302-g2e22882f3ec88f540c2255ddce4fb69ac69911b7
Author: Kewen Lin 
Date:   Fri Nov 15 03:46:33 2024 +

rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p4

All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 4, it further checks for comparison opeators
LT/UNGE.  In rs6000_emit_vector_compare, for the handling
of LT, it switches to use code GT, swaps operands and try
again, it's exactly the same as what we have in vector.md:

; lt(a,b)   = gt(b,a)

As to UNGE, in rs6000_emit_vector_compare, it uses reversed
code LT and further operates on the result with one_cmpl,
it's also the same as what's in vector.md:

; unge(a,b) = ~lt(a,b)

This patch should not have any functionality change too.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Emit 
rtx
comparison for operators LT/UNGE of MODE_VECTOR_FLOAT directly.
(rs6000_emit_vector_compare): Move assertion of no 
MODE_VECTOR_FLOAT to
function beginning.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 24 
 1 file changed, 4 insertions(+), 20 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 9cde30853f76..16e7b3521019 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16015,6 +16015,7 @@ static rtx
 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
 {
   machine_mode mode = GET_MODE (op0);
+  gcc_assert (GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT);
 
   switch (code)
 {
@@ -16024,7 +16025,6 @@ rs6000_emit_vector_compare_inner (enum rtx_code code, 
rtx op0, rtx op1)
 case EQ:
 case GT:
 case GTU:
-  gcc_assert (GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT);
   rtx mask = gen_reg_rtx (mode);
   emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
   return mask;
@@ -16049,18 +16049,8 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
  comparison operators in a comparison rtl pattern, we can
  just emit the comparison rtx insn directly here.  Besides,
  we should have a centralized place to handle the possibility
- of raising invalid exception.  For EQ/GT/GE/UNORDERED/
- ORDERED/LTGT/UNEQ, they are handled equivalently as before;
- for NE/UNLE/UNLT, they are handled with reversed code
- and inverting, it's the same as before; for LE/UNGT, they
- are handled with LE ior EQ previously, emitting directly
- here will make use of GE later, it's slightly better;
-
- FIXME: Handle the remaining vector float comparison operators
- here.  */
-  if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT
-  && rcode != LT
-  && rcode != UNGE)
+ of raising invalid exception.  */
+  if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT)
 {
   mask = gen_reg_rtx (dmode);
   emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
@@ -16088,23 +16078,17 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   try_again = true;
   break;
 case NE:
-case UNGE:
   /* Invert condition and try again.
 e.g., A != B becomes ~(A==B).  */
   {
-   enum rtx_code rev_code;
enum insn_code nor_code;
rtx mask2;
 
-   rev_code = reverse_condition_maybe_unordered (rcode);
-   if (rev_code == UNKNOWN)
- return NULL_RTX;
-
nor_code = optab_handler (one_cmpl_optab, dmode);
if (nor_code == CODE_FOR_nothing)
  return NULL_RTX;
 
-   mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
+   mask2 = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
if (!mask2)
  return NULL_RTX;

[gcc r15-5303] rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p1

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:311bcf9d4c3950e75a8ea83f8b1dd1facffd1910

commit r15-5303-g311bcf9d4c3950e75a8ea83f8b1dd1facffd1910
Author: Kewen Lin 
Date:   Fri Nov 15 03:46:33 2024 +

rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p1

The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 1, it's to remove the helper function
rs6000_emit_vector_compare_inner and move the logics into
rs6000_emit_vector_compare.  This patch doesn't introduce any
functionality change.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): 
Remove.
(rs6000_emit_vector_compare): Emit rtx comparison for operators EQ/
GT/GTU directly.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 37 +
 1 file changed, 9 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 16e7b3521019..44477657bc29 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16009,30 +16009,6 @@ output_cbranch (rtx op, const char *label, int 
reversed, rtx_insn *insn)
   return string;
 }
 
-/* Return insn for VSX or Altivec comparisons.  */
-
-static rtx
-rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
-{
-  machine_mode mode = GET_MODE (op0);
-  gcc_assert (GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT);
-
-  switch (code)
-{
-default:
-  break;
-
-case EQ:
-case GT:
-case GTU:
-  rtx mask = gen_reg_rtx (mode);
-  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
-  return mask;
-}
-
-  return NULL_RTX;
-}
-
 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
DMODE is expected destination mode. This is a recursive function.  */
 
@@ -16057,10 +16033,15 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   return mask;
 }
 
-  /* See if the comparison works as is.  */
-  mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
-  if (mask)
-return mask;
+  /* For any of vector integer comparison operators for which we
+ have direct hardware instructions, just emit it directly
+ here.  */
+  if (rcode == EQ || rcode == GT || rcode == GTU)
+{
+  mask = gen_reg_rtx (dmode);
+  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
+  return mask;
+}
 
   bool swap_operands = false;
   bool try_again = false;

[gcc r15-5306] rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p4

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:c8e5c0e01ecfc8b7bb98359242d36614155a6606

commit r15-5306-gc8e5c0e01ecfc8b7bb98359242d36614155a6606
Author: Kewen Lin 
Date:   Fri Nov 15 03:46:33 2024 +

rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p4

The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 4, it's to rework the handlings on GE/GEU/LE/LEU,
also make the function not recursive any more.  This patch
doesn't introduce any functionality change.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refine the
handlings for operators GE/GEU/LE/LEU.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 87 +
 1 file changed, 17 insertions(+), 70 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 1f20782d66b1..bad5e4196537 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16010,7 +16010,7 @@ output_cbranch (rtx op, const char *label, int 
reversed, rtx_insn *insn)
 }
 
 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
-   DMODE is expected destination mode. This is a recursive function.  */
+   DMODE is expected destination mode.  */
 
 static rtx
 rs6000_emit_vector_compare (enum rtx_code rcode,
@@ -16019,7 +16019,7 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
 {
   gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
   gcc_assert (GET_MODE (op0) == GET_MODE (op1));
-  rtx mask;
+  rtx mask = gen_reg_rtx (dmode);
 
   /* In vector.md, we support all kinds of vector float point
  comparison operators in a comparison rtl pattern, we can
@@ -16028,7 +16028,6 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
  of raising invalid exception.  */
   if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT)
 {
-  mask = gen_reg_rtx (dmode);
   emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
   return mask;
 }
@@ -16037,11 +16036,7 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
  have direct hardware instructions, just emit it directly
  here.  */
   if (rcode == EQ || rcode == GT || rcode == GTU)
-{
-  mask = gen_reg_rtx (dmode);
-  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
-  return mask;
-}
+emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
   else if (rcode == LT || rcode == LTU)
 {
   /* lt{,u}(a,b) = gt{,u}(b,a)  */
@@ -16049,76 +16044,28 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   std::swap (op0, op1);
   mask = gen_reg_rtx (dmode);
   emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, dmode, op0, op1)));
-  return mask;
 }
-  else if (rcode == NE)
+  else if (rcode == NE || rcode == LE || rcode == LEU)
 {
-  /* ne(a,b) = ~eq(a,b)  */
+  /* ne(a,b) = ~eq(a,b); le{,u}(a,b) = ~gt{,u}(a,b)  */
+  enum rtx_code code = reverse_condition (rcode);
   mask = gen_reg_rtx (dmode);
-  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (EQ, dmode, op0, op1)));
+  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, dmode, op0, op1)));
+  enum insn_code nor_code = optab_handler (one_cmpl_optab, dmode);
+  gcc_assert (nor_code != CODE_FOR_nothing);
+  emit_insn (GEN_FCN (nor_code) (mask, mask));
+} else {
+  /* ge{,u}(a,b) = ~gt{,u}(b,a)  */
+  gcc_assert (rcode == GE || rcode == GEU);
+  enum rtx_code code = rcode == GE ? GT : GTU;
+  mask = gen_reg_rtx (dmode);
+  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, dmode, op0, op1)));
   enum insn_code nor_code = optab_handler (one_cmpl_optab, dmode);
   gcc_assert (nor_code != CODE_FOR_nothing);
   emit_insn (GEN_FCN (nor_code) (mask, mask));
-  return mask;
-}
-
-  switch (rcode)
-{
-case GE:
-case GEU:
-case LE:
-case LEU:
-  /* Try GT/GTU/LT/LTU OR EQ */
-  {
-   rtx c_rtx, eq_rtx;
-   enum insn_code ior_code;
-   enum rtx_code new_code;
-
-   switch (rcode)
- {
- case  GE:
-   new_code = GT;
-   break;
-
- case GEU:
-   new_code = GTU;
-   break;
-
- case LE:
-   new_code = LT;
-   break;
-
- case LEU:
-   new_code = LTU;
-   break;
-
- default:
-   gcc_unreachable ();
- }
-
-   ior_code = optab_handler (ior_optab, dmode);
-   if (ior_code == CODE_FOR_nothing)
- return NULL_RTX;
-
-   c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
-   if (!c_rtx)
- return NULL_RTX;
-
-   eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
-   if (!eq_rtx)
- return NULL_

[gcc r15-5301] rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p3

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:893ee27356b05e706c79e4551b628fb93645623e

commit r15-5301-g893ee27356b05e706c79e4551b628fb93645623e
Author: Kewen Lin 
Date:   Fri Nov 15 03:46:32 2024 +

rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p3

All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 3, it further checks for comparison opeators
LE/UNGT.  In rs6000_emit_vector_compare, UNGT is handled
with reversed code LE and inverting with one_cmpl_optab,
LE is handled with LT ior EQ, while in vector.md, we have
the support:

; le(a,b)   = ge(b,a)
; ungt(a,b) = ~le(a,b)

The associated test case shows it's an improvement.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Emit rtx
comparison for operators LE/UNGT of MODE_VECTOR_FLOAT directly.

gcc/testsuite/ChangeLog:

* gcc.target/powerpc/vcond-fp.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  9 -
 gcc/testsuite/gcc.target/powerpc/vcond-fp.c | 26 ++
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 793fb95b660b..9cde30853f76 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16052,15 +16052,15 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
  of raising invalid exception.  For EQ/GT/GE/UNORDERED/
  ORDERED/LTGT/UNEQ, they are handled equivalently as before;
  for NE/UNLE/UNLT, they are handled with reversed code
- and inverting, it's the same as before.
+ and inverting, it's the same as before; for LE/UNGT, they
+ are handled with LE ior EQ previously, emitting directly
+ here will make use of GE later, it's slightly better;
 
  FIXME: Handle the remaining vector float comparison operators
  here.  */
   if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT
   && rcode != LT
-  && rcode != LE
-  && rcode != UNGE
-  && rcode != UNGT)
+  && rcode != UNGE)
 {
   mask = gen_reg_rtx (dmode);
   emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
@@ -16089,7 +16089,6 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   break;
 case NE:
 case UNGE:
-case UNGT:
   /* Invert condition and try again.
 e.g., A != B becomes ~(A==B).  */
   {
diff --git a/gcc/testsuite/gcc.target/powerpc/vcond-fp.c 
b/gcc/testsuite/gcc.target/powerpc/vcond-fp.c
new file mode 100644
index ..2a9f056a2aa2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vcond-fp.c
@@ -0,0 +1,26 @@
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model" } */
+/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } 
} } */
+
+/* Test we use xvcmpge[sd]p rather than xvcmpeq[sd]p and xvcmpgt[sd]p
+   for UNGT and LE handlings.  */
+
+#define UNGT(a, b) (!__builtin_islessequal ((a), (b)))
+#define LE(a, b) (((a) <= (b)))
+
+#define TEST_VECT(NAME, TYPE)  
\
+  __attribute__ ((noipa)) void test_##NAME##_##TYPE (TYPE *x, TYPE *y, 
\
+int *res, int n)  \
+  {
\
+for (int i = 0; i < n; i++)
\
+  res[i] = NAME (x[i], y[i]);  
\
+  }
+
+#define TEST(TYPE) 
\
+  TEST_VECT (UNGT, TYPE)   
\
+  TEST_VECT (LE, TYPE)
+
+TEST (float)
+TEST (double)
+
+/* { dg-final { scan-assembler-not {\mxvcmp(gt|eq)[sd]p\M} } } */

[gcc r15-5299] rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p1

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:a2da2fca004fd3002d45ba298f6203c7972f9eb6

commit r15-5299-ga2da2fca004fd3002d45ba298f6203c7972f9eb6
Author: Kewen Lin 
Date:   Fri Nov 15 03:46:32 2024 +

rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p1

All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 1, it only handles the operators which are
already emitted with an rtx comparison previously in function
rs6000_emit_vector_compare_inner, they are EQ/GT/GE/ORDERED/
UNORDERED/UNEQ/LTGT.  There is no functionality change.

With this change, rs6000_emit_vector_compare_inner would
only work for vector integer comparison handling, it would
be cleaned up later in vector integer comparison rework.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Move
MODE_VECTOR_FLOAT handlings out.
(rs6000_emit_vector_compare): Emit rtx comparison for operators 
EQ/GT/
GE/UNORDERED/ORDERED/UNEQ/LTGT of MODE_VECTOR_FLOAT directly, and
adjust one call site of rs6000_emit_vector_compare_inner to
rs6000_emit_vector_compare.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 47 ++---
 1 file changed, 31 insertions(+), 16 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 950fd947fda3..692acbb76535 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16014,7 +16014,6 @@ output_cbranch (rtx op, const char *label, int 
reversed, rtx_insn *insn)
 static rtx
 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
 {
-  rtx mask;
   machine_mode mode = GET_MODE (op0);
 
   switch (code)
@@ -16022,19 +16021,11 @@ rs6000_emit_vector_compare_inner (enum rtx_code code, 
rtx op0, rtx op1)
 default:
   break;
 
-case GE:
-  if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
-   return NULL_RTX;
-  /* FALLTHRU */
-
 case EQ:
 case GT:
 case GTU:
-case ORDERED:
-case UNORDERED:
-case UNEQ:
-case LTGT:
-  mask = gen_reg_rtx (mode);
+  gcc_assert (GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT);
+  rtx mask = gen_reg_rtx (mode);
   emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
   return mask;
 }
@@ -16050,18 +16041,42 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
rtx op0, rtx op1,
machine_mode dmode)
 {
-  rtx mask;
-  bool swap_operands = false;
-  bool try_again = false;
-
   gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
   gcc_assert (GET_MODE (op0) == GET_MODE (op1));
+  rtx mask;
+
+  /* In vector.md, we support all kinds of vector float point
+ comparison operators in a comparison rtl pattern, we can
+ just emit the comparison rtx insn directly here.  Besides,
+ we should have a centralized place to handle the possibility
+ of raising invalid exception.  As the first step, only check
+ operators EQ/GT/GE/UNORDERED/ORDERED/LTGT/UNEQ for now, they
+ are handled equivalently as before.
+
+ FIXME: Handle the remaining vector float comparison operators
+ here.  */
+  if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT
+  && (rcode == EQ
+ || rcode == GT
+ || rcode == GE
+ || rcode == UNORDERED
+ || rcode == ORDERED
+ || rcode == LTGT
+ || rcode == UNEQ))
+{
+  mask = gen_reg_rtx (dmode);
+  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
+  return mask;
+}
 
   /* See if the comparison works as is.  */
   mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
   if (mask)
 return mask;
 
+  bool swap_operands = false;
+  bool try_again = false;
+
   switch (rcode)
 {
 case LT:
@@ -16161,7 +16176,7 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   if (swap_operands)
std::swap (op0, op1);
 
-  mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
+  mask = rs6000_emit_vector_compare (rcode, op0, op1, dmode);
   if (mask)
return mask;
 }

[gcc r15-5300] rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p2

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:5210565ec17728eab289104aedd09d50731da8ec

commit r15-5300-g5210565ec17728eab289104aedd09d50731da8ec
Author: Kewen Lin 
Date:   Fri Nov 15 03:46:32 2024 +

rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p2

All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 2, it further checks for comparison opeators
NE/UNLE/UNLT.  In rs6000_emit_vector_compare, they are
handled with reversed code which is queried from function
reverse_condition_maybe_unordered and inverting with
one_cmpl_optab.  It's the same as what we have in vector.md:

; ne(a,b)   = ~eq(a,b)
; unle(a,b) = ~gt(a,b)
; unlt(a,b) = ~ge(a,b)

The operators on the right side have been supported in part 1.
This patch should not have any functionality change too.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Emit rtx
comparison for operators NE/UNLE/UNLT of MODE_VECTOR_FLOAT directly.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 20 
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 692acbb76535..793fb95b660b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16049,20 +16049,18 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
  comparison operators in a comparison rtl pattern, we can
  just emit the comparison rtx insn directly here.  Besides,
  we should have a centralized place to handle the possibility
- of raising invalid exception.  As the first step, only check
- operators EQ/GT/GE/UNORDERED/ORDERED/LTGT/UNEQ for now, they
- are handled equivalently as before.
+ of raising invalid exception.  For EQ/GT/GE/UNORDERED/
+ ORDERED/LTGT/UNEQ, they are handled equivalently as before;
+ for NE/UNLE/UNLT, they are handled with reversed code
+ and inverting, it's the same as before.
 
  FIXME: Handle the remaining vector float comparison operators
  here.  */
   if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT
-  && (rcode == EQ
- || rcode == GT
- || rcode == GE
- || rcode == UNORDERED
- || rcode == ORDERED
- || rcode == LTGT
- || rcode == UNEQ))
+  && rcode != LT
+  && rcode != LE
+  && rcode != UNGE
+  && rcode != UNGT)
 {
   mask = gen_reg_rtx (dmode);
   emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
@@ -16090,8 +16088,6 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   try_again = true;
   break;
 case NE:
-case UNLE:
-case UNLT:
 case UNGE:
 case UNGT:
   /* Invert condition and try again.

[gcc r15-5307] rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p5

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:96a468842ef8b5d9b971428c7ba4e14fdab5ea94

commit r15-5307-g96a468842ef8b5d9b971428c7ba4e14fdab5ea94
Author: Kewen Lin 
Date:   Fri Nov 15 03:46:33 2024 +

rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p5

The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 5, it's to refactor all the handlings of vector
integer comparison to make it neat.  This patch doesn't
introduce any functionality change.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refactor the
handlings of vector integer comparison.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 68 +
 1 file changed, 44 insertions(+), 24 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index bad5e4196537..0d7ee1e5bdf2 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16032,34 +16032,54 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   return mask;
 }
 
-  /* For any of vector integer comparison operators for which we
- have direct hardware instructions, just emit it directly
- here.  */
-  if (rcode == EQ || rcode == GT || rcode == GTU)
-emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
-  else if (rcode == LT || rcode == LTU)
+  bool swap_operands = false;
+  bool need_invert = false;
+  enum rtx_code code = rcode;
+
+  switch (rcode)
 {
+case EQ:
+case GT:
+case GTU:
+  /* Emit directly with native hardware insn.  */
+  break;
+case LT:
+case LTU:
   /* lt{,u}(a,b) = gt{,u}(b,a)  */
-  enum rtx_code code = swap_condition (rcode);
-  std::swap (op0, op1);
-  mask = gen_reg_rtx (dmode);
-  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, dmode, op0, op1)));
+  code = swap_condition (rcode);
+  swap_operands = true;
+  break;
+case NE:
+case LE:
+case LEU:
+  /* ne(a,b) = ~eq(a,b); le{,u}(a,b) = ~gt{,u}(a,b)  */
+  code = reverse_condition (rcode);
+  need_invert = true;
+  break;
+case GE:
+  /* ge(a,b) = ~gt(b,a)  */
+  code = GT;
+  swap_operands = true;
+  need_invert = true;
+  break;
+case GEU:
+  /* geu(a,b) = ~gtu(b,a)  */
+  code = GTU;
+  swap_operands = true;
+  need_invert = true;
+  break;
+default:
+  gcc_unreachable ();
+  break;
 }
-  else if (rcode == NE || rcode == LE || rcode == LEU)
+
+  if (swap_operands)
+std::swap (op0, op1);
+
+  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, dmode, op0, op1)));
+
+  if (need_invert)
 {
-  /* ne(a,b) = ~eq(a,b); le{,u}(a,b) = ~gt{,u}(a,b)  */
-  enum rtx_code code = reverse_condition (rcode);
-  mask = gen_reg_rtx (dmode);
-  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, dmode, op0, op1)));
-  enum insn_code nor_code = optab_handler (one_cmpl_optab, dmode);
-  gcc_assert (nor_code != CODE_FOR_nothing);
-  emit_insn (GEN_FCN (nor_code) (mask, mask));
-} else {
-  /* ge{,u}(a,b) = ~gt{,u}(b,a)  */
-  gcc_assert (rcode == GE || rcode == GEU);
-  enum rtx_code code = rcode == GE ? GT : GTU;
-  mask = gen_reg_rtx (dmode);
-  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, dmode, op0, op1)));
   enum insn_code nor_code = optab_handler (one_cmpl_optab, dmode);
   gcc_assert (nor_code != CODE_FOR_nothing);
   emit_insn (GEN_FCN (nor_code) (mask, mask));

[gcc r15-5304] rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p2

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:d35ee820b43e80a1298deecc60fdee32d9416eff

commit r15-5304-gd35ee820b43e80a1298deecc60fdee32d9416eff
Author: Kewen Lin 
Date:   Fri Nov 15 03:46:33 2024 +

rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p2

The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 2, it's to refactor the handlings on LT and LTU.
This patch doesn't introduce any functionality change.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refine the
handlings for operators LT and LTU.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 32 +---
 1 file changed, 9 insertions(+), 23 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 44477657bc29..718d65951e7f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16042,22 +16042,18 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
   return mask;
 }
-
-  bool swap_operands = false;
-  bool try_again = false;
+  else if (rcode == LT || rcode == LTU)
+{
+  /* lt{,u}(a,b) = gt{,u}(b,a)  */
+  enum rtx_code code = swap_condition (rcode);
+  std::swap (op0, op1);
+  mask = gen_reg_rtx (dmode);
+  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, dmode, op0, op1)));
+  return mask;
+}
 
   switch (rcode)
 {
-case LT:
-  rcode = GT;
-  swap_operands = true;
-  try_again = true;
-  break;
-case LTU:
-  rcode = GTU;
-  swap_operands = true;
-  try_again = true;
-  break;
 case NE:
   /* Invert condition and try again.
 e.g., A != B becomes ~(A==B).  */
@@ -16131,16 +16127,6 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   return NULL_RTX;
 }
 
-  if (try_again)
-{
-  if (swap_operands)
-   std::swap (op0, op1);
-
-  mask = rs6000_emit_vector_compare (rcode, op0, op1, dmode);
-  if (mask)
-   return mask;
-}
-
   /* You only get two chances.  */
   return NULL_RTX;
 }

[gcc(refs/users/meissner/heads/work186)] Change TARGET_MODULO to TARGET_POWER9.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3cd85c02958b54a1a6a799cf81539e2fab1c70db

commit 3cd85c02958b54a1a6a799cf81539e2fab1c70db
Author: Michael Meissner 
Date:   Thu Nov 14 22:58:32 2024 -0500

Change TARGET_MODULO to TARGET_POWER9.

This patch changes TARGET_MODULO to TARGET_POWER9.  The -mmodulo switch is 
not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 3.0 (Power9).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_MODULO to TARGET_POWER9.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
(TARGET_POWER9): New macro.
* gcc/config/rs6000/rs6000.md (enabled attribute): Change 
TARGET_MODULO
to TARGET_POWER9.
(mod3): Likewise.
(umod3): Likewise.
(divide/modulo peephole2): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  7 ---
 gcc/config/rs6000/rs6000.md | 14 +++---
 4 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index dae43b672ea7..b6093b3cb64c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_MODULO;
+  return TARGET_POWER9;
 case ENB_P9_64:
-  return TARGET_MODULO && TARGET_POWERPC64;
+  return TARGET_POWER9 && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7c43f9ab4356..6b58c060f539 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3886,7 +3886,7 @@ rs6000_option_override_internal (bool global_init_p)
 
   /* For the newer switches (vsx, dfp, etc.) set some of the older options,
  unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
+  if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_P9_MINMAX)
 {
@@ -22416,7 +22416,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int 
outer_code,
*total = rs6000_cost->divsi;
}
   /* Add in shift and subtract for MOD unless we have a mod instruction. */
-  if ((!TARGET_MODULO
+  if ((!TARGET_POWER9
   || (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode)))
 && (code == MOD || code == UMOD))
*total += COSTS_N_INSNS (2);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 94853e11fc8b..3d55e078df0b 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -463,9 +463,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIWUZ TARGET_POWER7
 /* Only powerpc64 and powerpc476 support fctid.  */
 #define TARGET_FCTID   (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD  TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD  TARGET_POWER9
 
 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.  
*/
 #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -506,6 +506,7 @@ extern int rs6000_vector_align[];
 #define TARGET_POWER5X TARGET_FPRND
 #define TARGET_POWER6  TARGET_CMPB
 #define TARGET_POWER7  TARGET_POPCNTD
+#define TARGET_POWER9  TARGET_MODULO
 
 /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_.  The MASK_
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bff898a4eff1..bb83e30311e5 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -403,7 +403,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
  (const_int 1)
 
  (and (eq_attr "isa" "p9v")
@@ -3457,7 +3457,7 @@
   || INTVAL (operands[2]) <= 0
   || (i = exact_log2 (INTVAL (operands[2]))) < 0)
 {
-  if (!TARGET_MODULO)
+  if (!TARGET_POWER9)
FAIL;
 
   operands[2] = force_reg (mode, operands[2]);
@@ -3491,7 +3491,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
 (mod:GPR (match_oper

[gcc(refs/users/meissner/heads/work186)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:913335601c922c2dfbd53931a9d60e413e0a9cc8

commit 913335601c922c2dfbd53931a9d60e413e0a9cc8
Author: Michael Meissner 
Date:   Thu Nov 14 23:35:32 2024 -0500

Do not allow -mvsx to boost processor to power7.

This patch restructures the code so that -mvsx for example will not silently
convert the processor to power7.  The user must now use -mcpu=power7 or 
higher.
This means if the user does -mvsx and the default processor does not have 
VSX
support, it will be an error.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

I updated the 2 tests that used -mvsx to raise the cpu to power7.

Can I install this patch on the GCC 15 trunk?

2024-11-14  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

2024-11-06  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
instructions.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c |  38 +--
 gcc/testsuite/gcc.target/powerpc/pr115688.c |   3 +-
 3 files changed, 110 insertions(+), 60 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 288f476330e8..e026690700d0 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1173,6 +1173,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3695,7 +3696,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3964,59 +3964,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POWER7)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MA

[gcc(refs/users/meissner/heads/work186)] Change TARGET_POPCNTD to TARGET_POWER7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3ff1beca1ade2737f1e09c35edb9509041d58850

commit 3ff1beca1ade2737f1e09c35edb9509041d58850
Author: Michael Meissner 
Date:   Thu Nov 14 22:44:41 2024 -0500

Change TARGET_POPCNTD to TARGET_POWER7.

This patch changes TARGET_POPCNTD to TARGET_POWER7 and OPTION_MASK_POPCNTD 
to
OPTION_MASK_POWER7.  The -mpopcntd switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 2.6 
(Power7).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/dfp.md (cmp_internal1): Change 
TARGET_POPCNTD
to TARGET_POWER7.
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* gcc/config/rs6000/rs6000-string.cc (expand_block_compare): 
Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_popcount): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_POWER7): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(ctz2): Likewise.
(popcntd2): Likewise.
(lrintsi2): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.

Diff:
---
 gcc/config/rs6000/dfp.md|  2 +-
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-string.cc  |  2 +-
 gcc/config/rs6000/rs6000.cc | 14 +++---
 gcc/config/rs6000/rs6000.h  | 21 +++--
 gcc/config/rs6000/rs6000.md | 24 
 6 files changed, 34 insertions(+), 33 deletions(-)

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa9d7dd45dd3..b8189390d410 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POPCNTD"
+  "TARGET_DFP && TARGET_POWER7"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 76421bd1de0b..dae43b672ea7 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P6_64:
   return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
-  return TARGET_POPCNTD;
+  return TARGET_POWER7;
 case ENB_P7_64:
-  return TARGET_POPCNTD && TARGET_POWERPC64;
+  return TARGET_POWER7 && TARGET_POWERPC64;
 case ENB_P8:
   return TARGET_POWER8;
 case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index de618da9b5dc..b633d80110d0 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1949,7 +1949,7 @@ bool
 expand_block_compare (rtx operands[])
 {
   /* TARGET_POPCNTD is already guarded at expand cmpmemsi.  */
-  gcc_assert (TARGET_POPCNTD);
+  gcc_assert (TARGET_POWER7);
 
   /* For P8, this case is complicated to handle because the subtract
  with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3e673c54729b..7c43f9ab4356 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1922,7 +1922,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
  if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
 
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
 
  if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -3916,7 +3916,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_VSX)
 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
+  else if (TARGET_POWER7)
 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_DFP)
 rs60

[gcc(refs/users/meissner/heads/work186)] Change TARGET_POPCNTB to TARGET_POWER5.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c07fafdc90d34fa3c4ae6fae6628e4e63059cb42

commit c07fafdc90d34fa3c4ae6fae6628e4e63059cb42
Author: Michael Meissner 
Date:   Thu Nov 14 22:03:16 2024 -0500

Change TARGET_POPCNTB to TARGET_POWER5.

This patch changes TARGET_POPCNTB to TARGET_POWER5.  The -mpopcntb switch 
is not
being changed in this patch, just the name of the macros used to determine 
if
the PowerPC processor supports ISA 2.2 (Power5).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_POPCNTB to TARGET_POWER5.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_POWER5): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTB to TARGET_POWER5.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount2): Change TARGET_POPCNTB to TARGET_POWER5.  Delete
redundant test for TARGET_POPCNTD.
(popcntb): Change TARGET_POPCNTB to TARGET_POWER5.
(popcntd): Likewise.
(parity2): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000.cc |  8 
 gcc/config/rs6000/rs6000.h  | 11 +++
 gcc/config/rs6000/rs6000.md | 10 +-
 4 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 950fd947fda3..551676681f22 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3924,7 +3924,7 @@ rs6000_option_override_internal (bool global_init_p)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
   else if (TARGET_FPRND)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
+  else if (TARGET_POWER5)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
   else if (TARGET_ALTIVEC)
 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
@@ -23208,8 +23208,8 @@ rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
   return;
 }
 
-/* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
-   (Power7) targets.  DST is the target, and SRC is the argument operand.  */
+/* Emit popcount intrinsic on TARGET_POWER5 and TARGET_POPCNTD (Power7)
+   targets.  DST is the target, and SRC is the argument operand.  */
 
 void
 rs6000_emit_popcount (rtx dst, rtx src)
@@ -23250,7 +23250,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
 }
 
 
-/* Emit parity intrinsic on TARGET_POPCNTB targets.  DST is the
+/* Emit parity intrinsic on TARGET_POWER5 targets.  DST is the
target, and SRC is the argument operand.  */
 
 void
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d460eb065448..80d954e1178c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -448,7 +448,7 @@ extern int rs6000_vector_align[];
Enable 32-bit fcfid's on any of the switches for newer ISA machines.  */
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
-|| TARGET_POPCNTB  /* ISA 2.02 */  \
+|| TARGET_POWER5   /* ISA 2.02 */  \
 || TARGET_CMPB /* ISA 2.05 */  \
 || TARGET_POPCNTD) /* ISA 2.06 */
 
@@ -501,6 +501,9 @@ extern int rs6000_vector_align[];
 #define TARGET_MINMAX  (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
 && (TARGET_P9_MINMAX || !flag_trapping_math))
 
+/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
+#define TARGET_POWER5  TARGET_POPCNTB
+
 /* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_ instead of MASK_.  The MASK_
options that have not yet been replaced by their OPTION_MASK_
@@ -527,7 +530,7 @@ extern int rs6000_vector_align[];
 
 #define TARGET_EXTRA_BUILTINS  (TARGET_POWERPC64\
 || TARGET_PPC_GPOPT /* 970/power4 */\
-|| TARGET_POPCNTB   /* ISA 2.02 */  \
+|| TARGET_POWER5/* ISA 2.02 */  \
   

[gcc(refs/users/meissner/heads/work186)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:165cf8fe46471558c4f5de134875f6e08cbe524a

commit 165cf8fe46471558c4f5de134875f6e08cbe524a
Author: Michael Meissner 
Date:   Thu Nov 14 13:52:21 2024 -0500

Revert changes

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  6 +++---
 gcc/config/rs6000/rs6000-c.cc   |  6 +++---
 gcc/config/rs6000/rs6000-cpus.def   | 36 -
 gcc/config/rs6000/rs6000.cc | 32 ++---
 gcc/config/rs6000/rs6000.h  | 14 ++---
 gcc/config/rs6000/rs6000.md | 40 ++---
 gcc/config/rs6000/rs6000.opt| 18 ++---
 7 files changed, 73 insertions(+), 79 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 76421bd1de0b..9bdbae1ecf94 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,11 +155,11 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POWER5;
+  return TARGET_POPCNTB;
 case ENB_P6:
-  return TARGET_POWER6;
+  return TARGET_CMPB;
 case ENB_P6_64:
-  return TARGET_POWER6 && TARGET_POWERPC64;
+  return TARGET_CMPB && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index b721c9925e19..4dc80e598fa4 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,11 +422,11 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POWER5) != 0)
+  if ((flags & OPTION_MASK_POPCNTB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_POWER5X) != 0)
+  if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_POWER6) != 0)
+  if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 77cc199073e3..84fac8bdac1d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,14 +21,14 @@
 /* ISA masks.  */
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
-#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_POWER5X)
+#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
  as optional.  Group masks by server and embedded. */
 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS  \
-| OPTION_MASK_POWER6   \
+| OPTION_MASK_CMPB \
 | OPTION_MASK_RECIP_PRECISION  \
 | OPTION_MASK_PPC_GFXOPT   \
 | OPTION_MASK_PPC_GPOPT)
@@ -117,14 +117,14 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
-| OPTION_MASK_POWER6   \
+| OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
 | OPTION_MASK_DLMZB\
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
 | OPTION_MASK_FLOAT128_KEYWORD \
-| OPTION_MASK_POWER5X  \
+| OPTION_MASK_FPRND\
 | OPTION_MASK_POWER10  \
 | OPTION_MASK_POWER11  \
 | OPTION_MASK_P10_FUSION   \
@@ -143,7 +143,7 @@
 | OPTION_MASK_P9_VECTOR\
 | OPTION_MASK_PCREL\
 | OPTION_MASK_PCREL_OPT\
-

[gcc(refs/users/meissner/heads/work186)] Change TARGET_CMPB to TARGET_POWER6.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0f2e33206170e385a4c1e50f1754929c54d4b622

commit 0f2e33206170e385a4c1e50f1754929c54d4b622
Author: Michael Meissner 
Date:   Thu Nov 14 13:51:19 2024 -0500

Change TARGET_CMPB to TARGET_POWER6.

This patch changes TARGET_CMPB to TARGET_POWER6 and OPTION_MASK_CMPB to
OPTION_MASK_POWER6.  The -mcmpb switch is not being changed, just the name 
of
the macros used to determine if the PowerPC processor supports ISA 2.5 
(Power6).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.  Change OPTION_MASK_CMPB to
OPTION_MASK_POWER6.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): 
Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power6 cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_clone_map): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Change TARGET_CMPB to TARGET_POWER6.  Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6.  Eliminate redundant
TARGET_POWER5 test.
(cmpb3): Change TARGET_CMPB to TARGET_POWER6.  Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.
* gcc/config/rs6000/rs6000.opt (-mcmpb): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 14 +++---
 gcc/config/rs6000/rs6000.cc | 12 ++--
 gcc/config/rs6000/rs6000.h  |  6 +++---
 gcc/config/rs6000/rs6000.md | 16 
 gcc/config/rs6000/rs6000.opt|  6 --
 7 files changed, 31 insertions(+), 29 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index c9ef36b77639..b721c9925e19 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -426,7 +426,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((flags & OPTION_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index b347053576db..77cc199073e3 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -28,7 +28,7 @@
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
  as optional.  Group masks by server and embedded. */
 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS  \
-| OPTION_MASK_CMPB \
+| OPTION_MASK_POWER6   \
 | OPTION_MASK_RECIP_PRECISION  \
 | OPTION_MASK_PPC_GFXOPT   \
 | OPTION_MASK_PPC_GPOPT)
@@ -117,7 +117,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
-| OPTION_MASK_CMPB \
+| OPTION_MASK_POWER6   \
 | OPTION_MASK_CRYPTO   \
 

[gcc(refs/users/meissner/heads/work186)] Change TARGET_FPRND to TARGET_POWER5X.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b427253c9361e20158cd4863aa8c53d388657a61

commit b427253c9361e20158cd4863aa8c53d388657a61
Author: Michael Meissner 
Date:   Thu Nov 14 13:19:50 2024 -0500

Change TARGET_FPRND to TARGET_POWER5X.

This patch changes TARGET_POWER5X to TARGET_POWER5 and OPTION_MASK_POWER5X 
to
OPTION_MASK_POWER5.  The -mfprnd switch is not being changed, just the name 
of
the macros used to determine if the PowerPC processor supports ISA 2.4 
(Power5x).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Change
TARGET_FPRND to TARGET_POWER5X.  Change OPTION_MASK_FPRND to
OPTION_MASK_POWER5X.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_4_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(464fp cpu definition): Likewise
(476fp cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.md (fmod3): Likewise.
(remainder3): Likewise.
(fctiwuz_): Likewise.
("ceil2): Likewise.
(floor2): Likewise.
(round2): Likewise.
* gcc/config/rs6000/rs6000.opt (-mfprnd): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc |  2 +-
 gcc/config/rs6000/rs6000-cpus.def | 14 +++---
 gcc/config/rs6000/rs6000.cc   | 10 +-
 gcc/config/rs6000/rs6000.md   | 14 +++---
 gcc/config/rs6000/rs6000.opt  |  6 --
 5 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index da3a9c2d8406..c9ef36b77639 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -424,7 +424,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
   if ((flags & OPTION_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((flags & OPTION_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
   if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index d600f123d6a7..b347053576db 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -22,7 +22,7 @@
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
 #define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
-#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
+#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_POWER5X)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
@@ -124,7 +124,7 @@
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
 | OPTION_MASK_FLOAT128_KEYWORD \
-| OPTION_MASK_FPRND\
+| OPTION_MASK_POWER5X  \
 | OPTION_MASK_POWER10  \
 | OPTION_MASK_POWER11  \
 | OPTION_MASK_P10_FUSION   \
@@ -185,10 +185,10 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
 RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
-   | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
+   | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
 RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
-   | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_FPRND
+   | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_POWER5X
| OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
 RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
@@ -239,14 +239,14 @@ RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | 
OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5)
 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
-   | 

[gcc(refs/users/meissner/heads/work186)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b2a6bbdb031696e2eac733a22ddaa89a2063deb7

commit b2a6bbdb031696e2eac733a22ddaa89a2063deb7
Author: Michael Meissner 
Date:   Thu Nov 14 21:25:41 2024 -0500

Revert changes

Diff:
---
 gcc/config/rs6000/default64.h |  11 ---
 gcc/config/rs6000/rs6000.cc   | 215 +++---
 gcc/config/rs6000/rs6000.h|  24 -
 gcc/config/rs6000/rs6000.opt  |   8 --
 4 files changed, 36 insertions(+), 222 deletions(-)

diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
index afa6542e040c..10e3dec78aca 100644
--- a/gcc/config/rs6000/default64.h
+++ b/gcc/config/rs6000/default64.h
@@ -21,7 +21,6 @@ along with GCC; see the file COPYING3.  If not see
 #define RS6000_CPU(NAME, CPU, FLAGS)
 #include "rs6000-cpus.def"
 #undef RS6000_CPU
-#undef TARGET_CPU_DEFAULT
 
 #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
 #undef TARGET_DEFAULT
@@ -29,20 +28,10 @@ along with GCC; see the file COPYING3.  If not see
| MASK_LITTLE_ENDIAN)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower8"
-#define TARGET_CPU_DEFAULT "power8"
-
 #else
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower4"
-
-#if (TARGET_DEFAULT & MASK_POWERPC64)
-#define TARGET_CPU_DEFAULT "powerpc64"
-
-#else
-#define TARGET_CPU_DEFAULT "powerpc"
-#endif
-
 #endif
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b658c1f2bcc4..2c101b589d9a 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -252,17 +252,17 @@ enum {
 
 /* Map compiler ISA bits into HWCAP names.  */
 struct clone_map {
-  HOST_WIDE_INT arch_mask; /* rs6000_arch mask */
+  HOST_WIDE_INT isa_mask;  /* rs6000_isa mask */
   const char *name;/* name to use in __builtin_cpu_supports.  */
 };
 
 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
-  { 0, "" },   /* Default options.  */
-  { ARCH_MASK_POWER6,  "arch_2_05" },  /* ISA 2.5 (power6).  */
-  { ARCH_MASK_POWER7,  "arch_2_06" },  /* ISA 2.6 (power7).  */
-  { ARCH_MASK_POWER8,  "arch_2_07" },  /* ISA 2.7 (power8).  */
-  { ARCH_MASK_POWER9,  "arch_3_00" },  /* ISA 3.0 (power9).  */
-  { ARCH_MASK_POWER10, "arch_3_1" },   /* ISA 3.1 (power10).  */
+  { 0, "" },   /* Default options.  */
+  { OPTION_MASK_POWER6,"arch_2_05" },  /* ISA 2.05 (power6).  
*/
+  { OPTION_MASK_POWER7,"arch_2_06" },  /* ISA 2.06 (power7).  
*/
+  { OPTION_MASK_P8_VECTOR, "arch_2_07" },  /* ISA 2.07 (power8).  */
+  { OPTION_MASK_P9_VECTOR, "arch_3_00" },  /* ISA 3.0 (power9).  */
+  { OPTION_MASK_POWER10,   "arch_3_1" },   /* ISA 3.1 (power10).  */
 };
 
 
@@ -1171,7 +1171,7 @@ enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, 
enum reg_class)
 const int INSN_NOT_AVAILABLE = -1;
 
 static void rs6000_print_isa_options (FILE *, int, const char *,
- HOST_WIDE_INT, HOST_WIDE_INT);
+ HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
@@ -1818,82 +1818,6 @@ rs6000_cpu_name_lookup (const char *name)
   return -1;
 }
 
-
-/* Map the processor into the arch bits that are set off of -mcpu= instead
-   of having an internal -m option.  */
-
-static HOST_WIDE_INT
-get_arch_flags (int cpu_index)
-{
-  HOST_WIDE_INT ret = 0;
-
-  const HOST_WIDE_INT ARCH_COMBO_POWER4  = ARCH_MASK_POWER4;
-  const HOST_WIDE_INT ARCH_COMBO_POWER5  = ARCH_MASK_POWER5  | 
ARCH_COMBO_POWER4;
-  const HOST_WIDE_INT ARCH_COMBO_POWER5X = ARCH_MASK_POWER5X | 
ARCH_COMBO_POWER5;
-  const HOST_WIDE_INT ARCH_COMBO_POWER6  = ARCH_MASK_POWER6  | 
ARCH_COMBO_POWER5X;
-  const HOST_WIDE_INT ARCH_COMBO_POWER7  = ARCH_MASK_POWER7  | 
ARCH_COMBO_POWER6;
-  const HOST_WIDE_INT ARCH_COMBO_POWER8  = ARCH_MASK_POWER8  | 
ARCH_COMBO_POWER7;
-  const HOST_WIDE_INT ARCH_COMBO_POWER9  = ARCH_MASK_POWER9  | 
ARCH_COMBO_POWER8;
-  const HOST_WIDE_INT ARCH_COMBO_POWER10 = ARCH_MASK_POWER10 | 
ARCH_COMBO_POWER9;
-  const HOST_WIDE_INT ARCH_COMBO_POWER11 = ARCH_MASK_POWER11 | 
ARCH_COMBO_POWER10;
-
-  if (cpu_index >= 0)
-switch (processor_target_table[cpu_index].processor)
-  {
-  case PROCESSOR_POWER11:
-   ret = ARCH_COMBO_POWER11;
-   break;
-
-  case PROCESSOR_POWER10:
-   ret = ARCH_COMBO_POWER10;
-   break;
-
-  case PROCESSOR_POWER9:
-   ret = ARCH_COMBO_POWER9;
-   break;
-
-  case PROCESSOR_POWER8:
-   ret = ARCH_COMBO_POWER8;
-   break;
-
-  case PROCESSOR_POWER7:
-   ret = ARCH_COMBO_POWER7;
-   break;
-
-  case PROCESSOR_PPCA2:
-  case PROCESSOR_POWER6:
-   ret = ARCH_COMBO_POWER6;
-   break;
-
-  case

[gcc(refs/users/meissner/heads/work186)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:328df38218badb434c8638c611d913438fc27881

commit 328df38218badb434c8638c611d913438fc27881
Author: Michael Meissner 
Date:   Thu Nov 14 21:24:41 2024 -0500

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

This patch also changes the target_clones support to use an architecture 
mask
instead of isa bits.

This patch also switches the handling of .machine to use architecture masks 
if
they exist (power4 through power11).  All of the other PowerPCs will 
continue to
use the existing code for setting the .machine option.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-11-14  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an architecture flags argument, 
change
all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Switch to using architecture masks 
instead
of ISA masks.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_clone_priority): Switch to using architecture masks instead 
of
ISA masks.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the 
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/default64.h |  11 +++
 gcc/config/rs6000/rs6000.cc   | 215 +++---
 gcc/config/rs6000/rs6000.h|  24 +
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 222 insertions(+), 36 deletions(-)

diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
index 10e3dec78aca..afa6542e040c 100644
--- a/gcc/config/rs6000/default64.h
+++ b/gcc/config/rs6000/default64.h
@@ -21,6 +21,7 @@ along with GCC; see the file COPYING3.  If not see
 #define RS6000_CPU(NAME, CPU, FLAGS)
 #include "rs6000-cpus.def"
 #undef RS6000_CPU
+#undef TARGET_CPU_DEFAULT
 
 #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
 #undef TARGET_DEFAULT
@@ -28,10 +29,20 @@ along with GCC; see the file COPYING3.  If not see
| MASK_LITTLE_ENDIAN)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower8"
+#define TARGET_CPU_DEFAULT "power8"
+
 #else
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower4"
+
+#if (TARGET_DEFAULT & MASK_POWERPC64)
+#define TARGET_CPU_DEFAULT "powerpc64"
+
+#else
+#define TARGET_CPU_DEFAULT "powerpc"
+#endif
+
 #endif
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 2c101b589d9a..b658c1f2bcc4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -252,17 +252,17 @@ enum {
 
 /* Map compiler ISA bits into HWCAP names.  */
 struct clone_map {
-  HOST_WIDE_INT isa_mask;  /* rs6000_isa mask */
+  HOST_WIDE_INT arch_mask; /* rs6000_arch mask */
   const char *name;/* name to use in __builtin_cpu_supports.  */
 };
 
 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
-  { 0,

[gcc r15-5261] aarch64: Add ACLE __chkfeat intrinsic

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:68d8a00bdad3204f3909f5a6c01903f8f1bfdef5

commit r15-5261-g68d8a00bdad3204f3909f5a6c01903f8f1bfdef5
Author: Yury Khrustalev 
Date:   Thu Nov 14 16:15:05 2024 +

aarch64: Add ACLE __chkfeat intrinsic

Note that compared to __builtin_aarch64_chkfeat (x) the ACLE __chkfeat(x)
flips the bits to be more intuitive (xor the input to output).

gcc/ChangeLog:
* config/aarch64/arm_acle.h (__chkfeat): New.

Diff:
---
 gcc/config/aarch64/arm_acle.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index ab4e7e60e046..ca9aabf8ebb9 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -190,8 +190,21 @@ __rint64x (double __a)
 
 #pragma GCC pop_options
 
+
 #pragma GCC push_options
+#pragma GCC target ("+nothing")
+
+__extension__ extern __inline uint64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__chkfeat (uint64_t __feat)
+{
+  return __builtin_aarch64_chkfeat (__feat) ^ __feat;
+}
 
+#pragma GCC pop_options
+
+
+#pragma GCC push_options
 #pragma GCC target ("+nothing+crc")
 
 __extension__ extern __inline uint32_t

[gcc r15-5268] aarch64: Add non-local goto and jump tests for GCS

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:89c7ebdee1177ee8131bb50dc2c8fc6217c66d9e

commit r15-5268-g89c7ebdee1177ee8131bb50dc2c8fc6217c66d9e
Author: Szabolcs Nagy 
Date:   Thu Nov 14 16:15:09 2024 +

aarch64: Add non-local goto and jump tests for GCS

These are scan asm tests only, relying on existing execution tests
for runtime coverage.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/gcs-nonlocal-1.c: New test.
* gcc.target/aarch64/gcs-nonlocal-1-track-speculation.c: New test.
* gcc.target/aarch64/gcs-nonlocal-2.c: New test.
* gcc.target/aarch64/gcs-nonlocal-2-track-speculation.c: New test.
* gcc.target/aarch64/gcs-nonlocal-1.h: New header file.
* gcc.target/aarch64/gcs-nonlocal-2.h: New header file.

Diff:
---
 .../aarch64/gcs-nonlocal-1-track-speculation.c   |  7 +++
 gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1.c|  7 +++
 gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1.h| 20 
 .../aarch64/gcs-nonlocal-2-track-speculation.c   |  7 +++
 gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2.c|  7 +++
 gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2.h| 16 
 6 files changed, 64 insertions(+)

diff --git 
a/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1-track-speculation.c 
b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1-track-speculation.c
new file mode 100644
index ..4ee05ca55035
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1-track-speculation.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbranch-protection=gcs -mtrack-speculation" } */
+/* { dg-final { scan-assembler-times "hint\\t40 // chkfeat x16" 2 } } */
+/* { dg-final { scan-assembler-times "mrs\\tx\[0-9\]+, s3_3_c2_c5_1 // 
gcspr_el0" 2 } } */
+/* { dg-final { scan-assembler-times "sysl\\txzr, #3, c7, c7, #1 // gcspopm" 1 
} } */
+
+#include "gcs-nonlocal-1.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1.c 
b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1.c
new file mode 100644
index ..57d865577add
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbranch-protection=gcs" } */
+/* { dg-final { scan-assembler-times "hint\\t40 // chkfeat x16" 2 } } */
+/* { dg-final { scan-assembler-times "mrs\\tx\[0-9\]+, s3_3_c2_c5_1 // 
gcspr_el0" 2 } } */
+/* { dg-final { scan-assembler-times "sysl\\txzr, #3, c7, c7, #1 // gcspopm" 1 
} } */
+
+#include "gcs-nonlocal-1.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1.h 
b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1.h
new file mode 100644
index ..6a3e47d2db0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-1.h
@@ -0,0 +1,20 @@
+
+int bar1 (int);
+int bar2 (int);
+
+void foo (int cmd)
+{
+  __label__ start;
+  int x = 0;
+
+  void nonlocal_goto (void)
+  {
+x++;
+goto start;
+  }
+
+start:
+  while (bar1 (x))
+if (bar2 (x))
+  nonlocal_goto ();
+}
diff --git 
a/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2-track-speculation.c 
b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2-track-speculation.c
new file mode 100644
index ..fdf9e6121428
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2-track-speculation.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbranch-protection=gcs -mtrack-speculation" } */
+/* { dg-final { scan-assembler-times "hint\\t40 // chkfeat x16" 2 } } */
+/* { dg-final { scan-assembler-times "mrs\\tx\[0-9\]+, s3_3_c2_c5_1 // 
gcspr_el0" 2 } } */
+/* { dg-final { scan-assembler-times "sysl\\txzr, #3, c7, c7, #1 // gcspopm" 1 
} } */
+
+#include "gcs-nonlocal-2.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2.c 
b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2.c
new file mode 100644
index ..2414332906ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbranch-protection=gcs" } */
+/* { dg-final { scan-assembler-times "hint\\t40 // chkfeat x16" 2 } } */
+/* { dg-final { scan-assembler-times "mrs\\tx\[0-9\]+, s3_3_c2_c5_1 // 
gcspr_el0" 2 } } */
+/* { dg-final { scan-assembler-times "sysl\\txzr, #3, c7, c7, #1 // gcspopm" 1 
} } */
+
+#include "gcs-nonlocal-2.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2.h 
b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2.h
new file mode 100644
index ..dd6e307b4bda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/gcs-nonlocal-2.h
@@ -0,0 +1,16 @@
+
+void longj (void *buf)
+{
+  __builtin_longjmp (buf, 1);
+}
+
+void foo (void);
+void bar (void);
+
+void setj (void *buf)
+{
+  if (__builtin_setjmp (buf))
+foo ();
+  else
+bar ();
+}

[gcc(refs/users/meissner/heads/work186)] Change TARGET_CMPB to TARGET_POWER6.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ea3294aa02e54f46a37083805e9f83b4e55ab7b6

commit ea3294aa02e54f46a37083805e9f83b4e55ab7b6
Author: Michael Meissner 
Date:   Thu Nov 14 18:10:51 2024 -0500

Change TARGET_CMPB to TARGET_POWER6.

This patch changes TARGET_CMPB to TARGET_POWER6 and OPTION_MASK_CMPB to
OPTION_MASK_POWER6.  The -mcmpb switch is not being changed, just the name 
of
the macros used to determine if the PowerPC processor supports ISA 2.5 
(Power6).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.  Change OPTION_MASK_CMPB to
OPTION_MASK_POWER6.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): 
Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power6 cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_clone_map): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Change TARGET_CMPB to TARGET_POWER6.  Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6.  Eliminate redundant
TARGET_POWER5 test.
(cmpb3): Change TARGET_CMPB to TARGET_POWER6.  Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.
* gcc/config/rs6000/rs6000.opt (-mcmpb): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 14 +++---
 gcc/config/rs6000/rs6000.cc | 12 ++--
 gcc/config/rs6000/rs6000.h  |  6 +++---
 gcc/config/rs6000/rs6000.md | 16 
 gcc/config/rs6000/rs6000.opt|  8 +---
 7 files changed, 32 insertions(+), 30 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index c9ef36b77639..b721c9925e19 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -426,7 +426,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((flags & OPTION_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index b347053576db..77cc199073e3 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -28,7 +28,7 @@
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
  as optional.  Group masks by server and embedded. */
 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS  \
-| OPTION_MASK_CMPB \
+| OPTION_MASK_POWER6   \
 | OPTION_MASK_RECIP_PRECISION  \
 | OPTION_MASK_PPC_GFXOPT   \
 | OPTION_MASK_PPC_GPOPT)
@@ -117,7 +117,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
-| OPTION_MASK_CMPB \
+| OPTION_MASK_POWER6   \
 | OPTION_MASK_CRYPTO   \
   

[gcc(refs/users/meissner/heads/work186)] Change TARGET_FPRND to TARGET_POWER5X.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:91f163d8135da00d6edac03ea81d5c29a78582aa

commit 91f163d8135da00d6edac03ea81d5c29a78582aa
Author: Michael Meissner 
Date:   Thu Nov 14 18:06:55 2024 -0500

Change TARGET_FPRND to TARGET_POWER5X.

This patch changes TARGET_POWER5X to TARGET_POWER5 and OPTION_MASK_POWER5X 
to
OPTION_MASK_POWER5.  The -mfprnd switch is not being changed, just the name 
of
the macros used to determine if the PowerPC processor supports ISA 2.4 
(Power5x).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Change
TARGET_FPRND to TARGET_POWER5X.  Change OPTION_MASK_FPRND to
OPTION_MASK_POWER5X.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_4_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(464fp cpu definition): Likewise
(476fp cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.md (fmod3): Likewise.
(remainder3): Likewise.
(fctiwuz_): Likewise.
("ceil2): Likewise.
(floor2): Likewise.
(round2): Likewise.
* gcc/config/rs6000/rs6000.opt (-mfprnd): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc |  2 +-
 gcc/config/rs6000/rs6000-cpus.def | 14 +++---
 gcc/config/rs6000/rs6000.cc   | 10 +-
 gcc/config/rs6000/rs6000.md   | 14 +++---
 gcc/config/rs6000/rs6000.opt  |  6 --
 5 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index da3a9c2d8406..c9ef36b77639 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -424,7 +424,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
   if ((flags & OPTION_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((flags & OPTION_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
   if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index d600f123d6a7..b347053576db 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -22,7 +22,7 @@
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
 #define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
-#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
+#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_POWER5X)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
@@ -124,7 +124,7 @@
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
 | OPTION_MASK_FLOAT128_KEYWORD \
-| OPTION_MASK_FPRND\
+| OPTION_MASK_POWER5X  \
 | OPTION_MASK_POWER10  \
 | OPTION_MASK_POWER11  \
 | OPTION_MASK_P10_FUSION   \
@@ -185,10 +185,10 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
 RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
-   | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
+   | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
 RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
-   | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_FPRND
+   | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_POWER5X
| OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
 RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
@@ -239,14 +239,14 @@ RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | 
OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5)
 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
-   | 

[gcc(refs/users/meissner/heads/work186)] Change TARGET_POPCNTB to TARGET_POWER5.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:044e77421a761e6d3b579d938dd664884c415194

commit 044e77421a761e6d3b579d938dd664884c415194
Author: Michael Meissner 
Date:   Thu Nov 14 18:00:53 2024 -0500

Change TARGET_POPCNTB to TARGET_POWER5.

This patch changes TARGET_POPCNTB to TARGET_POWER5 and OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.  The -mpopcntb switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 2.2 
(Power5).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_POPCNTB to TARGET_POWER5.  Change OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_2_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power5 cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_emit_popcount): Update comment.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Change TARGET_POPCNTB to TARGET_POWER5.  Change
OPTION_MASK_POPCNTB to OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount2): Likewise.
(popcntb): Likewise.
(popcntd): Likewise.
(parity2): Likewise.
* gcc/config/rs6000/rs6000.md (-mpopcntb): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 18 +-
 gcc/config/rs6000/rs6000.cc | 10 +-
 gcc/config/rs6000/rs6000.h  |  8 
 gcc/config/rs6000/rs6000.md | 10 +-
 gcc/config/rs6000/rs6000.opt|  6 --
 7 files changed, 29 insertions(+), 27 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 4dc80e598fa4..da3a9c2d8406 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,7 +422,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((flags & OPTION_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..d600f123d6a7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,7 +21,7 @@
 /* ISA masks.  */
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
 #define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
@@ -143,7 +143,7 @@
 | OPTION_MASK_P9_VECTOR\
 | OPTION_MASK_PCREL\
 | OPTION_MASK_PCREL_OPT\
-| OPTION_MASK_POPCNTB  \
+| OPTION_MASK_POWER5   \
 | OPTION_MASK_POPCNTD  \
 | OPTION_MASK_POWERPC64\
 | OPTION_MASK_PPC_GFXOPT   \
@@ -184,11 +184,11 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS60

[gcc(refs/users/meissner/heads/work186)] Change TARGET_POPCNTD to TARGET_POWER7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d930a1c044147ab5d73b1bc5ec0ee46541865e44

commit d930a1c044147ab5d73b1bc5ec0ee46541865e44
Author: Michael Meissner 
Date:   Thu Nov 14 18:13:45 2024 -0500

Change TARGET_POPCNTD to TARGET_POWER7.

This patch changes TARGET_POPCNTD to TARGET_POWER7 and OPTION_MASK_POPCNTD 
to
OPTION_MASK_POWER7.  The -mpopcntd switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 2.6 
(Power7).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/dfp.md (cmp_internal1): Change 
TARGET_POPCNTD
to TARGET_POWER7.  Change OPTION_MASK_POPCNTD to OPTION_MASK_POWER7.
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_EMBEDDED): 
Likewise.
(ISA_2_6_MASKS_SERVER): Likewise.
(POWERPC_MASKS): Likewise.
* gcc/config/rs6000/rs6000-string.cc (expand_block_compare): 
Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(ctz2): Likewise.
(ffs2): Likewise.
(popcntb2): Likewise.
(lrintsi): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.
* gcc/config/rs6000/rs6000.opt (-mpopcntd): Likewise.

Diff:
---
 gcc/config/rs6000/dfp.md|  2 +-
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   |  6 +++---
 gcc/config/rs6000/rs6000-string.cc  |  2 +-
 gcc/config/rs6000/rs6000.cc | 18 +-
 gcc/config/rs6000/rs6000.h  | 20 ++--
 gcc/config/rs6000/rs6000.md | 26 +-
 gcc/config/rs6000/rs6000.opt|  6 --
 9 files changed, 44 insertions(+), 42 deletions(-)

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa9d7dd45dd3..b8189390d410 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POPCNTD"
+  "TARGET_DFP && TARGET_POWER7"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 76421bd1de0b..dae43b672ea7 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P6_64:
   return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
-  return TARGET_POPCNTD;
+  return TARGET_POWER7;
 case ENB_P7_64:
-  return TARGET_POPCNTD && TARGET_POWERPC64;
+  return TARGET_POWER7 && TARGET_POWERPC64;
 case ENB_P8:
   return TARGET_POWER8;
 case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index b721c9925e19..5bdd6a45db6a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -428,7 +428,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
   if ((flags & OPTION_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POPCNTD) != 0)
+  if ((flags & OPTION_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
   if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 77cc199073e3..01ab0c0d6b7c 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -37,9 +37,9 @@
 
   /* For ISA 2.06, don't add ISEL, since 

[gcc(refs/users/meissner/heads/work186)] Change TARGET_MODULO to TARGET_POWER9.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:da42fa4e7dee68d56707fd12ce1b976536619fc1

commit da42fa4e7dee68d56707fd12ce1b976536619fc1
Author: Michael Meissner 
Date:   Thu Nov 14 18:17:18 2024 -0500

Change TARGET_MODULO to TARGET_POWER9.

This patch changes TARGET_MODULO to TARGET_POWER9 and OPTION_MASK_MODULO to
OPTION_MASK_POWER9.  The -mmodulo switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 3.0 
(Power9).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_MODULO to TARGET_POWER9.  Change OPTION_MASK_MODULO to
OPTION_MASK_POWER9.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): 
Likewise.
(POWERPC_MASKS): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(mod3): Likewise.
(umod3): Likewise.
(divide/modulo peephole2): Likewise.
* gcc/config/rs6000/rs6000.opt (-mmodulo): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   |  4 ++--
 gcc/config/rs6000/rs6000.cc |  6 +++---
 gcc/config/rs6000/rs6000.h  |  6 +++---
 gcc/config/rs6000/rs6000.md | 14 +++---
 gcc/config/rs6000/rs6000.opt|  6 --
 7 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index dae43b672ea7..b6093b3cb64c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_MODULO;
+  return TARGET_POWER9;
 case ENB_P9_64:
-  return TARGET_MODULO && TARGET_POWERPC64;
+  return TARGET_POWER9 && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 5bdd6a45db6a..25c662a9ca86 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -432,7 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
   if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
-  if ((flags & OPTION_MASK_MODULO) != 0)
+  if ((flags & OPTION_MASK_POWER9) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
   if ((flags & OPTION_MASK_POWER10) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 01ab0c0d6b7c..c84af0c54cae 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -62,7 +62,7 @@
FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
 #define ISA_3_0_MASKS_SERVER   ((ISA_2_7_MASKS_SERVER  \
  | OPTION_MASK_ISEL\
- | OPTION_MASK_MODULO  \
+ | OPTION_MASK_POWER9  \
  | OPTION_MASK_P9_MINMAX   \
  | OPTION_MASK_P9_MISC \
  | OPTION_MASK_P9_VECTOR)  \
@@ -132,7 +132,7 @@
 | OPTION_MASK_ISEL \
 | OPTION_MASK_MFCRF\
 | OPTION_MASK_MMA  \
-| OPTION_MASK_MODULO   \
+| OPTION_MASK_POWER9   \
 | OPTION_MASK_MULHW\
 | OPTION_MASK_NO_UPDATE\
 | OPTION_MASK_POWER8   \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index eae5937972ed..2c101b589d9a 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3886,7 +3886,7 @@ rs6000_option_override_internal (bool global_init_p)
 
   /* For the newer switches (vsx, dfp, etc.) set some of the older options,
  unless the user explicitly used the -mno- to 

[gcc r15-5308] RISC-V: Move scalar SAT_ADD test cases to a isolated folder

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:e0a402b3e28545abe8b190fb84ccc180d0744b13

commit r15-5308-ge0a402b3e28545abe8b190fb84ccc180d0744b13
Author: Pan Li 
Date:   Fri Nov 15 11:42:13 2024 +0800

RISC-V: Move scalar SAT_ADD test cases to a isolated folder

Move the scalar SAT_ADD includes both the signed and unsigned
integer to the folder gcc.target/riscv/sat.  According to the
implementation the below options will be appended for each
test cases.

* -O2
* -O3
* -Ofast
* -Os
* -Oz

Then we can see the test log similar as below:

Executing on host: .../sat_s_add-1-i8.c ...  -O2 -march=rv64gc -S -o 
sat_s_add-1-i8.s
Executing on host: .../sat_s_add-1-i8.c ...  -O3 -march=rv64gc -S -o 
sat_s_add-1-i8.s
Executing on host: .../sat_s_add-1-i8.c ...  -Ofast -march=rv64gc -S -o 
sat_s_add-1-i8.s
Executing on host: .../sat_s_add-1-i8.c ...  -Oz -march=rv64gc -S -o 
sat_s_add-1-i8.s
Executing on host: .../sat_s_add-1-i8.c ...  -Os -march=rv64gc -S -o 
sat_s_add-1-i8.s

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

Committed as pre-approved by kito.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/riscv.exp: Add new folder sat under riscv
and add 5 options for each sat test.
* gcc.target/riscv/sat_s_add-1-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_add-1-i16.c: ...here.
* gcc.target/riscv/sat_s_add-1-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_add-1-i32.c: ...here.
* gcc.target/riscv/sat_s_add-1-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_add-1-i64.c: ...here.
* gcc.target/riscv/sat_s_add-1-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_add-1-i8.c: ...here.
* gcc.target/riscv/sat_s_add-2-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_add-2-i16.c: ...here.
* gcc.target/riscv/sat_s_add-2-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_add-2-i32.c: ...here.
* gcc.target/riscv/sat_s_add-2-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_add-2-i64.c: ...here.
* gcc.target/riscv/sat_s_add-2-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_add-2-i8.c: ...here.
* gcc.target/riscv/sat_s_add-3-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_add-3-i16.c: ...here.
* gcc.target/riscv/sat_s_add-3-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_add-3-i32.c: ...here.
* gcc.target/riscv/sat_s_add-3-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_add-3-i64.c: ...here.
* gcc.target/riscv/sat_s_add-3-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_add-3-i8.c: ...here.
* gcc.target/riscv/sat_s_add-4-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_add-4-i16.c: ...here.
* gcc.target/riscv/sat_s_add-4-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_add-4-i32.c: ...here.
* gcc.target/riscv/sat_s_add-4-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_add-4-i64.c: ...here.
* gcc.target/riscv/sat_s_add-4-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_add-4-i8.c: ...here.
* gcc.target/riscv/sat_s_add-run-1-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-1-i16.c: ...here.
* gcc.target/riscv/sat_s_add-run-1-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-1-i32.c: ...here.
* gcc.target/riscv/sat_s_add-run-1-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-1-i64.c: ...here.
* gcc.target/riscv/sat_s_add-run-1-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-1-i8.c: ...here.
* gcc.target/riscv/sat_s_add-run-2-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-2-i16.c: ...here.
* gcc.target/riscv/sat_s_add-run-2-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-2-i32.c: ...here.
* gcc.target/riscv/sat_s_add-run-2-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-2-i64.c: ...here.
* gcc.target/riscv/sat_s_add-run-2-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-2-i8.c: ...here.
* gcc.target/riscv/sat_s_add-run-3-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-3-i16.c: ...here.
* gcc.target/riscv/sat_s_add-run-3-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-3-i32.c: ...here.
* gcc.target/riscv/sat_s_add-run-3-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-3-i64.c: ...here.
* gcc.target/riscv/sat_s_add-run-3-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_add-run-3-i8.c: ...here.
* gcc.target/riscv/sat_s_add-run-4-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_

[gcc(refs/users/meissner/heads/work186)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0a746dd1f8ed5d199b026a8f3a05a28f3b1f7418

commit 0a746dd1f8ed5d199b026a8f3a05a28f3b1f7418
Author: Michael Meissner 
Date:   Thu Nov 14 23:16:46 2024 -0500

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

This patch also changes the target_clones support to use an architecture 
mask
instead of isa bits.

This patch also switches the handling of .machine to use architecture masks 
if
they exist (power4 through power11).  All of the other PowerPCs will 
continue to
use the existing code for setting the .machine option.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

The only difference in this patch compared to the first version posted on
November 6th is that I the correct attribution and copyright year (i.e. 
that I
created rs6000-arch.def in 2024).

Can I install this patch on the GCC 15 trunk?

2024-11-13  Michael Meissner  

gcc/

* config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu 
name.
* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an architecture flags argument, 
change
all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Switch to using architecture masks 
instead
of ISA masks.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_clone_priority): Switch to using architecture masks instead 
of
ISA masks.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the 
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/default64.h |  11 ++
 gcc/config/rs6000/rs6000-arch.def |  48 +
 gcc/config/rs6000/rs6000.cc   | 215 +++---
 gcc/config/rs6000/rs6000.h|  24 +
 gcc/config/rs6000/rs6000.opt  |   8 ++
 5 files changed, 270 insertions(+), 36 deletions(-)

diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
index 10e3dec78aca..afa6542e040c 100644
--- a/gcc/config/rs6000/default64.h
+++ b/gcc/config/rs6000/default64.h
@@ -21,6 +21,7 @@ along with GCC; see the file COPYING3.  If not see
 #define RS6000_CPU(NAME, CPU, FLAGS)
 #include "rs6000-cpus.def"
 #undef RS6000_CPU
+#undef TARGET_CPU_DEFAULT
 
 #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
 #undef TARGET_DEFAULT
@@ -28,10 +29,20 @@ along with GCC; see the file COPYING3.  If not see
| MASK_LITTLE_ENDIAN)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower8"
+#define TARGET_CPU_DEFAULT "power8"
+
 #else
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower4"
+
+#if (TARGET_DEFAULT & MASK_POWERPC64)
+#define TARGET_CPU_DEFAULT "powerpc64"
+
+#else
+#define TARGET_CPU_DEFAULT "powerpc"
+#endif
+
 #endif
diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..da5a43dfe2cf
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@

[gcc(refs/users/meissner/heads/work186)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:fa4f0516317565a9aa06c0509da47f803f36c1cc

commit fa4f0516317565a9aa06c0509da47f803f36c1cc
Author: Michael Meissner 
Date:   Thu Nov 14 23:25:02 2024 -0500

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
-mpower11 option was removed completely, since it was just added in GCC 15. 
 The
other two options were marked as WarnRemoved, and the various ISA bits were
removed.

TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

Can I install this patch on the GCC 15 trunk?

2024-11-14  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11, which are no 
longer
in the ISA flags.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TpARGET_POWER5): New macro.
(TARGET_POWER5X): Likewise.
(TARGET_POWER6): Likewise.
(TARGET_POWER7): Likewise.
(TARGET_POWER8): Likewise.
(TARGET_POWER9): Likewise.
(TARGET_POWER10): Likewise.
(TARGET_POWER11): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag 
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 27 +++
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h| 18 --
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 4dc80e598fa4..abc82beefa17 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -339,7 +339,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -412,7 +413,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -420,23 +421,25 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((flags & OPTION_MASK_POWERPC64) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags &

[gcc r15-5293] The fix for PR117191

[Denis Chertykov via Gcc-cvs]

https://gcc.gnu.org/g:fe1486e118d72d660284af43cb739e20d094b585

commit r15-5293-gfe1486e118d72d660284af43cb739e20d094b585
Author: Denis Chertykov 
Date:   Fri Nov 15 00:50:36 2024 +0400

The fix for PR117191

Wrong code appears after dse2 pass because it removes necessary insns.
(ie insn 554 - store to frame spill slot)
This happened because LRA pass doesn't cleanup the code exactly like reload 
does.
The reload1.c has a special pass for such cleanup.
The reload removes CLOBBER insns with spill slots like this:
(insn 202 184 186 7 (clobber (mem/c:TI (plus:HI (reg/f:HI 28 r28)
(const_int 1 [0x1])) [3 %sfp+1 S16 A8])) -1
 (nil))

Fragment from reload1.c:


  reload_completed = 1;

  /* Make a pass over all the insns and delete all USEs which we inserted
 only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and 
REG_UNUSED
 notes.  Delete all CLOBBER insns, except those that refer to the return
 value and the special mem:BLK CLOBBERs added to prevent the scheduler
 from misarranging variable-array code, and simplify (subreg (reg))
 operands.  Strip and regenerate REG_INC notes that may have been moved
 around.  */

  for (insn = first; insn; insn = NEXT_INSN (insn))
if (INSN_P (insn))
  {
rtx *pnote;

if (CALL_P (insn))
  replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
  VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));

if ((GET_CODE (PATTERN (insn)) == USE
 /* We mark with QImode USEs introduced by reload itself.  */
 && (GET_MODE (insn) == QImode
 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
|| (GET_CODE (PATTERN (insn)) == CLOBBER
&& (!MEM_P (XEXP (PATTERN (insn), 0))
|| GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
|| (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != 
SCRATCH
&& XEXP (XEXP (PATTERN (insn), 0), 0)
!= stack_pointer_rtx))
&& (!REG_P (XEXP (PATTERN (insn), 0))
|| ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)
  {
delete_insn (insn);
continue;
  }



LRA have a similar place where it removes unnecessary insns, but not 
CLOBBER insns with
memory spill slots. It's `lra_final_code_change' function.

I just mark a CLOBBER insn with pseudo spilled to memory for removing it 
later together
with LRA temporary CLOBBER insns.

PR rtl-optimization/117191
gcc/
* lra-spills.cc (spill_pseudos): Mark a CLOBBER insn with pseudo
spilled to memory for removing it later together with LRA temporary
CLOBBER insns.

Diff:
---
 gcc/lra-spills.cc | 5 +
 1 file changed, 5 insertions(+)

diff --git a/gcc/lra-spills.cc b/gcc/lra-spills.cc
index c149c3388cdb..3f5c8d2bcb00 100644
--- a/gcc/lra-spills.cc
+++ b/gcc/lra-spills.cc
@@ -537,6 +537,11 @@ spill_pseudos (void)
  break;
}
}
+ if (GET_CODE (PATTERN (insn)) == CLOBBER)
+   /* This is a CLOBBER insn with pseudo spilled to memory.
+  Mark it for removing it later together with LRA temporary
+  CLOBBER insns.  */
+   LRA_TEMP_CLOBBER_P (PATTERN (insn)) = 1;
  if (lra_dump_file != NULL)
fprintf (lra_dump_file,
 "Changing spilled pseudos to memory in insn #%u\n",

[gcc r15-5294] gcc: regenerate configure

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:7744da67e95824e15de5773e608aeb3d2bbd8653

commit r15-5294-g7744da67e95824e15de5773e608aeb3d2bbd8653
Author: Sam James 
Date:   Thu Nov 14 20:52:43 2024 +

gcc: regenerate configure

r15-5257-g56ded80b96b0f6 didn't regenerate configure correctly.

See 
https://inbox.sourceware.org/gcc-patches/zzzf69gorvpro...@zen.kayari.org/.

gcc/ChangeLog:

* configure: Regenerate.

Diff:
---
 gcc/configure | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/gcc/configure b/gcc/configure
index df64af3af57e..19cb5d069590 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -1780,11 +1780,13 @@ Optional Features:
   Use nano version formatted IO
 
   --enable-standard-branch-protection
-  enable Branch Target Identification Mechanism and
-  Return Address Signing by default for AArch64
+  enable Branch Target Identification Mechanism,
+  Return Address Signing, and Guarded Control Stack by
+  default for AArch64
   --disable-standard-branch-protection
-  disable Branch Target Identification Mechanism and
-  Return Address Signing by default for AArch64
+  disable Branch Target Identification Mechanism,
+  Return Address Signing, and Guarded Control Stack by
+  default for AArch64
 
 
   --enable-fix-cortex-a53-835769
@@ -21454,7 +21456,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 21457 "configure"
+#line 21459 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -21560,7 +21562,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 21563 "configure"
+#line 21565 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H

[gcc(refs/users/meissner/heads/work186)] Change TARGET_POPCNTB to TARGET_POWER5.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:41228ab6e1c248db4e1abdca65caddc5d5c7242c

commit 41228ab6e1c248db4e1abdca65caddc5d5c7242c
Author: Michael Meissner 
Date:   Thu Nov 14 13:01:08 2024 -0500

Change TARGET_POPCNTB to TARGET_POWER5.

This patch changes TARGET_POPCNTB to TARGET_POWER5 and OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.  The -mpopcntb switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 2.2 
(Power5).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_POPCNTB to TARGET_POWER5.  Change OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_2_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power5 cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_emit_popcount): Update comment.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Change TARGET_POPCNTB to TARGET_POWER5.  Change
OPTION_MASK_POPCNTB to OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount2): Likewise.
(popcntb): Likewise.
(popcntd): Likewise.
(parity2): Likewise.
* gcc/config/rs6000/rs6000.md (-mpopcntb): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 18 +-
 gcc/config/rs6000/rs6000.cc | 10 +-
 gcc/config/rs6000/rs6000.h  |  8 
 gcc/config/rs6000/rs6000.md | 12 ++--
 gcc/config/rs6000/rs6000.opt|  6 --
 7 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 4dc80e598fa4..da3a9c2d8406 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,7 +422,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((flags & OPTION_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..d600f123d6a7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,7 +21,7 @@
 /* ISA masks.  */
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
 #define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
@@ -143,7 +143,7 @@
 | OPTION_MASK_P9_VECTOR\
 | OPTION_MASK_PCREL\
 | OPTION_MASK_PCREL_OPT\
-| OPTION_MASK_POPCNTB  \
+| OPTION_MASK_POWER5   \
 | OPTION_MASK_POPCNTD  \
 | OPTION_MASK_POWERPC64\
 | OPTION_MASK_PPC_GFXOPT   \
@@ -184,11 +184,11 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS

[gcc(refs/users/meissner/heads/work186)] Change TARGET_POPCNTD to TARGET_POWER7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cd71abc54f8d44ac9f63dd832554d7c8d95706c6

commit cd71abc54f8d44ac9f63dd832554d7c8d95706c6
Author: Michael Meissner 
Date:   Thu Nov 14 14:25:45 2024 -0500

Change TARGET_POPCNTD to TARGET_POWER7.

This patch changes TARGET_POPCNTD to TARGET_POWER7 and OPTION_MASK_POPCNTD 
to
OPTION_MASK_POWER7.  The -mpopcntd switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 2.6 
(Power7).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/dfp.md (cmp_internal1): Change 
TARGET_POPCNTD
to TARGET_POWER7.  Change OPTION_MASK_POPCNTD to OPTION_MASK_POWER7.
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_EMBEDDED): 
Likewise.
(ISA_2_6_MASKS_SERVER): Likewise.
(POWERPC_MASKS): Likewise.
* gcc/config/rs6000/rs6000-string.cc (expand_block_compare): 
Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(ctz2): Likewise.
(ffs2): Likewise.
(popcntb2): Likewise.
(lrintsi): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.
* gcc/config/rs6000/rs6000.opt (-mpopcntd): Likewise.

Diff:
---
 gcc/config/rs6000/dfp.md|  2 +-
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   |  6 +++---
 gcc/config/rs6000/rs6000-string.cc  |  2 +-
 gcc/config/rs6000/rs6000.cc | 18 +-
 gcc/config/rs6000/rs6000.h  | 20 ++--
 gcc/config/rs6000/rs6000.md | 26 +-
 gcc/config/rs6000/rs6000.opt|  6 --
 9 files changed, 44 insertions(+), 42 deletions(-)

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa9d7dd45dd3..b8189390d410 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POPCNTD"
+  "TARGET_DFP && TARGET_POWER7"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 76421bd1de0b..dae43b672ea7 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P6_64:
   return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
-  return TARGET_POPCNTD;
+  return TARGET_POWER7;
 case ENB_P7_64:
-  return TARGET_POPCNTD && TARGET_POWERPC64;
+  return TARGET_POWER7 && TARGET_POWERPC64;
 case ENB_P8:
   return TARGET_POWER8;
 case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index b721c9925e19..5bdd6a45db6a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -428,7 +428,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
   if ((flags & OPTION_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POPCNTD) != 0)
+  if ((flags & OPTION_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
   if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 77cc199073e3..01ab0c0d6b7c 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -37,9 +37,9 @@
 
   /* For ISA 2.06, don't add ISEL, since 

[gcc(refs/users/meissner/heads/work186)] Change TARGET_CMPB to TARGET_POWER6.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:22c49a15753526225d2ef7853d2c4483359a5239

commit 22c49a15753526225d2ef7853d2c4483359a5239
Author: Michael Meissner 
Date:   Thu Nov 14 13:59:39 2024 -0500

Change TARGET_CMPB to TARGET_POWER6.

This patch changes TARGET_CMPB to TARGET_POWER6 and OPTION_MASK_CMPB to
OPTION_MASK_POWER6.  The -mcmpb switch is not being changed, just the name 
of
the macros used to determine if the PowerPC processor supports ISA 2.5 
(Power6).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.  Change OPTION_MASK_CMPB to
OPTION_MASK_POWER6.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): 
Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power6 cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_clone_map): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Change TARGET_CMPB to TARGET_POWER6.  Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6.  Eliminate redundant
TARGET_POWER5 test.
(cmpb3): Change TARGET_CMPB to TARGET_POWER6.  Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.
* gcc/config/rs6000/rs6000.opt (-mcmpb): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 14 +++---
 gcc/config/rs6000/rs6000.cc | 12 ++--
 gcc/config/rs6000/rs6000.h  |  6 +++---
 gcc/config/rs6000/rs6000.md | 16 
 gcc/config/rs6000/rs6000.opt|  8 +---
 7 files changed, 32 insertions(+), 30 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index c9ef36b77639..b721c9925e19 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -426,7 +426,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((flags & OPTION_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index b347053576db..77cc199073e3 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -28,7 +28,7 @@
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
  as optional.  Group masks by server and embedded. */
 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS  \
-| OPTION_MASK_CMPB \
+| OPTION_MASK_POWER6   \
 | OPTION_MASK_RECIP_PRECISION  \
 | OPTION_MASK_PPC_GFXOPT   \
 | OPTION_MASK_PPC_GPOPT)
@@ -117,7 +117,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
-| OPTION_MASK_CMPB \
+| OPTION_MASK_POWER6   \
 | OPTION_MASK_CRYPTO   \
   

[gcc(refs/users/meissner/heads/work186)] Change TARGET_FPRND to TARGET_POWER5X.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c0f96b024f68b31752041e7d6dfa83811c5a10ac

commit c0f96b024f68b31752041e7d6dfa83811c5a10ac
Author: Michael Meissner 
Date:   Thu Nov 14 13:59:16 2024 -0500

Change TARGET_FPRND to TARGET_POWER5X.

This patch changes TARGET_POWER5X to TARGET_POWER5 and OPTION_MASK_POWER5X 
to
OPTION_MASK_POWER5.  The -mfprnd switch is not being changed, just the name 
of
the macros used to determine if the PowerPC processor supports ISA 2.4 
(Power5x).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Change
TARGET_FPRND to TARGET_POWER5X.  Change OPTION_MASK_FPRND to
OPTION_MASK_POWER5X.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_4_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(464fp cpu definition): Likewise
(476fp cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.md (fmod3): Likewise.
(remainder3): Likewise.
(fctiwuz_): Likewise.
("ceil2): Likewise.
(floor2): Likewise.
(round2): Likewise.
* gcc/config/rs6000/rs6000.opt (-mfprnd): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc |  2 +-
 gcc/config/rs6000/rs6000-cpus.def | 14 +++---
 gcc/config/rs6000/rs6000.cc   | 10 +-
 gcc/config/rs6000/rs6000.md   | 14 +++---
 gcc/config/rs6000/rs6000.opt  |  6 --
 5 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index da3a9c2d8406..c9ef36b77639 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -424,7 +424,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
   if ((flags & OPTION_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((flags & OPTION_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
   if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index d600f123d6a7..b347053576db 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -22,7 +22,7 @@
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
 #define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
-#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
+#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_POWER5X)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
@@ -124,7 +124,7 @@
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
 | OPTION_MASK_FLOAT128_KEYWORD \
-| OPTION_MASK_FPRND\
+| OPTION_MASK_POWER5X  \
 | OPTION_MASK_POWER10  \
 | OPTION_MASK_POWER11  \
 | OPTION_MASK_P10_FUSION   \
@@ -185,10 +185,10 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
 RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
-   | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
+   | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
 RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
-   | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_FPRND
+   | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_POWER5X
| OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
 RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
@@ -239,14 +239,14 @@ RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | 
OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5)
 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
-   | 

[gcc(refs/users/meissner/heads/work186)] Change TARGET_POPCNTB to TARGET_POWER5.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3d69c6780399fdb6630834cc53d5ef57dbfb6f3f

commit 3d69c6780399fdb6630834cc53d5ef57dbfb6f3f
Author: Michael Meissner 
Date:   Thu Nov 14 13:58:49 2024 -0500

Change TARGET_POPCNTB to TARGET_POWER5.

This patch changes TARGET_POPCNTB to TARGET_POWER5 and OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.  The -mpopcntb switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 2.2 
(Power5).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_POPCNTB to TARGET_POWER5.  Change OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_2_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power5 cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_emit_popcount): Update comment.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Change TARGET_POPCNTB to TARGET_POWER5.  Change
OPTION_MASK_POPCNTB to OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount2): Likewise.
(popcntb): Likewise.
(popcntd): Likewise.
(parity2): Likewise.
* gcc/config/rs6000/rs6000.md (-mpopcntb): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 18 +-
 gcc/config/rs6000/rs6000.cc | 10 +-
 gcc/config/rs6000/rs6000.h  |  8 
 gcc/config/rs6000/rs6000.md | 12 ++--
 gcc/config/rs6000/rs6000.opt|  6 --
 7 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 4dc80e598fa4..da3a9c2d8406 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,7 +422,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((flags & OPTION_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..d600f123d6a7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,7 +21,7 @@
 /* ISA masks.  */
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
 #define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
@@ -143,7 +143,7 @@
 | OPTION_MASK_P9_VECTOR\
 | OPTION_MASK_PCREL\
 | OPTION_MASK_PCREL_OPT\
-| OPTION_MASK_POPCNTB  \
+| OPTION_MASK_POWER5   \
 | OPTION_MASK_POPCNTD  \
 | OPTION_MASK_POWERPC64\
 | OPTION_MASK_PPC_GFXOPT   \
@@ -184,11 +184,11 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS

[gcc(refs/users/meissner/heads/work186)] Change TARGET_MODULO to TARGET_POWER9.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d68704997f2e73fcecf75d74fc1559b7fe055463

commit d68704997f2e73fcecf75d74fc1559b7fe055463
Author: Michael Meissner 
Date:   Thu Nov 14 14:47:53 2024 -0500

Change TARGET_MODULO to TARGET_POWER9.

This patch changes TARGET_MODULO to TARGET_POWER9 and OPTION_MASK_MODULO to
OPTION_MASK_POWER9.  The -mmodulo switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 3.0 
(Power9).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_MODULO to TARGET_POWER9.  Change OPTION_MASK_MODULO to
OPTION_MASK_POWER9.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): 
Likewise.
(POWERPC_MASKS): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(mod3): Likewise.
(umod3): Likewise.
(divide/modulo peephole2): Likewise.
* gcc/config/rs6000/rs6000.opt (-mmodulo): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   |  4 ++--
 gcc/config/rs6000/rs6000.cc |  6 +++---
 gcc/config/rs6000/rs6000.h  |  6 +++---
 gcc/config/rs6000/rs6000.md | 14 +++---
 gcc/config/rs6000/rs6000.opt|  6 --
 7 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index dae43b672ea7..b6093b3cb64c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_MODULO;
+  return TARGET_POWER9;
 case ENB_P9_64:
-  return TARGET_MODULO && TARGET_POWERPC64;
+  return TARGET_POWER9 && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 5bdd6a45db6a..25c662a9ca86 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -432,7 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
   if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
-  if ((flags & OPTION_MASK_MODULO) != 0)
+  if ((flags & OPTION_MASK_POWER9) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
   if ((flags & OPTION_MASK_POWER10) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 01ab0c0d6b7c..c84af0c54cae 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -62,7 +62,7 @@
FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
 #define ISA_3_0_MASKS_SERVER   ((ISA_2_7_MASKS_SERVER  \
  | OPTION_MASK_ISEL\
- | OPTION_MASK_MODULO  \
+ | OPTION_MASK_POWER9  \
  | OPTION_MASK_P9_MINMAX   \
  | OPTION_MASK_P9_MISC \
  | OPTION_MASK_P9_VECTOR)  \
@@ -132,7 +132,7 @@
 | OPTION_MASK_ISEL \
 | OPTION_MASK_MFCRF\
 | OPTION_MASK_MMA  \
-| OPTION_MASK_MODULO   \
+| OPTION_MASK_POWER9   \
 | OPTION_MASK_MULHW\
 | OPTION_MASK_NO_UPDATE\
 | OPTION_MASK_POWER8   \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index eae5937972ed..2c101b589d9a 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3886,7 +3886,7 @@ rs6000_option_override_internal (bool global_init_p)
 
   /* For the newer switches (vsx, dfp, etc.) set some of the older options,
  unless the user explicitly used the -mno- to 

[gcc(refs/users/meissner/heads/work186)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e98592aa5924c0569df27db5bddbc277dea78f21

commit e98592aa5924c0569df27db5bddbc277dea78f21
Author: Michael Meissner 
Date:   Fri Nov 15 00:56:39 2024 -0500

Do not allow -mvsx to boost processor to power7.

This patch restructures the code so that -mvsx for example will not silently
convert the processor to power7.  The user must now use -mcpu=power7 or 
higher.
This means if the user does -mvsx and the default processor does not have 
VSX
support, it will be an error.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

I updated the 2 tests that used -mvsx to raise the cpu to power7.

Can I install this patch on the GCC 15 trunk?

2024-11-15  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add -mdejagnu-cpu=power6 when
requesting VSX instructions.
* gcc.target/powerpc/pr87496-1.c: Update optins to use
-mdejagnu-cpu=power6 to get the appropriate error message.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c |  38 +--
 gcc/testsuite/gcc.target/powerpc/pr115688.c |   3 +-
 gcc/testsuite/gcc.target/powerpc/pr87496-1.c|   2 +-
 4 files changed, 111 insertions(+), 61 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 000501ef01d0..96603ca61d84 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1173,6 +1173,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3700,7 +3701,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3969,59 +3969,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ign

[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:81b2cdf680f510a230b88c8f86e1caffb9ef71cd

commit 81b2cdf680f510a230b88c8f86e1caffb9ef71cd
Author: Michael Meissner 
Date:   Fri Nov 15 00:57:55 2024 -0500

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b119fcae6a40..842a7726a645 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -84,8 +84,10 @@ gcc/testsuite/
* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
to generate only Altivec instructions.
-   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
-   instructions.
+   * gcc.target/powerpc/pr115688.c: Add -mdejagnu-cpu=power6 when
+   requesting VSX instructions.
+   * gcc.target/powerpc/pr87496-1.c: Update optins to use
+   -mdejagnu-cpu=power6 to get the appropriate error message.
 
  Branch work186, patch #11 

[gcc(refs/users/meissner/heads/work186)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2879c3ba1500ac75a3b8dd17580c885add1aa885

commit 2879c3ba1500ac75a3b8dd17580c885add1aa885
Author: Michael Meissner 
Date:   Fri Nov 15 00:52:20 2024 -0500

Revert changes

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c |  38 ++-
 gcc/testsuite/gcc.target/powerpc/pr115688.c |   3 +-
 3 files changed, 60 insertions(+), 110 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 96603ca61d84..000501ef01d0 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1173,7 +1173,6 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
-static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3701,6 +3700,7 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
+  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3969,13 +3969,59 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
-  report_architecture_mismatch ();
+  /* Handle explicit -mno-{altivec,vsx} and turn off all of
+ the options that depend on those flags.  */
+  ignore_masks = rs6000_disable_incompatible_switches ();
+
+  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
+ unless the user explicitly used the -mno- to disable the code.  */
+  if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
+rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_P9_MINMAX)
+{
+  if (cpu_index >= 0)
+   {
+ if (cpu_index == PROCESSOR_POWER9)
+   {
+ /* legacy behavior: allow -mcpu=power9 with certain
+capabilities explicitly disabled.  */
+ rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
+   }
+ else
+   error ("power9 target option is incompatible with %<%s=%> "
+  "for  less than power9", "-mcpu");
+   }
+  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
+  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
+  & rs6000_isa_flags_explicit))
+   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
+  were explicitly cleared.  */
+   error ("%qs incompatible with explicitly disabled options",
+  "-mpower9-minmax");
+  else
+   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
+}
+  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
+rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_VSX)
+rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_POWER7)
+rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
+  else if (TARGET_DFP)
+rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_POWER6)
+rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
+  else if (TARGET_POWER5X)
+rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
+  else if (TARGET_POWER5)
+rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
+  else if (TARGET_ALTIVEC)
+rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
  unless the altivec ABI was set.  This is set by default for 64-bit, but
- not for 32-bit.  Don't move this before report_architecture_mismatch
+ not for 32-bit.  Don't move this before the above code using ignore_masks,
  since it can reset the cleared VSX/ALTIVEC flag again.  */
   if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
 {
@@ -25379,81 +25425,6 @@ rs6000_disable_incompatible_switches (void)
   return ignore_masks;
 }
 
-/* In the past, we would boost up the ISA if you selected an -m option but
-   did not specify the correct -mcpu= option.  I.e. if you added -mvsx,
-   GCC implictly would assume that you were building for at least power7.  Now,
-   don't allow the -m option to boost up the ISA level.  But you can still
-   do -mcpu=power7 -mno-vsx or -mcpu=power5 -mno-vsx.  */
-
-static void
-report_architecture_mismatch (void)
-{
-  HOST_WIDE_INT ignore_masks = rs6000_disable_incompatible_switches ();
-
-  static const struct {
-const HOST_WIDE_INT isa_flags; /* -m optiona.  */
-const HOST_WIDE_INT arch_flags;/* -mcpu= level.  

[gcc(refs/users/meissner/heads/work186)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d553483426809f56c5a3fa80d598bc5549a9d74a

commit d553483426809f56c5a3fa80d598bc5549a9d74a
Author: Michael Meissner 
Date:   Thu Nov 14 21:37:18 2024 -0500

Revert changes

Diff:
---
 gcc/config/rs6000/default64.h   |  11 --
 gcc/config/rs6000/dfp.md|   2 +-
 gcc/config/rs6000/rs6000-arch.def   |  48 ---
 gcc/config/rs6000/rs6000-builtin.cc |  14 +-
 gcc/config/rs6000/rs6000-c.cc   |  10 +-
 gcc/config/rs6000/rs6000-cpus.def   |  46 +++
 gcc/config/rs6000/rs6000-string.cc  |   2 +-
 gcc/config/rs6000/rs6000.cc | 263 
 gcc/config/rs6000/rs6000.h  |  64 +++--
 gcc/config/rs6000/rs6000.md |  76 +--
 gcc/config/rs6000/rs6000.opt|  38 ++
 11 files changed, 165 insertions(+), 409 deletions(-)

diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
index afa6542e040c..10e3dec78aca 100644
--- a/gcc/config/rs6000/default64.h
+++ b/gcc/config/rs6000/default64.h
@@ -21,7 +21,6 @@ along with GCC; see the file COPYING3.  If not see
 #define RS6000_CPU(NAME, CPU, FLAGS)
 #include "rs6000-cpus.def"
 #undef RS6000_CPU
-#undef TARGET_CPU_DEFAULT
 
 #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
 #undef TARGET_DEFAULT
@@ -29,20 +28,10 @@ along with GCC; see the file COPYING3.  If not see
| MASK_LITTLE_ENDIAN)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower8"
-#define TARGET_CPU_DEFAULT "power8"
-
 #else
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower4"
-
-#if (TARGET_DEFAULT & MASK_POWERPC64)
-#define TARGET_CPU_DEFAULT "powerpc64"
-
-#else
-#define TARGET_CPU_DEFAULT "powerpc"
-#endif
-
 #endif
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index b8189390d410..fa9d7dd45dd3 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POWER7"
+  "TARGET_DFP && TARGET_POPCNTD"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
deleted file mode 100644
index e5b6e9581331..
--- a/gcc/config/rs6000/rs6000-arch.def
+++ /dev/null
@@ -1,48 +0,0 @@
-/* IBM RS/6000 CPU architecture features by processor type.
-   Copyright (C) 1991-2024 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
-
-   This file is part of GCC.
-
-   GCC is free software; you can redistribute it and/or modify it
-   under the terms of the GNU General Public License as published
-   by the Free Software Foundation; either version 3, or (at your
-   option) any later version.
-
-   GCC is distributed in the hope that it will be useful, but WITHOUT
-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-   License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GCC; see the file COPYING3.  If not see
-   .  */
-
-/* This file defines architecture features that are based on the -mcpu=
-   option, and not on user options that can be turned on or off.  The intention
-   is for newer processors (power7 and above) to not add new ISA bits for the
-   particular processor, but add these bits.  Otherwise we have to add a bunch
-   of hidden options, just so we have the proper ISA bits.
-
-   For example, in the past we added -mpower8-internal, so that on power8,
-   power9, and power10 would inherit the option, but we had to mark the option
-   generate a warning if the user actually used it.  These options have been
-   moved from the ISA flags to the arch flags.
-
-   To use this, define the macro ARCH_EXPAND which takes 2 arguments.  The
-   first argument is the processor name in upper case, and the second argument
-   is a text name for the processor.
-
-   The function get_arch_flags when passed a processor index number will set up
-   the appropriate architecture flags based on the actual processor
-   enumeration.  */
-
-ARCH_EXPAND(POWER4,  "power4")
-ARCH_EXPAND(POWER5,  "power5")
-ARCH_EXPAND(POWER5X, "power5+")
-ARCH_EXPAND(POWER6,  "power6")
-ARCH_EXPAND(POWER7,  "power7")
-ARCH_EXPAND(POWER8,  "power8")
-ARCH_EXPAND(POWER9,  "power9")
-ARCH_EXPAND(POWER10, "power10")
-ARCH_EXPAND(POWER11, "power11")
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index b6093b3cb64c..9bdbae1ecf94 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,23 +155,23 @@ rs6000_builtin_is_supported (enum rs6000_gen_buil

[gcc(refs/users/meissner/heads/work186)] Add support for -mcpu=future

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8bbd4d135285dff469a2435f34f694d6e5ce084b

commit 8bbd4d135285dff469a2435f34f694d6e5ce084b
Author: Michael Meissner 
Date:   Thu Nov 14 23:40:18 2024 -0500

Add support for -mcpu=future

This patch adds the support that can be used in developing GCC support for
future PowerPC processors.

2024-11-14  Michael Meissner  

* config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for 
-mcpu=future.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-arch.def: Add future cpu.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
-mcpu=future, define _ARCH_FUTURE.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(future cpu): Define.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power10_cost): Update comment.
(get_arch_flags): Add support for future processor.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
(TARGET_POWER11): New macro.
* config/rs6000/rs6000.md (cpu attribute): Likewise.

Diff:
---
 gcc/config.gcc  |  4 ++--
 gcc/config/rs6000/aix71.h   |  1 +
 gcc/config/rs6000/aix72.h   |  1 +
 gcc/config/rs6000/aix73.h   |  1 +
 gcc/config/rs6000/driver-rs6000.cc  |  2 ++
 gcc/config/rs6000/rs6000-arch.def   |  1 +
 gcc/config/rs6000/rs6000-c.cc   |  2 ++
 gcc/config/rs6000/rs6000-cpus.def   |  3 +++
 gcc/config/rs6000/rs6000-opts.h |  1 +
 gcc/config/rs6000/rs6000-tables.opt | 11 +++
 gcc/config/rs6000/rs6000.cc | 34 ++
 gcc/config/rs6000/rs6000.h  |  2 ++
 gcc/config/rs6000/rs6000.md |  2 +-
 13 files changed, 50 insertions(+), 15 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 9b616bd6e1f8..d45d1faba7a0 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -541,7 +541,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h 
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
@@ -5649,7 +5649,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
-   "" | common | native \
+   "" | common | native | future \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 4350dcd89524..505986b33d63 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b48..242ca94bd065 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1318b0b3662d..2bd6b4bb3c4f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -

[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8c6b674e36d5918fda788bb26b5bceb1bdb484f2

commit 8c6b674e36d5918fda788bb26b5bceb1bdb484f2
Author: Michael Meissner 
Date:   Thu Nov 14 23:44:04 2024 -0500

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 214 +
 1 file changed, 214 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 23f7f779b59c..4c21bfdabe10 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,217 @@
+ Branch work186, patch #21 
+
+Add -mcpu=future tuning support.
+
+This patch makes -mtune=future use the same tuning decision as -mtune=power11.
+
+2024-11-14  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/power10.md (all reservations): Add future as an
+   alterntive to power10 and power11.
+
+ Branch work186, patch #20 
+
+Add support for -mcpu=future
+
+This patch adds the support that can be used in developing GCC support for
+future PowerPC processors.
+
+2024-11-14  Michael Meissner  
+
+   * config.gcc (powerpc*-*-*): Add support for --with-cpu=future.
+   * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future.
+   * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+   * config/rs6000/rs6000-arch.def: Add future cpu.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If
+   -mcpu=future, define _ARCH_FUTURE.
+   * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
+   (future cpu): Define.
+   * config/rs6000/rs6000-opts.h (enum processor_type): Add
+   PROCESSOR_FUTURE.
+   * config/rs6000/rs6000-tables.opt: Regenerate.
+   * config/rs6000/rs6000.cc (power10_cost): Update comment.
+   (get_arch_flags): Add support for future processor.
+   (rs6000_option_override_internal): Likewise.
+   (rs6000_machine_from_flags): Likewise.
+   (rs6000_reassociation_width): Likewise.
+   (rs6000_adjust_cost): Likewise.
+   (rs6000_issue_rate): Likewise.
+   (rs6000_sched_reorder): Likewise.
+   (rs6000_sched_reorder2): Likewise.
+   (rs6000_register_move_cost): Likewise.
+   * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+   (TARGET_POWER11): New macro.
+   * config/rs6000/rs6000.md (cpu attribute): Likewise.
+
+ Branch work186, patch #12 
+
+Do not allow -mvsx to boost processor to power7.
+
+This patch restructures the code so that -mvsx for example will not silently
+convert the processor to power7.  The user must now use -mcpu=power7 or higher.
+This means if the user does -mvsx and the default processor does not have VSX
+support, it will be an error.
+
+I have built both big endian and little endian bootstrap compilers and there
+were no regressions.
+
+In addition, I constructed a test case that used every archiecture define (like
+_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I ran
+this test for all supported combinations of -mcpu, big/little endian, and 32/64
+bit support.  Every single instance generated exactly the same code with the
+patches installed compared to the compiler before installing the patches.
+
+I updated the 2 tests that used -mvsx to raise the cpu to power7.
+
+Can I install this patch on the GCC 15 trunk?
+
+2024-11-14  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
+   Report an error if the user used an option such as -mvsx when the
+   default processor would not allow the option.
+   (rs6000_option_override_internal): Move some ISA checking code into
+   report_architecture_mismatch.
+
+2024-11-06  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
+   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
+   to generate only Altivec instructions.
+   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
+   instructions.
+
+ Branch work186, patch #11 
+
+Use architecture flags for defining _ARCH_PWR macros.
+
+For the newer architectures, this patch changes GCC to define the _ARCH_PWR
+macros using the new architecture flags instead of relying on isa options like
+-mpower10.
+
+The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
+-mpower11 option was removed completely, since it was just added in GCC 15.  
The
+other two options were marked as WarnRemoved, and the various ISA bits were
+removed.
+
+TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
+instead of the ISA bits.
+
+There are other internal isa bits that aren't removed with this patch because
+the built-in function support uses thos

[gcc(refs/users/meissner/heads/work186)] Add -mcpu=future tuning support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:49de9e438732c1d9a5f7703b4e0dba052bbb5df3

commit 49de9e438732c1d9a5f7703b4e0dba052bbb5df3
Author: Michael Meissner 
Date:   Thu Nov 14 23:41:52 2024 -0500

Add -mcpu=future tuning support.

This patch makes -mtune=future use the same tuning decision as 
-mtune=power11.

2024-11-14  Michael Meissner  

gcc/

* config/rs6000/power10.md (all reservations): Add future as an
alterntive to power10 and power11.

Diff:
---
 gcc/config/rs6000/power10.md | 144 +--
 1 file changed, 72 insertions(+), 72 deletions(-)

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 2310c4603457..e42b057dc45b 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,4 @@
-;; Scheduling description for the IBM Power10 and Power11 processors.
+;; Scheduling description for the IBM Power10, Power11, and Future processors.
 ;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +97,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
(eq_attr "update" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@
   (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +178,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle latency for updat

[gcc r15-5305] rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p3

[Kewen Lin via Gcc-cvs]

https://gcc.gnu.org/g:35c83e66c0085bc67fcb21b4413bace452ce0ca0

commit r15-5305-g35c83e66c0085bc67fcb21b4413bace452ce0ca0
Author: Kewen Lin 
Date:   Fri Nov 15 03:46:33 2024 +

rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p3

The current handlings in rs6000_emit_vector_compare is a bit
complicated to me, especially after we emit vector float
comparison insn with the given code directly.  So it's better
to refactor the handlings of vector integer comparison here.

This is part 3, it's to refactor the handlings on NE.
This patch doesn't introduce any functionality change.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refactor the
handlings for operator NE.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 30 ++
 1 file changed, 10 insertions(+), 20 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 718d65951e7f..1f20782d66b1 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16051,29 +16051,19 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
   emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, dmode, op0, op1)));
   return mask;
 }
+  else if (rcode == NE)
+{
+  /* ne(a,b) = ~eq(a,b)  */
+  mask = gen_reg_rtx (dmode);
+  emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (EQ, dmode, op0, op1)));
+  enum insn_code nor_code = optab_handler (one_cmpl_optab, dmode);
+  gcc_assert (nor_code != CODE_FOR_nothing);
+  emit_insn (GEN_FCN (nor_code) (mask, mask));
+  return mask;
+}
 
   switch (rcode)
 {
-case NE:
-  /* Invert condition and try again.
-e.g., A != B becomes ~(A==B).  */
-  {
-   enum insn_code nor_code;
-   rtx mask2;
-
-   nor_code = optab_handler (one_cmpl_optab, dmode);
-   if (nor_code == CODE_FOR_nothing)
- return NULL_RTX;
-
-   mask2 = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
-   if (!mask2)
- return NULL_RTX;
-
-   mask = gen_reg_rtx (dmode);
-   emit_insn (GEN_FCN (nor_code) (mask, mask2));
-   return mask;
-  }
-  break;
 case GE:
 case GEU:
 case LE:

[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:67e4c2848c8fce5874286ebaf3b53c50bc9e8793

commit 67e4c2848c8fce5874286ebaf3b53c50bc9e8793
Author: Michael Meissner 
Date:   Thu Nov 14 23:04:02 2024 -0500

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 137 +
 1 file changed, 46 insertions(+), 91 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c1b29fd68f37..23f7f779b59c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -2,58 +2,50 @@
 
 Change TARGET_MODULO to TARGET_POWER9.
 
-This patch changes TARGET_MODULO to TARGET_POWER9 and OPTION_MASK_MODULO to
-OPTION_MASK_POWER9.  The -mmodulo switch is not being changed, just the name of
-the macros used to determine if the PowerPC processor supports ISA 3.0 
(Power9).
+This patch changes TARGET_MODULO to TARGET_POWER9.  The -mmodulo switch is not
+being changed, just the name of the macros used to determine if the PowerPC
+processor supports ISA 3.0 (Power9).
 
 2024-11-14  Michael Meissner  
 
 gcc/
 
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
-   Change TARGET_MODULO to TARGET_POWER9.  Change OPTION_MASK_MODULO to
-   OPTION_MASK_POWER9.
-   * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise.
-   * gcc/config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Likewise.
-   (POWERPC_MASKS): Likewise.
+   Change TARGET_MODULO to TARGET_POWER9.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
-   (rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
-   * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
+   (TARGET_POWER9): New macro.
+   * gcc/config/rs6000/rs6000.md (enabled attribute): Change TARGET_MODULO
+   to TARGET_POWER9.
(mod3): Likewise.
(umod3): Likewise.
(divide/modulo peephole2): Likewise.
-   * gcc/config/rs6000/rs6000.opt (-mmodulo): Likewise.
 
  Branch work186, patch #4 
 
 Change TARGET_POPCNTD to TARGET_POWER7.
 
-This patch changes TARGET_POPCNTD to TARGET_POWER7 and OPTION_MASK_POPCNTD to
-OPTION_MASK_POWER7.  The -mpopcntd switch is not being changed, just the name 
of
-the macros used to determine if the PowerPC processor supports ISA 2.6 
(Power7).
+This patch changes TARGET_POPCNTD to TARGET_POWER7.  The -mpopcntd switch is 
not
+being changed, just the name of the macros used to determine if the PowerPC
+processor supports ISA 2.6 (Power7).
 
 2024-11-14  Michael Meissner  
 
 gcc/
 
* gcc/config/rs6000/dfp.md (cmp_internal1): Change TARGET_POPCNTD
-   to TARGET_POWER7.  Change OPTION_MASK_POPCNTD to OPTION_MASK_POWER7.
+   to TARGET_POWER7.
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
-   * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise.
-   * gcc/config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_EMBEDDED): Likewise.
-   (ISA_2_6_MASKS_SERVER): Likewise.
-   (POWERPC_MASKS): Likewise.
* gcc/config/rs6000/rs6000-string.cc (expand_block_compare): Likewise.
-   * gcc/config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise.
-   (rs6000_hard_regno_mode_ok_uncached): Likewise.
+   * gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
+   Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
-   (rs6000_opt_masks): Likewise.
+   (rs6000_emit_popcount): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
(TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
@@ -63,13 +55,13 @@ gcc/
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_FCTIDUZ): Likewise.
-   (TARGET_EXTRA_BUILTINS): Likewise.
+   (TARGET_POWER7): New macro.
+   (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(ctz2): Likewise.
-   (ffs2): Likewise.
-   (popcntb2): Likewise.
-   (lrintsi): Likewise.
+   (popcntd2): Likewise.
+   (lrintsi2): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
@@ -78,125 +70,88 @@ gcc/
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.
-   * gcc/config/rs6000/rs6000.opt (-mpopcntd): Likewise.
 
  Branch work186, patch #3 
 
 Change TARGET_CMPB to TARGET_POWER6.
 
-This patch changes TARGET_CMPB to TARGET_POWER6 and OPTION_MASK_CMPB to
-OPTION_MASK_POWER6.  The -mcmpb switch is not being changed, just the name of
-the macros used to determine if the PowerPC processor supports ISA 2.5 
(Power6).
+This p

[gcc r15-5309] testsuite: fix g++.dg/tree-ssa/pr58483.C

[Marek Polacek via Gcc-cvs]

https://gcc.gnu.org/g:3757009af71cd8404198909f087b5140ce42500a

commit r15-5309-g3757009af71cd8404198909f087b5140ce42500a
Author: Marek Polacek 
Date:   Fri Nov 15 00:02:44 2024 -0500

testsuite: fix g++.dg/tree-ssa/pr58483.C

This test mistakenly used two dg-do compile.  Since it passes
in C++11 as well, we can run it in C++11 and up.

gcc/testsuite/ChangeLog:

* g++.dg/tree-ssa/pr58483.C: Run in C++11 and up.

Diff:
---
 gcc/testsuite/g++.dg/tree-ssa/pr58483.C | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr58483.C 
b/gcc/testsuite/g++.dg/tree-ssa/pr58483.C
index c99664b57577..c0e8495ca545 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/pr58483.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/pr58483.C
@@ -1,5 +1,4 @@
-// { dg-do compile { target c++14 } }
-// { dg-do compile }
+// { dg-do compile { target c++11 } }
 // { dg-options "-O1 -fdump-tree-optimized" }
 #include

[gcc r15-5310] c: Add _Decimal64x support

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:1910ecf15bfcc560dc5089d42c9d75bc30b35c2a

commit r15-5310-g1910ecf15bfcc560dc5089d42c9d75bc30b35c2a
Author: Jakub Jelinek 
Date:   Fri Nov 15 08:43:48 2024 +0100

c: Add _Decimal64x support

The following patch adds _Decimal64x type support.  Our dfp libraries (dpd &
libbid) can only handle decimal32, decimal64 and decimal128 formats and I
don't see that changing any time soon, so the following patch just hardcodes
that _Decimal64x has the same mode as _Decimal128 (but is a distinct type).
In the unlikely event some target would introduce something different that
can be of course changed with target hooks but would be an ABI change.
_Decimal128x is optional and we don't have a wider decimal type, so that
type isn't added.

2024-11-15  Jakub Jelinek  

gcc/
* tree-core.h (enum tree_index): Add TI_DFLOAT64X_TYPE.
* tree.h (dfloat64x_type_node): Define.
* tree.cc (build_common_tree_nodes): Initialize dfloat64x_type_node.
* builtin-types.def (BT_DFLOAT64X): New DEF_PRIMITIVE_TYPE.
(BT_FN_DFLOAT64X): New DEF_FUNCTION_TYPE_0.
(BT_FN_DFLOAT64X_CONST_STRING, BT_FN_DFLOAT64X_DFLOAT64X): New
DEF_FUNCTION_TYPE_1.
* builtins.def (BUILT_IN_FABSD64X, BUILT_IN_INFD64X, 
BUILT_IN_NAND64X,
BUILT_IN_NANSD64X): New builtins.
* builtins.cc (expand_builtin): Handle BUILT_IN_FABSD64X.
(fold_builtin_0): Handle BUILT_IN_INFD64X.
(fold_builtin_1): Handle BUILT_IN_FABSD64X.
* fold-const-call.cc (fold_const_call): Handle CFN_BUILT_IN_NAND64X
and CFN_BUILT_IN_NANSD64X.
* ginclude/float.h (DEC64X_MANT_DIG, DEC64X_MIN_EXP, DEC64X_MAX_EXP,
DEC64X_MAX, DEC64X_EPSILON, DEC64X_MIN, DEC64X_TRUE_MIN,
DEC64X_SNAN): Redefine.
gcc/c-family/
* c-common.h (enum rid): Add RID_DFLOAT64X.
* c-common.cc (c_global_trees): Fix comment typo.  Add
dfloat64x_type_node.
(c_common_nodes_and_builtins): Handle RID_DFLOAT64X.
* c-cppbuiltin.cc (c_cpp_builtins): Call
builtin_define_decimal_float_constants also for dfloat64x_type_node
if non-NULL.
* c-lex.cc (interpret_float): Handle d64x suffixes.
* c-pretty-print.cc (pp_c_floating_constant): Print d64x suffixes
on dfloat64x_type_node typed constants.
gcc/c/
* c-tree.h (enum c_typespec_keyword): Add cts_dfloat64x and adjust
comment.
* c-parser.cc (c_keyword_starts_typename, c_token_starts_declspecs,
c_parser_declspecs, c_parser_gnu_attribute_any_word): Handle
RID_DFLOAT64X.
(c_parser_postfix_expression): Handle _Decimal64x arguments in
__builtin_tgmath.
(warn_for_abs): Handle BUILT_IN_FABSD64X.
* c-decl.cc (declspecs_add_type): Handle cts_dfloat64x and
RID_DFLOAT64X.
(finish_declspecs): Handle cts_dfloat64x.
* c-typeck.cc (c_common_type): Handle dfloat64x_type_node.
gcc/testsuite/
* gcc.dg/dfp/c11-decimal64x-1.c: New test.
* gcc.dg/dfp/c11-decimal64x-2.c: New test.
* gcc.dg/dfp/c23-decimal64x-1.c: New test.
* gcc.dg/dfp/c23-decimal64x-2.c: New test.
* gcc.dg/dfp/c23-decimal64x-3.c: New test.
* gcc.dg/dfp/c23-decimal64x-4.c: New test.
libcpp/
* expr.cc (interpret_float_suffix): Handle d64x and D64x
suffixes, adjust comment.

Diff:
---
 gcc/builtin-types.def   |  7 +++
 gcc/builtins.cc |  3 ++
 gcc/builtins.def|  4 ++
 gcc/c-family/c-common.cc|  5 +-
 gcc/c-family/c-common.h |  2 +-
 gcc/c-family/c-cppbuiltin.cc|  3 ++
 gcc/c-family/c-lex.cc   |  4 ++
 gcc/c-family/c-pretty-print.cc  |  2 +
 gcc/c/c-decl.cc | 38 +--
 gcc/c/c-parser.cc   | 14 +-
 gcc/c/c-tree.h  |  5 +-
 gcc/c/c-typeck.cc   |  5 ++
 gcc/fold-const-call.cc  |  2 +
 gcc/ginclude/float.h| 21 
 gcc/testsuite/gcc.dg/dfp/c11-decimal64x-1.c |  7 +++
 gcc/testsuite/gcc.dg/dfp/c11-decimal64x-2.c |  7 +++
 gcc/testsuite/gcc.dg/dfp/c23-decimal64x-1.c | 74 +
 gcc/testsuite/gcc.dg/dfp/c23-decimal64x-2.c |  7 +++
 gcc/testsuite/gcc.dg/dfp/c23-decimal64x-3.c | 26 ++
 gcc/testsuite/gcc.dg/dfp/c23-decimal64x-4.c | 43 +
 gcc/tree-core.h |  1 +
 gcc/tree.cc |  5 ++
 gcc/tree.h  |  1 +
 libcpp/expr.cc  | 13 +++--
 24 files 

[gcc r15-5290] libstdc++: Implement LWG 3563 changes to keys_view and values_view

[Patrick Palka via Libstdc++-cvs]

https://gcc.gnu.org/g:361050589b144913ec05d9d8e10639afa98319a8

commit r15-5290-g361050589b144913ec05d9d8e10639afa98319a8
Author: Patrick Palka 
Date:   Thu Nov 14 13:27:41 2024 -0500

libstdc++: Implement LWG 3563 changes to keys_view and values_view

This LWG issue corrects the definition of these alias templates to make
them suitable for alias CTAD.

libstdc++-v3/ChangeLog:

* include/std/ranges (keys_view): Adjust as per LWG 3563.
(values_view): Likewise.
* testsuite/std/ranges/adaptors/elements.cc (test08): New test.

Reviewed-by: Jonathan Wakely 

Diff:
---
 libstdc++-v3/include/std/ranges|  6 --
 libstdc++-v3/testsuite/std/ranges/adaptors/elements.cc | 14 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/include/std/ranges b/libstdc++-v3/include/std/ranges
index 743429dbceae..5153dcc26c4f 100644
--- a/libstdc++-v3/include/std/ranges
+++ b/libstdc++-v3/include/std/ranges
@@ -4551,11 +4551,13 @@ namespace views::__adaptor
 inline constexpr bool enable_borrowed_range>
   = enable_borrowed_range<_Tp>;
 
+  // _GLIBCXX_RESOLVE_LIB_DEFECTS
+  // 3563. keys_view example is broken
   template
-using keys_view = elements_view, 0>;
+using keys_view = elements_view<_Range, 0>;
 
   template
-using values_view = elements_view, 1>;
+using values_view = elements_view<_Range, 1>;
 
   namespace views
   {
diff --git a/libstdc++-v3/testsuite/std/ranges/adaptors/elements.cc 
b/libstdc++-v3/testsuite/std/ranges/adaptors/elements.cc
index a15192bf0ecf..0a05ce7378f9 100644
--- a/libstdc++-v3/testsuite/std/ranges/adaptors/elements.cc
+++ b/libstdc++-v3/testsuite/std/ranges/adaptors/elements.cc
@@ -148,6 +148,19 @@ test07()
   b == e;
 }
 
+void
+test08()
+{
+  // LWG 3563 - keys_view example is broken
+  std::pair x[] = {{1,2},{3,4}};
+  auto v = ranges::keys_view{views::all(x)};
+  auto w = ranges::values_view{views::all(x)};
+  using ty1 = decltype(v);
+  using ty1 = ranges::elements_view, 0>;
+  using ty2 = decltype(w);
+  using ty2 = ranges::elements_view, 1>;
+}
+
 int
 main()
 {
@@ -158,4 +171,5 @@ main()
   test05();
   test06();
   test07();
+  test08();
 }

[gcc(refs/users/meissner/heads/work186)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:132ff16c4986dc2fbb8cbe089a379fcb2887dfae

commit 132ff16c4986dc2fbb8cbe089a379fcb2887dfae
Author: Michael Meissner 
Date:   Thu Nov 14 13:57:40 2024 -0500

Revert changes

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  6 +++---
 gcc/config/rs6000/rs6000-c.cc   |  6 +++---
 gcc/config/rs6000/rs6000-cpus.def   | 36 -
 gcc/config/rs6000/rs6000.cc | 32 ++---
 gcc/config/rs6000/rs6000.h  | 14 ++---
 gcc/config/rs6000/rs6000.md | 40 ++---
 gcc/config/rs6000/rs6000.opt| 18 ++---
 7 files changed, 73 insertions(+), 79 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 76421bd1de0b..9bdbae1ecf94 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,11 +155,11 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POWER5;
+  return TARGET_POPCNTB;
 case ENB_P6:
-  return TARGET_POWER6;
+  return TARGET_CMPB;
 case ENB_P6_64:
-  return TARGET_POWER6 && TARGET_POWERPC64;
+  return TARGET_CMPB && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index b721c9925e19..4dc80e598fa4 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,11 +422,11 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POWER5) != 0)
+  if ((flags & OPTION_MASK_POPCNTB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_POWER5X) != 0)
+  if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_POWER6) != 0)
+  if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 77cc199073e3..84fac8bdac1d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,14 +21,14 @@
 /* ISA masks.  */
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
-#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_POWER5X)
+#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
  as optional.  Group masks by server and embedded. */
 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS  \
-| OPTION_MASK_POWER6   \
+| OPTION_MASK_CMPB \
 | OPTION_MASK_RECIP_PRECISION  \
 | OPTION_MASK_PPC_GFXOPT   \
 | OPTION_MASK_PPC_GPOPT)
@@ -117,14 +117,14 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
-| OPTION_MASK_POWER6   \
+| OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
 | OPTION_MASK_DLMZB\
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
 | OPTION_MASK_FLOAT128_KEYWORD \
-| OPTION_MASK_POWER5X  \
+| OPTION_MASK_FPRND\
 | OPTION_MASK_POWER10  \
 | OPTION_MASK_POWER11  \
 | OPTION_MASK_P10_FUSION   \
@@ -143,7 +143,7 @@
 | OPTION_MASK_P9_VECTOR\
 | OPTION_MASK_PCREL\
 | OPTION_MASK_PCREL_OPT\
-

[gcc(refs/users/meissner/heads/work186)] Change TARGET_FPRND to TARGET_POWER5X.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:dda19c152e7b80234d85323b13b83e865c5b7cc2

commit dda19c152e7b80234d85323b13b83e865c5b7cc2
Author: Michael Meissner 
Date:   Thu Nov 14 13:53:51 2024 -0500

Change TARGET_FPRND to TARGET_POWER5X.

This patch changes TARGET_POWER5X to TARGET_POWER5 and OPTION_MASK_POWER5X 
to
OPTION_MASK_POWER5.  The -mfprnd switch is not being changed, just the name 
of
the macros used to determine if the PowerPC processor supports ISA 2.4 
(Power5x).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Change
TARGET_FPRND to TARGET_POWER5X.  Change OPTION_MASK_FPRND to
OPTION_MASK_POWER5X.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_4_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(464fp cpu definition): Likewise
(476fp cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.md (fmod3): Likewise.
(remainder3): Likewise.
(fctiwuz_): Likewise.
("ceil2): Likewise.
(floor2): Likewise.
(round2): Likewise.
* gcc/config/rs6000/rs6000.opt (-mfprnd): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc |  2 +-
 gcc/config/rs6000/rs6000-cpus.def | 14 +++---
 gcc/config/rs6000/rs6000.cc   | 10 +-
 gcc/config/rs6000/rs6000.md   | 14 +++---
 gcc/config/rs6000/rs6000.opt  |  6 --
 5 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index da3a9c2d8406..c9ef36b77639 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -424,7 +424,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
   if ((flags & OPTION_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((flags & OPTION_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
   if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index d600f123d6a7..b347053576db 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -22,7 +22,7 @@
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
 #define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
-#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
+#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_POWER5X)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
@@ -124,7 +124,7 @@
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
 | OPTION_MASK_FLOAT128_KEYWORD \
-| OPTION_MASK_FPRND\
+| OPTION_MASK_POWER5X  \
 | OPTION_MASK_POWER10  \
 | OPTION_MASK_POWER11  \
 | OPTION_MASK_P10_FUSION   \
@@ -185,10 +185,10 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
 RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
-   | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
+   | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
 RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
-   | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_FPRND
+   | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_POWER5X
| OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
 RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
@@ -239,14 +239,14 @@ RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | 
OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5)
 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
-   | 

[gcc(refs/users/meissner/heads/work186)] Change TARGET_POPCNTB to TARGET_POWER5.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:4001e93682384f195628f5c2609b52332558c7c8

commit 4001e93682384f195628f5c2609b52332558c7c8
Author: Michael Meissner 
Date:   Thu Nov 14 13:52:47 2024 -0500

Change TARGET_POPCNTB to TARGET_POWER5.

This patch changes TARGET_POPCNTB to TARGET_POWER5 and OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.  The -mpopcntb switch is not being changed, just the 
name of
the macros used to determine if the PowerPC processor supports ISA 2.2 
(Power5).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_POPCNTB to TARGET_POWER5.  Change OPTION_MASK_POPCNTB 
to
OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_2_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power5 cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_emit_popcount): Update comment.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Change TARGET_POPCNTB to TARGET_POWER5.  Change
OPTION_MASK_POPCNTB to OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount2): Likewise.
(popcntb): Likewise.
(popcntd): Likewise.
(parity2): Likewise.
* gcc/config/rs6000/rs6000.md (-mpopcntb): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 18 +-
 gcc/config/rs6000/rs6000.cc | 10 +-
 gcc/config/rs6000/rs6000.h  |  8 
 gcc/config/rs6000/rs6000.md | 12 ++--
 gcc/config/rs6000/rs6000.opt|  6 --
 7 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 4dc80e598fa4..da3a9c2d8406 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,7 +422,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((flags & OPTION_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..d600f123d6a7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,7 +21,7 @@
 /* ISA masks.  */
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
 #define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
@@ -143,7 +143,7 @@
 | OPTION_MASK_P9_VECTOR\
 | OPTION_MASK_PCREL\
 | OPTION_MASK_PCREL_OPT\
-| OPTION_MASK_POPCNTB  \
+| OPTION_MASK_POWER5   \
 | OPTION_MASK_POPCNTD  \
 | OPTION_MASK_POWERPC64\
 | OPTION_MASK_PPC_GFXOPT   \
@@ -184,11 +184,11 @@ RS6000_CPU ("464", PROCESSOR_PPC440, 
OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
 RS

[gcc(refs/users/meissner/heads/work186)] Change TARGET_CMPB to TARGET_POWER6.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:59e6b014546fc80fedf332a71bc8d05a1a93819f

commit 59e6b014546fc80fedf332a71bc8d05a1a93819f
Author: Michael Meissner 
Date:   Thu Nov 14 13:54:45 2024 -0500

Change TARGET_CMPB to TARGET_POWER6.

This patch changes TARGET_CMPB to TARGET_POWER6 and OPTION_MASK_CMPB to
OPTION_MASK_POWER6.  The -mcmpb switch is not being changed, just the name 
of
the macros used to determine if the PowerPC processor supports ISA 2.5 
(Power6).

2024-11-14  Michael Meissner  

gcc/

* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.  Change OPTION_MASK_CMPB to
OPTION_MASK_POWER6.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): 
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): 
Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power6 cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_clone_map): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Change TARGET_CMPB to TARGET_POWER6.  Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6.  Eliminate redundant
TARGET_POWER5 test.
(cmpb3): Change TARGET_CMPB to TARGET_POWER6.  Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.
* gcc/config/rs6000/rs6000.opt (-mcmpb): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-c.cc   |  2 +-
 gcc/config/rs6000/rs6000-cpus.def   | 14 +++---
 gcc/config/rs6000/rs6000.cc | 12 ++--
 gcc/config/rs6000/rs6000.h  |  6 +++---
 gcc/config/rs6000/rs6000.md | 16 
 gcc/config/rs6000/rs6000.opt|  8 +---
 7 files changed, 32 insertions(+), 30 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index c9ef36b77639..b721c9925e19 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -426,7 +426,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((flags & OPTION_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index b347053576db..77cc199073e3 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -28,7 +28,7 @@
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
  as optional.  Group masks by server and embedded. */
 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS  \
-| OPTION_MASK_CMPB \
+| OPTION_MASK_POWER6   \
 | OPTION_MASK_RECIP_PRECISION  \
 | OPTION_MASK_PPC_GFXOPT   \
 | OPTION_MASK_PPC_GPOPT)
@@ -117,7 +117,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=.  */
 #define POWERPC_MASKS  (OPTION_MASK_ALTIVEC\
-| OPTION_MASK_CMPB \
+| OPTION_MASK_POWER6   \
 | OPTION_MASK_CRYPTO   \
   

[gcc(refs/users/meissner/heads/work186)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e81e3b2208e24210af9ca003d56fb12a1d03ba3f

commit e81e3b2208e24210af9ca003d56fb12a1d03ba3f
Author: Michael Meissner 
Date:   Thu Nov 14 17:39:14 2024 -0500

Revert changes

Diff:
---
 gcc/config/rs6000/dfp.md|  2 +-
 gcc/config/rs6000/rs6000-builtin.cc | 14 +++
 gcc/config/rs6000/rs6000-c.cc   | 10 ++---
 gcc/config/rs6000/rs6000-cpus.def   | 46 +++---
 gcc/config/rs6000/rs6000-string.cc  |  2 +-
 gcc/config/rs6000/rs6000.cc | 52 -
 gcc/config/rs6000/rs6000.h  | 40 +--
 gcc/config/rs6000/rs6000.md | 78 ++---
 gcc/config/rs6000/rs6000.opt| 30 +-
 9 files changed, 132 insertions(+), 142 deletions(-)

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index b8189390d410..fa9d7dd45dd3 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POWER7"
+  "TARGET_DFP && TARGET_POPCNTD"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index b6093b3cb64c..9bdbae1ecf94 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,23 +155,23 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POWER5;
+  return TARGET_POPCNTB;
 case ENB_P6:
-  return TARGET_POWER6;
+  return TARGET_CMPB;
 case ENB_P6_64:
-  return TARGET_POWER6 && TARGET_POWERPC64;
+  return TARGET_CMPB && TARGET_POWERPC64;
 case ENB_P7:
-  return TARGET_POWER7;
+  return TARGET_POPCNTD;
 case ENB_P7_64:
-  return TARGET_POWER7 && TARGET_POWERPC64;
+  return TARGET_POPCNTD && TARGET_POWERPC64;
 case ENB_P8:
   return TARGET_POWER8;
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_POWER9;
+  return TARGET_MODULO;
 case ENB_P9_64:
-  return TARGET_POWER9 && TARGET_POWERPC64;
+  return TARGET_MODULO && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 25c662a9ca86..4dc80e598fa4 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,17 +422,17 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POWER5) != 0)
+  if ((flags & OPTION_MASK_POPCNTB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_POWER5X) != 0)
+  if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_POWER6) != 0)
+  if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POWER7) != 0)
+  if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
   if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
-  if ((flags & OPTION_MASK_POWER9) != 0)
+  if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
   if ((flags & OPTION_MASK_POWER10) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index c84af0c54cae..84fac8bdac1d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,14 +21,14 @@
 /* ISA masks.  */
 #ifndef ISA_2_1_MASKS
 #define ISA_2_1_MASKS  OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POWER5)
-#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_POWER5X)
+#define ISA_2_2_MASKS  (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_4_MASKS  (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
   /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
  power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
  as optional.  Group masks by server and embedded. */
 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS  \
-| OPTION_MASK_POWER6   \
+| OPTION_MASK_CMPB \
 | OPTION_MASK_RECIP_PRECISION  \
 | OPTION_MASK_PPC_GFXOPT   \
 | 

[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:578f73b983bf04e1ee7724548e298ad4487bdd22

commit 578f73b983bf04e1ee7724548e298ad4487bdd22
Author: Michael Meissner 
Date:   Thu Nov 14 14:50:10 2024 -0500

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 233 +
 1 file changed, 233 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 81b644bdeb4f..c1b29fd68f37 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,238 @@
+ Branch work186, patch #5 
+
+Change TARGET_MODULO to TARGET_POWER9.
+
+This patch changes TARGET_MODULO to TARGET_POWER9 and OPTION_MASK_MODULO to
+OPTION_MASK_POWER9.  The -mmodulo switch is not being changed, just the name of
+the macros used to determine if the PowerPC processor supports ISA 3.0 
(Power9).
+
+2024-11-14  Michael Meissner  
+
+gcc/
+
+   * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
+   Change TARGET_MODULO to TARGET_POWER9.  Change OPTION_MASK_MODULO to
+   OPTION_MASK_POWER9.
+   * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise.
+   * gcc/config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Likewise.
+   (POWERPC_MASKS): Likewise.
+   * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
+   Likewise.
+   (rs6000_opt_masks): Likewise.
+   * gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
+   (TARGET_EXTSWSLI): Likewise.
+   (TARGET_MADDLD): Likewise.
+   * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
+   (mod3): Likewise.
+   (umod3): Likewise.
+   (divide/modulo peephole2): Likewise.
+   * gcc/config/rs6000/rs6000.opt (-mmodulo): Likewise.
+
+ Branch work186, patch #4 
+
+Change TARGET_POPCNTD to TARGET_POWER7.
+
+This patch changes TARGET_POPCNTD to TARGET_POWER7 and OPTION_MASK_POPCNTD to
+OPTION_MASK_POWER7.  The -mpopcntd switch is not being changed, just the name 
of
+the macros used to determine if the PowerPC processor supports ISA 2.6 
(Power7).
+
+2024-11-14  Michael Meissner  
+
+gcc/
+
+   * gcc/config/rs6000/dfp.md (cmp_internal1): Change TARGET_POPCNTD
+   to TARGET_POWER7.  Change OPTION_MASK_POPCNTD to OPTION_MASK_POWER7.
+   * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
+   Likewise.
+   * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise.
+   * gcc/config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_EMBEDDED): Likewise.
+   (ISA_2_6_MASKS_SERVER): Likewise.
+   (POWERPC_MASKS): Likewise.
+   * gcc/config/rs6000/rs6000-string.cc (expand_block_compare): Likewise.
+   * gcc/config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise.
+   (rs6000_hard_regno_mode_ok_uncached): Likewise.
+   (rs6000_option_override_internal): Likewise.
+   (rs6000_rtx_costs): Likewise.
+   (rs6000_opt_masks): Likewise.
+   * gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise.
+   (TARGET_FCFID): Likewise.
+   (TARGET_LFIWZX): Likewise.
+   (TARGET_FCFIDS): Likewise.
+   (TARGET_FCFIDU): Likewise.
+   (TARGET_FCFIDUS): Likewise.
+   (TARGET_FCTIDUZ): Likewise.
+   (TARGET_FCTIWUZ): Likewise.
+   (TARGET_FCTIDUZ): Likewise.
+   (TARGET_EXTRA_BUILTINS): Likewise.
+   (CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
+   * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
+   (ctz2): Likewise.
+   (ffs2): Likewise.
+   (popcntb2): Likewise.
+   (lrintsi): Likewise.
+   (lrintsi): Likewise.
+   (lrintsi_di): Likewise.
+   (cmpmemsi): Likewise.
+   (bpermd_): Likewise.
+   (addg6s): Likewise.
+   (cdtbcd): Likewise.
+   (cbcdtd): Likewise.
+   (div_): Likewise.
+   * gcc/config/rs6000/rs6000.opt (-mpopcntd): Likewise.
+
+ Branch work186, patch #3 
+
+Change TARGET_CMPB to TARGET_POWER6.
+
+This patch changes TARGET_CMPB to TARGET_POWER6 and OPTION_MASK_CMPB to
+OPTION_MASK_POWER6.  The -mcmpb switch is not being changed, just the name of
+the macros used to determine if the PowerPC processor supports ISA 2.5 
(Power6).
+
+2024-11-14  Michael Meissner  
+
+gcc/
+
+   * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
+   Change TARGET_CMPB to TARGET_POWER6.  Change OPTION_MASK_CMPB to
+   OPTION_MASK_POWER6.
+   * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise.
+   * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): Likewise.
+   (POWERPC_MASKS): Likewise.
+   (476 cpu definition): Likewise.
+   (476fp cpu definition): Likewise.
+   (a2 cpu definition): Likewise.
+   (power6 cpu definition): Likewise.
+   * gcc/config/rs6000/rs6000.cc (rs6000_clone_map): Likewise.
+   (rs6000_option_override_internal): Likewise.
+   (rs6000_rtx_costs): Likewise.
+   (rs6000

[gcc r15-5291] ipa: Rationalize IPA-VR computations across pass-through jump functions

[Martin Jambor via Gcc-cvs]

https://gcc.gnu.org/g:012f5a22bac26a898ab66655965b07ac23201fdd

commit r15-5291-g012f5a22bac26a898ab66655965b07ac23201fdd
Author: Martin Jambor 
Date:   Thu Nov 14 20:55:06 2024 +0100

ipa: Rationalize IPA-VR computations across pass-through jump functions

Currently ipa_value_range_from_jfunc and
propagate_vr_across_jump_function contain similar but not same code
for dealing with pass-through jump functions.  This patch puts these
common bits into one function which can also handle comparison
operations.

gcc/ChangeLog:

2024-11-01  Martin Jambor  

PR ipa/114985
* ipa-cp.cc (ipa_vr_intersect_with_arith_jfunc): New function.
(ipa_value_range_from_jfunc): Move the common functionality to the
above new function, adjust the rest so that it works with it well.
(propagate_vr_across_jump_function): Likewise.

Diff:
---
 gcc/ipa-cp.cc | 181 ++
 1 file changed, 67 insertions(+), 114 deletions(-)

diff --git a/gcc/ipa-cp.cc b/gcc/ipa-cp.cc
index fb65ec0c6a62..25741cf47bb0 100644
--- a/gcc/ipa-cp.cc
+++ b/gcc/ipa-cp.cc
@@ -1692,6 +1692,55 @@ ipa_vr_operation_and_type_effects (vrange &dst_vr,
dst_type, src_type);
 }
 
+/* Given a PASS_THROUGH jump function JFUNC that takes as its source SRC_VR of
+   SRC_TYPE and the result needs to be DST_TYPE, if any value range information
+   can be deduced at all, intersect VR with it.  */
+
+static void
+ipa_vr_intersect_with_arith_jfunc (vrange &vr,
+  ipa_jump_func *jfunc,
+  const value_range &src_vr,
+  tree src_type,
+  tree dst_type)
+{
+  if (src_vr.undefined_p () || src_vr.varying_p ())
+return;
+
+  enum tree_code operation = ipa_get_jf_pass_through_operation (jfunc);
+  if (TREE_CODE_CLASS (operation) == tcc_unary)
+{
+  value_range tmp_res (dst_type);
+  if (ipa_vr_operation_and_type_effects (tmp_res, src_vr, operation,
+dst_type, src_type))
+   vr.intersect (tmp_res);
+  return;
+}
+
+  tree operand = ipa_get_jf_pass_through_operand (jfunc);
+  range_op_handler handler (operation);
+  if (!handler)
+return;
+  value_range op_vr (TREE_TYPE (operand));
+  ipa_range_set_and_normalize (op_vr, operand);
+
+  tree operation_type;
+  if (TREE_CODE_CLASS (operation) == tcc_comparison)
+operation_type = boolean_type_node;
+  else
+operation_type = src_type;
+
+  value_range op_res (dst_type);
+  if (!ipa_vr_supported_type_p (operation_type)
+  || !handler.operand_check_p (operation_type, src_type, op_vr.type ())
+  || !handler.fold_range (op_res, operation_type, src_vr, op_vr))
+return;
+
+  value_range tmp_res (dst_type);
+  if (ipa_vr_operation_and_type_effects (tmp_res, op_res, NOP_EXPR, dst_type,
+operation_type))
+  vr.intersect (tmp_res);
+}
+
 /* Determine range of JFUNC given that INFO describes the caller node or
the one it is inlined to, CS is the call graph edge corresponding to JFUNC
and PARM_TYPE of the parameter.  */
@@ -1701,18 +1750,18 @@ ipa_value_range_from_jfunc (vrange &vr,
ipa_node_params *info, cgraph_edge *cs,
ipa_jump_func *jfunc, tree parm_type)
 {
-  vr.set_undefined ();
+  vr.set_varying (parm_type);
 
-  if (jfunc->m_vr)
+  if (jfunc->m_vr && jfunc->m_vr->known_p ())
 ipa_vr_operation_and_type_effects (vr,
   *jfunc->m_vr,
   NOP_EXPR, parm_type,
   jfunc->m_vr->type ());
   if (vr.singleton_p ())
 return;
+
   if (jfunc->type == IPA_JF_PASS_THROUGH)
 {
-  int idx;
   ipcp_transformation *sum
= ipcp_get_transformation_summary (cs->caller->inlined_to
   ? cs->caller->inlined_to
@@ -1720,54 +1769,15 @@ ipa_value_range_from_jfunc (vrange &vr,
   if (!sum || !sum->m_vr)
return;
 
-  idx = ipa_get_jf_pass_through_formal_id (jfunc);
+  int idx = ipa_get_jf_pass_through_formal_id (jfunc);
 
   if (!(*sum->m_vr)[idx].known_p ())
return;
-  tree vr_type = ipa_get_type (info, idx);
+  tree src_type = ipa_get_type (info, idx);
   value_range srcvr;
   (*sum->m_vr)[idx].get_vrange (srcvr);
 
-  enum tree_code operation = ipa_get_jf_pass_through_operation (jfunc);
-
-  if (TREE_CODE_CLASS (operation) == tcc_unary)
-   {
- value_range res (parm_type);
-
- if (ipa_vr_operation_and_type_effects (res,
-srcvr,
-operation, parm_type,
-vr_type))
- 

[gcc r15-5292] libstdc++: Make equal and is_permutation short-circuit (LWG 3560)

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:45cc42d6dc0642612e7076e95820438a1aab5479

commit r15-5292-g45cc42d6dc0642612e7076e95820438a1aab5479
Author: Jonathan Wakely 
Date:   Thu Nov 14 16:57:17 2024 +

libstdc++: Make equal and is_permutation short-circuit (LWG 3560)

We already implement short-circuiting for random access iterators, but
we also need to do so for ranges::equal and ranges::is_permutation when
given sized ranges that are not random access ranges (e.g. std::list).

libstdc++-v3/ChangeLog:

* include/bits/ranges_algo.h (__is_permutation_fn::operator()):
Short-circuit for sized ranges with different sizes, as per LWG
3560.
* include/bits/ranges_algobase.h (__equal_fn::operator()):
Likewise.
* include/bits/stl_algo.h (__is_permutation): Use if-constexpr
for random access iterator branches.
* include/bits/stl_algobase.h (__equal4): Likewise.
* testsuite/25_algorithms/equal/lwg3560.cc: New test.
* testsuite/25_algorithms/is_permutation/lwg3560.cc: New test.

Reviewed-by: Patrick Palka 

Diff:
---
 libstdc++-v3/include/bits/ranges_algo.h|  7 +++
 libstdc++-v3/include/bits/ranges_algobase.h|  7 +++
 libstdc++-v3/include/bits/stl_algo.h   | 13 +++---
 libstdc++-v3/include/bits/stl_algobase.h   | 44 ++-
 .../testsuite/25_algorithms/equal/lwg3560.cc   | 49 +
 .../25_algorithms/is_permutation/lwg3560.cc| 51 ++
 6 files changed, 145 insertions(+), 26 deletions(-)

diff --git a/libstdc++-v3/include/bits/ranges_algo.h 
b/libstdc++-v3/include/bits/ranges_algo.h
index bae36637b3e3..80d4f5a0d574 100644
--- a/libstdc++-v3/include/bits/ranges_algo.h
+++ b/libstdc++-v3/include/bits/ranges_algo.h
@@ -595,6 +595,13 @@ namespace ranges
   operator()(_Range1&& __r1, _Range2&& __r2, _Pred __pred = {},
 _Proj1 __proj1 = {}, _Proj2 __proj2 = {}) const
   {
+   // _GLIBCXX_RESOLVE_LIB_DEFECTS
+   // 3560. ranges::is_permutation should short-circuit for sized_ranges
+   if constexpr (sized_range<_Range1>)
+ if constexpr (sized_range<_Range2>)
+   if (ranges::distance(__r1) != ranges::distance(__r2))
+ return false;
+
return (*this)(ranges::begin(__r1), ranges::end(__r1),
   ranges::begin(__r2), ranges::end(__r2),
   std::move(__pred),
diff --git a/libstdc++-v3/include/bits/ranges_algobase.h 
b/libstdc++-v3/include/bits/ranges_algobase.h
index df4e770e7a65..150e990f9ae8 100644
--- a/libstdc++-v3/include/bits/ranges_algobase.h
+++ b/libstdc++-v3/include/bits/ranges_algobase.h
@@ -172,6 +172,13 @@ namespace ranges
   operator()(_Range1&& __r1, _Range2&& __r2, _Pred __pred = {},
 _Proj1 __proj1 = {}, _Proj2 __proj2 = {}) const
   {
+   // _GLIBCXX_RESOLVE_LIB_DEFECTS
+   // 3560. ranges::equal [...] should short-circuit for sized_ranges
+   if constexpr (sized_range<_Range1>)
+ if constexpr (sized_range<_Range2>)
+   if (ranges::distance(__r1) != ranges::distance(__r2))
+ return false;
+
return (*this)(ranges::begin(__r1), ranges::end(__r1),
   ranges::begin(__r2), ranges::end(__r2),
   std::move(__pred),
diff --git a/libstdc++-v3/include/bits/stl_algo.h 
b/libstdc++-v3/include/bits/stl_algo.h
index 04bdaa669816..d8a7668ff831 100644
--- a/libstdc++-v3/include/bits/stl_algo.h
+++ b/libstdc++-v3/include/bits/stl_algo.h
@@ -3471,6 +3471,8 @@ _GLIBCXX_END_INLINE_ABI_NAMESPACE(_V2)
 }
 
 #if __cplusplus > 201103L
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wc++17-extensions" // if constexpr
   template
 _GLIBCXX20_CONSTEXPR
@@ -3485,12 +3487,10 @@ _GLIBCXX_END_INLINE_ABI_NAMESPACE(_V2)
= typename iterator_traits<_ForwardIterator2>::iterator_category;
   using _It1_is_RA = is_same<_Cat1, random_access_iterator_tag>;
   using _It2_is_RA = is_same<_Cat2, random_access_iterator_tag>;
-  constexpr bool __ra_iters = _It1_is_RA() && _It2_is_RA();
-  if (__ra_iters)
+  constexpr bool __ra_iters = __and_<_It1_is_RA, _It2_is_RA>::value;
+  if constexpr (__ra_iters)
{
- auto __d1 = std::distance(__first1, __last1);
- auto __d2 = std::distance(__first2, __last2);
- if (__d1 != __d2)
+ if ((__last1 - __first1) != (__last2 - __first2))
return false;
}
 
@@ -3501,7 +3501,7 @@ _GLIBCXX_END_INLINE_ABI_NAMESPACE(_V2)
if (!__pred(__first1, __first2))
  break;
 
-  if (__ra_iters)
+  if constexpr (__ra_iters)
{
  if (__first1 == __last1)
return true;
@@ -3532,6 +3532,7 @@ _GLIBCXX_END_INLINE_ABI_NAMESPACE(_V2)
}
   return true;
 }
+#pragma GCC diagnostic pop
 
   /**
*  @brief  Checks whether a

[gcc r15-5265] aarch64: Add ACLE __gcs* intrinsics

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:a2bb4588f653148ea61913102965337c366cc79b

commit r15-5265-ga2bb4588f653148ea61913102965337c366cc79b
Author: Yury Khrustalev 
Date:   Thu Nov 14 16:15:07 2024 +

aarch64: Add ACLE __gcs* intrinsics

Add the following ACLE intrinsics:

 - void *__gcspr(void);
 - uint64_t __gcspopm(void);
 - void *__gcsss(void *);

gcc/ChangeLog:
* config/aarch64/arm_acle.h (__gcspr): New.
(__gcspopm): New.
(__gcsss): New.

Diff:
---
 gcc/config/aarch64/arm_acle.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h
index ca9aabf8ebb9..7fe61c736ed8 100644
--- a/gcc/config/aarch64/arm_acle.h
+++ b/gcc/config/aarch64/arm_acle.h
@@ -201,6 +201,15 @@ __chkfeat (uint64_t __feat)
   return __builtin_aarch64_chkfeat (__feat) ^ __feat;
 }
 
+#define __gcspr() \
+  __builtin_aarch64_gcspr ()
+
+#define __gcspopm() \
+  __builtin_aarch64_gcspopm ()
+
+#define __gcsss(__stack) \
+  __builtin_aarch64_gcsss (__stack)
+
 #pragma GCC pop_options

[gcc r15-5277] aarch64: Add tests and docs for indirect_return attribute

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:e36249f8228d9b861550e81b117025462d876a0b

commit r15-5277-ge36249f8228d9b861550e81b117025462d876a0b
Author: Richard Ball 
Date:   Thu Nov 14 16:15:13 2024 +

aarch64: Add tests and docs for indirect_return attribute

This patch adds a new testcase and docs for indirect_return
attribute.

gcc/ChangeLog:

* doc/extend.texi: Add AArch64 docs for indirect_return
attribute.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/indirect_return-1.c: New test.
* gcc.target/aarch64/indirect_return-2.c: New test.
* gcc.target/aarch64/indirect_return-3.c: New test.

Co-authored-by: Yury Khrustalev 

Diff:
---
 gcc/doc/extend.texi| 10 
 .../gcc.target/aarch64/indirect_return-1.c | 53 ++
 .../gcc.target/aarch64/indirect_return-2.c | 49 
 .../gcc.target/aarch64/indirect_return-3.c |  9 
 4 files changed, 121 insertions(+)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index c566474074d7..59644606261c 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -4761,6 +4761,16 @@ Enable or disable calls to out-of-line helpers to 
implement atomic operations.
 This corresponds to the behavior of the command-line options
 @option{-moutline-atomics} and @option{-mno-outline-atomics}.
 
+@cindex @code{indirect_return} function attribute, AArch64
+@item indirect_return
+The @code{indirect_return} attribute can be applied to a function type
+to indicate that the function may return via an indirect branch instead
+of via a normal return instruction.  For example, this can be true of
+functions that implement manual context switching between user space
+threads, such as the POSIX @code{swapcontext} function.  This attribute
+adds a @code{BTI J} instruction when BTI is enabled e.g. via
+@option{-mbranch-protection}.
+
 @end table
 
 The above target attributes can be specified as follows:
diff --git a/gcc/testsuite/gcc.target/aarch64/indirect_return-1.c 
b/gcc/testsuite/gcc.target/aarch64/indirect_return-1.c
new file mode 100644
index ..9ab133ffb7ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/indirect_return-1.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mbranch-protection=bti" } */
+
+int
+__attribute((indirect_return,weak))
+foo (int a)
+{
+  return a;
+}
+
+/*
+**func1:
+** hint34 // bti c
+** ...
+** bl  foo
+** hint36 // bti j
+** ...
+** ret
+*/
+int
+func1 (int a, int b)
+{
+  return foo (a + b);
+}
+
+/*
+**func2:
+** hint34 // bti c
+** ...
+** b   foo
+*/
+int __attribute((indirect_return,weak))
+func2 (int a, int b)
+{
+  return foo (a - b);
+}
+
+/*
+**func3:
+** hint34 // bti c
+** ...
+** bl  func2
+** hint36 // bti j
+** ...
+** ret
+*/
+int
+func3 (int x, int y)
+{
+  return func2 (x, y);
+}
+
+/* { dg-final { check-function-bodies "**" "" "" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/indirect_return-2.c 
b/gcc/testsuite/gcc.target/aarch64/indirect_return-2.c
new file mode 100644
index ..4759ed67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/indirect_return-2.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mbranch-protection=none" } */
+
+int
+__attribute((indirect_return,weak))
+foo (int a)
+{
+  return a;
+}
+
+/*
+**func1:
+** ...
+** bl  foo
+** ...
+** ret
+*/
+int
+func1 (int a, int b)
+{
+  return foo (a + b);
+}
+
+/*
+**func2:
+** ...
+** b   foo
+*/
+int __attribute((indirect_return,weak))
+func2 (int a, int b)
+{
+  return foo (a - b);
+}
+
+/*
+**func3:
+** ...
+** bl  func2
+** ...
+** ret
+*/
+int
+func3 (int x, int y)
+{
+  return func2 (x, y);
+}
+
+/* { dg-final { check-function-bodies "**" "" "" } } */
+/* { dg-final { scan-assembler-not {\thint\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/indirect_return-3.c 
b/gcc/testsuite/gcc.target/aarch64/indirect_return-3.c
new file mode 100644
index ..382138c5e25a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/indirect_return-3.c
@@ -0,0 +1,9 @@
+/* Check that mismatching attribute on function pointers is an error.  */
+/* { dg-do compile } */
+
+void f(void);
+void (*f_ptr)(void) __attribute__((indirect_return)) = f; /* { dg-error 
{incompatible pointer type} } */
+
+void g(void) __attribute__((indirect_return));
+void (*g_ptr1)(void) = g; /* { dg-error {incompatible pointer type} } */
+void (*g_ptr2)(void) __attribute__((indirect_return)) = g;

[gcc r15-5297] libstdc++: Fix indentation in std::list::emplace_back

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:71f221a8bee6274f37af99138b41c3ae451527ef

commit r15-5297-g71f221a8bee6274f37af99138b41c3ae451527ef
Author: Jonathan Wakely 
Date:   Fri Nov 15 00:00:38 2024 +

libstdc++: Fix indentation in std::list::emplace_back

libstdc++-v3/ChangeLog:

* include/bits/stl_list.h (list::emplace_back): Fix indentation.

Diff:
---
 libstdc++-v3/include/bits/stl_list.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/bits/stl_list.h 
b/libstdc++-v3/include/bits/stl_list.h
index 3c313cec1d89..7deb04b4bfe4 100644
--- a/libstdc++-v3/include/bits/stl_list.h
+++ b/libstdc++-v3/include/bits/stl_list.h
@@ -1410,7 +1410,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
{
  this->_M_insert(end(), std::forward<_Args>(__args)...);
 #if __cplusplus > 201402L
-   return back();
+ return back();
 #endif
}
 #endif

[gcc r15-5296] [RISC-V][V2] Fix type on vector move patterns

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:aaada43a2a91194a3c50e364d9dde277fb4b764b

commit r15-5296-gaaada43a2a91194a3c50e364d9dde277fb4b764b
Author: Jeff Law 
Date:   Thu Nov 14 16:57:50 2024 -0700

[RISC-V][V2] Fix type on vector move patterns

Updated version of my prior patch to fix type attributes on the
pre-allocation vector move pattern.  This version just adds a suitable
set of attributes to a second pattern that was obviously wrong.

Passed on my tester for rv64 and rv32 crosses.  Bootstrapped and
regression tested on riscv64-linux-gnu as well.

--

So I was looking into a horrific schedule for SAD a week or so ago and
came across this gem.

Basically we were treating a vector load as a vector move from a
scheduling standpoint during sched1.  Naturally we didn't expose much
ILP during sched1.  That in turn caused the register allocator to pack
the pseudos onto the physical vector registers tightly.  regrename
didn't do anything useful and the resulting code had too many false
dependencies for sched2 to do anything useful.

As a result we were taking many load->use stalls in x264's SAD routine.

I'm confident the types are fine, but I'm a lot less sure about the
other attributes (mode, avl_type_index, mode_idx).  If someone could
take a look at that, it'd be greatly appreciated.

There's other cases that may need similar treatment.  But I didn't want
to muck with them until I understood those other attributes and how they
need adjustments.

In particular mov_lra appears to have the same
problem.

--

gcc/
* config/riscv/vector.md (mov pattern/splitter): Fix type and
other attributes.
(mov_lra): Likewise.

Diff:
---
 gcc/config/riscv/vector.md | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index c29e69d5c36d..a75c7ab9d086 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1395,7 +1395,10 @@
 gcc_assert (ok_p);
 DONE;
   }
-  [(set_attr "type" "vmov")]
+  [(set_attr "type" "vlde,vste,vmov")
+   (set_attr "mode" "")
+   (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
+   (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))]
 )
 
 (define_expand "mov"
@@ -1442,7 +1445,10 @@
 }
   DONE;
 }
-  [(set_attr "type" "vmov")]
+  [(set_attr "type" "vlde,vste,vmov")
+   (set_attr "mode" "")
+   (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
+   (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))]
 )
 
 (define_insn "*mov_vls"

[gcc r15-5295] Fortran: fix passing of NULL() actual argument to character dummy [PR104819]

[Harald Anlauf via Gcc-cvs]

https://gcc.gnu.org/g:f70c1d517e09c4dde421774a8cec591ca3c479a0

commit r15-5295-gf70c1d517e09c4dde421774a8cec591ca3c479a0
Author: Harald Anlauf 
Date:   Thu Nov 14 21:38:04 2024 +0100

Fortran: fix passing of NULL() actual argument to character dummy [PR104819]

Ensure that character length is set and passed by the call to a procedure
when its dummy argument is NULL() with MOLD argument present, or set length
to either 0 or the callee's expected character length.  For assumed-rank
dummies, use the rank of the MOLD argument.  Generate temporaries for
passed arguments when needed.

PR fortran/104819

gcc/fortran/ChangeLog:

* trans-expr.cc (conv_null_actual): Helper function to handle
passing of NULL() to non-optional dummy arguments of non-bind(c)
procedures.
(gfc_conv_procedure_call): Use it for character dummies.

gcc/testsuite/ChangeLog:

* gfortran.dg/null_actual_6.f90: New test.

Diff:
---
 gcc/fortran/trans-expr.cc   |  79 ++
 gcc/testsuite/gfortran.dg/null_actual_6.f90 | 221 
 2 files changed, 300 insertions(+)

diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index ddbb5ecf068a..f004af713344 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -6378,6 +6378,76 @@ conv_dummy_value (gfc_se * parmse, gfc_expr * e, 
gfc_symbol * fsym,
 }
 
 
+/* Helper function for the handling of NULL() actual arguments associated with
+   non-optional dummy variables.  Argument parmse should already be set up.  */
+static void
+conv_null_actual (gfc_se * parmse, gfc_expr * e, gfc_symbol * fsym)
+{
+  gcc_assert (fsym && !fsym->attr.optional);
+
+  /* Obtain the character length for a NULL() actual with a character
+ MOLD argument.  Otherwise substitute a suitable dummy length.
+ Here we handle only non-optional dummies of non-bind(c) procedures.  */
+  if (fsym->ts.type == BT_CHARACTER)
+{
+  if (e->ts.type == BT_CHARACTER
+ && e->symtree->n.sym->ts.type == BT_CHARACTER)
+   {
+ /* MOLD is present.  Substitute a temporary character NULL pointer.
+For an assumed-rank dummy we need a descriptor that passes the
+correct rank.  */
+ if (fsym->as && fsym->as->type == AS_ASSUMED_RANK)
+   {
+ tree rank;
+ tree tmp = parmse->expr;
+ tmp = gfc_conv_scalar_to_descriptor (parmse, tmp, fsym->attr);
+ rank = gfc_conv_descriptor_rank (tmp);
+ gfc_add_modify (&parmse->pre, rank,
+ build_int_cst (TREE_TYPE (rank), e->rank));
+ parmse->expr = gfc_build_addr_expr (NULL_TREE, tmp);
+   }
+ else
+   {
+ tree tmp = gfc_create_var (TREE_TYPE (parmse->expr), "null");
+ gfc_add_modify (&parmse->pre, tmp,
+ build_zero_cst (TREE_TYPE (tmp)));
+ parmse->expr = gfc_build_addr_expr (NULL_TREE, tmp);
+   }
+
+ /* Ensure that a usable length is available.  */
+ if (parmse->string_length == NULL_TREE)
+   {
+ gfc_typespec *ts = &e->symtree->n.sym->ts;
+
+ if (ts->u.cl->length != NULL
+ && ts->u.cl->length->expr_type == EXPR_CONSTANT)
+   gfc_conv_const_charlen (ts->u.cl);
+
+ if (ts->u.cl->backend_decl)
+   parmse->string_length = ts->u.cl->backend_decl;
+   }
+   }
+  else if (e->ts.type == BT_UNKNOWN && parmse->string_length == NULL_TREE)
+   {
+ /* MOLD is not present.  Pass length of associated dummy character
+argument if constant, or zero.  */
+ if (fsym->ts.u.cl->length != NULL
+ && fsym->ts.u.cl->length->expr_type == EXPR_CONSTANT)
+   {
+ gfc_conv_const_charlen (fsym->ts.u.cl);
+ parmse->string_length = fsym->ts.u.cl->backend_decl;
+   }
+ else
+   {
+ parmse->string_length = gfc_create_var (gfc_charlen_type_node,
+ "slen");
+ gfc_add_modify (&parmse->pre, parmse->string_length,
+ build_zero_cst (gfc_charlen_type_node));
+   }
+   }
+}
+}
+
 
 /* Generate code for a procedure call.  Note can return se->post != NULL.
If se->direct_byref is set then se->expr contains the return parameter.
@@ -7542,6 +7612,15 @@ gfc_conv_procedure_call (gfc_se * se, gfc_symbol * sym,
  gfc_conv_const_charlen (e->symtree->n.sym->ts.u.cl);
  parmse.string_length = e->symtree->n.sym->ts.u.cl->backend_decl;
}
+
+ /* Obtain the character length for a NULL() actual with a character
+MOLD argument.  Otherwise substitute a suitable dummy length.
+Here we handle non-optional dummies of 

[gcc(refs/users/meissner/heads/work186)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:af57d156bc1a828accc4f089d92a10e56432ff93

commit af57d156bc1a828accc4f089d92a10e56432ff93
Author: Michael Meissner 
Date:   Thu Nov 14 21:26:05 2024 -0500

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

This patch also changes the target_clones support to use an architecture 
mask
instead of isa bits.

This patch also switches the handling of .machine to use architecture masks 
if
they exist (power4 through power11).  All of the other PowerPCs will 
continue to
use the existing code for setting the .machine option.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define 
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I 
ran
this test for all supported combinations of -mcpu, big/little endian, and 
32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-11-14  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an architecture flags argument, 
change
all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Switch to using architecture masks 
instead
of ISA masks.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_clone_priority): Switch to using architecture masks instead 
of
ISA masks.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the 
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/default64.h |  11 ++
 gcc/config/rs6000/rs6000-arch.def |  48 +
 gcc/config/rs6000/rs6000.cc   | 215 +++---
 gcc/config/rs6000/rs6000.h|  24 +
 gcc/config/rs6000/rs6000.opt  |   8 ++
 5 files changed, 270 insertions(+), 36 deletions(-)

diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
index 10e3dec78aca..afa6542e040c 100644
--- a/gcc/config/rs6000/default64.h
+++ b/gcc/config/rs6000/default64.h
@@ -21,6 +21,7 @@ along with GCC; see the file COPYING3.  If not see
 #define RS6000_CPU(NAME, CPU, FLAGS)
 #include "rs6000-cpus.def"
 #undef RS6000_CPU
+#undef TARGET_CPU_DEFAULT
 
 #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
 #undef TARGET_DEFAULT
@@ -28,10 +29,20 @@ along with GCC; see the file COPYING3.  If not see
| MASK_LITTLE_ENDIAN)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower8"
+#define TARGET_CPU_DEFAULT "power8"
+
 #else
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpower4"
+
+#if (TARGET_DEFAULT & MASK_POWERPC64)
+#define TARGET_CPU_DEFAULT "powerpc64"
+
+#else
+#define TARGET_CPU_DEFAULT "powerpc"
+#endif
+
 #endif
diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..e5b6e9581331
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,48 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or 

[gcc r15-5227] tree-optimization/117556 - SLP of live stmts from load-lanes

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:4b4aa47ed296968507b2fde70d2e651129ff3b36

commit r15-5227-g4b4aa47ed296968507b2fde70d2e651129ff3b36
Author: Richard Biener 
Date:   Wed Nov 13 14:43:27 2024 +0100

tree-optimization/117556 - SLP of live stmts from load-lanes

The following fixes SLP live lane generation for load-lanes which
fails to analyze for gcc.dg/vect/vect-live-slp-3.c because the
VLA division doesn't work out but it would also wrongly use the
transposed vector defs I think.  The following properly disables
the actual load-lanes SLP node from live lane processing and instead
relies on the SLP permute node representing the live lane where we
can use extract-last to extract the last lane.  This also fixes
the reported Ada miscompile.

PR tree-optimization/117556
PR tree-optimization/117553
* tree-vect-stmts.cc (vect_analyze_stmt): Do not analyze
the SLP load-lanes node for live lanes, but only the
permute node.
(vect_transform_stmt): Likewise for the transform.

* gcc.dg/vect/vect-live-slp-3.c: Expect us to SLP even for
VLA vectors (in single-lane mode).

Diff:
---
 gcc/testsuite/gcc.dg/vect/vect-live-slp-3.c | 2 +-
 gcc/tree-vect-stmts.cc  | 6 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/vect-live-slp-3.c 
b/gcc/testsuite/gcc.dg/vect/vect-live-slp-3.c
index e37822406751..3caeea71ad7f 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-live-slp-3.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-live-slp-3.c
@@ -73,5 +73,5 @@ main (void)
 }
 
 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" { 
xfail vect_variable_length } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4 "vect" } 
} */
 /* { dg-final { scan-tree-dump-times "vec_stmt_relevant_p: stmt live but not 
relevant" 4 "vect" } } */
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index f77a223b0c4f..2b3dd52a607d 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -13594,6 +13594,7 @@ vect_analyze_stmt (vec_info *vinfo,
   if (!bb_vinfo
   && STMT_VINFO_TYPE (stmt_info) != reduc_vec_info_type
   && STMT_VINFO_TYPE (stmt_info) != lc_phi_info_type
+  && (!node || !node->ldst_lanes || SLP_TREE_CODE (node) == VEC_PERM_EXPR)
   && !can_vectorize_live_stmts (as_a  (vinfo),
stmt_info, node, node_instance,
false, cost_vec))
@@ -13756,7 +13757,10 @@ vect_transform_stmt (vec_info *vinfo,
   if (!slp_node && vec_stmt)
 gcc_assert (STMT_VINFO_VEC_STMTS (stmt_info).exists ());
 
-  if (STMT_VINFO_TYPE (stmt_info) != store_vec_info_type)
+  if (STMT_VINFO_TYPE (stmt_info) != store_vec_info_type
+  && (!slp_node
+ || !slp_node->ldst_lanes
+ || SLP_TREE_CODE (slp_node) == VEC_PERM_EXPR))
 {
   /* Handle stmts whose DEF is used outside the loop-nest that is
 being vectorized.  */

[gcc r15-5229] tree-optimization/117554 - correct single-element interleaving check

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:72df175c93d81d4eea67d889d76fda7381fb6743

commit r15-5229-g72df175c93d81d4eea67d889d76fda7381fb6743
Author: Richard Biener 
Date:   Wed Nov 13 15:05:00 2024 +0100

tree-optimization/117554 - correct single-element interleaving check

In addition to a single DR we also require a single lane, not a splat.

PR tree-optimization/117554
* tree-vect-stmts.cc (get_group_load_store_type): We can
use gather/scatter only for a single-lane single element group
access.

Diff:
---
 gcc/tree-vect-stmts.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 2b3dd52a607d..3147ff247a54 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -2277,6 +2277,7 @@ get_group_load_store_type (vec_info *vinfo, stmt_vec_info 
stmt_info,
   if ((*memory_access_type == VMAT_ELEMENTWISE
|| *memory_access_type == VMAT_STRIDED_SLP)
   && single_element_p
+  && (!slp_node || SLP_TREE_LANES (slp_node) == 1)
   && loop_vinfo
   && vect_use_strided_gather_scatters_p (stmt_info, loop_vinfo,
 masked_p, gs_info))

[gcc r15-5230] Do not consider overrun for VMAT_ELEMENTWISE

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:6d85a0bc2e09221bdb412bc47aefbcd10c546fd5

commit r15-5230-g6d85a0bc2e09221bdb412bc47aefbcd10c546fd5
Author: Richard Biener 
Date:   Wed Nov 13 11:32:13 2024 +0100

Do not consider overrun for VMAT_ELEMENTWISE

When we classify an SLP access as VMAT_ELEMENTWISE we still consider
overrun - the reset of it is later overwritten.  The following fixes
this, resolving a few RISC-V FAILs with --param vect-force-slp=1.

* tree-vect-stmts.cc (get_group_load_store_type): For
VMAT_ELEMENTWISE there's no overrun.

Diff:
---
 gcc/tree-vect-stmts.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 3147ff247a54..5d731205675e 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -2093,7 +2093,6 @@ get_group_load_store_type (vec_info *vinfo, stmt_vec_info 
stmt_info,
  if (SLP_TREE_LANES (slp_node) == 1)
{
  *memory_access_type = VMAT_ELEMENTWISE;
- overrun_p = false;
  if (dump_enabled_p ())
dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
 "single-element interleaving not supported 
"
@@ -2110,7 +2109,8 @@ get_group_load_store_type (vec_info *vinfo, stmt_vec_info 
stmt_info,
}
}
 
- overrun_p = loop_vinfo && gap != 0;
+ overrun_p = (loop_vinfo && gap != 0
+  && *memory_access_type != VMAT_ELEMENTWISE);
  if (overrun_p && vls_type != VLS_LOAD)
{
  dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,

[gcc r15-5231] MATCH: Simplify `a rrotate (32-b) -> a lrotate b` [PR109906]

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:879c1619ab5a708514cbb1f3754e59f30ba29e6c

commit r15-5231-g879c1619ab5a708514cbb1f3754e59f30ba29e6c
Author: Eikansh Gupta 
Date:   Mon Nov 11 17:06:04 2024 +0530

MATCH: Simplify `a rrotate (32-b) -> a lrotate b` [PR109906]

The pattern `a rrotate (32-b)` should be optimized to `a lrotate b`.
The same is also true for `a lrotate (32-b)`. It can be optimized to
`a rrotate b`.

This patch adds following patterns:
a rrotate (32-b) -> a lrotate b
a lrotate (32-b) -> a rrotate b

Bootstrapped and tested on x86_64-linux-gnu with no regressions.

PR tree-optimization/109906

gcc/ChangeLog:

* match.pd (a rrotate (32-b) -> a lrotate b): New pattern
(a lrotate (32-b) -> a rrotate b): New pattern

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/pr109906.c: New test.

Signed-off-by: Eikansh Gupta 

Diff:
---
 gcc/match.pd |  9 +++
 gcc/testsuite/gcc.dg/tree-ssa/pr109906.c | 41 
 2 files changed, 50 insertions(+)

diff --git a/gcc/match.pd b/gcc/match.pd
index 6fa1b59fc971..0ac5674f24be 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -5020,6 +5020,15 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
build_int_cst (TREE_TYPE (@1),
   element_precision (type)), @1); }))
 
+/* a rrotate (32-b) -> a lrotate b */
+/* a lrotate (32-b) -> a rrotate b */
+(for rotate (lrotate rrotate)
+ orotate (rrotate lrotate)
+ (simplify
+  (rotate @0 (minus INTEGER_CST@1 @2))
+   (if (element_precision (TREE_TYPE (@0)) == wi::to_wide (@1))
+ (orotate @0 @2
+
 /* Turn (a OP c1) OP c2 into a OP (c1+c2).  */
 (for op (lrotate rrotate rshift lshift)
  (simplify
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr109906.c 
b/gcc/testsuite/gcc.dg/tree-ssa/pr109906.c
new file mode 100644
index ..9aa015d8c65c
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr109906.c
@@ -0,0 +1,41 @@
+/* PR tree-optimization/109906 */
+/* { dg-do compile } */
+/* { dg-options "-O1 -fdump-tree-optimized-raw" } */
+/* { dg-require-effective-target int32 } */
+
+/* Implementation of rotate right operation */
+static inline
+unsigned rrotate(unsigned x, int t)
+{
+  if (t >= 32) __builtin_unreachable();
+  unsigned tl = x >> (t);
+  unsigned th = x << (32 - t);
+  return tl | th;
+}
+
+/* Here rotate left is achieved by doing rotate right by (32 - x) */
+unsigned rotateleft(unsigned t, int x)
+{
+  return rrotate (t, 32 - x);
+}
+
+/* Implementation of rotate left operation */
+static inline
+unsigned lrotate(unsigned x, int t)
+{
+  if (t >= 32) __builtin_unreachable();
+  unsigned tl = x << (t);
+  unsigned th = x >> (32 - t);
+  return tl | th;
+}
+
+/* Here rotate right is achieved by doing rotate left by (32 - x) */
+unsigned rotateright(unsigned t, int x)
+{
+  return lrotate (t, 32 - x);
+}
+
+/* Shouldn't have instruction for (32 - x). */
+/* { dg-final { scan-tree-dump-not "minus_expr" "optimized" } } */
+/* { dg-final { scan-tree-dump "rrotate_expr" "optimized" } } */
+/* { dg-final { scan-tree-dump "lrotate_expr" "optimized" } } */

[gcc r15-5232] cfgexpand: Skip doing conflicts if there is only 1 variable

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:301dab51be5d8a3c690cd9b0cea462fb11a3ad4b

commit r15-5232-g301dab51be5d8a3c690cd9b0cea462fb11a3ad4b
Author: Andrew Pinski 
Date:   Tue Nov 12 22:13:35 2024 -0800

cfgexpand: Skip doing conflicts if there is only 1 variable

This is a small speed up. If there is only one know stack variable, there
is no reason figure out the scope conflicts as there are none. So don't
go through all the live range calculations just to see there are none.

Bootstrapped and tested on x86_64-linux-gnu with no regressions.

gcc/ChangeLog:

* cfgexpand.cc (add_scope_conflicts): Return right away
if there are only one stack variable.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/cfgexpand.cc | 5 +
 1 file changed, 5 insertions(+)

diff --git a/gcc/cfgexpand.cc b/gcc/cfgexpand.cc
index f3a33ff9a07d..ed890f692e58 100644
--- a/gcc/cfgexpand.cc
+++ b/gcc/cfgexpand.cc
@@ -703,6 +703,11 @@ add_scope_conflicts_1 (basic_block bb, bitmap work, bool 
for_conflict)
 static void
 add_scope_conflicts (void)
 {
+  /* If there is only one variable, there is nothing to be done as
+ there is only possible partition.  */
+  if (stack_vars_num == 1)
+return;
+
   basic_block bb;
   bool changed;
   bitmap work = BITMAP_ALLOC (NULL);

[gcc r15-5237] libstdc++: Add missing parts of LWG 3480 for directory iterators [PR117560]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:eec6e8923586b9a54e37f32cef112d26d86e8f01

commit r15-5237-geec6e8923586b9a54e37f32cef112d26d86e8f01
Author: Jonathan Wakely 
Date:   Thu Nov 14 01:14:44 2024 +

libstdc++: Add missing parts of LWG 3480 for directory iterators [PR117560]

It looks like I only read half the resolution of LWG 3480 and decided we
already supported it. As well as making the non-member overloads of end
take their parameters by value, we need some specializations of the
enable_borrowed_range and enable_view variable templates.

libstdc++-v3/ChangeLog:

PR libstdc++/117560
* include/bits/fs_dir.h (enable_borrowed_range, enable_view):
Define specializations for directory iterators, as per LWG 3480.
* testsuite/27_io/filesystem/iterators/lwg3480.cc: New test.

Diff:
---
 libstdc++-v3/include/bits/fs_dir.h | 22 ++
 .../27_io/filesystem/iterators/lwg3480.cc  | 16 
 2 files changed, 38 insertions(+)

diff --git a/libstdc++-v3/include/bits/fs_dir.h 
b/libstdc++-v3/include/bits/fs_dir.h
index d669f2a74681..79dc6764b7b2 100644
--- a/libstdc++-v3/include/bits/fs_dir.h
+++ b/libstdc++-v3/include/bits/fs_dir.h
@@ -39,6 +39,7 @@
 #if __cplusplus >= 202002L
 # include // std::strong_ordering
 # include// std::default_sentinel_t
+# include  // enable_view, enable_borrowed_range
 #endif
 
 namespace std _GLIBCXX_VISIBILITY(default)
@@ -626,6 +627,27 @@ _GLIBCXX_END_NAMESPACE_CXX11
   extern template class
 __shared_ptr;
 
+#if __glibcxx_ranges // >= C++20
+// _GLIBCXX_RESOLVE_LIB_DEFECTS
+// 3480. directory_iterator and recursive_directory_iterator are not ranges
+namespace ranges
+{
+  template<>
+inline constexpr bool
+enable_borrowed_range = true;
+  template<>
+inline constexpr bool
+enable_borrowed_range = true;
+
+  template<>
+inline constexpr bool
+enable_view = true;
+  template<>
+inline constexpr bool
+enable_view = true;
+} // namespace ranges
+#endif // ranges
+
 _GLIBCXX_END_NAMESPACE_VERSION
 } // namespace std
 
diff --git a/libstdc++-v3/testsuite/27_io/filesystem/iterators/lwg3480.cc 
b/libstdc++-v3/testsuite/27_io/filesystem/iterators/lwg3480.cc
new file mode 100644
index ..15e0286fff6f
--- /dev/null
+++ b/libstdc++-v3/testsuite/27_io/filesystem/iterators/lwg3480.cc
@@ -0,0 +1,16 @@
+// { dg-do compile { target c++20 } }
+// { dg-require-filesystem-ts "" }
+
+// LWG 3480
+// directory_iterator and recursive_directory_iterator are not C++20 ranges
+
+#include 
+
+namespace fs = std::filesystem;
+namespace rg = std::ranges;
+
+static_assert( rg::borrowed_range );
+static_assert( rg::borrowed_range );
+
+static_assert( rg::view );
+static_assert( rg::view );

[gcc r15-5228] tree-optimization/117559 - avoid hybrid SLP for masked load/store lanes

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:ba192895d17c4fc4676444fe1bd4a593d20e6def

commit r15-5228-gba192895d17c4fc4676444fe1bd4a593d20e6def
Author: Richard Biener 
Date:   Wed Nov 13 13:56:13 2024 +0100

tree-optimization/117559 - avoid hybrid SLP for masked load/store lanes

Hybrid analysis is confused by the mask_conversion pattern making a
uniform mask non-uniform.  As load/store lanes only uses a single
lane to mask all data lanes the SLP graph doesn't cover the alternate
(redundant) mask lanes and thus their pattern defs.  The following adds
a hack to mark them covered.

Fixes gcc.target/aarch64/sve/mask_struct_store_?.c with forced SLP.

PR tree-optimization/117559
* tree-vect-slp.cc (vect_mark_slp_stmts): Pass in vinfo,
mark all mask defs of a load/store-lane .MASK_LOAD/STORE
as pure.
(vect_make_slp_decision): Adjust.
(vect_slp_analyze_bb_1): Likewise.

Diff:
---
 gcc/tree-vect-slp.cc | 37 ++---
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index d69fdc04b9df..97ea77214a98 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -3200,7 +3200,8 @@ debug (slp_instance instance)
 /* Mark the tree rooted at NODE with PURE_SLP.  */
 
 static void
-vect_mark_slp_stmts (slp_tree node, hash_set &visited)
+vect_mark_slp_stmts (vec_info *vinfo, slp_tree node,
+hash_set &visited)
 {
   int i;
   stmt_vec_info stmt_info;
@@ -3214,18 +3215,40 @@ vect_mark_slp_stmts (slp_tree node, hash_set 
&visited)
 
   FOR_EACH_VEC_ELT (SLP_TREE_SCALAR_STMTS (node), i, stmt_info)
 if (stmt_info)
-  STMT_SLP_TYPE (stmt_info) = pure_slp;
+  {
+   STMT_SLP_TYPE (stmt_info) = pure_slp;
+   /* ???  For .MASK_LOAD and .MASK_STORE detected as load/store-lanes
+  when there is the mask_conversion pattern applied we have lost the
+  alternate lanes of the uniform mask which nevertheless
+  have separate pattern defs.  To not confuse hybrid
+  analysis we mark those as covered as well here.  */
+   if (node->ldst_lanes)
+ if (gcall *call = dyn_cast  (stmt_info->stmt))
+   if (gimple_call_internal_p (call, IFN_MASK_LOAD)
+   || gimple_call_internal_p (call, IFN_MASK_STORE))
+ {
+   tree mask = gimple_call_arg (call,
+internal_fn_mask_index
+(gimple_call_internal_fn (call)));
+   if (TREE_CODE (mask) == SSA_NAME)
+ if (stmt_vec_info mask_info = vinfo->lookup_def (mask))
+   {
+ mask_info = vect_stmt_to_vectorize (mask_info);
+ STMT_SLP_TYPE (mask_info) = pure_slp;
+   }
+ }
+  }
 
   FOR_EACH_VEC_ELT (SLP_TREE_CHILDREN (node), i, child)
 if (child)
-  vect_mark_slp_stmts (child, visited);
+  vect_mark_slp_stmts (vinfo, child, visited);
 }
 
 static void
-vect_mark_slp_stmts (slp_tree node)
+vect_mark_slp_stmts (vec_info *vinfo, slp_tree node)
 {
   hash_set visited;
-  vect_mark_slp_stmts (node, visited);
+  vect_mark_slp_stmts (vinfo, node, visited);
 }
 
 /* Mark the statements of the tree rooted at NODE as relevant (vect_used).  */
@@ -7407,7 +7430,7 @@ vect_make_slp_decision (loop_vec_info loop_vinfo)
   /* Mark all the stmts that belong to INSTANCE as PURE_SLP stmts.  Later 
we
 call vect_detect_hybrid_slp () to find stmts that need hybrid SLP and
 loop-based vectorization.  Such stmts will be marked as HYBRID.  */
-  vect_mark_slp_stmts (SLP_INSTANCE_TREE (instance));
+  vect_mark_slp_stmts (loop_vinfo, SLP_INSTANCE_TREE (instance));
   decided_to_slp++;
 }
 
@@ -9341,7 +9364,7 @@ vect_slp_analyze_bb_1 (bb_vec_info bb_vinfo, int n_stmts, 
bool &fatal,
 
   /* Mark all the statements that we want to vectorize as pure SLP and
 relevant.  */
-  vect_mark_slp_stmts (SLP_INSTANCE_TREE (instance));
+  vect_mark_slp_stmts (bb_vinfo, SLP_INSTANCE_TREE (instance));
   vect_mark_slp_stmts_relevant (SLP_INSTANCE_TREE (instance));
   unsigned j;
   stmt_vec_info root;

[gcc r15-5234] tree-optimization/117567 - make SLP reassoc resilent against NULL lanes

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:f56343c5ea9a11fa740e0330ec121b826e349879

commit r15-5234-gf56343c5ea9a11fa740e0330ec121b826e349879
Author: Richard Biener 
Date:   Thu Nov 14 10:17:23 2024 +0100

tree-optimization/117567 - make SLP reassoc resilent against NULL lanes

The following tries to make the SLP chain association code resilent
against not present lanes (the other option would have been to disable
it in this case).  Not present lanes can now more widely appear as
part of mask load SLP discovery when there is gaps involved.  Requiring
a present first lane shouldn't be a restriction since in unpermuted
state all DR groups have their first lane not a gap.

PR tree-optimization/117567
* tree-vect-slp.cc (vect_build_slp_tree_2): Handle not present
lanes when doing re-association.

* gcc.dg/torture/pr117567.c: New testcase.

Diff:
---
 gcc/testsuite/gcc.dg/torture/pr117567.c | 17 ++
 gcc/tree-vect-slp.cc| 55 -
 2 files changed, 57 insertions(+), 15 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/torture/pr117567.c 
b/gcc/testsuite/gcc.dg/torture/pr117567.c
new file mode 100644
index ..e9630a524c48
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr117567.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target int32plus } */
+/* { dg-additional-options "-fwrapv" } */
+
+extern signed char a[];
+long b;
+signed char *c;
+short *d;
+int main() {
+  for (int e = -63; e < 9; e += -4294967292) {
+int f_init = (b ? (8959267630 + c[e]) % 1365941252 : 0);
+for (int f = f_init; f < 9; f += 10) {
+  int h = d[e + 1];
+  a[e] = d[e - 2] ?: h;
+}
+  }
+}
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 97ea77214a98..440ecd72bb44 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -2217,6 +2217,17 @@ vect_build_slp_tree_2 (vec_info *vinfo, slp_tree node,
   bool hard_fail = true;
   for (unsigned lane = 0; lane < group_size; ++lane)
{
+ if (!stmts[lane])
+   {
+ /* ???  Below we require lane zero is present.  */
+ if (lane == 0)
+   {
+ hard_fail = false;
+ break;
+   }
+ chains.quick_push (vNULL);
+ continue;
+   }
  /* For each lane linearize the addition/subtraction (or other
 uniform associatable operation) expression tree.  */
  gimple *op_stmt = NULL, *other_op_stmt = NULL;
@@ -2270,10 +2281,13 @@ vect_build_slp_tree_2 (vec_info *vinfo, slp_tree node,
   get_tree_code_name (code));
  for (unsigned lane = 0; lane < group_size; ++lane)
{
- for (unsigned opnum = 0; opnum < chain_len; ++opnum)
-   dump_printf (MSG_NOTE, "%s %T ",
-get_tree_code_name (chains[lane][opnum].code),
-chains[lane][opnum].op);
+ if (!stmts[lane])
+   dump_printf (MSG_NOTE, "--");
+ else
+   for (unsigned opnum = 0; opnum < chain_len; ++opnum)
+ dump_printf (MSG_NOTE, "%s %T ",
+  get_tree_code_name 
(chains[lane][opnum].code),
+  chains[lane][opnum].op);
  dump_printf (MSG_NOTE, "\n");
}
}
@@ -2283,7 +2297,7 @@ vect_build_slp_tree_2 (vec_info *vinfo, slp_tree node,
  vect_def_type dt = chains[0][n].dt;
  unsigned lane;
  for (lane = 0; lane < group_size; ++lane)
-   if (chains[lane][n].dt != dt)
+   if (stmts[lane] && chains[lane][n].dt != dt)
  {
if (dt == vect_constant_def
&& chains[lane][n].dt == vect_external_def)
@@ -2322,7 +2336,10 @@ vect_build_slp_tree_2 (vec_info *vinfo, slp_tree node,
  vec ops;
  ops.create (group_size);
  for (lane = 0; lane < group_size; ++lane)
-   ops.quick_push (chains[lane][n].op);
+   if (stmts[lane])
+ ops.quick_push (chains[lane][n].op);
+   else
+ ops.quick_push (NULL_TREE);
  slp_tree child = vect_create_new_slp_node (ops);
  SLP_TREE_DEF_TYPE (child) = dt;
  children.safe_push (child);
@@ -2352,8 +2369,11 @@ vect_build_slp_tree_2 (vec_info *vinfo, slp_tree node,
{
  op_stmts.truncate (0);
  for (lane = 0; lane < group_size; ++lane)
-   op_stmts.quick_push
- (vinfo->lookup_def (chains[lane][n].op));
+   if (stmts[lane])
+ op_stmts.quick_pus

[gcc r15-5235] Remove last comparison-code expand_vec_cond_expr_p call from vectorizer

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:86708a88fb53518f1a54105c1fd006b57f14e7ce

commit r15-5235-g86708a88fb53518f1a54105c1fd006b57f14e7ce
Author: Richard Biener 
Date:   Tue Nov 12 13:55:14 2024 +0100

Remove last comparison-code expand_vec_cond_expr_p call from vectorizer

The following refactors the check with the last remaininig
expand_vec_cond_expr_p call with a comparison code to make it
obvious we are not relying on those anymore.

* tree-vect-stmts.cc (vectorizable_condition): Refactor
target support check.

Diff:
---
 gcc/tree-vect-stmts.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 5d731205675e..a83a46ea0dd9 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -12460,9 +12460,9 @@ vectorizable_condition (vec_info *vinfo,
   if (reduction_type == EXTRACT_LAST_REDUCTION)
/* Count one reduction-like operation per vector.  */
kind = vec_to_scalar;
-  else if (!expand_vec_cond_expr_p (vectype, comp_vectype, cond_code)
-  && (masked
-  || (!expand_vec_cmp_expr_p (comp_vectype, vec_cmp_type,
+  else if ((masked && !expand_vec_cond_expr_p (vectype, comp_vectype))
+  || (!masked
+  && (!expand_vec_cmp_expr_p (comp_vectype, vec_cmp_type,
   cond_code)
   || !expand_vec_cond_expr_p (vectype, vec_cmp_type
return false;

[gcc r15-5226] RISC-V: Rearrange the test files for scalar SAT_ADD [NFC]

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:735f5260fb42919a651ed8e381c9e1a11e753345

commit r15-5226-g735f5260fb42919a651ed8e381c9e1a11e753345
Author: Pan Li 
Date:   Thu Nov 14 14:16:15 2024 +0800

RISC-V: Rearrange the test files for scalar SAT_ADD [NFC]

The test files of scalar SAT_ADD only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}.  For example,
test form 3 for uint32_t SAT_ADD will have -3-u32.c for asm check and
-run-3-u32.c for the run test.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_s_add-2.c: Move to...
* gcc.target/riscv/sat_s_add-1-i16.c: ...here.
* gcc.target/riscv/sat_s_add-3.c: Move to...
* gcc.target/riscv/sat_s_add-1-i32.c: ...here.
* gcc.target/riscv/sat_s_add-4.c: Move to...
* gcc.target/riscv/sat_s_add-1-i64.c: ...here.
* gcc.target/riscv/sat_s_add-1.c: Move to...
* gcc.target/riscv/sat_s_add-1-i8.c: ...here.
* gcc.target/riscv/sat_s_add-6.c: Move to...
* gcc.target/riscv/sat_s_add-2-i16.c: ...here.
* gcc.target/riscv/sat_s_add-7.c: Move to...
* gcc.target/riscv/sat_s_add-2-i32.c: ...here.
* gcc.target/riscv/sat_s_add-8.c: Move to...
* gcc.target/riscv/sat_s_add-2-i64.c: ...here.
* gcc.target/riscv/sat_s_add-5.c: Move to...
* gcc.target/riscv/sat_s_add-2-i8.c: ...here.
* gcc.target/riscv/sat_s_add-10.c: Move to...
* gcc.target/riscv/sat_s_add-3-i16.c: ...here.
* gcc.target/riscv/sat_s_add-11.c: Move to...
* gcc.target/riscv/sat_s_add-3-i32.c: ...here.
* gcc.target/riscv/sat_s_add-12.c: Move to...
* gcc.target/riscv/sat_s_add-3-i64.c: ...here.
* gcc.target/riscv/sat_s_add-9.c: Move to...
* gcc.target/riscv/sat_s_add-3-i8.c: ...here.
* gcc.target/riscv/sat_s_add-14.c: Move to...
* gcc.target/riscv/sat_s_add-4-i16.c: ...here.
* gcc.target/riscv/sat_s_add-15.c: Move to...
* gcc.target/riscv/sat_s_add-4-i32.c: ...here.
* gcc.target/riscv/sat_s_add-16.c: Move to...
* gcc.target/riscv/sat_s_add-4-i64.c: ...here.
* gcc.target/riscv/sat_s_add-13.c: Move to...
* gcc.target/riscv/sat_s_add-4-i8.c: ...here.
* gcc.target/riscv/sat_s_add-run-2.c: Move to...
* gcc.target/riscv/sat_s_add-run-1-i16.c: ...here.
* gcc.target/riscv/sat_s_add-run-3.c: Move to...
* gcc.target/riscv/sat_s_add-run-1-i32.c: ...here.
* gcc.target/riscv/sat_s_add-run-4.c: Move to...
* gcc.target/riscv/sat_s_add-run-1-i64.c: ...here.
* gcc.target/riscv/sat_s_add-run-1.c: Move to...
* gcc.target/riscv/sat_s_add-run-1-i8.c: ...here.
* gcc.target/riscv/sat_s_add-run-6.c: Move to...
* gcc.target/riscv/sat_s_add-run-2-i16.c: ...here.
* gcc.target/riscv/sat_s_add-run-7.c: Move to...
* gcc.target/riscv/sat_s_add-run-2-i32.c: ...here.
* gcc.target/riscv/sat_s_add-run-8.c: Move to...
* gcc.target/riscv/sat_s_add-run-2-i64.c: ...here.
* gcc.target/riscv/sat_s_add-run-5.c: Move to...
* gcc.target/riscv/sat_s_add-run-2-i8.c: ...here.
* gcc.target/riscv/sat_s_add-run-10.c: Move to...
* gcc.target/riscv/sat_s_add-run-3-i16.c: ...here.
* gcc.target/riscv/sat_s_add-run-11.c: Move to...
* gcc.target/riscv/sat_s_add-run-3-i32.c: ...here.
* gcc.target/riscv/sat_s_add-run-12.c: Move to...
* gcc.target/riscv/sat_s_add-run-3-i64.c: ...here.
* gcc.target/riscv/sat_s_add-run-9.c: Move to...
* gcc.target/riscv/sat_s_add-run-3-i8.c: ...here.
* gcc.target/riscv/sat_s_add-run-14.c: Move to...
* gcc.target/riscv/sat_s_add-run-4-i16.c: ...here.
* gcc.target/riscv/sat_s_add-run-15.c: Move to...
* gcc.target/riscv/sat_s_add-run-4-i32.c: ...here.
* gcc.target/riscv/sat_s_add-run-16.c: Move to...
* gcc.target/riscv/sat_s_add-run-4-i64.c: ...here.
* gcc.target/riscv/sat_s_add-run-13.c: Move to...
* gcc.target/riscv/sat_s_add-run-4-i8.c: ...here.
* gcc.target/riscv/sat_u_add-2.c: Move to...
* gcc.target/riscv/sat_u_add-1-u16.c: ...here.
* gcc.target/riscv/sat_u_add-3.c: Move to...
* gcc.target/riscv/sat_u_add-1-u32.c: ...here.
* gcc.target/riscv/sat_u_add-4.c: Move to...
* gcc.target/riscv/sat_u_add-1-u64.c: ...here.
* gcc.target/riscv/sat_u_add-1.c: Move to...
* gcc.target/riscv/sat_u_add-1-u8.c: ...here.
* gcc.target/riscv/sat_u_add-6.c: Move to.

[gcc r15-5233] libgcc: Fix COPY_ARG_VAL initializer (PR 117537)

[Christophe Lyon via Gcc-cvs]

https://gcc.gnu.org/g:13a966d56fe60418cf88c11cbd45797f1cbfed5f

commit r15-5233-g13a966d56fe60418cf88c11cbd45797f1cbfed5f
Author: Christophe Lyon 
Date:   Wed Nov 13 21:20:13 2024 +

libgcc: Fix COPY_ARG_VAL initializer (PR 117537)

We recently forced -Werror when building libgcc for aarch64, to make
sure we'd catch and fix the kind of problem described in the PR.

In this case, when building for aarch64_be (so, big endian), gcc emits
this warning/error:
libgcc/config/libbid/bid_conf.h:847:25: error: missing braces around 
initializer [-Werror=missing-braces]
  847 |UINT128 arg_name={ bid_##arg_name.w[1], bid_##arg_name.w[0]};
libgcc/config/libbid/bid_conf.h:871:8: note: in expansion of macro 
'COPY_ARG_VAL'
  871 |COPY_ARG_VAL(arg_name)

This patch fixes the problem by adding curly braces around the
initializer for COPY_ARG_VAL in the big endian case.

It seems that COPY_ARG_REF (just above COPY_ARG_VAL) has a similar
issue, but DECIMAL_CALL_BY_REFERENCE seems always defined to 0, so
COPY_ARG_REF is never used.  The patch fixes it too, though.

libgcc/config/libbid/ChangeLog:

PR libgcc/117537
* bid_conf.h (COPY_ARG_REF): Fix initializer.
(COPY_ARG_VAL): Likewise.

Diff:
---
 libgcc/config/libbid/bid_conf.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/libgcc/config/libbid/bid_conf.h b/libgcc/config/libbid/bid_conf.h
index 587713d92214..1c12c1bd830f 100644
--- a/libgcc/config/libbid/bid_conf.h
+++ b/libgcc/config/libbid/bid_conf.h
@@ -842,9 +842,9 @@ extern BID_THREAD _IDEC_excepthandling 
_IDEC_glbexcepthandling;
 
 #if BID_BIG_ENDIAN
 #define COPY_ARG_REF(arg_name) \
-   UINT128 arg_name={ pbid_##arg_name->w[1], pbid_##arg_name->w[0]};
+   UINT128 arg_name={ { pbid_##arg_name->w[1], pbid_##arg_name->w[0] }};
 #define COPY_ARG_VAL(arg_name) \
-   UINT128 arg_name={ bid_##arg_name.w[1], bid_##arg_name.w[0]};
+   UINT128 arg_name={ { bid_##arg_name.w[1], bid_##arg_name.w[0] }};
 #else
 #define COPY_ARG_REF(arg_name) \
UINT128 arg_name=*pbid_##arg_name;

[gcc r15-5236] Avoid expand_vec_cond_expr_p with comparison code

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:9ede072ffafcde27d0e9fe76bb7ffacb4f48a2d6

commit r15-5236-g9ede072ffafcde27d0e9fe76bb7ffacb4f48a2d6
Author: Richard Biener 
Date:   Tue Nov 12 14:45:02 2024 +0100

Avoid expand_vec_cond_expr_p with comparison code

This removes the obsolete API use by vector divmod lowering.

* tree-vect-generic.cc (expand_vector_divmod): Query vector
comparison and vec_cond_mask capability.

Diff:
---
 gcc/tree-vect-generic.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/tree-vect-generic.cc b/gcc/tree-vect-generic.cc
index 21d906e9c559..72f251f09620 100644
--- a/gcc/tree-vect-generic.cc
+++ b/gcc/tree-vect-generic.cc
@@ -765,8 +765,10 @@ expand_vector_divmod (gimple_stmt_iterator *gsi, tree 
type, tree op0,
  type, cur_op);
}
}
+ tree mask_type = truth_type_for (type);
  if (addend == NULL_TREE
- && expand_vec_cond_expr_p (type, type, LT_EXPR))
+ && expand_vec_cmp_expr_p (type, mask_type, LT_EXPR)
+ && expand_vec_cond_expr_p (type, mask_type))
{
  tree zero, cst, mask_type, mask;
  gimple *stmt, *cond;