[PATCH] stagin: clocking-wizard: Handle invalid clk in notifier
Even though it should never happen, handle the case that the clock
notifier is called with an unexpected clock handle. This avoids the
compiler warning:
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c: In function
'clk_wzrd_clk_notifier':
>> drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c:99:6: warning: 'max'
>> may be used uninitialized in this function [-Wmaybe-uninitialized]
if (ndata->new_rate > max)
^
Reported-by: kbuild test robot
Signed-off-by: Soren Brinkmann
---
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
index 471d0877f382..048247fa9e34 100644
--- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
+++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
@@ -91,8 +91,10 @@ static int clk_wzrd_clk_notifier(struct notifier_block *nb,
unsigned long event,
if (ndata->clk == clk_wzrd->clk_in1)
max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1];
- if (ndata->clk == clk_wzrd->axi_clk)
+ else if (ndata->clk == clk_wzrd->axi_clk)
max = WZRD_ACLK_MAX_FREQ;
+ else
+ return NOTIFY_DONE; /* should never happen */
switch (event) {
case PRE_RATE_CHANGE:
--
2.2.1.1.gb42cc81
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH] staging: Add Xilinx Clocking Wizard driver
Add a driver for the Xilinx Clocking Wizard soft IP. The clocking wizard
provides an AXI interface to dynamically reconfigure the clocking
resources of Xilinx FPGAs.
Signed-off-by: Soren Brinkmann
---
drivers/staging/Kconfig| 2 +
drivers/staging/Makefile | 1 +
drivers/staging/clocking-wizard/Kconfig| 9 +
drivers/staging/clocking-wizard/Makefile | 1 +
drivers/staging/clocking-wizard/TODO | 12 +
.../clocking-wizard/clk-xlnx-clock-wizard.c| 304 +
drivers/staging/clocking-wizard/dt-binding.txt | 30 ++
7 files changed, 359 insertions(+)
create mode 100644 drivers/staging/clocking-wizard/Kconfig
create mode 100644 drivers/staging/clocking-wizard/Makefile
create mode 100644 drivers/staging/clocking-wizard/TODO
create mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
create mode 100644 drivers/staging/clocking-wizard/dt-binding.txt
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 35b494f5667f..7daf345bec0e 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -118,4 +118,6 @@ source "drivers/staging/skein/Kconfig"
source "drivers/staging/unisys/Kconfig"
+source "drivers/staging/clocking-wizard/Kconfig"
+
endif # STAGING
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index e66a5dbd9b02..03fec7f981cc 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/
obj-$(CONFIG_BT_NOKIA_H4P) += nokia_h4p/
obj-$(CONFIG_CRYPTO_SKEIN) += skein/
obj-$(CONFIG_UNISYSSPAR) += unisys/
+obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/
diff --git a/drivers/staging/clocking-wizard/Kconfig
b/drivers/staging/clocking-wizard/Kconfig
new file mode 100644
index ..3243c92f6e6d
--- /dev/null
+++ b/drivers/staging/clocking-wizard/Kconfig
@@ -0,0 +1,9 @@
+#
+# Xilinx Clocking Wizard Driver
+#
+
+config COMMON_CLK_XLNX_CLKWZRD
+ bool "Xilinx Clocking Wizard"
+ depends on COMMON_CLK && OF
+ ---help---
+ Support for the Xilinx Clocking Wizard IP core clock generator.
diff --git a/drivers/staging/clocking-wizard/Makefile
b/drivers/staging/clocking-wizard/Makefile
new file mode 100644
index ..5ad352f521fe
--- /dev/null
+++ b/drivers/staging/clocking-wizard/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
diff --git a/drivers/staging/clocking-wizard/TODO
b/drivers/staging/clocking-wizard/TODO
new file mode 100644
index ..ebe99db7d153
--- /dev/null
+++ b/drivers/staging/clocking-wizard/TODO
@@ -0,0 +1,12 @@
+TODO:
+ - support for fractional multiplier
+ - support for fractional divider (output 0 only)
+ - support for set_rate() operations (may benefit from Stephen Boyd's
+ refactoring of the clk primitives: https://lkml.org/lkml/2014/9/5/766)
+ - review arithmetic
+ - overflow after multiplication?
+ - maximize accuracy before divisions
+
+Patches to:
+ Greg Kroah-Hartman
+ Sören Brinkmann
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
new file mode 100644
index ..ad126e1c43c1
--- /dev/null
+++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
@@ -0,0 +1,304 @@
+/*
+ * Xilinx 'Clocking Wizard' driver
+ *
+ * Copyright (C) 2013 - 2014 Xilinx
+ *
+ * Sören Brinkmann
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define WZRD_NUM_OUTPUTS 7
+#define WZRD_ACLK_MAX_FREQ 25000UL
+
+#define WZRD_CLK_CFG_REG(n)(0x200 + 4 * n)
+
+#define WZRD_CLkOUT0_FRAC_EN BIT(18)
+#define WZRD_CLkFBOUT_FRAC_EN BIT(26)
+
+#define WZRD_CLKFBOUT_MULT_SHIFT 8
+#define WZRD_CLKFBOUT_MULT_MASK(0xff <<
WZRD_CLKFBOUT_MULT_SHIFT)
+#define WZRD_DIVCLK_DIVIDE_SHIFT 0
+#define WZRD_DIVCLK_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
+#define WZRD_CLKOUT_DIVIDE_SHIFT 0
+#define WZRD_CLKOUT_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
+
+enum clk_wzrd_inp_clks {
+ wzrd_clk_in1,
+ wzrd_s_
[PATCH v2] staging: Add Xilinx Clocking Wizard driver
Add a driver for the Xilinx Clocking Wizard soft IP. The clocking wizard provides an AXI interface to dynamically reconfigure the clocking resources of Xilinx FPGAs. Signed-off-by: Soren Brinkmann --- Hi Greg, Dan, I fixed the things Dan pointed out, please take this v2 instead of the original patch. Also, don't get caught up too much with style issues around the code that registers the clocks. To support set_rate() opeartions this will have to change anyway. It doesn't make a lot of sense to spend much time on those parts. Thanks, Sören v2: - implement dev_pm_ops - don't use array for clock inputs - add more information in error output - fix style issues - fix error path --- drivers/staging/Kconfig| 2 + drivers/staging/Makefile | 1 + drivers/staging/clocking-wizard/Kconfig| 9 + drivers/staging/clocking-wizard/Makefile | 1 + drivers/staging/clocking-wizard/TODO | 12 + .../clocking-wizard/clk-xlnx-clock-wizard.c| 336 + drivers/staging/clocking-wizard/dt-binding.txt | 30 ++ 7 files changed, 391 insertions(+) create mode 100644 drivers/staging/clocking-wizard/Kconfig create mode 100644 drivers/staging/clocking-wizard/Makefile create mode 100644 drivers/staging/clocking-wizard/TODO create mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c create mode 100644 drivers/staging/clocking-wizard/dt-binding.txt diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 35b494f5667f..7daf345bec0e 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -118,4 +118,6 @@ source "drivers/staging/skein/Kconfig" source "drivers/staging/unisys/Kconfig" +source "drivers/staging/clocking-wizard/Kconfig" + endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index e66a5dbd9b02..03fec7f981cc 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/ obj-$(CONFIG_BT_NOKIA_H4P) += nokia_h4p/ obj-$(CONFIG_CRYPTO_SKEIN) += skein/ obj-$(CONFIG_UNISYSSPAR) += unisys/ +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/ diff --git a/drivers/staging/clocking-wizard/Kconfig b/drivers/staging/clocking-wizard/Kconfig new file mode 100644 index ..3243c92f6e6d --- /dev/null +++ b/drivers/staging/clocking-wizard/Kconfig @@ -0,0 +1,9 @@ +# +# Xilinx Clocking Wizard Driver +# + +config COMMON_CLK_XLNX_CLKWZRD + bool "Xilinx Clocking Wizard" + depends on COMMON_CLK && OF + ---help--- + Support for the Xilinx Clocking Wizard IP core clock generator. diff --git a/drivers/staging/clocking-wizard/Makefile b/drivers/staging/clocking-wizard/Makefile new file mode 100644 index ..5ad352f521fe --- /dev/null +++ b/drivers/staging/clocking-wizard/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o diff --git a/drivers/staging/clocking-wizard/TODO b/drivers/staging/clocking-wizard/TODO new file mode 100644 index ..ebe99db7d153 --- /dev/null +++ b/drivers/staging/clocking-wizard/TODO @@ -0,0 +1,12 @@ +TODO: + - support for fractional multiplier + - support for fractional divider (output 0 only) + - support for set_rate() operations (may benefit from Stephen Boyd's + refactoring of the clk primitives: https://lkml.org/lkml/2014/9/5/766) + - review arithmetic + - overflow after multiplication? + - maximize accuracy before divisions + +Patches to: + Greg Kroah-Hartman + Sören Brinkmann diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c new file mode 100644 index ..d807058b6f9f --- /dev/null +++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c @@ -0,0 +1,336 @@ +/* + * Xilinx 'Clocking Wizard' driver + * + * Copyright (C) 2013 - 2014 Xilinx + * + * Sören Brinkmann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define WZRD_NUM_OUTPUTS 7 +#define WZRD_ACLK_MAX_FREQ 25000UL + +#define WZRD_CLK_CFG_REG(n)(0x200 + 4 * n) + +#defi
[PATCH v3] staging: Add Xilinx Clocking Wizard driver
Add a driver for the Xilinx Clocking Wizard soft IP. The clocking wizard provides an AXI interface to dynamically reconfigure the clocking resources of Xilinx FPGAs. Signed-off-by: Soren Brinkmann --- v3: - allow building the driver as module - make speed grade positive - document valid values for speed-grade DT property v2: - implement dev_pm_ops - don't use array for clock inputs - add more information in error output - fix style issues - fix error path --- drivers/staging/Kconfig| 2 + drivers/staging/Makefile | 1 + drivers/staging/clocking-wizard/Kconfig| 9 + drivers/staging/clocking-wizard/Makefile | 1 + drivers/staging/clocking-wizard/TODO | 12 + .../clocking-wizard/clk-xlnx-clock-wizard.c| 335 + drivers/staging/clocking-wizard/dt-binding.txt | 30 ++ 7 files changed, 390 insertions(+) create mode 100644 drivers/staging/clocking-wizard/Kconfig create mode 100644 drivers/staging/clocking-wizard/Makefile create mode 100644 drivers/staging/clocking-wizard/TODO create mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c create mode 100644 drivers/staging/clocking-wizard/dt-binding.txt diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 35b494f5667f..7daf345bec0e 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -118,4 +118,6 @@ source "drivers/staging/skein/Kconfig" source "drivers/staging/unisys/Kconfig" +source "drivers/staging/clocking-wizard/Kconfig" + endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index e66a5dbd9b02..03fec7f981cc 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/ obj-$(CONFIG_BT_NOKIA_H4P) += nokia_h4p/ obj-$(CONFIG_CRYPTO_SKEIN) += skein/ obj-$(CONFIG_UNISYSSPAR) += unisys/ +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/ diff --git a/drivers/staging/clocking-wizard/Kconfig b/drivers/staging/clocking-wizard/Kconfig new file mode 100644 index ..357af02c562c --- /dev/null +++ b/drivers/staging/clocking-wizard/Kconfig @@ -0,0 +1,9 @@ +# +# Xilinx Clocking Wizard Driver +# + +config COMMON_CLK_XLNX_CLKWZRD + tristate "Xilinx Clocking Wizard" + depends on COMMON_CLK && OF + ---help--- + Support for the Xilinx Clocking Wizard IP core clock generator. diff --git a/drivers/staging/clocking-wizard/Makefile b/drivers/staging/clocking-wizard/Makefile new file mode 100644 index ..5ad352f521fe --- /dev/null +++ b/drivers/staging/clocking-wizard/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o diff --git a/drivers/staging/clocking-wizard/TODO b/drivers/staging/clocking-wizard/TODO new file mode 100644 index ..ebe99db7d153 --- /dev/null +++ b/drivers/staging/clocking-wizard/TODO @@ -0,0 +1,12 @@ +TODO: + - support for fractional multiplier + - support for fractional divider (output 0 only) + - support for set_rate() operations (may benefit from Stephen Boyd's + refactoring of the clk primitives: https://lkml.org/lkml/2014/9/5/766) + - review arithmetic + - overflow after multiplication? + - maximize accuracy before divisions + +Patches to: + Greg Kroah-Hartman + Sören Brinkmann diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c new file mode 100644 index ..b8d89525bffd --- /dev/null +++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c @@ -0,0 +1,335 @@ +/* + * Xilinx 'Clocking Wizard' driver + * + * Copyright (C) 2013 - 2014 Xilinx + * + * Sören Brinkmann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define WZRD_NUM_OUTPUTS 7 +#define WZRD_ACLK_MAX_FREQ 25000UL + +#define WZRD_CLK_CFG_REG(n)(0x200 + 4 * n) + +#define WZRD_CLkOUT0_FRAC_EN BIT(18) +#define WZRD_CLkFBOUT_FRAC_EN BIT(26) + +#define WZRD_CLKFBOUT_MULT_SHIFT 8 +#define WZRD_CLKFBOUT_MULT_MASK(0xff << WZRD_CLKFBOUT_MULT_SHIFT) +#define WZRD_DIVCLK_DIVIDE_SHIFT 0 +#define WZR
[PATCH] staging: clocking-wizard: Contain macro argument in parenthesis
A macro doing some arithmetic to calculate a register offset, did not contain an argument to the macro in parentheses, potentially leading to unexpected results when using that macro with arithmetic expressions as argument. Signed-off-by: Soren Brinkmann --- drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c index b8d89525bffd..7202d8e889aa 100644 --- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c +++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c @@ -29,7 +29,7 @@ #define WZRD_NUM_OUTPUTS 7 #define WZRD_ACLK_MAX_FREQ 25000UL -#define WZRD_CLK_CFG_REG(n)(0x200 + 4 * n) +#define WZRD_CLK_CFG_REG(n)(0x200 + 4 * (n)) #define WZRD_CLkOUT0_FRAC_EN BIT(18) #define WZRD_CLkFBOUT_FRAC_EN BIT(26) -- 2.1.2.1.g5e69ed6 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
