[PATCH v3 0/2] Add support for nuvoton ma35 nand controller
This patch series adds the mtd nand driver for the nuvoton ma35 ARMv8 SoC. It includes DT binding documentation and the ma35 mtd nand driver. v3: - Update ma35d1 mtd nand driver - Release IRQ handler. - Remove unused functions. - Remove '.owner'. v2: - Update nuvoton,ma35d1-nand.yaml - Adjust the order and remove any unnecessary items. - Add 'nand-ecc-step-size' and 'nand-ecc-strength' to the required list. - Update ma35d1 mtd nand driver - Fix coding style. - Use 'devm_clk_get' instead of 'of_clk_get'. - Use 'dev_err_probe' instead of 'dev_err'. - Remove 'pr_info' and 'of_match_ptr'. - Remove 'module_init' and 'module_exit'. Hui-Ping Chen (2): dt-bindings: mtd: nuvoton,ma35d1-nand: add new bindings mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC .../bindings/mtd/nuvoton,ma35d1-nand.yaml | 93 ++ drivers/mtd/nand/raw/Kconfig |8 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c| 1068 + 4 files changed, 1170 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c -- 2.25.1
[PATCH v3 1/2] dt-bindings: mtd: nuvoton, ma35d1-nand: add new bindings
Add dt-bindings for the Nuvoton MA35 SoC NAND Controller.
Signed-off-by: Hui-Ping Chen
Reviewed-by: Krzysztof Kozlowski
---
.../bindings/mtd/nuvoton,ma35d1-nand.yaml | 93 +++
1 file changed, 93 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
diff --git a/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
new file mode 100644
index ..152784e73263
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
+
+maintainers:
+ - Hui-Ping Chen
+
+allOf:
+ - $ref: nand-controller.yaml#
+
+properties:
+ compatible:
+enum:
+ - nuvoton,ma35d1-nand
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+type: object
+$ref: raw-nand-chip.yaml
+properties:
+ nand-ecc-step-size:
+enum: [512, 1024]
+
+ nand-ecc-strength:
+enum: [8, 12, 24]
+
+required:
+ - nand-ecc-step-size
+ - nand-ecc-strength
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+nand-controller@401A {
+compatible = "nuvoton,ma35d1-nand";
+reg = <0x0 0x401A 0x0 0x1000>;
+interrupts = ;
+clocks = <&clk NAND_GATE>;
+#address-cells = <1>;
+#size-cells = <0>;
+
+nand@0 {
+reg = <0>;
+
+nand-on-flash-bbt;
+nand-ecc-step-size = <512>;
+nand-ecc-strength = <8>;
+
+partitions {
+compatible = "fixed-partitions";
+#address-cells = <1>;
+#size-cells = <1>;
+
+uboot@0 {
+label = "nand-uboot";
+read-only;
+reg = <0x0 0x30>;
+};
+};
+};
+};
+};
+
+...
--
2.25.1
[PATCH v3 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
Nuvoton MA35 SoCs NAND Flash Interface Controller supports 2KB, 4KB and 8KB page size, and up to 8-bit, 12-bit, and 24-bit hardware ECC calculation circuit to protect data communication. Signed-off-by: Hui-Ping Chen --- drivers/mtd/nand/raw/Kconfig |8 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c | 1068 3 files changed, 1077 insertions(+) create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 614257308516..932bf2215470 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -448,6 +448,14 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. +config MTD_NAND_NVT_MA35 + tristate "Nuvoton MA35 SoC NAND controller" + depends on ARCH_MA35 || COMPILE_TEST + depends on OF + help + Enables support for the NAND controller found on + the Nuvoton MA35 series SoCs. + comment "Misc" config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 25120a4afada..cdfdfee3f5f3 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o obj-$(CONFIG_MTD_NAND_ROCKCHIP)+= rockchip-nand-controller.o obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o +obj-$(CONFIG_MTD_NAND_NVT_MA35)+= nuvoton_ma35d1_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c new file mode 100644 index ..b4586d7a7a45 --- /dev/null +++ b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c @@ -0,0 +1,1068 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Nuvoton Technology Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* NFI DMA Registers */ +#define MA35_NFI_REG_BUFFER0 (0x000) +#define MA35_NFI_REG_DMACTL(0x400) +#define DMA_EN BIT(0) +#define DMA_RST BIT(1) +#define DMA_BUSY BIT(9) + +#define MA35_NFI_REG_DMASA (0x408) +#define MA35_NFI_REG_DMABCNT (0x40C) +#define MA35_NFI_REG_DMAINTEN (0x410) +#define MA35_NFI_REG_DMAINTSTS (0x414) + +/* NFI Global Registers */ +#define MA35_NFI_REG_GCTL (0x800) +#define NAND_EN BIT(3) +#define MA35_NFI_REG_GINTEN(0x804) +#define MA35_NFI_REG_GINTSTS (0x808) + +/* NAND-type Flash Registers */ +#define MA35_NFI_REG_NANDCTL (0x8A0) +#define SWRSTBIT(0) +#define DMA_W_EN BIT(1) +#define DMA_R_EN BIT(2) +#define ECC_CHK BIT(7) +#define PROT3BEN BIT(8) +#define PSIZE_2K (1 << 16) +#define PSIZE_4K (2 << 16) +#define PSIZE_8K (3 << 16) +#define PSIZE_MASK (3 << 16) +#define BCH_T24 BIT(18) +#define BCH_T8 BIT(20) +#define BCH_T12 BIT(21) +#define BCH_NONE (0x0) +#define BCH_MASK (0x1f << 18) +#define ECC_EN BIT(23) +#define DISABLE_CS0 BIT(25) + +#define MA35_NFI_REG_NANDTMCTL (0x8A4) +#define MA35_NFI_REG_NANDINTEN (0x8A8) +#define MA35_NFI_REG_NANDINTSTS(0x8AC) +#define INT_DMA BIT(0) +#define INT_ECC BIT(2) +#define INT_RB0 BIT(10) +#define INT_RB0_STS BIT(18) + +#define MA35_NFI_REG_NANDCMD (0x8B0) +#define MA35_NFI_REG_NANDADDR (0x8B4) +#define ENDADDR BIT(31) + +#define MA35_NFI_REG_NANDDATA (0x8B8) +#define MA35_NFI_REG_NANDRACTL (0x8BC) +#define MA35_NFI_REG_NANDECTL (0x8C0) +#define ENABLE_WP(0x0) +#define DISABLE_WP BIT(0) + +#define MA35_NFI_REG_NANDECCES0(0x8D0) +#define ECC_STATUS_MASK (0x3) +#define ECC_ERR_CNT_MASK (0x1f) + +#define MA35_NFI_REG_NANDECCES1(0x8
Re: [PATCH v3 1/2] dt-bindings: mtd: nuvoton,ma35d1-nand: add new bindings
Dear Miquèl, Thank you for your reply. On 2024/8/24 上午 12:26, Miquel Raynal wrote: Hi, hpchen0...@gmail.com wrote on Wed, 21 Aug 2024 07:11:31 +: Add dt-bindings for the Nuvoton MA35 SoC NAND Controller. Signed-off-by: Hui-Ping Chen Reviewed-by: Krzysztof Kozlowski --- .../bindings/mtd/nuvoton,ma35d1-nand.yaml | 93 +++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml diff --git a/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml new file mode 100644 index ..152784e73263 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller + +maintainers: + - Hui-Ping Chen + +allOf: + - $ref: nand-controller.yaml# + +properties: + compatible: +enum: + - nuvoton,ma35d1-nand Can we please use the -nand-controller suffix. A NAND is a the common name for a chip with storage inside. You are describing a host controller that can be connected to in order to talk to a NAND. Okay, I will change it to nuvoton,ma35d1-nfi. Because in our platform, it is the NAND Flash Interface. Thanks, Miquèl Best regards, Hui-Ping Chen
Re: [PATCH v3 1/2] dt-bindings: mtd: nuvoton,ma35d1-nand: add new bindings
Dear Miquel, Thank you for your reply. On 2024/8/28 下午 03:48, Miquel Raynal wrote: Hi Hui-Ping, hpchen0...@gmail.com wrote on Wed, 28 Aug 2024 10:47:17 +0800: Dear Miquèl, Thank you for your reply. On 2024/8/24 上午 12:26, Miquel Raynal wrote: Hi, hpchen0...@gmail.com wrote on Wed, 21 Aug 2024 07:11:31 +: Add dt-bindings for the Nuvoton MA35 SoC NAND Controller. Signed-off-by: Hui-Ping Chen Reviewed-by: Krzysztof Kozlowski --- .../bindings/mtd/nuvoton,ma35d1-nand.yaml | 93 +++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml diff --git a/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml new file mode 100644 index ..152784e73263 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller + +maintainers: + - Hui-Ping Chen + +allOf: + - $ref: nand-controller.yaml# + +properties: + compatible: +enum: + - nuvoton,ma35d1-nand Can we please use the -nand-controller suffix. A NAND is a the common name for a chip with storage inside. You are describing a host controller that can be connected to in order to talk to a NAND. Okay, I will change it to nuvoton,ma35d1-nfi. Because in our platform, it is the NAND Flash Interface. nfi is not an acronym that is understandable by everyone. Please use -nand-controller. Don't be worried by the size of the string. You can use the acronym as prefix for your NAND controller functions though. Okay, I will change it to nuvoton,ma35d1-nand-controller. Thanks, Miquèl Best regards, Hui-Ping Chen
Re: [PATCH v3 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
Dear Miquel, Thank you for your reply. On 2024/8/24 上午 01:02, Miquel Raynal wrote: Hi Hui-Ping, hpchen0...@gmail.com wrote on Wed, 21 Aug 2024 07:11:32 +: Nuvoton MA35 SoCs NAND Flash Interface Controller supports 2KB, 4KB and 8KB page size, and up to 8-bit, Suffix is: kiB Okay, I will fix that. 12-bit, and 24-bit hardware ECC calculation circuit to protect data communication. It's not the communication, it's the data itself. Okay, I will remove that. Signed-off-by: Hui-Ping Chen --- drivers/mtd/nand/raw/Kconfig |8 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c | 1068 3 files changed, 1077 insertions(+) create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 614257308516..932bf2215470 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -448,6 +448,14 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. +config MTD_NAND_NVT_MA35 Is NVT so common or is it just one opportunity to save 4 chars in a Kconfig file?? I'd prefer something more easy to understand. I will change it to MTD_NAND_NUVOTON_MA35. + tristate "Nuvoton MA35 SoC NAND controller" + depends on ARCH_MA35 || COMPILE_TEST + depends on OF + help + Enables support for the NAND controller found on + the Nuvoton MA35 series SoCs. + comment "Misc" config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 25120a4afada..cdfdfee3f5f3 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o obj-$(CONFIG_MTD_NAND_ROCKCHIP) += rockchip-nand-controller.o obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o obj-$(CONFIG_MTD_NAND_RENESAS)+= renesas-nand-controller.o +obj-$(CONFIG_MTD_NAND_NVT_MA35)+= nuvoton_ma35d1_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c new file mode 100644 index ..b4586d7a7a45 --- /dev/null +++ b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c @@ -0,0 +1,1068 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Nuvoton Technology Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + Not sure why you didn't sort the below includes with the ones above? I will sort it. +#include +#include +#include +#include +#include + +/* NFI DMA Registers */ +#define MA35_NFI_REG_BUFFER0 (0x000) You don't need all these parentheses Okay, I will remove it. +#define MA35_NFI_REG_DMACTL(0x400) +#define DMA_EN BIT(0) +#define DMA_RST BIT(1) +#define DMA_BUSY BIT(9) + +#define MA35_NFI_REG_DMASA (0x408) +#define MA35_NFI_REG_DMABCNT (0x40C) +#define MA35_NFI_REG_DMAINTEN (0x410) +#define MA35_NFI_REG_DMAINTSTS (0x414) + +/* NFI Global Registers */ +#define MA35_NFI_REG_GCTL (0x800) +#define NAND_EN BIT(3) +#define MA35_NFI_REG_GINTEN(0x804) +#define MA35_NFI_REG_GINTSTS (0x808) + +/* NAND-type Flash Registers */ +#define MA35_NFI_REG_NANDCTL (0x8A0) +#define SWRSTBIT(0) +#define DMA_W_EN BIT(1) +#define DMA_R_EN BIT(2) +#define ECC_CHK BIT(7) +#define PROT3BEN BIT(8) +#define PSIZE_2K (1 << 16) +#define PSIZE_4K (2 << 16) +#define PSIZE_8K (3 << 16) +#define PSIZE_MASK (3 << 16) +#define BCH_T24 BIT(18) +#define BCH_T8 BIT(20) +#define BCH_T12 BIT(21) +#define BCH_NONE (0x0) +#define BCH_MASK (0x1f << 18) +#define ECC_EN BIT(23) +#define DISABLE_CS0 BIT(25) + +#define MA35_NFI_REG_NANDTMCTL (0x8A4) +#define MA35_NFI_REG_NANDINTEN (0x8A8) +#define MA35_NFI_REG_NANDINTSTS(0x8AC) +#define INT_DMA BIT(0) +#define INT_ECC BIT(2) +#define INT_RB0
[PATCH 1/2] dt-bindings: mtd: nuvoton,ma35d1-nand: add new bindings
Add dt-bindings for the Nuvoton MA35 SoC NAND Controller.
Signed-off-by: Hui-Ping Chen
---
.../bindings/mtd/nuvoton,ma35d1-nand.yaml | 97 +++
1 file changed, 97 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
diff --git a/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
new file mode 100644
index ..988c43bc6e99
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
+
+allOf:
+ - $ref: nand-controller.yaml#
+
+maintainers:
+ - Hui-Ping Chen
+
+properties:
+ compatible:
+enum:
+ - nuvoton,ma35d1-nand
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+minItems: 1
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+type: object
+$ref: raw-nand-chip.yaml
+properties:
+ nand-ecc-mode:
+const: hw
+
+ nand-ecc-step-size:
+enum: [512, 1024]
+
+ nand-ecc-strength:
+enum: [8, 12, 24]
+
+ nand-bus-width:
+const: 8
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+nand-controller@401A {
+compatible = "nuvoton,ma35d1-nand";
+reg = <0x0 0x401A 0x0 0x1000>;
+interrupts = ;
+clocks = <&clk NAND_GATE>;
+#address-cells = <1>;
+#size-cells = <0>;
+
+nand@0 {
+reg = <0>;
+
+nand-on-flash-bbt;
+nand-ecc-mode = "hw";
+nand-ecc-step-size = <512>;
+nand-ecc-strength = <8>;
+nand-bus-width = <8>;
+
+partitions {
+compatible = "fixed-partitions";
+#address-cells = <1>;
+#size-cells = <1>;
+
+uboot@0 {
+label = "nand-uboot";
+read-only;
+reg = <0x0 0x30>;
+};
+};
+};
+};
+};
+
+...
--
2.25.1
[PATCH 0/2] Add support for nuvoton ma35 nand controller
This patch series adds the mtd nand driver for the nuvoton ma35 ARMv8 SoC. It includes DT binding documentation and the ma35 mtd nand driver. Hui-Ping Chen (2): dt-bindings: mtd: nuvoton,ma35d1-nand: add new bindings mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC .../bindings/mtd/nuvoton,ma35d1-nand.yaml | 97 ++ drivers/mtd/nand/raw/Kconfig |8 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c| 1109 + 4 files changed, 1215 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c -- 2.25.1
[PATCH 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
Nuvoton MA35 SoCs NAND Flash Interface Controller supports 2KB, 4KB and 8KB page size, and up to 8-bit, 12-bit, and 24-bit hardware ECC calculation circuit to protect data communication. Signed-off-by: Hui-Ping Chen --- drivers/mtd/nand/raw/Kconfig |8 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c | 1109 3 files changed, 1118 insertions(+) create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 614257308516..932bf2215470 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -448,6 +448,14 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. +config MTD_NAND_NVT_MA35 + tristate "Nuvoton MA35 SoC NAND controller" + depends on ARCH_MA35 || COMPILE_TEST + depends on OF + help + Enables support for the NAND controller found on + the Nuvoton MA35 series SoCs. + comment "Misc" config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 25120a4afada..cdfdfee3f5f3 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o obj-$(CONFIG_MTD_NAND_ROCKCHIP)+= rockchip-nand-controller.o obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o +obj-$(CONFIG_MTD_NAND_NVT_MA35)+= nuvoton_ma35d1_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c new file mode 100644 index ..7445eb489c38 --- /dev/null +++ b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c @@ -0,0 +1,1109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Nuvoton Technology Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* NFI DMA Registers */ +#define MA35_NFI_REG_BUFFER0 (0x000) +#define MA35_NFI_REG_DMACTL(0x400) +#define DMA_EN BIT(0) +#define DMA_RST BIT(1) +#define DMA_BUSY BIT(9) + +#define MA35_NFI_REG_DMASA (0x408) +#define MA35_NFI_REG_DMABCNT (0x40C) +#define MA35_NFI_REG_DMAINTEN (0x410) +#define MA35_NFI_REG_DMAINTSTS (0x414) + +/* NFI Global Registers */ +#define MA35_NFI_REG_GCTL (0x800) +#define NAND_EN BIT(3) +#define MA35_NFI_REG_GINTEN(0x804) +#define MA35_NFI_REG_GINTSTS (0x808) + +/* NAND-type Flash Registers */ +#define MA35_NFI_REG_NANDCTL (0x8A0) +#define SWRSTBIT(0) +#define DMA_W_EN BIT(1) +#define DMA_R_EN BIT(2) +#define ECC_CHK BIT(7) +#define PROT3BEN BIT(8) +#define PSIZE_2K (1 << 16) +#define PSIZE_4K (2 << 16) +#define PSIZE_8K (3 << 16) +#define PSIZE_MASK (3 << 16) +#define BCH_T24 BIT(18) +#define BCH_T8 BIT(20) +#define BCH_T12 BIT(21) +#define BCH_MASK (0x1f << 18) +#define ECC_EN BIT(23) +#define DISABLE_CS0 BIT(25) + +#define MA35_NFI_REG_NANDTMCTL (0x8A4) +#define MA35_NFI_REG_NANDINTEN (0x8A8) +#define MA35_NFI_REG_NANDINTSTS(0x8AC) +#define INT_DMA BIT(0) +#define INT_ECC BIT(2) +#define INT_RB0 BIT(10) +#define INT_RB0_STS BIT(18) + +#define MA35_NFI_REG_NANDCMD (0x8B0) +#define MA35_NFI_REG_NANDADDR (0x8B4) +#define ENDADDR BIT(31) + +#define MA35_NFI_REG_NANDDATA (0x8B8) +#define MA35_NFI_REG_NANDRACTL (0x8BC) +#define MA35_NFI_REG_NANDECTL (0x8C0) +#define ENABLE_WP(0x0) +#define DISABLE_WP BIT(0) + +#define MA35_NFI_REG_NANDECCES0(0x8D0) +#define ECC_STATUS_MASK (0x3) +#define ECC_ERR_CNT_MASK (0x1f) + +#define MA35_NFI_REG_NANDECCES1(0x8D4) +#define MA35_NFI_REG_NANDECCES2(0x8D8) +#define
[PATCH v2 1/2] dt-bindings: mtd: nuvoton, ma35d1-nand: add new bindings
Add dt-bindings for the Nuvoton MA35 SoC NAND Controller.
Signed-off-by: Hui-Ping Chen
---
.../bindings/mtd/nuvoton,ma35d1-nand.yaml | 93 +++
1 file changed, 93 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
diff --git a/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
new file mode 100644
index ..152784e73263
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
+
+maintainers:
+ - Hui-Ping Chen
+
+allOf:
+ - $ref: nand-controller.yaml#
+
+properties:
+ compatible:
+enum:
+ - nuvoton,ma35d1-nand
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+type: object
+$ref: raw-nand-chip.yaml
+properties:
+ nand-ecc-step-size:
+enum: [512, 1024]
+
+ nand-ecc-strength:
+enum: [8, 12, 24]
+
+required:
+ - nand-ecc-step-size
+ - nand-ecc-strength
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+nand-controller@401A {
+compatible = "nuvoton,ma35d1-nand";
+reg = <0x0 0x401A 0x0 0x1000>;
+interrupts = ;
+clocks = <&clk NAND_GATE>;
+#address-cells = <1>;
+#size-cells = <0>;
+
+nand@0 {
+reg = <0>;
+
+nand-on-flash-bbt;
+nand-ecc-step-size = <512>;
+nand-ecc-strength = <8>;
+
+partitions {
+compatible = "fixed-partitions";
+#address-cells = <1>;
+#size-cells = <1>;
+
+uboot@0 {
+label = "nand-uboot";
+read-only;
+reg = <0x0 0x30>;
+};
+};
+};
+};
+};
+
+...
--
2.25.1
[PATCH v2 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
Nuvoton MA35 SoCs NAND Flash Interface Controller supports 2KB, 4KB and 8KB page size, and up to 8-bit, 12-bit, and 24-bit hardware ECC calculation circuit to protect data communication. Signed-off-by: Hui-Ping Chen --- drivers/mtd/nand/raw/Kconfig |8 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c | 1070 3 files changed, 1079 insertions(+) create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 614257308516..932bf2215470 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -448,6 +448,14 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. +config MTD_NAND_NVT_MA35 + tristate "Nuvoton MA35 SoC NAND controller" + depends on ARCH_MA35 || COMPILE_TEST + depends on OF + help + Enables support for the NAND controller found on + the Nuvoton MA35 series SoCs. + comment "Misc" config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 25120a4afada..cdfdfee3f5f3 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o obj-$(CONFIG_MTD_NAND_ROCKCHIP)+= rockchip-nand-controller.o obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o +obj-$(CONFIG_MTD_NAND_NVT_MA35)+= nuvoton_ma35d1_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c new file mode 100644 index ..f13ef00628e0 --- /dev/null +++ b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c @@ -0,0 +1,1070 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Nuvoton Technology Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* NFI DMA Registers */ +#define MA35_NFI_REG_BUFFER0 (0x000) +#define MA35_NFI_REG_DMACTL(0x400) +#define DMA_EN BIT(0) +#define DMA_RST BIT(1) +#define DMA_BUSY BIT(9) + +#define MA35_NFI_REG_DMASA (0x408) +#define MA35_NFI_REG_DMABCNT (0x40C) +#define MA35_NFI_REG_DMAINTEN (0x410) +#define MA35_NFI_REG_DMAINTSTS (0x414) + +/* NFI Global Registers */ +#define MA35_NFI_REG_GCTL (0x800) +#define NAND_EN BIT(3) +#define MA35_NFI_REG_GINTEN(0x804) +#define MA35_NFI_REG_GINTSTS (0x808) + +/* NAND-type Flash Registers */ +#define MA35_NFI_REG_NANDCTL (0x8A0) +#define SWRSTBIT(0) +#define DMA_W_EN BIT(1) +#define DMA_R_EN BIT(2) +#define ECC_CHK BIT(7) +#define PROT3BEN BIT(8) +#define PSIZE_2K (1 << 16) +#define PSIZE_4K (2 << 16) +#define PSIZE_8K (3 << 16) +#define PSIZE_MASK (3 << 16) +#define BCH_T24 BIT(18) +#define BCH_T8 BIT(20) +#define BCH_T12 BIT(21) +#define BCH_NONE (0x0) +#define BCH_MASK (0x1f << 18) +#define ECC_EN BIT(23) +#define DISABLE_CS0 BIT(25) + +#define MA35_NFI_REG_NANDTMCTL (0x8A4) +#define MA35_NFI_REG_NANDINTEN (0x8A8) +#define MA35_NFI_REG_NANDINTSTS(0x8AC) +#define INT_DMA BIT(0) +#define INT_ECC BIT(2) +#define INT_RB0 BIT(10) +#define INT_RB0_STS BIT(18) + +#define MA35_NFI_REG_NANDCMD (0x8B0) +#define MA35_NFI_REG_NANDADDR (0x8B4) +#define ENDADDR BIT(31) + +#define MA35_NFI_REG_NANDDATA (0x8B8) +#define MA35_NFI_REG_NANDRACTL (0x8BC) +#define MA35_NFI_REG_NANDECTL (0x8C0) +#define ENABLE_WP(0x0) +#define DISABLE_WP BIT(0) + +#define MA35_NFI_REG_NANDECCES0(0x8D0) +#define ECC_STATUS_MASK (0x3) +#define ECC_ERR_CNT_MASK (0x1f) + +#define MA35_NFI_REG_NANDECCES1(0x8
[PATCH v2 0/2] Add support for nuvoton ma35 nand controller
This patch series adds the mtd nand driver for the nuvoton ma35 ARMv8 SoC. It includes DT binding documentation and the ma35 mtd nand driver. v2: - Update nuvoton,ma35d1-nand.yaml - Adjust the order and remove any unnecessary items. - Add 'nand-ecc-step-size' and 'nand-ecc-strength' to the required list. - Update ma35d1 mtd nand driver - Fix coding style. - Use 'devm_clk_get' instead of 'of_clk_get'. - Use 'dev_err_probe' instead of 'dev_err'. - Remove 'pr_info' and 'of_match_ptr'. - Remove 'module_init' and 'module_exit'. Hui-Ping Chen (2): dt-bindings: mtd: nuvoton,ma35d1-nand: add new bindings mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC .../bindings/mtd/nuvoton,ma35d1-nand.yaml | 93 ++ drivers/mtd/nand/raw/Kconfig |8 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c| 1070 + 4 files changed, 1172 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c -- 2.25.1
Re: [PATCH v2 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
Dear Krzysztof,
Thank you for your reply.
On 2024/8/19 下午 07:19, Krzysztof Kozlowski wrote:
On Mon, Aug 19, 2024 at 09:20:37AM +, Hui-Ping Chen wrote:
Nuvoton MA35 SoCs NAND Flash Interface Controller
supports 2KB, 4KB and 8KB page size, and up to 8-bit,
12-bit, and 24-bit hardware ECC calculation circuit
to protect data communication.
Signed-off-by: Hui-Ping Chen
...
+static int ma35_nand_probe(struct platform_device *pdev)
+{
+ struct ma35_nand_info *nand;
+ struct nand_chip *chip;
+ struct mtd_info *mtd;
+ int retval = 0;
+
+ nand = devm_kzalloc(&pdev->dev, sizeof(*nand), GFP_KERNEL);
+ if (!nand)
+ return -ENOMEM;
+
+ nand_controller_init(&nand->controller);
+
+ nand->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(nand->regs))
+ return PTR_ERR(nand->regs);
+
+ nand->dev = &pdev->dev;
+ chip = &nand->chip;
+ mtd = nand_to_mtd(chip);
+ nand_set_controller_data(chip, nand);
+ nand_set_flash_node(chip, pdev->dev.of_node);
+
+ mtd->priv = chip;
+ mtd->owner = THIS_MODULE;
+ mtd->dev.parent = &pdev->dev;
+
+ nand->clk = devm_clk_get(&pdev->dev, "nand_gate");
+ if (IS_ERR(nand->clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(nand->clk),
+"failed to find nand clock\n");
+
+ retval = clk_prepare_enable(nand->clk);
+ if (retval < 0) {
+ dev_err(&pdev->dev, "failed to enable clock\n");
+ retval = -ENXIO;
+ }
+
+ nand->chip.controller= &nand->controller;
+
+ chip->legacy.cmdfunc = ma35_nand_command;
+ chip->legacy.waitfunc= ma35_waitfunc;
+ chip->legacy.read_byte = ma35_nand_read_byte;
+ chip->legacy.select_chip = ma35_nand_select_chip;
+ chip->legacy.read_buf= ma35_read_buf_dma;
+ chip->legacy.write_buf = ma35_write_buf_dma;
+ chip->legacy.dev_ready = ma35_nand_devready;
+ chip->legacy.chip_delay = 25; /* us */
+
+ /* Read OOB data first, then HW read page */
+ chip->ecc.hwctl = ma35_nand_enable_hwecc;
+ chip->ecc.calculate = ma35_nand_calculate_ecc;
+ chip->ecc.correct= ma35_nand_correct_data;
+ chip->ecc.write_page = ma35_nand_write_page_hwecc;
+ chip->ecc.read_page = ma35_nand_read_page_hwecc_oob_first;
+ chip->ecc.read_oob = ma35_nand_read_oob_hwecc;
+ chip->options |= (NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA);
+
+ ma35_nand_initialize(nand);
+ platform_set_drvdata(pdev, nand);
+
+ nand->controller.ops = &ma35_nand_controller_ops;
+
+ nand->irq = platform_get_irq(pdev, 0);
+ if (nand->irq < 0)
+ return dev_err_probe(&pdev->dev, nand->irq,
+"failed to get platform irq\n");
+
+ if (request_irq(nand->irq, ma35_nand_irq, IRQF_TRIGGER_HIGH,
"ma35d1-nand", nand)) {
+ dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
+ return -ENXIO;
+ }
+
+ retval = nand_scan(chip, 1);
+ if (retval)
+ return retval;
+
+ if (mtd_device_register(mtd, nand->parts, nand->nr_parts)) {
+ nand_cleanup(chip);
+ devm_kfree(&pdev->dev, nand);
+ return retval;
+ }
+
+ return retval;
+}
+
+static void ma35_nand_remove(struct platform_device *pdev)
+{
+ struct ma35_nand_info *nand = platform_get_drvdata(pdev);
+ struct nand_chip *chip = &nand->chip;
+ int ret;
+
Where do you release IRQ handler?
I will add a release IRQ handler to this function.
+ ret = mtd_device_unregister(nand_to_mtd(chip));
+ WARN_ON(ret);
+ nand_cleanup(chip);
+
+ clk_disable_unprepare(nand->clk);
+
+ kfree(nand);
NAK, you never tested your code.
I will strengthen the testing of this function.
+ platform_set_drvdata(pdev, NULL);
Why? Drop.
I will remove it.
+}
+
+/* PM Support */
+#ifdef CONFIG_PM
+static int ma35_nand_suspend(struct platform_device *pdev, pm_message_t pm)
+{
+ struct ma35_nand_info *nand = platform_get_drvdata(pdev);
+ unsigned long timeo = jiffies + HZ/2;
+
+ /* wait DMAC to ready */
+ while (1) {
+ if ((readl(nand->regs + MA35_NFI_REG_DMACTL) & DMA_BUSY) == 0)
+ break;
+ if (time_after(jiffies, timeo))
+ return -ETIMEDOUT;
+ }
+
+ clk_disable(nand->clk);
+
+ return 0;
+}
+
+static int ma35_nand_resume(struct platform_device *pdev)
+{
+ struct ma35_nand_info *nand = platform_
Re: [PATCH v4 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
Dear Sascha,
Thank you for your reply.
On 2024/9/18 下午 06:58, Sascha Hauer wrote:
Hi,
The driver has a few minor whitespace issues, please run through
checkpatch.pl to catch them.
I will fix it.
Some more things inline.
On Wed, Sep 18, 2024 at 09:03:08AM +, Hui-Ping Chen wrote:
Nuvoton MA35 SoCs NAND Flash Interface Controller
supports 2kiB, 4kiB and 8kiB page size, and up to
8-bit, 12-bit, and 24-bit hardware ECC calculation
circuit to protect data.
Signed-off-by: Hui-Ping Chen
---
drivers/mtd/nand/raw/Kconfig | 8 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c | 935 +
3 files changed, 944 insertions(+)
create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c
+#define SKIP_SPARE_BYTES 4
Unused, please drop.
I will remove it.
+static int ma35_nfi_ecc_check(struct nand_chip *chip, unsigned long addr)
+{
+ struct ma35_nand_info *nand = nand_get_controller_data(chip);
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int status, i, j, nchunks = 0;
status should be unsigned.
Okay, I will modify it.
+ int report_err = 0;
+ int err_cnt = 0;
+
+ nchunks = mtd->writesize / chip->ecc.steps;
+ if (nchunks < 4)
+ nchunks = 1;
+ else
+ nchunks /= 4;
+
+ for (j = 0; j < nchunks; j++) {
+ status = readl(nand->regs + MA35_NFI_REG_NANDECCES0 + j*4);
+ if (!status)
+ continue;
+
+ for (i = 0; i < 4; i++) {
+ if (!(status & ECC_STATUS_MASK)) {
+ /* No error */
+ status >>= 8;
+ continue;
+
+ } else if ((status & ECC_STATUS_MASK) == 0x01) {
+ /* Correctable error */
+ err_cnt = (status >> 2) & ECC_ERR_CNT_MASK;
+ dev_warn(nand->dev, "nchunks (%d, %d) have %d
error!\n",
+ j, i, err_cnt);
Correctable bitflips are expected. Please don't spam the log with it.
I will remove it.
+ ma35_nfi_correct(nand, j*4+i, err_cnt, (u8
*)addr);
+ report_err += err_cnt;
+
+ } else {
+ /* uncorrectable error */
+ dev_warn(nand->dev, "uncorrectable error!
0x%4x\n", status);
+ return -1;
+ }
+ status >>= 8;
+ }
+ }
+ return report_err;
There are a few things wrong here. Your chip->ecc.read_page op must
return the maximum number of bitflips occured on a subpage while
reading a page.
To archieve this I suggest you fix the return value of this function
accordingly and call it from chip->ecc.read_page rather than from the
interrupt handler.
Nevertheless mtd->ecc_stats.corrected counts the total number of
bitflips, so you must handle this counter in this function.
See rk_nfc_read_page_hwecc() as an example of a driver which gets it
right.
The background is that we have to rewrite the page once one ECC block
hits a critical bitflip limit. A whole page might be fine when the
bitflips are evenly distributed across the subpages, but it's not when
all bitflips are occur in a single subpage.
I will refer to rk_nfc_read_page_hwecc() and then rewrite it.
+static int ma35_nand_do_write(struct nand_chip *chip, const u8 *addr, u32 len)
+{
+ struct ma35_nand_info *nand = nand_get_controller_data(chip);
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ dma_addr_t dma_addr;
+ int ret = 0, i;
+ u32 val, reg;
+
+ ma35_nand_target_enable(nand);
+
+ if (len != mtd->writesize) {
+ for (i = 0; i < len; i++)
+ writel(addr[i], nand->regs + MA35_NFI_REG_NANDDATA);
+ ma35_nand_target_disable(nand);
+ return ret;
+ }
+
+ /* Check the DMA status before enabling the DMA */
+ ret = readl_poll_timeout(nand->regs + MA35_NFI_REG_DMACTL, val,
+!(val & DMA_BUSY), 50, HZ/2);
+ if (ret)
+ dev_warn(nand->dev, "dma busy\n");
+
+ /* Reinitial dmac */
+ ma35_nand_dmac_init(nand);
The function name already says it and the comment doesn't offer any
additional information. Please drop such comments.
I will remove it.
+
+ writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL);
+
+ /* setup and start DMA using dma_addr */
+ writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTEN);
+ /* To mark this page as dirty. */
+ reg = readl(nand->regs + MA35_NFI_REG_
[PATCH v4 1/2] dt-bindings: mtd: nuvoton, ma35d1-nand: add new bindings
Add dt-bindings for the Nuvoton MA35 SoC NAND Controller.
Signed-off-by: Hui-Ping Chen
Reviewed-by: Krzysztof Kozlowski
---
.../bindings/mtd/nuvoton,ma35d1-nand.yaml | 93 +++
1 file changed, 93 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
diff --git a/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
new file mode 100644
index ..a8a549644c98
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
+
+maintainers:
+ - Hui-Ping Chen
+
+allOf:
+ - $ref: nand-controller.yaml#
+
+properties:
+ compatible:
+enum:
+ - nuvoton,ma35d1-nand-controller
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+type: object
+$ref: raw-nand-chip.yaml
+properties:
+ nand-ecc-step-size:
+enum: [512, 1024]
+
+ nand-ecc-strength:
+enum: [8, 12, 24]
+
+required:
+ - nand-ecc-step-size
+ - nand-ecc-strength
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+nand-controller@401A {
+compatible = "nuvoton,ma35d1-nand-controller";
+reg = <0x0 0x401A 0x0 0x1000>;
+interrupts = ;
+clocks = <&clk NAND_GATE>;
+#address-cells = <1>;
+#size-cells = <0>;
+
+nand@0 {
+reg = <0>;
+
+nand-on-flash-bbt;
+nand-ecc-step-size = <512>;
+nand-ecc-strength = <8>;
+
+partitions {
+compatible = "fixed-partitions";
+#address-cells = <1>;
+#size-cells = <1>;
+
+uboot@0 {
+label = "nand-uboot";
+read-only;
+reg = <0x0 0x30>;
+};
+};
+};
+};
+};
+
+...
--
2.25.1
[PATCH v4 2/2] mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
Nuvoton MA35 SoCs NAND Flash Interface Controller supports 2kiB, 4kiB and 8kiB page size, and up to 8-bit, 12-bit, and 24-bit hardware ECC calculation circuit to protect data. Signed-off-by: Hui-Ping Chen --- drivers/mtd/nand/raw/Kconfig | 8 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c | 935 + 3 files changed, 944 insertions(+) create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 614257308516..a95d91e61c42 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -448,6 +448,14 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. +config MTD_NAND_NUVOTON_MA35 + tristate "Nuvoton MA35 SoC NAND controller" + depends on ARCH_MA35 || COMPILE_TEST + depends on OF + help + Enables support for the NAND controller found on + the Nuvoton MA35 series SoCs. + comment "Misc" config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 25120a4afada..b8e1b3af6942 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o obj-$(CONFIG_MTD_NAND_ROCKCHIP)+= rockchip-nand-controller.o obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o +obj-$(CONFIG_MTD_NAND_NUVOTON_MA35)+= nuvoton_ma35d1_nand.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o diff --git a/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c new file mode 100644 index ..30cbcb999f1a --- /dev/null +++ b/drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c @@ -0,0 +1,935 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Nuvoton Technology Corp. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* NFI Registers */ +#define MA35_NFI_REG_DMACTL0x400 +#define DMA_EN BIT(0) +#define DMA_RST BIT(1) +#define DMA_BUSY BIT(9) + +#define MA35_NFI_REG_DMASA 0x408 +#define MA35_NFI_REG_GCTL 0x800 +#define NAND_EN BIT(3) + +#define MA35_NFI_REG_NANDCTL 0x8A0 +#define SWRSTBIT(0) +#define DMA_R_EN BIT(1) +#define DMA_W_EN BIT(2) +#define ECC_CHK BIT(7) +#define PROT3BEN BIT(8) +#define PSIZE_2K (1 << 16) +#define PSIZE_4K (2 << 16) +#define PSIZE_8K (3 << 16) +#define PSIZE_MASK (3 << 16) +#define BCH_T24 BIT(18) +#define BCH_T8 BIT(20) +#define BCH_T12 BIT(21) +#define BCH_NONE (0x0) +#define BCH_MASK (0x1f << 18) +#define ECC_EN BIT(23) +#define DISABLE_CS0 BIT(25) + +#define MA35_NFI_REG_NANDINTEN 0x8A8 +#define MA35_NFI_REG_NANDINTSTS0x8AC +#define INT_DMA BIT(0) +#define INT_ECC BIT(2) +#define INT_RB0 BIT(10) +#define INT_RB0_STS BIT(18) + +#define MA35_NFI_REG_NANDCMD 0x8B0 +#define MA35_NFI_REG_NANDADDR 0x8B4 +#define ENDADDR BIT(31) + +#define MA35_NFI_REG_NANDDATA 0x8B8 +#define MA35_NFI_REG_NANDRACTL 0x8BC +#define MA35_NFI_REG_NANDECTL 0x8C0 +#define ENABLE_WP0x0 +#define DISABLE_WP BIT(0) + +#define MA35_NFI_REG_NANDECCES00x8D0 +#define ECC_STATUS_MASK 0x3 +#define ECC_ERR_CNT_MASK 0x1f + +#define MA35_NFI_REG_NANDECCEA00x900 +#define MA35_NFI_REG_NANDECCED00x960 +#define MA35_NFI_REG_NANDRA0 0xA00 + +#define SKIP_SPARE_BYTES 4 + + +/* Define for the BCH hardware ECC engine */ +/* define the total padding bytes for 512/1024 data segment */ +#define MA35_BCH_PADDING_512 32 +#define MA35_BCH_PADDING_1024 64 +/* define the BCH parity code length for 512 bytes data pattern */ +#define MA35_PARITY_BCH8 15 +#d
[PATCH v4 0/2] Add support for nuvoton ma35 nand controller
This patch series adds the mtd nand driver for the nuvoton ma35 ARMv8 SoC.
It includes DT binding documentation and the ma35 mtd nand driver.
v4:
- Update nuvoton,ma35d1-nand.yaml
- rename 'nuvoton,ma35d1-nand' to 'nuvoton,ma35d1-nand-controller'.
- Update ma35d1 mtd nand driver
- Rewrite the NAND driver using the exec_op API.
v3:
- Update ma35d1 mtd nand driver
- Release IRQ handler.
- Remove unused functions.
- Remove '.owner'.
v2:
- Update nuvoton,ma35d1-nand.yaml
- Adjust the order and remove any unnecessary items.
- Add 'nand-ecc-step-size' and 'nand-ecc-strength' to the required list.
- Update ma35d1 mtd nand driver
- Fix coding style.
- Use 'devm_clk_get' instead of 'of_clk_get'.
- Use 'dev_err_probe' instead of 'dev_err'.
- Remove 'pr_info' and 'of_match_ptr'.
- Remove 'module_init' and 'module_exit'.
Hui-Ping Chen (2):
dt-bindings: mtd: nuvoton,ma35d1-nand: add new bindings
mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC
.../bindings/mtd/nuvoton,ma35d1-nand.yaml | 93 ++
drivers/mtd/nand/raw/Kconfig | 8 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c| 935 ++
4 files changed, 1037 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
create mode 100644 drivers/mtd/nand/raw/nuvoton_ma35d1_nand.c
--
2.25.1
