[PATCH v1 3/4] dt-bindings: display: panel: Document Renesas R69328 based DSI panel

[Svyatoslav Ryhel]

R69328 is liquid crystal driver for high-definition amorphous silicon
(a-Si) panels and is ideal for tablets and smartphones.

Signed-off-by: Svyatoslav Ryhel 
---
 .../display/panel/renesas,r69328.yaml | 72 +++
 1 file changed, 72 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/renesas,r69328.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/renesas,r69328.yaml 
b/Documentation/devicetree/bindings/display/panel/renesas,r69328.yaml
new file mode 100644
index ..1c1ce5ed6f2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/renesas,r69328.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/renesas,r69328.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R69328 based DSI Display Panel
+
+maintainers:
+  - Svyatoslav Ryhel 
+
+description:
+  The Renesas R69328 is a generic DSI Panel IC used to control LCD panels.
+
+allOf:
+  - $ref: panel-common.yaml#
+
+properties:
+  compatible:
+enum:
+# JDI DX12D100VM0EAA 4.7" WXGA TFT LCD panel
+  - jdi,dx12d100vm0eaa
+
+  reg:
+maxItems: 1
+
+  vdd-supply:
+description: Regulator for main power supply.
+
+  vddio-supply:
+description: Regulator for 1.8V IO power supply.
+
+  backlight: true
+
+  reset-gpios: true
+  port: true
+
+required:
+  - compatible
+  - port
+  - backlight
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+dsi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+panel@1 {
+compatible = "jdi,dx12d100vm0eaa";
+reg = <1>;
+
+reset-gpios = <&gpio 176 GPIO_ACTIVE_LOW>;
+
+vdd-supply = <&vdd_3v0_lcd>;
+vddio-supply = <&vdd_1v8_io>;
+
+backlight = <&backlight>;
+
+port {
+panel_in: endpoint {
+remote-endpoint = <&dsi_out>;
+};
+};
+};
+};
+
+...
-- 
2.43.0

[PATCH v1 0/4] drm: panel: add support for panels used in LG P880/P895

[Svyatoslav Ryhel]

Add support for panels used in LG P880/P895 which are based on Renesas IC
(not related to Renesas RISC-V architecture just the same manufacturer).

Maxim Schwalm (1):
  drm: panel: Add support for Renesas R69328 based MIPI DSI panel

Svyatoslav Ryhel (3):
  dt-bindings: display: panel: Document Renesas R61307 based DSI panel
  drm: panel: Add support for Renesas R61307 based MIPI DSI panel
  dt-bindings: display: panel: Document Renesas R69328 based DSI panel

 .../display/panel/renesas,r61307.yaml |  93 +
 .../display/panel/renesas,r69328.yaml |  72 
 drivers/gpu/drm/panel/Kconfig |  26 ++
 drivers/gpu/drm/panel/Makefile|   2 +
 drivers/gpu/drm/panel/panel-renesas-r61307.c  | 326 ++
 drivers/gpu/drm/panel/panel-renesas-r69328.c  | 282 +++
 6 files changed, 801 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/renesas,r61307.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/panel/renesas,r69328.yaml
 create mode 100644 drivers/gpu/drm/panel/panel-renesas-r61307.c
 create mode 100644 drivers/gpu/drm/panel/panel-renesas-r69328.c

-- 
2.43.0

[PATCH v1 1/4] dt-bindings: display: panel: Document Renesas R61307 based DSI panel

[Svyatoslav Ryhel]

R61307 is liquid crystal driver for high-definition amorphous silicon
(a-Si) panels and is ideal for tablets and smartphones.

Signed-off-by: Svyatoslav Ryhel 
---
 .../display/panel/renesas,r61307.yaml | 93 +++
 1 file changed, 93 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/renesas,r61307.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/renesas,r61307.yaml 
b/Documentation/devicetree/bindings/display/panel/renesas,r61307.yaml
new file mode 100644
index ..a98d2d2e02d2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/renesas,r61307.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/renesas,r61307.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R61307 based DSI Display Panel
+
+maintainers:
+  - Svyatoslav Ryhel 
+
+description:
+  The Renesas R61307 is a generic DSI Panel IC used to control LCD panels.
+
+allOf:
+  - $ref: panel-common.yaml#
+
+properties:
+  compatible:
+enum:
+# KOE/HITACHI TX13D100VM0EAA 5.0" XGA TFT LCD panel
+  - hit,tx13d100vm0eaa
+  - koe,tx13d100vm0eaa
+
+  reg:
+maxItems: 1
+
+  vcc-supply:
+description: Regulator for main power supply.
+
+  iovcc-supply:
+description: Regulator for 1.8V IO power supply.
+
+  backlight: true
+
+  renesas,gamma:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+  0 - disabled
+  1-3 - gamma setting A presets
+enum: [0, 1, 2, 3]
+
+  renesas,inversion:
+type: boolean
+description: switch between line and column inversion. The line
+  inversion is set by default.
+
+  renesas,contrast:
+type: boolean
+description: digital contrast adjustment
+
+  reset-gpios: true
+  port: true
+
+required:
+  - compatible
+  - port
+  - backlight
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+dsi {
+#address-cells = <1>;
+#size-cells = <0>;
+
+panel@1 {
+compatible = "koe,tx13d100vm0eaa";
+reg = <1>;
+
+reset-gpios = <&gpio 176 GPIO_ACTIVE_LOW>;
+
+renesas,gamma = <3>;
+renesas,inversion;
+renesas,contrast;
+
+vcc-supply = <&vcc_3v0_lcd>;
+iovcc-supply = <&iovcc_1v8_lcd>;
+
+backlight = <&backlight>;
+
+port {
+panel_in: endpoint {
+remote-endpoint = <&dsi_out>;
+};
+};
+};
+};
+
+...
-- 
2.43.0

[PATCH v1 2/4] drm: panel: Add support for Renesas R61307 based MIPI DSI panel

[Svyatoslav Ryhel]

R61307 is liquid crystal driver for high-definition amorphous silicon
(a-Si) panels and is ideal for tablets and smartphones.

Supported compatibles are:
- hit,tx13d100vm0eaa
- koe,tx13d100vm0eaa

Signed-off-by: Svyatoslav Ryhel 
---
 drivers/gpu/drm/panel/Kconfig|  13 +
 drivers/gpu/drm/panel/Makefile   |   1 +
 drivers/gpu/drm/panel/panel-renesas-r61307.c | 326 +++
 3 files changed, 340 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-renesas-r61307.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d7469c565d1d..e8723f42cafb 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -605,6 +605,19 @@ config DRM_PANEL_RAYDIUM_RM69380
  This panel controller can be found in the Lenovo Xiaoxin Pad Pro 2021
  in combination with an EDO OLED panel.
 
+config DRM_PANEL_RENESAS_R61307
+   tristate "Renesas R61307 DSI video mode panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to enable support for KOE tx13d100vm0eaa
+ IPS-LCD module with Renesas R69328 IC. The panel has a 1024x768
+ resolution and uses 24 bit RGB per pixel.
+
+ This panel controller can be found in LG Optimus Vu P895 smartphone
+ in combination with LCD panel.
+
 config DRM_PANEL_RONBO_RB070D30
tristate "Ronbo Electronics RB070D30 panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 7dcf72646cac..61d8853df1a7 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += 
panel-raydium-rm67191.o
 obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o
 obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM692E5) += panel-raydium-rm692e5.o
 obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM69380) += panel-raydium-rm69380.o
+obj-$(CONFIG_DRM_PANEL_RENESAS_R61307) += panel-renesas-r61307.o
 obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01) += panel-samsung-ams581vf01.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08) += panel-samsung-ams639rq08.o
diff --git a/drivers/gpu/drm/panel/panel-renesas-r61307.c 
b/drivers/gpu/drm/panel/panel-renesas-r61307.c
new file mode 100644
index ..7277541edb16
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-renesas-r61307.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+
+#define R61307_MACP0xb0 /* Manufacturer CMD Protect */
+#define   R61307_MACP_ON   0x03
+#define   R61307_MACP_OFF  0x04
+
+#define R61307_INVERSION   0xc1
+#define R61307_GAMMA_SET_A 0xc8 /* Gamma Setting A */
+#define R61307_GAMMA_SET_B 0xc9 /* Gamma Setting B */
+#define R61307_GAMMA_SET_C 0xca /* Gamma Setting C */
+#define R61307_CONTRAST_SET0xcc
+
+struct renesas_r61307 {
+   struct drm_panel panel;
+   struct mipi_dsi_device *dsi;
+
+   struct regulator *vcc_supply;
+   struct regulator *iovcc_supply;
+
+   struct gpio_desc *reset_gpio;
+
+   bool prepared;
+
+   bool dig_cont_adj;
+   bool inversion;
+   u32 gamma;
+};
+
+static const u8 gamma_setting[][25] = {
+   { /* sentinel */ },
+   {
+   R61307_GAMMA_SET_A,
+   0x00, 0x06, 0x0a, 0x0f,
+   0x14, 0x1f, 0x1f, 0x17,
+   0x12, 0x0c, 0x09, 0x06,
+   0x00, 0x06, 0x0a, 0x0f,
+   0x14, 0x1f, 0x1f, 0x17,
+   0x12, 0x0c, 0x09, 0x06
+   },
+   {
+   R61307_GAMMA_SET_A,
+   0x00, 0x05, 0x0b, 0x0f,
+   0x11, 0x1d, 0x20, 0x18,
+   0x18, 0x09, 0x07, 0x06,
+   0x00, 0x05, 0x0b, 0x0f,
+   0x11, 0x1d, 0x20, 0x18,
+   0x18, 0x09, 0x07, 0x06
+   },
+   {
+   R61307_GAMMA_SET_A,
+   0x0b, 0x0d, 0x10, 0x14,
+   0x13, 0x1d, 0x20, 0x18,
+   0x12, 0x09, 0x07, 0x06,
+   0x0a, 0x0c, 0x10, 0x14,
+   0x13, 0x1d, 0x20, 0x18,
+   0x12, 0x09, 0x07, 0x06
+   },
+};
+
+static inline struct renesas_r61307 *to_renesas_r61307(struct drm_panel *panel)
+{
+   return container_of(panel, struct renesas_r61307, panel);
+}
+
+static void renesas_r61307_reset(struct renesas_r61307 *priv)
+{
+   gpiod_set_value_cansleep(priv->reset_gpio, 1);
+   usleep_range(1, 11000);
+   gpiod_set_value_cansleep(priv->reset_gpio, 0);
+   usleep_range(2000, 3000);
+}
+
+static int renesas_r61307_prepare(struct drm_panel *panel)
+{
+   struct renesas_r61307 *priv = to_renesas_r61307(panel);
+   struct device *dev = &priv->dsi->dev;
+   int ret;
+
+   if (priv->prepared)
+ 

[PATCH v1 4/4] drm: panel: Add support for Renesas R69328 based MIPI DSI panel

[Svyatoslav Ryhel]

From: Maxim Schwalm 

Driver adds support for panels with Renesas R69328 IC

Currently supported compatible is:
- jdi,dx12d100vm0eaa

Co-developed-by: Svyatoslav Ryhel 
Signed-off-by: Svyatoslav Ryhel 
Signed-off-by: Maxim Schwalm 
---
 drivers/gpu/drm/panel/Kconfig|  13 +
 drivers/gpu/drm/panel/Makefile   |   1 +
 drivers/gpu/drm/panel/panel-renesas-r69328.c | 282 +++
 3 files changed, 296 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-renesas-r69328.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index e8723f42cafb..86c66f818a11 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -618,6 +618,19 @@ config DRM_PANEL_RENESAS_R61307
  This panel controller can be found in LG Optimus Vu P895 smartphone
  in combination with LCD panel.
 
+config DRM_PANEL_RENESAS_R69328
+   tristate "Renesas R69328 720x1280 DSI video mode panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to enable support for JDI dx12d100vm0eaa
+ IPS-LCD module with Renesas R69328 IC. The panel has a 720x1280
+ resolution and uses 24 bit RGB per pixel.
+
+ This panel controller can be found in LG Optimus 4X P895 smartphone
+ in combination with LCD panel.
+
 config DRM_PANEL_RONBO_RB070D30
tristate "Ronbo Electronics RB070D30 panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 61d8853df1a7..37e4e13165a9 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += 
panel-raydium-rm68200.o
 obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM692E5) += panel-raydium-rm692e5.o
 obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM69380) += panel-raydium-rm69380.o
 obj-$(CONFIG_DRM_PANEL_RENESAS_R61307) += panel-renesas-r61307.o
+obj-$(CONFIG_DRM_PANEL_RENESAS_R69328) += panel-renesas-r69328.o
 obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01) += panel-samsung-ams581vf01.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08) += panel-samsung-ams639rq08.o
diff --git a/drivers/gpu/drm/panel/panel-renesas-r69328.c 
b/drivers/gpu/drm/panel/panel-renesas-r69328.c
new file mode 100644
index ..207067b29473
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-renesas-r69328.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+
+#define R69328_MACP0xb0 /* Manufacturer Access CMD Protect */
+#define   R69328_MACP_ON   0x03
+#define   R69328_MACP_OFF  0x04
+
+#define R69328_GAMMA_SET_A 0xc8 /* Gamma Setting A */
+#define R69328_GAMMA_SET_B 0xc9 /* Gamma Setting B */
+#define R69328_GAMMA_SET_C 0xca /* Gamma Setting C */
+
+#define R69328_POWER_SET   0xd1
+
+struct renesas_r69328 {
+   struct drm_panel panel;
+   struct mipi_dsi_device *dsi;
+
+   struct regulator *vdd_supply;
+   struct regulator *vddio_supply;
+   struct gpio_desc *reset_gpio;
+
+   bool prepared;
+};
+
+static inline struct renesas_r69328 *to_renesas_r69328(struct drm_panel *panel)
+{
+   return container_of(panel, struct renesas_r69328, panel);
+}
+
+static void renesas_r69328_reset(struct renesas_r69328 *priv)
+{
+   gpiod_set_value_cansleep(priv->reset_gpio, 1);
+   usleep_range(1, 11000);
+   gpiod_set_value_cansleep(priv->reset_gpio, 0);
+   usleep_range(2000, 3000);
+}
+
+static int renesas_r69328_prepare(struct drm_panel *panel)
+{
+   struct renesas_r69328 *priv = to_renesas_r69328(panel);
+   struct device *dev = &priv->dsi->dev;
+   int ret;
+
+   if (priv->prepared)
+   return 0;
+
+   ret = regulator_enable(priv->vdd_supply);
+   if (ret) {
+   dev_err(dev, "failed to enable vdd power supply\n");
+   return ret;
+   }
+
+   usleep_range(1, 11000);
+
+   ret = regulator_enable(priv->vddio_supply);
+   if (ret < 0) {
+   dev_err(dev, "failed to enable vddio power supply\n");
+   return ret;
+   }
+
+   usleep_range(1, 11000);
+
+   renesas_r69328_reset(priv);
+
+   priv->prepared = true;
+   return 0;
+}
+
+static int renesas_r69328_enable(struct drm_panel *panel)
+{
+   struct renesas_r69328 *priv = to_renesas_r69328(panel);
+   struct mipi_dsi_multi_context ctx = { .dsi = priv->dsi };
+
+   /* Set address mode */
+   mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
+   mipi_dsi_dcs_set_pixel_format_multi(&ctx, MIPI_DCS_PIXEL_FMT_24BIT << 
4);
+   mipi_dsi_dcs_exit_sleep_mode_multi(&ctx);
+
+   mipi_dsi_msleep(&ctx, 100);
+
+   /* MACP Off */
+   mip

Re: [lvc-project] [PATCH] drm/amdgpu: check a user-provided number of BOs in list

[Fedor Pchelkin]

On Thu, 10. Apr 11:07, Christian König wrote:
> Am 09.04.25 um 19:27 schrieb Linus Torvalds:
> > The VM layer allows larger allocations. But the "this is a simple
> > allocation, choose kmalloc or vmalloc automatically based on size"
> > helper says "you are being simple, I'm going to check your arguments
> > are actually sane".
> >
> > So the drm code can easily have a function that validates the input
> > for your specific cases, and then you (a) don't need the helper
> > function that does the overflow protection and (b) don't want it.
> >
> > But it should actually validate arguments for real sanity at that
> > point. Not just open-code kvmalloc() without the sanity check.
> 
> Yeah, exactly that has been proposed by driver maintainers before and we just 
> rejected it on the subsystem maintainers level.
> 
> For this particular use case here I will propose some hopefully high enough 
> hard coded limit, but I can't guarantee that this will work for all use cases.

FWIW, the current code anyway has this limit being some sort of 4Gb, not
more.

The resulting calculation of `bytes` wraps at 32 bits albeit itself being
of type *unsigned long*.

/* copy the handle array from userspace to a kernel buffer */
r = -EFAULT;
if (likely(info_size == in->bo_info_size)) {
unsigned long bytes = in->bo_number *
in->bo_info_size;

if (copy_from_user(info, uptr, bytes))
goto error_free;

Re: [PATCH 2/7] drm/bridge: analogix_dp: drop unused argument to analogix_dp_prepare_panel()

[Damon Ding]

Hi Dmitry,

On 2025/4/1 13:11, Dmitry Baryshkov wrote:

After previous cleanup all calling sites pass true as is_modeset_prepare
argument to analogix_dp_prepare_panel(). Drop dead code depending on
that argument being false.

Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 19 +--
  1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 
ab1cfc340aa95bbf13fe021bd33227b565a5458d..82dc4b01806f9728dc882b0128171838e81f21b0
 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -963,13 +963,13 @@ static int analogix_dp_disable_psr(struct 
analogix_dp_device *dp)
   * If @prepare is true, this function will prepare the panel. Conversely, if 
it
   * is false, the panel will be unprepared.
   *
- * If @is_modeset_prepare is true, the function will disregard the current 
state
+ * The function will disregard the current state
   * of the panel and either prepare/unprepare the panel based on @prepare. Once
   * it finishes, it will update dp->panel_is_modeset to reflect the current 
state
   * of the panel.
   */
  static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
-bool prepare, bool is_modeset_prepare)
+bool prepare)
  {
int ret = 0;
  
@@ -978,13 +978,6 @@ static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
  
  	mutex_lock(&dp->panel_lock);
  
-	/*

-* Exit early if this is a temporary prepare/unprepare and we're already
-* modeset (since we neither want to prepare twice or unprepare early).
-*/
-   if (dp->panel_is_modeset && !is_modeset_prepare)
-   goto out;
-
if (prepare)
ret = drm_panel_prepare(dp->plat_data->panel);
else
@@ -993,8 +986,7 @@ static int analogix_dp_prepare_panel(struct 
analogix_dp_device *dp,
if (ret)
goto out;
  
-	if (is_modeset_prepare)

-   dp->panel_is_modeset = prepare;
+   dp->panel_is_modeset = prepare;
  
  out:

mutex_unlock(&dp->panel_lock);
@@ -1072,7 +1064,6 @@ analogix_dp_detect(struct drm_connector *connector, bool 
force)
  {
struct analogix_dp_device *dp = to_dp(connector);
enum drm_connector_status status = connector_status_disconnected;
-   int ret;
  
  	if (dp->plat_data->panel)

return connector_status_connected;
@@ -1194,7 +1185,7 @@ static void analogix_dp_bridge_atomic_pre_enable(struct 
drm_bridge *bridge,
if (old_crtc_state && old_crtc_state->self_refresh_active)
return;
  
-	ret = analogix_dp_prepare_panel(dp, true, true);

+   ret = analogix_dp_prepare_panel(dp, true);
if (ret)
DRM_ERROR("failed to setup the panel ret = %d\n", ret);
  }
@@ -1294,7 +1285,7 @@ static void analogix_dp_bridge_disable(struct drm_bridge 
*bridge)
  
  	pm_runtime_put_sync(dp->dev);
  
-	ret = analogix_dp_prepare_panel(dp, false, true);

+   ret = analogix_dp_prepare_panel(dp, false);
if (ret)
DRM_ERROR("failed to setup the panel ret = %d\n", ret);
  



The patch has been verified with the eDP panel "lg,lp079qx1-sp0v" in 
RK3588S EVB1 board.


Tested-by: Damon Ding 

Best regards,
Damon

Re: [PATCH 3/7] drm/bridge: analogic_dp: drop panel_is_modeset

[Damon Ding]

Hi Dmitry,

On 2025/4/1 13:11, Dmitry Baryshkov wrote:

The dp->panel_is_modeset is now a write-only field. Drop it completely.

Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +--
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  1 -
  2 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 
82dc4b01806f9728dc882b0128171838e81f21b0..704c6169116eb2601d2ad02dc7294455ceff5460
 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -964,9 +964,7 @@ static int analogix_dp_disable_psr(struct 
analogix_dp_device *dp)
   * is false, the panel will be unprepared.
   *
   * The function will disregard the current state
- * of the panel and either prepare/unprepare the panel based on @prepare. Once
- * it finishes, it will update dp->panel_is_modeset to reflect the current 
state
- * of the panel.
+ * of the panel and either prepare/unprepare the panel based on @prepare.
   */
  static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
 bool prepare)
@@ -983,12 +981,6 @@ static int analogix_dp_prepare_panel(struct 
analogix_dp_device *dp,
else
ret = drm_panel_unprepare(dp->plat_data->panel);
  
-	if (ret)

-   goto out;
-
-   dp->panel_is_modeset = prepare;
-
-out:
mutex_unlock(&dp->panel_lock);
return ret;
  }
@@ -1532,7 +1524,6 @@ analogix_dp_probe(struct device *dev, struct 
analogix_dp_plat_data *plat_data)
dp->dpms_mode = DRM_MODE_DPMS_OFF;
  
  	mutex_init(&dp->panel_lock);

-   dp->panel_is_modeset = false;
  
  	/*

 * platform dp driver need containor_of the plat_data to get
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 
774d11574b095b093ddf2818ad5b84be6605c9bf..b679d5b71d276f458d905c936160f107225bc6c5
 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -170,7 +170,6 @@ struct analogix_dp_device {
boolpsr_supported;
  
  	struct mutex		panel_lock;

-   boolpanel_is_modeset;
  
  	struct analogix_dp_plat_data *plat_data;

  };



The patch has been verified with the eDP panel "lg,lp079qx1-sp0v" in 
RK3588S EVB1 board.


Tested-by: Damon Ding 

Best regards,
Damon

[PATCH RESEND] drm/amd/pm/powerplay/smumgr/fiji_smumgr: Fix wrong return value of fiji_populate_smc_boot_level()

[Wentao Liang]

The return value of fiji_populate_smc_boot_level() is always 0, which
represent the failure of the function. The result of phm_find_boot_level()
should be recored and return. An error handling is also needed to
phm_find_boot_level() to reset the boot level when the function fails.
A proper implementation can be found in tonga_populate_smc_boot_level().

Fixes: dcaf3483ae46 ("drm/amd/pm/powerplay/smumgr/fiji_smumgr: Remove unused 
variable 'result'")
Signed-off-by: Wentao Liang 
---
 .../drm/amd/pm/powerplay/smumgr/fiji_smumgr.c | 23 +--
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
index 5e43ad2b2956..7d0cb3741b94 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
@@ -1600,19 +1600,28 @@ static int fiji_populate_smc_uvd_level(struct pp_hwmgr 
*hwmgr,
 static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
struct SMU73_Discrete_DpmTable *table)
 {
+   int result = 0;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
table->GraphicsBootLevel = 0;
table->MemoryBootLevel = 0;
 
/* find boot level from dpm table */
-   phm_find_boot_level(&(data->dpm_table.sclk_table),
-   data->vbios_boot_state.sclk_bootup_value,
-   (uint32_t *)&(table->GraphicsBootLevel));
+   result = phm_find_boot_level(&(data->dpm_table.sclk_table),
+data->vbios_boot_state.sclk_bootup_value,
+(uint32_t *)&(table->GraphicsBootLevel));
+   if (result) {
+   table->GraphicsBootLevel = 0;
+   return 0;
+   }
 
-   phm_find_boot_level(&(data->dpm_table.mclk_table),
-   data->vbios_boot_state.mclk_bootup_value,
-   (uint32_t *)&(table->MemoryBootLevel));
+   result = phm_find_boot_level(&(data->dpm_table.mclk_table),
+data->vbios_boot_state.mclk_bootup_value,
+(uint32_t *)&(table->MemoryBootLevel));
+   if (result) {
+   table->MemoryBootLevel = 0;
+   return 0;
+   }
 
table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
VOLTAGE_SCALE;
@@ -1625,7 +1634,7 @@ static int fiji_populate_smc_boot_level(struct pp_hwmgr 
*hwmgr,
CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
 
-   return 0;
+   return result;
 }
 
 static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
-- 
2.42.0.windows.2

Re: [PATCH 01/10] drm/imagination: avoid unused-const-variable warning

[Andy Shevchenko]

On Thu, Apr 10, 2025 at 11:22:05AM +, Matt Coster wrote:
> On 09/04/2025 13:22, Arnd Bergmann wrote:

...

> > Rather than adding more #ifdef blocks, address this by changing the
> > existing #ifdef into equivalent IS_ENABLED() checks so gcc can see
> > where the symbol is used but still eliminate it from the object file.
> 
> Possibly a silly question, but wouldn't adding __maybe_unused to
> stid_fmts be a simpler change here?

I'm not Arnd (and I just have read his answer), but I would like to add that
__maybe_unused should be the last resort as it has more cons than more invasive
solutions. In particular, it makes build time increase with a lot of work to
be made at link time, and also it might hide the real bugs when somebody simply
forgot to use it (depending on the configuration options) or so.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v1 1/3] drm: function to get process name and pid

[Khatri, Sunil]

Ping?

On 4/11/2025 6:34 PM, Sunil Khatri wrote:

Add helper function which get the process information for
the drm_file and updates the user provided character buffer
with the information of process name and pid as a string.

Signed-off-by: Sunil Khatri 
---
  drivers/gpu/drm/drm_file.c | 30 ++
  include/drm/drm_file.h |  1 +
  2 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c
index cb5f22f5bbb6..4434258d21b5 100644
--- a/drivers/gpu/drm/drm_file.c
+++ b/drivers/gpu/drm/drm_file.c
@@ -965,6 +965,36 @@ void drm_show_fdinfo(struct seq_file *m, struct file *f)
  }
  EXPORT_SYMBOL(drm_show_fdinfo);
  
+/**

+ * drm_process_info - Fill info string with process name and pid
+ * @file_priv: context of interest for process name and pid
+ * @proc_info: user char ptr to write the string to
+ * @buff_size: size of the buffer passed for the string
+ *
+ * This update the user provided buffer with process
+ * name and pid information for @file_priv
+ */
+void drm_process_info(struct drm_file *file_priv, char *proc_info, size_t 
buff_size)
+{
+   struct task_struct *task;
+   struct pid *pid;
+   struct drm_device *dev = file_priv->minor->dev;
+
+   if (!proc_info) {
+   drm_err(dev, "Invalid user buffer\n");
+   return;
+   }
+
+   rcu_read_lock();
+   pid = rcu_dereference(file_priv->pid);
+   task = pid_task(pid, PIDTYPE_TGID);
+   if (task)
+   snprintf(proc_info, buff_size, "comm:%s pid:%d", task->comm, 
task->pid);
+
+   rcu_read_unlock();
+}
+EXPORT_SYMBOL(drm_process_info);
+
  /**
   * mock_drm_getfile - Create a new struct file for the drm device
   * @minor: drm minor to wrap (e.g. #drm_device.primary)
diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
index f0ef32e9fa5e..c01b34936968 100644
--- a/include/drm/drm_file.h
+++ b/include/drm/drm_file.h
@@ -501,6 +501,7 @@ void drm_print_memory_stats(struct drm_printer *p,
  
  void drm_show_memory_stats(struct drm_printer *p, struct drm_file *file);

  void drm_show_fdinfo(struct seq_file *m, struct file *f);
+void drm_process_info(struct drm_file *file_priv, char *proc_info, size_t 
buff_size);
  
  struct file *mock_drm_getfile(struct drm_minor *minor, unsigned int flags);
  

[PATCH 1/7] drm/msm: move wq handling to KMS code

[Dmitry Baryshkov]

The global workqueue is only used for vblanks inside KMS code. Move
allocation / flushing / deallcation of it to msm_kms.c

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/msm_drv.c | 21 ++---
 drivers/gpu/drm/msm/msm_kms.c | 16 +++-
 2 files changed, 17 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 
c3588dc9e53764a27efda1901b094724cec8928a..02beb40eb9146941aa43862d07a6d82ae21c965e
 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -82,13 +82,6 @@ static int msm_drm_uninit(struct device *dev)
drm_atomic_helper_shutdown(ddev);
}
 
-   /* We must cancel and cleanup any pending vblank enable/disable
-* work before msm_irq_uninstall() to avoid work re-enabling an
-* irq after uninstall has disabled it.
-*/
-
-   flush_workqueue(priv->wq);
-
msm_gem_shrinker_cleanup(ddev);
 
msm_perf_debugfs_cleanup(priv);
@@ -104,8 +97,6 @@ static int msm_drm_uninit(struct device *dev)
ddev->dev_private = NULL;
drm_dev_put(ddev);
 
-   destroy_workqueue(priv->wq);
-
return 0;
 }
 
@@ -227,12 +218,6 @@ static int msm_drm_init(struct device *dev, const struct 
drm_driver *drv)
ddev->dev_private = priv;
priv->dev = ddev;
 
-   priv->wq = alloc_ordered_workqueue("msm", 0);
-   if (!priv->wq) {
-   ret = -ENOMEM;
-   goto err_put_dev;
-   }
-
INIT_LIST_HEAD(&priv->objects);
mutex_init(&priv->obj_lock);
 
@@ -253,12 +238,12 @@ static int msm_drm_init(struct device *dev, const struct 
drm_driver *drv)
if (priv->kms_init) {
ret = drmm_mode_config_init(ddev);
if (ret)
-   goto err_destroy_wq;
+   goto err_put_dev;
}
 
ret = msm_init_vram(ddev);
if (ret)
-   goto err_destroy_wq;
+   goto err_put_dev;
 
dma_set_max_seg_size(dev, UINT_MAX);
 
@@ -304,8 +289,6 @@ static int msm_drm_init(struct device *dev, const struct 
drm_driver *drv)
 
 err_deinit_vram:
msm_deinit_vram(ddev);
-err_destroy_wq:
-   destroy_workqueue(priv->wq);
 err_put_dev:
drm_dev_put(ddev);
 
diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
index 
35d5397e73b4c5cb90b1770e8570277e782be7ec..821f0b9f968fc3d448e612bfae04639ceb770353
 100644
--- a/drivers/gpu/drm/msm/msm_kms.c
+++ b/drivers/gpu/drm/msm/msm_kms.c
@@ -227,6 +227,13 @@ void msm_drm_kms_uninit(struct device *dev)
 
BUG_ON(!kms);
 
+   /* We must cancel and cleanup any pending vblank enable/disable
+* work before msm_irq_uninstall() to avoid work re-enabling an
+* irq after uninstall has disabled it.
+*/
+
+   flush_workqueue(priv->wq);
+
/* clean up event worker threads */
for (i = 0; i < priv->num_crtcs; i++) {
if (priv->event_thread[i].worker)
@@ -243,6 +250,8 @@ void msm_drm_kms_uninit(struct device *dev)
 
if (kms && kms->funcs)
kms->funcs->destroy(kms);
+
+   destroy_workqueue(priv->wq);
 }
 
 int msm_drm_kms_init(struct device *dev, const struct drm_driver *drv)
@@ -258,10 +267,14 @@ int msm_drm_kms_init(struct device *dev, const struct 
drm_driver *drv)
if (ret)
return ret;
 
+   priv->wq = alloc_ordered_workqueue("msm", 0);
+   if (!priv->wq)
+   return -ENOMEM;
+
ret = priv->kms_init(ddev);
if (ret) {
DRM_DEV_ERROR(dev, "failed to load kms\n");
-   return ret;
+   goto err_msm_uninit;
}
 
/* Enable normalization of plane zpos */
@@ -319,6 +332,7 @@ int msm_drm_kms_init(struct device *dev, const struct 
drm_driver *drv)
return 0;
 
 err_msm_uninit:
+   destroy_workqueue(priv->wq);
return ret;
 }
 

-- 
2.39.5

[PATCH 6/7] drm/msm: rework binding of Imageon GPUs

[Dmitry Baryshkov]

Currently the msm driver creates an extra interim platform device for
Imageon GPUs. This is not ideal, as the device doesn't have
corresponding OF node. If the headless mode is used for newer GPUs, then
the msm_use_mmu() function can not detect corresponding IOMMU devices.
Also the DRM device (although it's headless) is created with modesetting
flags being set.

To solve all these issues, rework the way the Imageon devices are bound.
Remove the interim device, don't register a component and instead use a
cut-down version of the normal functions to probe or remove the driver.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 36 +++-
 drivers/gpu/drm/msm/msm_drv.c  | 91 --
 drivers/gpu/drm/msm/msm_drv.h  |  4 ++
 3 files changed, 72 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c 
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 
236b25c094cd5d462f4b6653de7b7910985cccb6..325cb710ea08ac8e5c3d9c80c8d8e18e1946e994
 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -241,42 +241,22 @@ static const struct component_ops a3xx_ops = {
.unbind = adreno_unbind,
 };
 
-static void adreno_device_register_headless(void)
-{
-   /* on imx5, we don't have a top-level mdp/dpu node
-* this creates a dummy node for the driver for that case
-*/
-   struct platform_device_info dummy_info = {
-   .parent = NULL,
-   .name = "msm",
-   .id = -1,
-   .res = NULL,
-   .num_res = 0,
-   .data = NULL,
-   .size_data = 0,
-   .dma_mask = ~0,
-   };
-   platform_device_register_full(&dummy_info);
-}
-
 static int adreno_probe(struct platform_device *pdev)
 {
-
-   int ret;
-
-   ret = component_add(&pdev->dev, &a3xx_ops);
-   if (ret)
-   return ret;
-
if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
-   adreno_device_register_headless();
+   return msm_gpu_probe(pdev, &a3xx_ops);
 
-   return 0;
+   return component_add(&pdev->dev, &a3xx_ops);
 }
 
 static void adreno_remove(struct platform_device *pdev)
 {
-   component_del(&pdev->dev, &a3xx_ops);
+   struct msm_drm_private *priv = platform_get_drvdata(pdev);
+
+   if (priv->kms_init)
+   component_del(&pdev->dev, &a3xx_ops);
+   else
+   msm_gpu_remove(pdev, &a3xx_ops);
 }
 
 static void adreno_shutdown(struct platform_device *pdev)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 
b296d1315aa249638e073d08d43e8d41a4354f3b..e5c1124d45fa146c91caaad39a39fb9d21e5f5f3
 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -62,7 +62,7 @@ module_param(modeset, bool, 0600);
 DECLARE_FAULT_ATTR(fail_gem_alloc);
 DECLARE_FAULT_ATTR(fail_gem_iova);
 
-static int msm_drm_uninit(struct device *dev)
+static int msm_drm_uninit(struct device *dev, const struct component_ops 
*gpu_ops)
 {
struct platform_device *pdev = to_platform_device(dev);
struct msm_drm_private *priv = platform_get_drvdata(pdev);
@@ -91,7 +91,10 @@ static int msm_drm_uninit(struct device *dev)
 
msm_deinit_vram(ddev);
 
-   component_unbind_all(dev, ddev);
+   if (gpu_ops)
+   gpu_ops->unbind(dev, dev, NULL);
+   else
+   component_unbind_all(dev, ddev);
 
ddev->dev_private = NULL;
drm_dev_put(ddev);
@@ -200,7 +203,8 @@ static void msm_deinit_vram(struct drm_device *ddev)
attrs);
 }
 
-static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
+static int msm_drm_init(struct device *dev, const struct drm_driver *drv,
+   const struct component_ops *gpu_ops)
 {
struct msm_drm_private *priv = dev_get_drvdata(dev);
struct drm_device *ddev;
@@ -247,7 +251,10 @@ static int msm_drm_init(struct device *dev, const struct 
drm_driver *drv)
dma_set_max_seg_size(dev, UINT_MAX);
 
/* Bind all our sub-components: */
-   ret = component_bind_all(dev, ddev);
+   if (gpu_ops)
+   ret = gpu_ops->bind(dev, dev, NULL);
+   else
+   ret = component_bind_all(dev, ddev);
if (ret)
goto err_deinit_vram;
 
@@ -259,11 +266,6 @@ static int msm_drm_init(struct device *dev, const struct 
drm_driver *drv)
ret = msm_drm_kms_init(dev, drv);
if (ret)
goto err_msm_uninit;
-   } else {
-   /* valid only for the dummy headless case, where of_node=NULL */
-   WARN_ON(dev->of_node);
-   ddev->driver_features &= ~DRIVER_MODESET;
-   ddev->driver_features &= ~DRIVER_ATOMIC;
}
 
ret = drm_dev_register(ddev, 0);
@@ -280,7 +282,7

[PATCH 5/7] drm/msm: rearrange symbol selection

[Dmitry Baryshkov]

Move symbol selection to be more fine grained: select DP helpers only if
DP driver is also enabled, move KMS and display helpers to the newly
introduced DRM_MSM_KMS.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/Kconfig | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 
0be31c5acdd1b7ef80f0e820ff430692616122e0..b3c6117ab035764d603cc257c28df651d9c38175
 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -15,18 +15,8 @@ config DRM_MSM
select IOMMU_IO_PGTABLE
select QCOM_MDT_LOADER if ARCH_QCOM
select REGULATOR
-   select DRM_CLIENT_SELECTION
-   select DRM_DISPLAY_DP_AUX_BUS
-   select DRM_DISPLAY_DP_HELPER
-   select DRM_DISPLAY_HELPER
-   select DRM_BRIDGE_CONNECTOR
select DRM_EXEC
-   select DRM_KMS_HELPER
-   select DRM_PANEL
-   select DRM_BRIDGE
-   select DRM_PANEL_BRIDGE
select DRM_SCHED
-   select FB_SYSMEM_HELPERS if DRM_FBDEV_EMULATION
select SHMEM
select TMPFS
select QCOM_SCM
@@ -69,10 +59,18 @@ config DRM_MSM_VALIDATE_XML
 config DRM_MSM_KMS
def_bool n
depends on DRM_MSM
+   select DRM_BRIDGE
+   select DRM_BRIDGE_CONNECTOR
+   select DRM_CLIENT_SELECTION
+   select DRM_DISPLAY_HELPER
+   select DRM_KMS_HELPER
+   select DRM_PANEL
+   select DRM_PANEL_BRIDGE
 
 config DRM_MSM_KMS_FBDEV
def_bool DRM_FBDEV_EMULATION
depends on DRM_MSM_KMS
+   select FB_SYSMEM_HELPERS
 
 config DRM_MSM_MDSS
bool
@@ -117,6 +115,8 @@ config DRM_MSM_DP
depends on DRM_MSM
depends on DRM_MSM_KMS
select RATIONAL
+   select DRM_DISPLAY_DP_AUX_BUS
+   select DRM_DISPLAY_DP_HELPER
default y
help
  Compile in support for DP driver in MSM DRM driver. DP external

-- 
2.39.5

[PATCH 4/7] drm/msm: bail out late_init_minor() if it is not a GPU device

[Dmitry Baryshkov]

Both perf and hangrd make sense only for GPU devices. Bail out if we are
registering a KMS-only device.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/msm_debugfs.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_debugfs.c 
b/drivers/gpu/drm/msm/msm_debugfs.c
index 
2b12f2851fadbc3c924827e11570352736869614..6e60a74b13d72c47e45cb9dc65ed67b977e900fa
 100644
--- a/drivers/gpu/drm/msm/msm_debugfs.c
+++ b/drivers/gpu/drm/msm/msm_debugfs.c
@@ -296,11 +296,16 @@ static struct drm_info_list msm_debugfs_list[] = {
 
 static int late_init_minor(struct drm_minor *minor)
 {
+   struct drm_device *dev = minor->dev;
+   struct msm_drm_private *priv = dev->dev_private;
int ret;
 
if (!minor)
return 0;
 
+   if (!priv->gpu_pdev)
+   return 0;
+
ret = msm_rd_debugfs_init(minor);
if (ret) {
DRM_DEV_ERROR(minor->dev->dev, "could not install rd 
debugfs\n");

-- 
2.39.5

[PATCH 2/7] drm/msm: move helper calls to msm_kms.c

[Dmitry Baryshkov]

Extract two more KMS-related codepieces to msm_kms.c, removing last
pieces of KMS code from msm_drv.c.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/msm_drv.c |  9 +++--
 drivers/gpu/drm/msm/msm_kms.c | 20 
 drivers/gpu/drm/msm/msm_kms.h |  2 ++
 3 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 
02beb40eb9146941aa43862d07a6d82ae21c965e..b296d1315aa249638e073d08d43e8d41a4354f3b
 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -11,7 +11,6 @@
 #include 
 #include 
 
-#include 
 #include 
 #include 
 #include 
@@ -79,7 +78,7 @@ static int msm_drm_uninit(struct device *dev)
if (ddev->registered) {
drm_dev_unregister(ddev);
if (priv->kms)
-   drm_atomic_helper_shutdown(ddev);
+   msm_drm_kms_unregister(dev);
}
 
msm_gem_shrinker_cleanup(ddev);
@@ -275,10 +274,8 @@ static int msm_drm_init(struct device *dev, const struct 
drm_driver *drv)
if (ret)
goto err_msm_uninit;
 
-   if (priv->kms_init) {
-   drm_kms_helper_poll_init(ddev);
-   drm_client_setup(ddev, NULL);
-   }
+   if (priv->kms_init)
+   msm_drm_kms_post_init(dev);
 
return 0;
 
diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
index 
821f0b9f968fc3d448e612bfae04639ceb770353..fdb22c41bdc1a772b45c6940dda787dd96879bc2
 100644
--- a/drivers/gpu/drm/msm/msm_kms.c
+++ b/drivers/gpu/drm/msm/msm_kms.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "disp/msm_disp_snapshot.h"
 #include "msm_drv.h"
@@ -217,6 +218,15 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct 
drm_device *dev)
return aspace;
 }
 
+void msm_drm_kms_unregister(struct device *dev)
+{
+   struct platform_device *pdev = to_platform_device(dev);
+   struct msm_drm_private *priv = platform_get_drvdata(pdev);
+   struct drm_device *ddev = priv->dev;
+
+   drm_atomic_helper_shutdown(ddev);
+}
+
 void msm_drm_kms_uninit(struct device *dev)
 {
struct platform_device *pdev = to_platform_device(dev);
@@ -373,3 +383,13 @@ void msm_kms_shutdown(struct platform_device *pdev)
if (drm && drm->registered && priv->kms)
drm_atomic_helper_shutdown(drm);
 }
+
+void msm_drm_kms_post_init(struct device *dev)
+{
+   struct platform_device *pdev = to_platform_device(dev);
+   struct msm_drm_private *priv = platform_get_drvdata(pdev);
+   struct drm_device *ddev = priv->dev;
+
+   drm_kms_helper_poll_init(ddev);
+   drm_client_setup(ddev, NULL);
+}
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 
43b58d052ee6aae0ce34d09c88e1e1c34f9c52ef..057b20367724a4ca60f2d60c038077dbcc1c7abc
 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -192,6 +192,8 @@ static inline void msm_kms_destroy(struct msm_kms *kms)
for_each_if (drm_crtc_mask(crtc) & (crtc_mask))
 
 int msm_drm_kms_init(struct device *dev, const struct drm_driver *drv);
+void msm_drm_kms_post_init(struct device *dev);
+void msm_drm_kms_unregister(struct device *dev);
 void msm_drm_kms_uninit(struct device *dev);
 
 #endif /* __MSM_KMS_H__ */

-- 
2.39.5

[PATCH 7/7] drm/msm: enable separate binding of GPU and display devices

[Dmitry Baryshkov]

There are cases when we want to have separate DRM devices for GPU and
display pipelines.
One example is development, when it is beneficial to be able to bind the
GPU driver separately, without the display pipeline (and without the
hacks adding "amd,imageon" to the compatible string).
Another example is some of Qualcomm platforms, which have two MDSS
units, but only one GPU. With current approach it is next to impossible
to support this usecase properly, while separate binding allows users to
have three DRM devices: two for MDSS units and a single headless GPU.

Add kernel param msm.separate_gpu_drm, which if set to true forces
creation of separate display and GPU DRM devices. Mesa supports this
setup by using the kmsro wrapper.

The param is disabled by default, in order to be able to test userspace
for the compatibility issues. Simple clients are able to handle this
setup automatically.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/adreno/adreno_device.c |  3 +-
 drivers/gpu/drm/msm/msm_drv.c  | 49 +++---
 drivers/gpu/drm/msm/msm_drv.h  |  2 ++
 3 files changed, 49 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c 
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 
325cb710ea08ac8e5c3d9c80c8d8e18e1946e994..2322a3301a5226c4e2590344e4744934addeea33
 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -243,7 +243,8 @@ static const struct component_ops a3xx_ops = {
 
 static int adreno_probe(struct platform_device *pdev)
 {
-   if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
+   if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") ||
+   msm_gpu_no_components())
return msm_gpu_probe(pdev, &a3xx_ops);
 
return component_add(&pdev->dev, &a3xx_ops);
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 
e5c1124d45fa146c91caaad39a39fb9d21e5f5f3..4502425d0a62e1efaca5b987fa5b657dc0a4e927
 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -59,9 +59,18 @@ static bool modeset = true;
 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 
0=disable)");
 module_param(modeset, bool, 0600);
 
+static bool separate_gpu_drm;
+MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU 
(0=single DRM device for both GPU and display (default), 1=two DRM devices)");
+module_param(separate_gpu_drm, bool, 0400);
+
 DECLARE_FAULT_ATTR(fail_gem_alloc);
 DECLARE_FAULT_ATTR(fail_gem_iova);
 
+bool msm_gpu_no_components(void)
+{
+   return separate_gpu_drm;
+}
+
 static int msm_drm_uninit(struct device *dev, const struct component_ops 
*gpu_ops)
 {
struct platform_device *pdev = to_platform_device(dev);
@@ -898,6 +907,32 @@ static const struct drm_driver msm_driver = {
.patchlevel = MSM_VERSION_PATCHLEVEL,
 };
 
+static const struct drm_driver msm_kms_driver = {
+   .driver_features= DRIVER_GEM |
+   DRIVER_ATOMIC |
+   DRIVER_MODESET |
+   DRIVER_SYNCOBJ_TIMELINE |
+   DRIVER_SYNCOBJ,
+   .open   = msm_open,
+   .postclose  = msm_postclose,
+   .dumb_create= msm_gem_dumb_create,
+   .dumb_map_offset= msm_gem_dumb_map_offset,
+   .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
+#ifdef CONFIG_DEBUG_FS
+   .debugfs_init   = msm_debugfs_init,
+#endif
+   MSM_FBDEV_DRIVER_OPS,
+   .show_fdinfo= msm_show_fdinfo,
+   .ioctls = msm_ioctls,
+   .num_ioctls = ARRAY_SIZE(msm_ioctls),
+   .fops   = &fops,
+   .name   = "msm-kms",
+   .desc   = "MSM Snapdragon DRM",
+   .major  = MSM_VERSION_MAJOR,
+   .minor  = MSM_VERSION_MINOR,
+   .patchlevel = MSM_VERSION_PATCHLEVEL,
+};
+
 static const struct drm_driver msm_gpu_driver = {
.driver_features= DRIVER_GEM |
DRIVER_RENDER |
@@ -1044,7 +1079,11 @@ static int add_gpu_components(struct device *dev,
 
 static int msm_drm_bind(struct device *dev)
 {
-   return msm_drm_init(dev, &msm_driver, NULL);
+   return msm_drm_init(dev,
+   msm_gpu_no_components() ?
+   &msm_kms_driver :
+   &msm_driver,
+   NULL);
 }
 
 static void msm_drm_unbind(struct device *dev)
@@ -1080,9 +1119,11 @@ int msm_drv_probe(struct device *master_dev,
return ret;
}
 
-   ret = add_gpu_components(master_dev, &match);
-   if (ret)
-   return ret;
+   if (!msm_gpu_no_components()) {
+   ret = add_gpu_components(master_dev, &match);
+   if 

[PATCH 2/2] drm: qxl: Remove unused debugfs code

[linux]

From: "Dr. David Alan Gilbert" 

qxl_debugfs_add_files() has been unused since 2022's
commit d0719e09264b ("drm/qxl: Use TTM builtin resource manager debugfs
code")

Remove it.

This now leaves the debugfs_count and debugfs members of struct
qxl_device unused.  Remove them.

QXL_DEBUGFS_MAX_COMPONENTS was only used as the size of the debugfs[]
array.  Remove it.

Signed-off-by: Dr. David Alan Gilbert 
---
 drivers/gpu/drm/qxl/qxl_debugfs.c | 29 -
 drivers/gpu/drm/qxl/qxl_drv.h | 10 --
 2 files changed, 39 deletions(-)

diff --git a/drivers/gpu/drm/qxl/qxl_debugfs.c 
b/drivers/gpu/drm/qxl/qxl_debugfs.c
index 2d9ed3b94574..bdfce1a8f006 100644
--- a/drivers/gpu/drm/qxl/qxl_debugfs.c
+++ b/drivers/gpu/drm/qxl/qxl_debugfs.c
@@ -95,32 +95,3 @@ qxl_debugfs_init(struct drm_minor *minor)
qxl_ttm_debugfs_init(dev);
 #endif
 }
-
-void qxl_debugfs_add_files(struct qxl_device *qdev,
-  struct drm_info_list *files,
-  unsigned int nfiles)
-{
-   unsigned int i;
-
-   for (i = 0; i < qdev->debugfs_count; i++) {
-   if (qdev->debugfs[i].files == files) {
-   /* Already registered */
-   return;
-   }
-   }
-
-   i = qdev->debugfs_count + 1;
-   if (i > QXL_DEBUGFS_MAX_COMPONENTS) {
-   DRM_ERROR("Reached maximum number of debugfs components.\n");
-   DRM_ERROR("Report so we increase 
QXL_DEBUGFS_MAX_COMPONENTS.\n");
-   return;
-   }
-   qdev->debugfs[qdev->debugfs_count].files = files;
-   qdev->debugfs[qdev->debugfs_count].num_files = nfiles;
-   qdev->debugfs_count = i;
-#if defined(CONFIG_DEBUG_FS)
-   drm_debugfs_create_files(files, nfiles,
-qdev->ddev.primary->debugfs_root,
-qdev->ddev.primary);
-#endif
-}
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index a6184aaebf62..ea977c238b27 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.h
+++ b/drivers/gpu/drm/qxl/qxl_drv.h
@@ -59,8 +59,6 @@ struct iosys_map;
 #define DRIVER_MINOR 1
 #define DRIVER_PATCHLEVEL 0
 
-#define QXL_DEBUGFS_MAX_COMPONENTS 32
-
 extern int qxl_num_crtc;
 
 #define QXL_INTERRUPT_MASK (\
@@ -227,10 +225,6 @@ struct qxl_device {
wait_queue_head_t io_cmd_event;
struct work_struct client_monitors_config_work;
 
-   /* debugfs */
-   struct qxl_debugfs  debugfs[QXL_DEBUGFS_MAX_COMPONENTS];
-   unsigned int debugfs_count;
-
struct mutexupdate_area_mutex;
 
struct idr  surf_id_idr;
@@ -423,10 +417,6 @@ void qxl_gem_prime_vunmap(struct drm_gem_object *obj,
 /* qxl_irq.c */
 int qxl_irq_init(struct qxl_device *qdev);
 
-void qxl_debugfs_add_files(struct qxl_device *qdev,
-  struct drm_info_list *files,
-  unsigned int nfiles);
-
 int qxl_surface_id_alloc(struct qxl_device *qdev,
 struct qxl_bo *surf);
 void qxl_surface_id_dealloc(struct qxl_device *qdev,
-- 
2.49.0

[PATCH 1/2] drm: qxl: Remove dead qxl_io_flush_* functions

[linux]

From: "Dr. David Alan Gilbert" 

qxl_io_flush_release() and qxl_io_flush_surfaces() were both added
in 2013's
commit f64122c1f6ad ("drm: add new QXL driver. (v1.4)")

but have remained unused.  Remove them.

Signed-off-by: Dr. David Alan Gilbert 
---
 drivers/gpu/drm/qxl/qxl_cmd.c | 10 --
 drivers/gpu/drm/qxl/qxl_drv.h |  2 --
 2 files changed, 12 deletions(-)

diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c
index d6ea01f3797b..1bdc5abf8dd1 100644
--- a/drivers/gpu/drm/qxl/qxl_cmd.c
+++ b/drivers/gpu/drm/qxl/qxl_cmd.c
@@ -356,16 +356,6 @@ void qxl_io_notify_oom(struct qxl_device *qdev)
outb(0, qdev->io_base + QXL_IO_NOTIFY_OOM);
 }
 
-void qxl_io_flush_release(struct qxl_device *qdev)
-{
-   outb(0, qdev->io_base + QXL_IO_FLUSH_RELEASE);
-}
-
-void qxl_io_flush_surfaces(struct qxl_device *qdev)
-{
-   wait_for_io_cmd(qdev, 0, QXL_IO_FLUSH_SURFACES_ASYNC);
-}
-
 void qxl_io_destroy_primary(struct qxl_device *qdev)
 {
wait_for_io_cmd(qdev, 0, QXL_IO_DESTROY_PRIMARY_ASYNC);
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index cc02b5f10ad9..a6184aaebf62 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.h
+++ b/drivers/gpu/drm/qxl/qxl_drv.h
@@ -355,8 +355,6 @@ int qxl_io_update_area(struct qxl_device *qdev, struct 
qxl_bo *surf,
 void qxl_io_reset(struct qxl_device *qdev);
 void qxl_io_monitors_config(struct qxl_device *qdev);
 int qxl_ring_push(struct qxl_ring *ring, const void *new_elt, bool 
interruptible);
-void qxl_io_flush_release(struct qxl_device *qdev);
-void qxl_io_flush_surfaces(struct qxl_device *qdev);
 
 union qxl_release_info *qxl_release_map(struct qxl_device *qdev,
struct qxl_release *release);
-- 
2.49.0

[PATCH 0/2] drm: qxl: Deadcoding

[linux]

From: "Dr. David Alan Gilbert" 

Hi,
  A couple of small deadcodings for qxl.  The first
just cleans up a couple of trivial unusued wrappers.
The second cleans out some debugfs code that's been unused
for a few years.

Dave
Signed-off-by: Dr. David Alan Gilbert 


Dr. David Alan Gilbert (2):
  drm: qxl: Remove dead qxl_io_flush_* functions
  drm: qxl: Remove unused debugfs code

 drivers/gpu/drm/qxl/qxl_cmd.c | 10 --
 drivers/gpu/drm/qxl/qxl_debugfs.c | 29 -
 drivers/gpu/drm/qxl/qxl_drv.h | 12 
 3 files changed, 51 deletions(-)

-- 
2.49.0

[PATCH 0/7] drm/msm: rework the ties between KMS and GPU parts of the driver

[Dmitry Baryshkov]

Currently the KMS and GPU parts of the msm driver are pretty much
intertwined. It is impossible to register a KMS-only device and
registering a GPU-only DRM device requires modifying the DT.  Not to
mention that binding the GPU-only device creates an interim platform
devices, which complicates IOMMU setup.

Rework the driver:
- Make it possible to disable KMS parts (if MDP4, MDP5 and DPU drivers
  are disabled).
- Register GPU-only devices without an interim platform device.
- Add module param that makes msm driver register GPU and KMS devices
  separately.

Signed-off-by: Dmitry Baryshkov 
---
Dmitry Baryshkov (7):
  drm/msm: move wq handling to KMS code
  drm/msm: move helper calls to msm_kms.c
  drm/msm: make it possible to disable KMS-related code.
  drm/msm: bail out late_init_minor() if it is not a GPU device
  drm/msm: rearrange symbol selection
  drm/msm: rework binding of Imageon GPUs
  drm/msm: enable separate binding of GPU and display devices

 drivers/gpu/drm/msm/Kconfig|  34 --
 drivers/gpu/drm/msm/Makefile   |  16 +--
 drivers/gpu/drm/msm/adreno/adreno_device.c |  39 ++-
 drivers/gpu/drm/msm/dp/dp_debug.c  |   4 +
 drivers/gpu/drm/msm/msm_debugfs.c  |  97 ++---
 drivers/gpu/drm/msm/msm_drv.c  | 168 +++--
 drivers/gpu/drm/msm/msm_drv.h  |  13 ++-
 drivers/gpu/drm/msm/msm_kms.c  |  36 ++-
 drivers/gpu/drm/msm/msm_kms.h  |  25 +
 9 files changed, 285 insertions(+), 147 deletions(-)
---
base-commit: a4e1d05abd6847ba11edf46734efecec86a1fe2c
change-id: 20250411-msm-gpu-split-2701e49e40f0

Best regards,
-- 
Dmitry Baryshkov 

[PATCH 3/7] drm/msm: make it possible to disable KMS-related code.

[Dmitry Baryshkov]

If the Adreno device is used in a headless mode, there is no need to
build all KMS components. Build corresponding parts conditionally, only
selecting them if modeset support is actually required.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/Kconfig   | 14 ++
 drivers/gpu/drm/msm/Makefile  | 16 +++
 drivers/gpu/drm/msm/dp/dp_debug.c |  4 ++
 drivers/gpu/drm/msm/msm_debugfs.c | 92 ++-
 drivers/gpu/drm/msm/msm_drv.h |  7 ++-
 drivers/gpu/drm/msm/msm_kms.h | 23 ++
 6 files changed, 108 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 
974bc7c0ea761147d3326bdce9039d6f26f290d0..0be31c5acdd1b7ef80f0e820ff430692616122e0
 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -66,6 +66,14 @@ config DRM_MSM_VALIDATE_XML
  Validate XML files with register definitions against rules-fd schema.
  This option is mostly targeting DRM MSM developers. If unsure, say N.
 
+config DRM_MSM_KMS
+   def_bool n
+   depends on DRM_MSM
+
+config DRM_MSM_KMS_FBDEV
+   def_bool DRM_FBDEV_EMULATION
+   depends on DRM_MSM_KMS
+
 config DRM_MSM_MDSS
bool
depends on DRM_MSM
@@ -74,6 +82,7 @@ config DRM_MSM_MDSS
 config DRM_MSM_MDP4
bool "Enable MDP4 support in MSM DRM driver"
depends on DRM_MSM
+   select DRM_MSM_KMS
default y
help
  Compile in support for the Mobile Display Processor v4 (MDP4) in
@@ -84,6 +93,7 @@ config DRM_MSM_MDP5
bool "Enable MDP5 support in MSM DRM driver"
depends on DRM_MSM
select DRM_MSM_MDSS
+   select DRM_MSM_KMS
default y
help
  Compile in support for the Mobile Display Processor v5 (MDP5) in
@@ -94,6 +104,7 @@ config DRM_MSM_DPU
bool "Enable DPU support in MSM DRM driver"
depends on DRM_MSM
select DRM_MSM_MDSS
+   select DRM_MSM_KMS
select DRM_DISPLAY_DSC_HELPER
default y
help
@@ -104,6 +115,7 @@ config DRM_MSM_DPU
 config DRM_MSM_DP
bool "Enable DisplayPort support in MSM DRM driver"
depends on DRM_MSM
+   depends on DRM_MSM_KMS
select RATIONAL
default y
help
@@ -114,6 +126,7 @@ config DRM_MSM_DP
 config DRM_MSM_DSI
bool "Enable DSI support in MSM DRM driver"
depends on DRM_MSM
+   depends on DRM_MSM_KMS
select DRM_PANEL
select DRM_MIPI_DSI
select DRM_DISPLAY_DSC_HELPER
@@ -169,6 +182,7 @@ config DRM_MSM_DSI_7NM_PHY
 config DRM_MSM_HDMI
bool "Enable HDMI support in MSM DRM driver"
depends on DRM_MSM
+   depends on DRM_MSM_KMS
default y
select DRM_DISPLAY_HDMI_HELPER
select DRM_DISPLAY_HDMI_STATE_HELPER
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 
5df20cbeafb8bf07c825a1fd72719d5a56c38613..3749b0af779e73a93d7c219d3fbd3865b9296b50
 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -101,18 +101,15 @@ msm-display-$(CONFIG_DRM_MSM_DPU) += \
 msm-display-$(CONFIG_DRM_MSM_MDSS) += \
msm_mdss.o \
 
-msm-display-y += \
+msm-display-$(CONFIG_DRM_MSM_KMS) += \
disp/mdp_format.o \
disp/mdp_kms.o \
disp/msm_disp_snapshot.o \
disp/msm_disp_snapshot_util.o \
 
 msm-y += \
-   msm_atomic.o \
-   msm_atomic_tracepoints.o \
msm_debugfs.o \
msm_drv.o \
-   msm_fb.o \
msm_fence.o \
msm_gem.o \
msm_gem_prime.o \
@@ -123,21 +120,24 @@ msm-y += \
msm_gpu_devfreq.o \
msm_io_utils.o \
msm_iommu.o \
-   msm_kms.o \
msm_perf.o \
msm_rd.o \
msm_ringbuffer.o \
msm_submitqueue.o \
msm_gpu_tracepoints.o \
 
-msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
+msm-$(CONFIG_DRM_MSM_KMS) += \
+   msm_atomic.o \
+   msm_atomic_tracepoints.o \
+   msm_fb.o \
+   msm_kms.o \
 
-msm-display-$(CONFIG_DEBUG_FS) += \
-   dp/dp_debug.o
+msm-$(CONFIG_DRM_MSM_KMS_FBDEV) += msm_fbdev.o
 
 msm-display-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_catalog.o \
dp/dp_ctrl.o \
+   dp/dp_debug.o \
dp/dp_display.o \
dp/dp_drm.o \
dp/dp_link.o \
diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c 
b/drivers/gpu/drm/msm/dp/dp_debug.c
index 
22fd946ee201397b72b43c8499714139deb7ba82..7835d93015b31a69aac824ca04dc65b374546e5c
 100644
--- a/drivers/gpu/drm/msm/dp/dp_debug.c
+++ b/drivers/gpu/drm/msm/dp/dp_debug.c
@@ -5,6 +5,8 @@
 
 #define pr_fmt(fmt)"[drm-dp] %s: " fmt, __func__
 
+#ifdef CONFIG_DEBUG_FS
+
 #include 
 #include 
 #include 
@@ -235,3 +237,5 @@ int msm_dp_debug_init(struct device *dev, struct 
msm_dp_panel *panel,
 
return 0;
 }
+
+#endif
diff --git a/drivers/gpu/drm/msm/msm_debugfs.c 
b/drivers/gpu/drm/msm/msm_debugfs.c
index 
7ab607252d183f78b99c3a8b878c949ed5f99fec..2b12f2851fadbc3c9

Re: [PATCH 4/7] drm/bridge: analogic_dp: drop panel_lock

[Damon Ding]

Hi Dmitry,

On 2025/4/1 13:11, Dmitry Baryshkov wrote:

The analogix_dp_prepare_panel() function is called from bridge's
atomic_pre_enable() and atomic_post_disable() callbacks, which can not
happen simultaneously. Drop the useless mutex.

Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 5 -
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 --
  2 files changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 
704c6169116eb2601d2ad02dc7294455ceff5460..1ec4d277fe6bb03ad9eb8451ae2af5ad5ada0978
 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -974,14 +974,11 @@ static int analogix_dp_prepare_panel(struct 
analogix_dp_device *dp,
if (!dp->plat_data->panel)
return 0;
  
-	mutex_lock(&dp->panel_lock);

-
if (prepare)
ret = drm_panel_prepare(dp->plat_data->panel);
else
ret = drm_panel_unprepare(dp->plat_data->panel);
  
-	mutex_unlock(&dp->panel_lock);

return ret;
  }
  
@@ -1523,8 +1520,6 @@ analogix_dp_probe(struct device *dev, struct analogix_dp_plat_data *plat_data)

dp->dev = &pdev->dev;
dp->dpms_mode = DRM_MODE_DPMS_OFF;
  
-	mutex_init(&dp->panel_lock);

-
/*
 * platform dp driver need containor_of the plat_data to get
 * the driver private data, so we need to store the point of
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 
b679d5b71d276f458d905c936160f107225bc6c5..2b54120ba4a3ef55af518a0629a5c8469f275a0f
 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -169,8 +169,6 @@ struct analogix_dp_device {
boolfast_train_enable;
boolpsr_supported;
  
-	struct mutex		panel_lock;

-
struct analogix_dp_plat_data *plat_data;
  };
  



The patch has been verified with the eDP panel "lg,lp079qx1-sp0v" in 
RK3588S EVB1 board.


Tested-by: Damon Ding 

Best regards,
Damon

Re: [PATCH 5/7] drm/bridge: analogix_dp: inline analogix_dp_prepare_panel()

[Damon Ding]

Hi Dmitry,

On 2025/4/1 13:11, Dmitry Baryshkov wrote:

The analogix_dp_prepare_panel() is now only calling a corresponding
drm_panel function. Inline it to simplify the code.

Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 43 +-
  1 file changed, 10 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 
1ec4d277fe6bb03ad9eb8451ae2af5ad5ada0978..f60068011008482f7b7b2edfcab5fb1b3e9e130f
 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -955,33 +955,6 @@ static int analogix_dp_disable_psr(struct 
analogix_dp_device *dp)
return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
  }
  
-/*

- * This function is a bit of a catch-all for panel preparation, hopefully
- * simplifying the logic of functions that need to prepare/unprepare the panel
- * below.
- *
- * If @prepare is true, this function will prepare the panel. Conversely, if it
- * is false, the panel will be unprepared.
- *
- * The function will disregard the current state
- * of the panel and either prepare/unprepare the panel based on @prepare.
- */
-static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
-bool prepare)
-{
-   int ret = 0;
-
-   if (!dp->plat_data->panel)
-   return 0;
-
-   if (prepare)
-   ret = drm_panel_prepare(dp->plat_data->panel);
-   else
-   ret = drm_panel_unprepare(dp->plat_data->panel);
-
-   return ret;
-}
-
  static int analogix_dp_get_modes(struct drm_connector *connector)
  {
struct analogix_dp_device *dp = to_dp(connector);
@@ -1174,9 +1147,11 @@ static void analogix_dp_bridge_atomic_pre_enable(struct 
drm_bridge *bridge,
if (old_crtc_state && old_crtc_state->self_refresh_active)
return;
  
-	ret = analogix_dp_prepare_panel(dp, true);

-   if (ret)
-   DRM_ERROR("failed to setup the panel ret = %d\n", ret);
+   if (dp->plat_data->panel) {
+   ret = drm_panel_prepare(dp->plat_data->panel);
+   if (ret)
+   DRM_ERROR("failed to prepare the panel ret = %d\n", 
ret);
+   }
  }
  
  static int analogix_dp_set_bridge(struct analogix_dp_device *dp)

@@ -1274,9 +1249,11 @@ static void analogix_dp_bridge_disable(struct drm_bridge 
*bridge)
  
  	pm_runtime_put_sync(dp->dev);
  
-	ret = analogix_dp_prepare_panel(dp, false);

-   if (ret)
-   DRM_ERROR("failed to setup the panel ret = %d\n", ret);
+   if (dp->plat_data->panel) {
+   ret = drm_panel_unprepare(dp->plat_data->panel);
+   if (ret)
+   DRM_ERROR("failed to unprepare the panel ret = %d\n", 
ret);
+   }
  
  	dp->fast_train_enable = false;

dp->psr_supported = false;



The patch has been verified with the eDP panel "lg,lp079qx1-sp0v" in 
RK3588S EVB1 board.


Tested-by: Damon Ding 

Best regards,
Damon

Re: [PATCH 6/7] drm/bridge: analogix_dp: ignore return values of drm_panel_* calls

[Damon Ding]

Hi Dmitry,

On 2025/4/1 13:11, Dmitry Baryshkov wrote:

Follow the example of other drivers and ignore return values of the
drm_panel_prepare() / unprepare() / enable() / disable() calls. There is
no possible error recovery, so the driver just logs a message.

Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 39 --
  1 file changed, 6 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 
f60068011008482f7b7b2edfcab5fb1b3e9e130f..c7dffdae31877ae194fc6b0a5bf21be203f7dcc4
 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -838,10 +838,7 @@ static int analogix_dp_commit(struct analogix_dp_device 
*dp)
int ret;
  
  	/* Keep the panel disabled while we configure video */

-   if (dp->plat_data->panel) {
-   if (drm_panel_disable(dp->plat_data->panel))
-   DRM_ERROR("failed to disable the panel\n");
-   }
+   drm_panel_disable(dp->plat_data->panel);
  
  	ret = analogix_dp_train_link(dp);

if (ret) {
@@ -863,13 +860,7 @@ static int analogix_dp_commit(struct analogix_dp_device 
*dp)
}
  
  	/* Safe to enable the panel now */

-   if (dp->plat_data->panel) {
-   ret = drm_panel_enable(dp->plat_data->panel);
-   if (ret) {
-   DRM_ERROR("failed to enable the panel\n");
-   return ret;
-   }
-   }
+   drm_panel_enable(dp->plat_data->panel);
  
  	/* Check whether panel supports fast training */

ret = analogix_dp_fast_link_train_detection(dp);
@@ -1136,7 +1127,6 @@ static void analogix_dp_bridge_atomic_pre_enable(struct 
drm_bridge *bridge,
struct analogix_dp_device *dp = bridge->driver_private;
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state;
-   int ret;
  
  	crtc = analogix_dp_get_new_crtc(dp, old_state);

if (!crtc)
@@ -1147,11 +1137,7 @@ static void analogix_dp_bridge_atomic_pre_enable(struct 
drm_bridge *bridge,
if (old_crtc_state && old_crtc_state->self_refresh_active)
return;
  
-	if (dp->plat_data->panel) {

-   ret = drm_panel_prepare(dp->plat_data->panel);
-   if (ret)
-   DRM_ERROR("failed to prepare the panel ret = %d\n", 
ret);
-   }
+   drm_panel_prepare(dp->plat_data->panel);
  }
  
  static int analogix_dp_set_bridge(struct analogix_dp_device *dp)

@@ -1231,17 +1217,11 @@ static void analogix_dp_bridge_atomic_enable(struct 
drm_bridge *bridge,
  static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
  {
struct analogix_dp_device *dp = bridge->driver_private;
-   int ret;
  
  	if (dp->dpms_mode != DRM_MODE_DPMS_ON)

return;
  
-	if (dp->plat_data->panel) {

-   if (drm_panel_disable(dp->plat_data->panel)) {
-   DRM_ERROR("failed to disable the panel\n");
-   return;
-   }
-   }
+   drm_panel_disable(dp->plat_data->panel);
  
  	disable_irq(dp->irq);
  
@@ -1249,11 +1229,7 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
  
  	pm_runtime_put_sync(dp->dev);
  
-	if (dp->plat_data->panel) {

-   ret = drm_panel_unprepare(dp->plat_data->panel);
-   if (ret)
-   DRM_ERROR("failed to unprepare the panel ret = %d\n", 
ret);
-   }
+   drm_panel_unprepare(dp->plat_data->panel);
  
  	dp->fast_train_enable = false;

dp->psr_supported = false;
@@ -1678,10 +1654,7 @@ void analogix_dp_unbind(struct analogix_dp_device *dp)
analogix_dp_bridge_disable(dp->bridge);
dp->connector.funcs->destroy(&dp->connector);
  
-	if (dp->plat_data->panel) {

-   if (drm_panel_unprepare(dp->plat_data->panel))
-   DRM_ERROR("failed to turnoff the panel\n");
-   }
+   drm_panel_unprepare(dp->plat_data->panel);
  
  	drm_dp_aux_unregister(&dp->aux);
  



The patch has been verified with the eDP panel "lg,lp079qx1-sp0v" in 
RK3588S EVB1 board.


Tested-by: Damon Ding 

Best regards,
Damon

Re: [PATCH 1/7] drm/bridge: analogix_dp: drop extra calls to analogix_dp_prepare_panel()

[Damon Ding]

On 2025/4/14 9:20, Damon Ding wrote:

Hi Dmitry,

On 2025/4/1 13:11, Dmitry Baryshkov wrote:

The analogix_dp_prepare_panel() returns immediately if there is no
attached panel. Drop several calls to this function which are performed
when dp->plat_data->panel is NULL.

Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 22 
+-

  1 file changed, 1 insertion(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/ 
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 
042154e2d8ccd74ac2dc27fe527e810a50e08a09..ab1cfc340aa95bbf13fe021bd33227b565a5458d 100644

--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1005,17 +1005,11 @@ static int analogix_dp_get_modes(struct 
drm_connector *connector)

  {
  struct analogix_dp_device *dp = to_dp(connector);
  const struct drm_edid *drm_edid;
-    int ret, num_modes = 0;
+    int num_modes = 0;
  if (dp->plat_data->panel) {
  num_modes += drm_panel_get_modes(dp->plat_data->panel, 
connector);

  } else {
-    ret = analogix_dp_prepare_panel(dp, true, false);
-    if (ret) {
-    DRM_ERROR("Failed to prepare panel (%d)\n", ret);
-    return 0;
-    }
-
  drm_edid = drm_edid_read_ddc(connector, &dp->aux.ddc);
  drm_edid_connector_update(&dp->connector, drm_edid);
@@ -1024,10 +1018,6 @@ static int analogix_dp_get_modes(struct 
drm_connector *connector)

  num_modes += drm_edid_connector_add_modes(&dp->connector);
  drm_edid_free(drm_edid);
  }
-
-    ret = analogix_dp_prepare_panel(dp, false, false);
-    if (ret)
-    DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
  }
  if (dp->plat_data->get_modes)
@@ -1087,19 +1077,9 @@ analogix_dp_detect(struct drm_connector 
*connector, bool force)

  if (dp->plat_data->panel)
  return connector_status_connected;
-    ret = analogix_dp_prepare_panel(dp, true, false);
-    if (ret) {
-    DRM_ERROR("Failed to prepare panel (%d)\n", ret);
-    return connector_status_disconnected;
-    }
-
  if (!analogix_dp_detect_hpd(dp))
  status = connector_status_connected;
-    ret = analogix_dp_prepare_panel(dp, false, false);
-    if (ret)
-    DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
-
  return status;
  }



With the patch series:
https://patchwork.kernel.org/project/linux-rockchip/list/?series=942183

When I verify this patch, there will be a small warning:
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c:1075:6: warning: 
unused variable 'ret' [-Wunused-variable]

     int ret;
     ^

It should be better to remove the unused 'ret'.

Best regards,
Damon





Tested-by: Damon Ding 

[PATCH 11/13] drm/i915/backlight: Use drm helper to initialize edp backlight

[Suraj Kandpal]

Now that drm_edp_backlight init has been to be able to setup
brightness manipulation via luminance we can just use that.

Signed-off-by: Suraj Kandpal 
---
 .../drm/i915/display/intel_dp_aux_backlight.c | 100 +-
 1 file changed, 49 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index be740fb72ebc..2eff9b545390 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -585,9 +585,36 @@ static int intel_dp_aux_vesa_setup_backlight(struct 
intel_connector *connector,
u8 current_mode;
int ret;
 
-   if (panel->backlight.edp.vesa.luminance_control_support) {
+   ret = drm_edp_backlight_init(&intel_dp->aux, 
&panel->backlight.edp.vesa.info,
+luminance_range, 
panel->vbt.backlight.pwm_freq_hz,
+intel_dp->edp_dpcd, ¤t_level, 
¤t_mode, true);
+   if (ret < 0)
+   return ret;
+
+   drm_dbg_kms(display->drm,
+   "[CONNECTOR:%d:%s] AUX VESA backlight enable is controlled 
through %s\n",
+   connector->base.base.id, connector->base.name,
+   dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_enable));
+   drm_dbg_kms(display->drm,
+   "[CONNECTOR:%d:%s] AUX VESA backlight level is controlled 
through %s\n",
+   connector->base.base.id, connector->base.name,
+   dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_set));
+
+   if (!panel->backlight.edp.vesa.info.luminance_set ||
+   !panel->backlight.edp.vesa.info.aux_set ||
+   !panel->backlight.edp.vesa.info.aux_enable) {
+   ret = panel->backlight.pwm_funcs->setup(connector, pipe);
+   if (ret < 0) {
+   drm_err(display->drm,
+   "[CONNECTOR:%d:%s] Failed to setup PWM 
backlight controls for eDP backlight: %d\n",
+   connector->base.base.id, connector->base.name, 
ret);
+   return ret;
+   }
+   }
+
+   if (panel->backlight.edp.vesa.info.luminance_set) {
if (luminance_range->max_luminance) {
-   panel->backlight.max = luminance_range->max_luminance;
+   panel->backlight.max = 
panel->backlight.edp.vesa.info.max;
panel->backlight.min = luminance_range->min_luminance;
} else {
panel->backlight.max = 512;
@@ -596,57 +623,28 @@ static int intel_dp_aux_vesa_setup_backlight(struct 
intel_connector *connector,
panel->backlight.level = 
intel_dp_aux_vesa_get_backlight(connector, 0);
panel->backlight.enabled = panel->backlight.level != 0;
drm_dbg_kms(display->drm,
-   "[CONNECTOR:%d:%s] AUX VESA Nits backlight level is 
controlled through DPCD\n",
-   connector->base.base.id, connector->base.name);
-   } else {
-   ret = drm_edp_backlight_init(&intel_dp->aux, 
&panel->backlight.edp.vesa.info,
-luminance_range, 
panel->vbt.backlight.pwm_freq_hz,
-intel_dp->edp_dpcd, 
¤t_level, ¤t_mode,
-false);
-   if (ret < 0)
-   return ret;
-
-   drm_dbg_kms(display->drm,
-   "[CONNECTOR:%d:%s] AUX VESA backlight enable is 
controlled through %s\n",
-   connector->base.base.id, connector->base.name,
-   
dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_enable));
-   drm_dbg_kms(display->drm,
-   "[CONNECTOR:%d:%s] AUX VESA backlight level is 
controlled through %s\n",
-   connector->base.base.id, connector->base.name,
-   
dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_set));
-
-   if (!panel->backlight.edp.vesa.info.aux_set ||
-   !panel->backlight.edp.vesa.info.aux_enable) {
-   ret = panel->backlight.pwm_funcs->setup(connector, 
pipe);
-   if (ret < 0) {
-   drm_err(display->drm,
-   "[CONNECTOR:%d:%s] Failed to setup PWM 
backlight controls for eDP backlight: %d\n",
-   connector->base.base.id, 
connector->base.name, ret);
-   return ret;
-   }
+   "[CONNECTOR:%d:%s] AUX VESA Nits backlight level is 
controlled through DPCD\n",
+   connector->base.base.id, connector->base.name);
+   } else if (panel->backlight.edp.vesa.i

[PATCH 01/13] drm/dp: Introduce new member in drm_backlight_info

[Suraj Kandpal]

Introduce luminance_set flag which indicates if we can manipulate
backlight using luminance value or not which is only possible
after eDP v1.5.

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c | 8 ++--
 include/drm/display/drm_dp_helper.h | 1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index 57828f2b7b5a..41de7a92d76d 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4253,11 +4253,15 @@ drm_edp_backlight_init(struct drm_dp_aux *aux, struct 
drm_edp_backlight_info *bl
bl->aux_set = true;
if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
bl->lsb_reg_used = true;
+   if ((edp_dpcd[0] & DP_EDP_15) && edp_dpcd[3] &
+   (DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE))
+   bl->luminance_set = true;
 
/* Sanity check caps */
-   if (!bl->aux_set && !(edp_dpcd[2] & 
DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
+   if (!bl->aux_set && !(edp_dpcd[2] & 
DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP) &&
+   !bl->luminance_set) {
drm_dbg_kms(aux->drm_dev,
-   "%s: Panel supports neither AUX or PWM brightness 
control? Aborting\n",
+   "%s: Panel does not support AUX, PWM or 
luminance-based brightness control. Aborting\n",
aux->name);
return -EINVAL;
}
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index d9614e2c8939..b8fdc09737fc 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -844,6 +844,7 @@ struct drm_edp_backlight_info {
bool lsb_reg_used : 1;
bool aux_enable : 1;
bool aux_set : 1;
+   bool luminance_set : 1;
 };
 
 int
-- 
2.34.1

[PATCH v9 11/19] drm/imx: Add i.MX8qxp Display Controller interrupt controller

[Liu Ying]

i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.  Add driver for it.

Reviewed-by: Maxime Ripard 
Reviewed-by: Dmitry Baryshkov 
Signed-off-by: Liu Ying 
---
v9:
* No change.

v8:
* Collect Dmitry's R-b tag.

v7:
* Fix regmap_config definition by removing name field, correcting read ranges
  and setting max_register field.
* Collect Maxime's R-b tag.

v6:
* No change.

v5:
* Replace .remove_new with .remove in dc-ic.c. (Uwe)

v4:
* Use regmap to define register map for all registers. (Dmitry)
* Use regmap APIs to access registers. (Dmitry)
* Use devm_kzalloc() to drmm_kzalloc() to allocate dc_ic_data data strutures.
* Set suppress_bind_attrs driver flag to true to avoid unnecessary sys
  interfaces to bind/unbind the driver.
* Take DC interrupt controller driver as a standalone driver instead of a
  component driver.
* Replace drmm_kcalloc() with devm_kcalloc() to allocate an array for
  struct dc_ic_entry.
* Call platform_get_irq() from DC interrupt controller driver to make sure
  parent interrupt controller driver is probed first.

v3:
* No change.

v2:
* No change.

 drivers/gpu/drm/imx/dc/Kconfig  |   1 +
 drivers/gpu/drm/imx/dc/Makefile |   2 +-
 drivers/gpu/drm/imx/dc/dc-drv.c |   1 +
 drivers/gpu/drm/imx/dc/dc-drv.h |   1 +
 drivers/gpu/drm/imx/dc/dc-ic.c  | 282 
 5 files changed, 286 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/imx/dc/dc-ic.c

diff --git a/drivers/gpu/drm/imx/dc/Kconfig b/drivers/gpu/drm/imx/dc/Kconfig
index e1ef76d82830..1fc84c7475de 100644
--- a/drivers/gpu/drm/imx/dc/Kconfig
+++ b/drivers/gpu/drm/imx/dc/Kconfig
@@ -1,6 +1,7 @@
 config DRM_IMX8_DC
tristate "Freescale i.MX8 Display Controller Graphics"
depends on DRM && COMMON_CLK && OF && (ARCH_MXC || COMPILE_TEST)
+   select GENERIC_IRQ_CHIP
select REGMAP
select REGMAP_MMIO
help
diff --git a/drivers/gpu/drm/imx/dc/Makefile b/drivers/gpu/drm/imx/dc/Makefile
index 2942ae6fd5bd..1ce3e8a8db22 100644
--- a/drivers/gpu/drm/imx/dc/Makefile
+++ b/drivers/gpu/drm/imx/dc/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
 imx8-dc-drm-objs := dc-cf.o dc-de.o dc-drv.o dc-ed.o dc-fg.o dc-fl.o dc-fu.o \
-   dc-fw.o dc-lb.o dc-pe.o dc-tc.o
+   dc-fw.o dc-ic.o dc-lb.o dc-pe.o dc-tc.o
 
 obj-$(CONFIG_DRM_IMX8_DC) += imx8-dc-drm.o
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.c b/drivers/gpu/drm/imx/dc/dc-drv.c
index 7c64acc863ad..fd68861f770a 100644
--- a/drivers/gpu/drm/imx/dc/dc-drv.c
+++ b/drivers/gpu/drm/imx/dc/dc-drv.c
@@ -15,6 +15,7 @@ static struct platform_driver * const dc_drivers[] = {
&dc_fg_driver,
&dc_fl_driver,
&dc_fw_driver,
+   &dc_ic_driver,
&dc_lb_driver,
&dc_pe_driver,
&dc_tc_driver,
diff --git a/drivers/gpu/drm/imx/dc/dc-drv.h b/drivers/gpu/drm/imx/dc/dc-drv.h
index b9fe12577a19..e4c2d564ab5d 100644
--- a/drivers/gpu/drm/imx/dc/dc-drv.h
+++ b/drivers/gpu/drm/imx/dc/dc-drv.h
@@ -54,6 +54,7 @@ extern struct platform_driver dc_ed_driver;
 extern struct platform_driver dc_fg_driver;
 extern struct platform_driver dc_fl_driver;
 extern struct platform_driver dc_fw_driver;
+extern struct platform_driver dc_ic_driver;
 extern struct platform_driver dc_lb_driver;
 extern struct platform_driver dc_pe_driver;
 extern struct platform_driver dc_tc_driver;
diff --git a/drivers/gpu/drm/imx/dc/dc-ic.c b/drivers/gpu/drm/imx/dc/dc-ic.c
new file mode 100644
index ..66884ce72b5b
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-ic.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define USERINTERRUPTMASK(n)   (0x8 + 4 * (n))
+#define INTERRUPTENABLE(n) (0x10 + 4 * (n))
+#define INTERRUPTPRESET(n) (0x18 + 4 * (n))
+#define INTERRUPTCLEAR(n)  (0x20 + 4 * (n))
+#define INTERRUPTSTATUS(n) (0x28 + 4 * (n))
+#define USERINTERRUPTENABLE(n) (0x40 + 4 * (n))
+#define USERINTERRUPTPRESET(n) (0x48 + 4 * (n))
+#define USERINTERRUPTCLEAR(n)  (0x50 + 4 * (n))
+#define USERINTERRUPTSTATUS(n) (0x58 + 4 * (n))
+
+#define IRQ_COUNT  49
+#define IRQ_RESERVED   35
+#define REG_NUM2
+
+struct dc_ic_data {
+   struct regmap   *regs;
+   struct clk  *clk_axi;
+   int irq[IRQ_COUNT];
+   struct irq_domain   *domain;
+};
+
+struct dc_ic_entry {
+   struct dc_ic_data *data;
+   int irq;
+};
+
+static const struct regmap_range dc_ic_regmap_write_ranges[] = {
+   regmap_reg_range(USERINTERRUPTMASK(0), INTERRUPTCLEAR(1)),
+   regmap_reg_range(USERINTERRUPTENABLE(0), USERINTERRUPTCLEAR(1)),
+};
+
+static const struct regmap_access_table dc_ic_regmap_write_table = {
+   .yes_ranges = dc_ic_regmap_write_ranges,
+   .n_yes_ranges = ARRAY_SIZE(dc

[PATCH v9 07/19] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller

[Liu Ying]

i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.

Signed-off-by: Liu Ying 
Reviewed-by: Rob Herring (Arm) 
---
v9:
* No change.

v8:
* No change.

v7:
* No change.

v6:
* No change.

v5:
* No change.

v4:
* No change.

v3:
* Collect Rob's R-b tag.

v2:
* Drop unneeded "|". (Krzysztof)

 .../fsl,imx8qxp-dc-intc.yaml  | 318 ++
 1 file changed, 318 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
 
b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
new file mode 100644
index ..6985ee644a25
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml
@@ -0,0 +1,318 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 
http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller interrupt controller
+
+description: |
+  The Display Controller has a built-in interrupt controller with the following
+  features for all relevant HW events:
+
+  * Enable bit (mask)
+  * Status bit (set by an HW event)
+  * Preset bit (can be used by SW to set status)
+  * Clear bit (used by SW to reset the status)
+
+  Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
+  Alternatively the un-masked trigger signals for all HW events are provided,
+  allowing it to use a global interrupt controller instead.
+
+  Each interrupt can be protected against SW running in user mode. In that 
case,
+  only privileged AHB access can control the interrupt status.
+
+maintainers:
+  - Liu Ying 
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-intc
+
+  reg:
+maxItems: 1
+
+  clocks:
+maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+const: 1
+
+  interrupts:
+items:
+  - description: store9 shadow load interrupt(blit engine)
+  - description: store9 frame complete interrupt(blit engine)
+  - description: store9 sequence complete interrupt(blit engine)
+  - description:
+  extdst0 shadow load interrupt
+  (display controller, content stream 0)
+  - description:
+  extdst0 frame complete interrupt
+  (display controller, content stream 0)
+  - description:
+  extdst0 sequence complete interrupt
+  (display controller, content stream 0)
+  - description:
+  extdst4 shadow load interrupt
+  (display controller, safety stream 0)
+  - description:
+  extdst4 frame complete interrupt
+  (display controller, safety stream 0)
+  - description:
+  extdst4 sequence complete interrupt
+  (display controller, safety stream 0)
+  - description:
+  extdst1 shadow load interrupt
+  (display controller, content stream 1)
+  - description:
+  extdst1 frame complete interrupt
+  (display controller, content stream 1)
+  - description:
+  extdst1 sequence complete interrupt
+  (display controller, content stream 1)
+  - description:
+  extdst5 shadow load interrupt
+  (display controller, safety stream 1)
+  - description:
+  extdst5 frame complete interrupt
+  (display controller, safety stream 1)
+  - description:
+  extdst5 sequence complete interrupt
+  (display controller, safety stream 1)
+  - description:
+  disengcfg0 shadow load interrupt
+  (display controller, display stream 0)
+  - description:
+  disengcfg0 frame complete interrupt
+  (display controller, display stream 0)
+  - description:
+  disengcfg0 sequence complete interrupt
+  (display controller, display stream 0)
+  - description:
+  framegen0 programmable interrupt0
+  (display controller, display stream 0)
+  - description:
+  framegen0 programmable interrupt1
+  (display controller, display stream 0)
+  - description:
+  framegen0 programmable interrupt2
+  (display controller, display stream 0)
+  - description:
+  framegen0 programmable interrupt3
+  (display controller, display stream 0)
+  - description:
+  signature0 shadow load interrupt
+  (display controller, display stream 0)
+  - description:
+  signature0 measurement valid interrupt
+  (display controller, display stream 0)
+  - description:
+  signature0 error condition interrupt
+  (display controller, display stream 0)
+  - description:
+  disengcfg1 shadow load interrupt
+  (display controller, display stre

[PATCH v9 13/19] MAINTAINERS: Add maintainer for i.MX8qxp Display Controller

[Liu Ying]

Add myself as the maintainer of i.MX8qxp Display Controller.

Signed-off-by: Liu Ying 
Reviewed-by: Maxime Ripard 
---
v9:
* Add Maxime's R-b tag.

v8:
* No change.

v7:
* No change.

v6:
* No change.

v5:
* No change.

v4:
* No change.

v3:
* No change.

v2:
* Improve file list. (Frank)

 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96b827049501..ee09cb88f51e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7908,6 +7908,14 @@ F:   Documentation/devicetree/bindings/display/imx/
 F: drivers/gpu/drm/imx/ipuv3/
 F: drivers/gpu/ipu-v3/
 
+DRM DRIVERS FOR FREESCALE IMX8 DISPLAY CONTROLLER
+M: Liu Ying 
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc*.yaml
+F: drivers/gpu/drm/imx/dc/
+
 DRM DRIVERS FOR FREESCALE IMX BRIDGE
 M: Liu Ying 
 L: dri-devel@lists.freedesktop.org
-- 
2.34.1

[PATCH v9 00/19] Add Freescale i.MX8qxp Display Controller support

[Liu Ying]

Hi,

This patch series aims to add Freescale i.MX8qxp Display Controller support.

The controller is comprised of three main components that include a blit
engine for 2D graphics accelerations, display controller for display output
processing, as well as a command sequencer.

Previous patch series attempts to do that can be found at:
https://patchwork.freedesktop.org/series/84524/

This series addresses Maxime's comments on the previous one:
a. Split the display controller into multiple internal devices.
   1) List display engine, pixel engine, interrupt controller and more as the
  controller's child devices.
   2) List display engine and pixel engine's processing units as their child
  devices.

b. Add minimal feature support.
   Only support two display pipelines with primary planes with XR24 fb,
   backed by two fetchunits.  No fetchunit dynamic allocation logic(to be done
   when necessary).

c. Use drm_dev_{enter, exit}().

Since this series changes a lot comparing to the previous one, I choose to
send it with a new patch series, not a new version.

To follow up i.MX8qxp TRM, I changed the controller name to "Display Controller"
instead of the previous "DPU".  "DPU" is only mentioned in the SoC block
diagram and represents the whole display subsystem which includes the display
controller and prefech engines, etc.

With an additional patch[1] for simple-pm-bus.c, this series facilitates
testing a LVDS panel on i.MX8qxp MEK.

Please do NOT merge patch 14-19.  They are only used to facilitate testing
the LVDS panel.

Maxime, patch 1-13 have already been reviewed by maintainers, can you please
consider to land patch 1-13?

[1] https://lkml.org/lkml/2023/1/25/120

v9:
* Rebase on v6.15-rc1.
* Collect Rob's R-b tag on patch 6.
* Collect Dmitry's R-b tags on patch 9&10.
* Collect Maxime's R-b tag on patch 13.

v8:
* Drop instance numbers from display controller internal devices' compatible
  strings. This means switching back to patches for DT bindings in v4. So, add
  Rob's previous R-b tags back on patches for DT bindings. (Dmitry)
* Get display controller internal device instance numbers through register
  start addresses of the devices in patch 9&10, instead of compatible strings.
  (Dmitry)
* s/shdld/shdload/ for IRQs in patch 9/10/12. (Dmitry)
* Drop dc_plane_check_no_off_screen() from patch 12. (Dmitry)
* Drop id member from struct dc_de from patch 9. (Dmitry)
* Add dc_{de,pe}_post_bind() to patch 9&10, to avoid dependency on the
  component helper's way of implementing component binding order. (Dmitry)
* Add dev_warn() to dc_lb_pec_dynamic_{prim,sec}_sel() in patch 10. (Dmitry)
* Drop lb_links[] and dc_fetchunit_all_fracs[] arrays from patch 10. (Dmitry)
* Collect Dmitry's R-b tags on patch 11&12.

v7:
* Drop using DT aliases for display controller internal devices and add
  instance numbers to display controller internal devices' compatible
  strings. Drop Rob's R-b tags on some DT bindings patches. (Rob)
* Drop using typeof in macros and explicitly define variable types in patch 12.
  (Dmitry)
* Add a comment for disable_irq_nosync() to explain why _nosync in patch 12.
  (Dmitry)
* Inline dc_crtc_check_clock() in patch 12. (Dmitry)
* Use global drm_dc->pe in patch 12. (Dmitry)
* Drop dc_crtc_disable_at_unbind() from KMS driver in patch 12. (Dmitry)
* Add kernel doc for struct dc_{crtc,drm_device,plane} in patch 9/10/12.
  (Dmitry)
* Define common IRQ handlers separately for each IRQs in patch 12. (Dmitry)
* Rebase this series upon next-20241220, so drop date entry from drm_driver
  and correctly include drm/clients/drm_client_setup.h.
* Fix regmap_config definitions for display controller internal device drivers
  in patch 9/10/11 by correcting name field, correcting read ranges and setting
  max_register field.
* Get instance numbers from device data(compatible strings) instead of OF
  aliases in display controller internal device drivers in patch 9/10/11.
* Collect Maxime's R-b tags on interrupt controller driver and display drivers.
* Trivial tweaks.

v6:
* Fix build warning by expanding sizeof(fu->name) from 13 to 21 in patch 10.
  (kernel test robot)

v5:
* Document display controller device's and some display controller internal
  devices' aliases in DT bindings. Hence, drop collected R-b tags from some
  patches for DT bindings. (Maxime)
* Replace .remove_new with .remove in all drivers. (Uwe)
* Select REGMAP and REGMAP_MMIO options in patch 9.
* Fix patch 9 & 10's commit message to state that display engine driver and
  pixel engine driver are component drivers instead of master/aggregate drivers.

v4:
* Collect Rob's R-b tags on DT binding patches(patch 1-5).
* Replace "fsl,iram" property with standard "sram" property in
  fsl,imx8qxp-dc-command-sequencer.yaml in patch 6. (Rob)
* Use regmap to define register map for all registers. (Dmitry)
* Use regmap APIs to access registers. (Dmitry)
* Inline some small functions. (Dmitry)
* Move dc_fg_displaymode(), dc_fg_panic_displaymode() 

RE: [PATCH 07/13] drm/dp: Change argument type for drm_edp_backlight_set_level

[Kandpal, Suraj]

> -Original Message-
> From: Jani Nikula 
> Sent: Friday, April 11, 2025 4:09 PM
> To: Kandpal, Suraj ; nouv...@lists.freedesktop.org;
> dri-devel@lists.freedesktop.org; intel...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Murthy, Arun R
> ; Kandpal, Suraj 
> Subject: Re: [PATCH 07/13] drm/dp: Change argument type for
> drm_edp_backlight_set_level
> 
> On Fri, 11 Apr 2025, Suraj Kandpal  wrote:
> > Use u32 for level variable as one may need to pass value for
> > DP_EDP_PANEL_TARGET_LUMINANCE_VALUE.
> >
> > Signed-off-by: Suraj Kandpal 
> > ---
> >  drivers/gpu/drm/display/drm_dp_helper.c | 6 +++---
> >  include/drm/display/drm_dp_helper.h | 2 +-
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
> > b/drivers/gpu/drm/display/drm_dp_helper.c
> > index bb1242a1bf6b..895ed4a22fc3 100644
> > --- a/drivers/gpu/drm/display/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> > @@ -3933,7 +3933,7 @@
> EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
> >   * Returns: %0 on success, negative error code on failure
> >   */
> >  int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct
> drm_edp_backlight_info *bl,
> > -   u16 level)
> > +   u32 level)
> >  {
> > int ret;
> > u8 buf[2] = { 0 };
> > @@ -4047,7 +4047,7 @@ int drm_edp_backlight_enable(struct drm_dp_aux
> *aux, const struct drm_edp_backli
> > return ret < 0 ? ret : -EIO;
> > }
> >
> > -   ret = drm_edp_backlight_set_level(aux, bl, level);
> > +   ret = drm_edp_backlight_set_level(aux, bl, (u32)level);
> 
> What difference do you think the cast makes?

You are right this is not needed the var should be automatically be promoted 
will fix this here
And in another patch where I have done the same mistake.

Regards,
Suraj Kandpal

> 
> > if (ret < 0)
> > return ret;
> > ret = drm_edp_backlight_set_enable(aux, bl, true); @@ -4327,7
> > +4327,7 @@ static int dp_aux_backlight_update_status(struct
> backlight_device *bd)
> > bl->enabled = true;
> > return 0;
> > }
> > -   ret = drm_edp_backlight_set_level(bl->aux, &bl->info,
> brightness);
> > +   ret = drm_edp_backlight_set_level(bl->aux, &bl->info,
> > +(u32)brightness);
> 
> Ditto.
> 
> > } else {
> > if (bl->enabled) {
> > drm_edp_backlight_disable(bl->aux, &bl->info); diff --
> git
> > a/include/drm/display/drm_dp_helper.h
> > b/include/drm/display/drm_dp_helper.h
> > index 62be80417ded..6bce0176efd3 100644
> > --- a/include/drm/display/drm_dp_helper.h
> > +++ b/include/drm/display/drm_dp_helper.h
> > @@ -853,7 +853,7 @@ drm_edp_backlight_init(struct drm_dp_aux *aux,
> struct drm_edp_backlight_info *bl
> >u16 driver_pwm_freq_hz, const u8
> edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
> >u32 *current_level, u8 *current_mode, bool
> need_luminance);
> > int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct
> drm_edp_backlight_info *bl,
> > -   u16 level);
> > +   u32 level);
> >  int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct
> drm_edp_backlight_info *bl,
> >  u16 level);
> >  int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct
> > drm_edp_backlight_info *bl);
> 
> --
> Jani Nikula, Intel

[PATCH 00/13] Modify drm helpers to use luminance

[Suraj Kandpal]

This series modifies drm dp edp helpers so that drivers can now use them
to manipulate brightness using luminance value via the
PANEL_TARGET_LUMINANCE_VALUE register. This feature was
introduced frin eDP 1.5.

Signed-off-by: Suraj Kandpal 

Suraj Kandpal (13):
  drm/dp: Introduce new member in drm_backlight_info
  drm/dp: Add argument in drm_edp_backlight_init
  drm/dp: Add argument for luminance range info in
drm_edp_backlight_init
  drm/dp: Move from u16 to u32 for max in drm_edp_backlight_info
  drm/dp: Change current_level argument type to u32
  drm/dp: Modify drm_edp_probe_state
  drm/dp: Change argument type for drm_edp_backlight_set_level
  drm/dp: Modify drm_edp_backlight_set_level
  drm/dp: Change argument type of drm_edp_backlight_enable
  drm/dp: Enable backlight control using luminance
  drm/i915/backlight: Use drm helper to initialize edp backlight
  drm/i915/backlight: Use drm helper to set edp backlight
  drm/i915/backlight: Use drm_edp_backlight_enable

 drivers/gpu/drm/display/drm_dp_helper.c   |  88 ---
 .../drm/i915/display/intel_dp_aux_backlight.c | 143 ++
 drivers/gpu/drm/nouveau/dispnv50/disp.c   |   2 +-
 drivers/gpu/drm/nouveau/nouveau_backlight.c   |   9 +-
 include/drm/display/drm_dp_helper.h   |  10 +-
 5 files changed, 126 insertions(+), 126 deletions(-)

-- 
2.34.1

[PATCH 10/13] drm/dp: Enable backlight control using luminance

[Suraj Kandpal]

Add flag to enable brightness control via luminance value
when enabling edp backlight.

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index 0421b2ed9bd4..4e2caba8311a 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4030,6 +4030,9 @@ int drm_edp_backlight_enable(struct drm_dp_aux *aux, 
const struct drm_edp_backli
else
dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM;
 
+   if (bl->luminance_set)
+   dpcd_buf |= DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
+
if (bl->pwmgen_bit_count) {
ret = drm_dp_dpcd_write_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, 
bl->pwmgen_bit_count);
if (ret < 0)
-- 
2.34.1

[PATCH 07/13] drm/dp: Change argument type for drm_edp_backlight_set_level

[Suraj Kandpal]

Use u32 for level variable as one may need to pass value for
DP_EDP_PANEL_TARGET_LUMINANCE_VALUE.

--v2
-Typecase is not needed [Jani]

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c | 2 +-
 include/drm/display/drm_dp_helper.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index bb1242a1bf6b..c4c52fb37191 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -3933,7 +3933,7 @@ EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
  * Returns: %0 on success, negative error code on failure
  */
 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
-   u16 level)
+   u32 level)
 {
int ret;
u8 buf[2] = { 0 };
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index 62be80417ded..6bce0176efd3 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -853,7 +853,7 @@ drm_edp_backlight_init(struct drm_dp_aux *aux, struct 
drm_edp_backlight_info *bl
   u16 driver_pwm_freq_hz, const u8 
edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
   u32 *current_level, u8 *current_mode, bool 
need_luminance);
 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
-   u16 level);
+   u32 level);
 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
 u16 level);
 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl);
-- 
2.34.1

[PATCH 06/13] drm/dp: Modify drm_edp_probe_state

[Suraj Kandpal]

Modify drm_edp_probe_state to read current level from
DP_EDP_PANEL_TARGET_LUMINANCE_VALUE. We divide it by
1000 since the value in this register is in millinits.

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c | 35 ++---
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index c58973d8c5f0..bb1242a1bf6b 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4185,7 +4185,7 @@ drm_edp_backlight_probe_state(struct drm_dp_aux *aux, 
struct drm_edp_backlight_i
  u8 *current_mode)
 {
int ret;
-   u8 buf[2];
+   u8 buf[3];
u8 mode_reg;
 
ret = drm_dp_dpcd_read_byte(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, 
&mode_reg);
@@ -4202,17 +4202,32 @@ drm_edp_backlight_probe_state(struct drm_dp_aux *aux, 
struct drm_edp_backlight_i
if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
int size = 1 + bl->lsb_reg_used;
 
-   ret = drm_dp_dpcd_read_data(aux, 
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
-   if (ret < 0) {
-   drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight 
level: %d\n",
-   aux->name, ret);
-   return ret;
+   if (bl->luminance_set) {
+   ret = drm_dp_dpcd_read_data(aux, 
DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
+   buf, sizeof(buf));
+   if (ret < 0) {
+   drm_dbg_kms(aux->drm_dev,
+   "%s: Failed to read backlight 
level: %d\n",
+   aux->name, ret);
+   return ret;
}
 
-   if (bl->lsb_reg_used)
-   return (buf[0] << 8) | buf[1];
-   else
-   return buf[0];
+   return (buf[0] | buf[1] << 8 | buf[2] << 16) / 1000;
+   } else {
+   ret = drm_dp_dpcd_read_data(aux, 
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+   buf, size);
+   if (ret < 0) {
+   drm_dbg_kms(aux->drm_dev,
+   "%s: Failed to read backlight 
level: %d\n",
+   aux->name, ret);
+   return ret;
+   }
+
+   if (bl->lsb_reg_used)
+   return (buf[0] << 8) | buf[1];
+   else
+   return buf[0];
+   }
}
 
/*
-- 
2.34.1

[PATCH 09/13] drm/dp: Change argument type of drm_edp_backlight_enable

[Suraj Kandpal]

Change the argument type to u32 for the default level being sent
since it has to now account for luminance value which has to be
set for DP_EDP_PANEL_LUMINANCE_TARGET_VALUE.

--v2
-No need to typecast [Jani]

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c | 2 +-
 drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
 include/drm/display/drm_dp_helper.h | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index dc0bda84d211..0421b2ed9bd4 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4020,7 +4020,7 @@ drm_edp_backlight_set_enable(struct drm_dp_aux *aux, 
const struct drm_edp_backli
  * Returns: %0 on success, negative error code on failure.
  */
 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
-const u16 level)
+const u32 level)
 {
int ret;
u8 dpcd_buf;
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c 
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 725331638a15..e3b8f6f510ef 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -1829,7 +1829,7 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, 
struct drm_atomic_state *sta
backlight = nv_connector->backlight;
if (backlight && backlight->uses_dpcd)
drm_edp_backlight_enable(&nv_connector->aux, 
&backlight->edp_info,
-
(u16)backlight->dev->props.brightness);
+
backlight->dev->props.brightness);
 #endif
 
break;
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index 6bce0176efd3..b6c03d3ca6c3 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -855,7 +855,7 @@ drm_edp_backlight_init(struct drm_dp_aux *aux, struct 
drm_edp_backlight_info *bl
 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
u32 level);
 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
-u16 level);
+u32 level);
 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl);
 
 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && 
(IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
-- 
2.34.1

[PATCH 04/13] drm/dp: Move from u16 to u32 for max in drm_edp_backlight_info

[Suraj Kandpal]

Use u32 instead of u16 for max variable in drm_edp_backlight_info
since it can now hold max luminance range value which is u32.
We will set this max with max_luminance value when luminance_set is
true.

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c | 10 +++---
 include/drm/display/drm_dp_helper.h |  2 +-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index 3b309ac5190b..1322bdfb6c8b 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4270,9 +4270,13 @@ drm_edp_backlight_init(struct drm_dp_aux *aux, struct 
drm_edp_backlight_info *bl
return -EINVAL;
}
 
-   ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, 
edp_dpcd);
-   if (ret < 0)
-   return ret;
+   if (bl->luminance_set) {
+   bl->max = lr->max_luminance;
+   } else {
+   ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, 
edp_dpcd);
+   if (ret < 0)
+   return ret;
+   }
 
ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
if (ret < 0)
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index 6f53921f5dce..39d644495f3e 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -839,7 +839,7 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum 
drm_dp_quirk quirk)
 struct drm_edp_backlight_info {
u8 pwmgen_bit_count;
u8 pwm_freq_pre_divider;
-   u16 max;
+   u32 max;
 
bool lsb_reg_used : 1;
bool aux_enable : 1;
-- 
2.34.1

[PATCH 13/13] drm/i915/backlight: Use drm_edp_backlight_enable

[Suraj Kandpal]

Use drm dp helper to enable backlight now that it has been modified
to set PANEL_LUMINANCE_CONTROL_ENABLE bit based on if capability
supports it and the driver wants it. Remove the dead code.

Signed-off-by: Suraj Kandpal 
---
 .../gpu/drm/i915/display/intel_dp_aux_backlight.c  | 14 --
 1 file changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 95b29d9af335..b8b0ace9e6fd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -499,20 +499,6 @@ intel_dp_aux_vesa_enable_backlight(const struct 
intel_crtc_state *crtc_state,
struct intel_connector *connector = 
to_intel_connector(conn_state->connector);
struct intel_panel *panel = &connector->panel;
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
-   int ret;
-
-   if (panel->backlight.edp.vesa.luminance_control_support) {
-   ret = drm_dp_dpcd_writeb(&intel_dp->aux, 
DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
-DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE);
-
-   if (ret == 1)
-   return;
-
-   if (!drm_edp_backlight_set_level(&intel_dp->aux,
-
&panel->backlight.edp.vesa.info,
-level))
-   return;
-   }
 
if (!panel->backlight.edp.vesa.info.aux_enable) {
u32 pwm_level;
-- 
2.34.1

[PATCH 05/13] drm/dp: Change current_level argument type to u32

[Suraj Kandpal]

Change the current_level argument type to u32 from u16
since it can now carry the value which it gets from
DP_EDP_PANEL_TARGET_LUMINANCE_VALUE.

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c   | 4 ++--
 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +-
 drivers/gpu/drm/nouveau/nouveau_backlight.c   | 2 +-
 include/drm/display/drm_dp_helper.h   | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index 1322bdfb6c8b..c58973d8c5f0 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4247,7 +4247,7 @@ int
 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info 
*bl,
   struct drm_luminance_range_info *lr,
   u16 driver_pwm_freq_hz, const u8 
edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
-  u16 *current_level, u8 *current_mode, bool 
need_luminance)
+  u32 *current_level, u8 *current_mode, bool 
need_luminance)
 {
int ret;
 
@@ -4355,7 +4355,7 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, 
struct drm_dp_aux *aux)
 {
struct dp_aux_backlight *bl;
struct backlight_properties props = { 0 };
-   u16 current_level;
+   u32 current_level;
u8 current_mode;
u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index abb5ad4eef5f..be740fb72ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -581,7 +581,7 @@ static int intel_dp_aux_vesa_setup_backlight(struct 
intel_connector *connector,
&connector->base.display_info.luminance_range;
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
-   u16 current_level;
+   u32 current_level;
u8 current_mode;
int ret;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c 
b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index a3681e101d56..a430ee30060e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -247,7 +247,7 @@ nv50_backlight_init(struct nouveau_backlight *bl,
 
if (nv_conn->type == DCB_CONNECTOR_eDP) {
int ret;
-   u16 current_level;
+   u32 current_level;
u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
u8 current_mode;
 
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index 39d644495f3e..62be80417ded 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -851,7 +851,7 @@ int
 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info 
*bl,
   struct drm_luminance_range_info *lr,
   u16 driver_pwm_freq_hz, const u8 
edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
-  u16 *current_level, u8 *current_mode, bool 
need_luminance);
+  u32 *current_level, u8 *current_mode, bool 
need_luminance);
 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
u16 level);
 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
-- 
2.34.1

[PATCH 08/13] drm/dp: Modify drm_edp_backlight_set_level

[Suraj Kandpal]

Modify drm_edp_backlight_set_level to be able to set the value
for register in DP_EDP_PANEL_TARGET_LUMINANCE_VALUE. We multiply
the level with 1000 since we get the value in Nits and the
register accepts it in milliNits.

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index c4c52fb37191..dc0bda84d211 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -3936,20 +3936,28 @@ int drm_edp_backlight_set_level(struct drm_dp_aux *aux, 
const struct drm_edp_bac
u32 level)
 {
int ret;
-   u8 buf[2] = { 0 };
+   unsigned int offset = DP_EDP_BACKLIGHT_BRIGHTNESS_MSB;
+   u8 buf[3] = { 0 };
 
/* The panel uses the PWM for controlling brightness levels */
-   if (!bl->aux_set)
+   if (!(bl->aux_set || bl->luminance_set))
return 0;
 
-   if (bl->lsb_reg_used) {
+   if (bl->luminance_set) {
+   level = level * 1000;
+   level &= 0xff;
+   buf[0] = (level & 0xff);
+   buf[1] = (level & 0x00ff00) >> 8;
+   buf[2] = (level & 0xff) >> 16;
+   offset = DP_EDP_PANEL_TARGET_LUMINANCE_VALUE;
+   } else if (bl->lsb_reg_used) {
buf[0] = (level & 0xff00) >> 8;
buf[1] = (level & 0x00ff);
} else {
buf[0] = level;
}
 
-   ret = drm_dp_dpcd_write_data(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, 
sizeof(buf));
+   ret = drm_dp_dpcd_write_data(aux, offset, buf, sizeof(buf));
if (ret < 0) {
drm_err(aux->drm_dev,
"%s: Failed to write aux backlight level: %d\n",
-- 
2.34.1

[PATCH 03/13] drm/dp: Add argument for luminance range info in drm_edp_backlight_init

[Suraj Kandpal]

Add new argument to drm_edp_backlight_init which gives the
drm_luminance_range_info struct which will be needed to set the min
and max values for backlight.

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c   | 5 -
 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 5 +++--
 drivers/gpu/drm/nouveau/nouveau_backlight.c   | 5 -
 include/drm/display/drm_dp_helper.h   | 1 +
 4 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index 99b27e5e3365..3b309ac5190b 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4227,6 +4227,8 @@ drm_edp_backlight_probe_state(struct drm_dp_aux *aux, 
struct drm_edp_backlight_i
  * interface.
  * @aux: The DP aux device to use for probing
  * @bl: The &drm_edp_backlight_info struct to fill out with information on the 
backlight
+ * @lr: The &drm_luminance_range_info struct which is used to get the min max 
when using
+ *luminance override
  * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
  * @edp_dpcd: A cached copy of the eDP DPCD
  * @current_level: Where to store the probed brightness level, if any
@@ -4243,6 +4245,7 @@ drm_edp_backlight_probe_state(struct drm_dp_aux *aux, 
struct drm_edp_backlight_i
  */
 int
 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info 
*bl,
+  struct drm_luminance_range_info *lr,
   u16 driver_pwm_freq_hz, const u8 
edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
   u16 *current_level, u8 *current_mode, bool 
need_luminance)
 {
@@ -4372,7 +4375,7 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, 
struct drm_dp_aux *aux)
 
bl->aux = aux;
 
-   ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
+   ret = drm_edp_backlight_init(aux, &bl->info, NULL, 0, edp_dpcd,
 ¤t_level, ¤t_mode, false);
if (ret < 0)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index d658e77b43d8..abb5ad4eef5f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -600,8 +600,9 @@ static int intel_dp_aux_vesa_setup_backlight(struct 
intel_connector *connector,
connector->base.base.id, connector->base.name);
} else {
ret = drm_edp_backlight_init(&intel_dp->aux, 
&panel->backlight.edp.vesa.info,
-panel->vbt.backlight.pwm_freq_hz, 
intel_dp->edp_dpcd,
-¤t_level, ¤t_mode, 
false);
+luminance_range, 
panel->vbt.backlight.pwm_freq_hz,
+intel_dp->edp_dpcd, 
¤t_level, ¤t_mode,
+false);
if (ret < 0)
return ret;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c 
b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index b938684a9422..a3681e101d56 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -234,6 +234,8 @@ nv50_backlight_init(struct nouveau_backlight *bl,
const struct backlight_ops **ops)
 {
struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
+   struct drm_luminance_range_info *luminance_range =
+   &nv_conn->base.display_info.luminance_range;
 
/*
 * Note when this runs the connectors have not been probed yet,
@@ -261,7 +263,8 @@ nv50_backlight_init(struct nouveau_backlight *bl,
NV_DEBUG(drm, "DPCD backlight controls supported on 
%s\n",
 nv_conn->base.name);
 
-   ret = drm_edp_backlight_init(&nv_conn->aux, 
&bl->edp_info, 0, edp_dpcd,
+   ret = drm_edp_backlight_init(&nv_conn->aux, 
&bl->edp_info,
+luminance_range, 0, 
edp_dpcd,
 ¤t_level, 
¤t_mode, false);
if (ret < 0)
return ret;
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index ef0786a0af4a..6f53921f5dce 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -849,6 +849,7 @@ struct drm_edp_backlight_info {
 
 int
 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info 
*bl,
+  struct drm_luminance_range_info *lr,
   u16 driver_pwm_freq_hz, const u8 
edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
   u16 *current_level, u8 *current

[PATCH v9 01/19] dt-bindings: display: imx: Add i.MX8qxp Display Controller processing units

[Liu Ying]

Freescale i.MX8qxp Display Controller is implemented as construction set of
building blocks with unified concept and standardized interfaces.  Document
all existing processing units.

Signed-off-by: Liu Ying 
Reviewed-by: Rob Herring (Arm) 
---
v9:
* No change.

v8:
* Drop instance numbers from compatible strings. This means switching back to
  the patch in v4. So, add Rob's previous R-b tag back. (Dmitry)

v7:
* Drop DT alias documentations and add instance numbers to compatible strings.
  (Rob)

v6:
* No change.

v5:
* Document aliases for processing units which have multiple instances in
  the Display Controller.  Drop Rob's previous R-b tag. (Maxime)

v4:
* Collect Rob's R-b tag.

v3:
* Combine fsl,imx8qxp-dc-fetchunit-common.yaml,
  fsl,imx8qxp-dc-fetchlayer.yaml and fsl,imx8qxp-dc-fetchwarp.yaml
  into 1 schema doc fsl,imx8qxp-dc-fetchunit.yaml. (Rob)
* Document all processing units. (Rob)

v2:
* Drop fsl,dc-*-id DT properties. (Krzysztof)
* Add port property to fsl,imx8qxp-dc-tcon.yaml. (Krzysztof)
* Fix register range sizes in examples.

 .../display/imx/fsl,imx8qxp-dc-blitblend.yaml |  41 +
 .../display/imx/fsl,imx8qxp-dc-clut.yaml  |  44 ++
 .../imx/fsl,imx8qxp-dc-constframe.yaml|  44 ++
 .../display/imx/fsl,imx8qxp-dc-dither.yaml|  45 ++
 .../display/imx/fsl,imx8qxp-dc-extdst.yaml|  72 +
 .../display/imx/fsl,imx8qxp-dc-fetchunit.yaml | 141 ++
 .../display/imx/fsl,imx8qxp-dc-filter.yaml|  43 ++
 .../display/imx/fsl,imx8qxp-dc-framegen.yaml  |  64 
 .../display/imx/fsl,imx8qxp-dc-gammacor.yaml  |  32 
 .../imx/fsl,imx8qxp-dc-layerblend.yaml|  39 +
 .../display/imx/fsl,imx8qxp-dc-matrix.yaml|  44 ++
 .../display/imx/fsl,imx8qxp-dc-rop.yaml   |  43 ++
 .../display/imx/fsl,imx8qxp-dc-safety.yaml|  34 +
 .../imx/fsl,imx8qxp-dc-scaling-engine.yaml|  83 +++
 .../display/imx/fsl,imx8qxp-dc-signature.yaml |  53 +++
 .../display/imx/fsl,imx8qxp-dc-store.yaml |  96 
 .../display/imx/fsl,imx8qxp-dc-tcon.yaml  |  45 ++
 17 files changed, 963 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blitblend.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-clut.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-dither.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-filter.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-gammacor.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-matrix.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-rop.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-safety.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-scaling-engine.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-signature.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-store.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blitblend.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blitblend.yaml
new file mode 100644
index ..095e65939fba
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blitblend.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blitblend.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Blit Blend Unit
+
+description:
+  Combines two input frames to a single output frame, all frames having the
+  same dimension.
+
+maintainers:
+  - Liu Ying 
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-blitblend
+
+  reg:
+maxItems: 2
+
+  reg-names:
+items:
+  - const: pec
+  - const: cfg
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+additionalProperties: false
+
+examples:
+  - |
+blitblend@56180920 {
+compatible = "fsl,imx8qxp-dc-blitblend";
+reg = <0x56180920 0x10>, <0x56183c00 0x3c>;
+reg-names = "pec", "cfg";
+};
diff --git 
a/Documentation/devicetree/bindi

[PATCH v9 03/19] dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine

[Liu Ying]

i.MX8qxp Display Controller display engine consists of all processing units
that operate in a display clock domain.

Signed-off-by: Liu Ying 
Reviewed-by: Rob Herring (Arm) 
---
v9:
* No change.

v8:
* Drop instance numbers from compatible strings. This means switching back to
  the patch in v4. So, add Rob's previous R-b tag back. (Dmitry)

v7:
* Drop DT alias documentations and add instance numbers to compatible strings.
  (Rob)

v6:
* No change.

v5:
* Document aliases.  Drop Rob's previous R-b tag. (Maxime)

v4:
* Collect Rob's R-b tag.

v3:
* No change.

v2:
* Drop fsl,dc-*-id DT properties. (Krzysztof)
* Drop port property. (Krzysztof)
* Fix register range sizes in example.

 .../imx/fsl,imx8qxp-dc-display-engine.yaml| 152 ++
 1 file changed, 152 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
new file mode 100644
index ..91f3bb77d8d0
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-display-engine.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 
http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Display Engine
+
+description:
+  All Processing Units that operate in a display clock domain. Pixel pipeline
+  is driven by a video timing and cannot be stalled. Implements all display
+  specific processing.
+
+maintainers:
+  - Liu Ying 
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-display-engine
+
+  reg:
+maxItems: 2
+
+  reg-names:
+items:
+  - const: top
+  - const: cfg
+
+  resets:
+maxItems: 1
+
+  interrupts:
+maxItems: 3
+
+  interrupt-names:
+items:
+  - const: shdload
+  - const: framecomplete
+  - const: seqcomplete
+
+  power-domains:
+maxItems: 1
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 1
+
+  ranges: true
+
+patternProperties:
+  "^dither@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-dither
+
+  "^framegen@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-framegen
+
+  "^gammacor@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-gammacor
+
+  "^matrix@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-matrix
+
+  "^signature@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-signature
+
+  "^tcon@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-tcon
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - power-domains
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+display-engine@5618b400 {
+compatible = "fsl,imx8qxp-dc-display-engine";
+reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
+reg-names = "top", "cfg";
+interrupt-parent = <&dc0_intc>;
+interrupts = <15>, <16>, <17>;
+interrupt-names = "shdload", "framecomplete", "seqcomplete";
+power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+framegen@5618b800 {
+compatible = "fsl,imx8qxp-dc-framegen";
+reg = <0x5618b800 0x98>;
+clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
+interrupt-parent = <&dc0_intc>;
+interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
+interrupt-names = "int0", "int1", "int2", "int3",
+  "primsync_on", "primsync_off",
+  "secsync_on", "secsync_off";
+};
+
+tcon@5618c800 {
+compatible = "fsl,imx8qxp-dc-tcon";
+reg = <0x5618c800 0x588>;
+
+port {
+dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
+remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
+};
+};
+};
+};
-- 
2.34.1

Re: [PATCH v2 2/3] accel/amdpk: add driver for AMD PKI accelerator

[Lukas Wunner]

On Fri, Apr 11, 2025 at 10:21:03AM +0530, Gupta, Nipun wrote:
> On 10-04-2025 13:06, Krzysztof Kozlowski wrote:
> > On Wed, Apr 09, 2025 at 11:00:32PM GMT, Nipun Gupta wrote:
> > > The AMD PKI accelerator driver provides a accel interface to interact
> > > with the device for offloading and accelerating asymmetric crypto
> > > operations.
> > > 
> > 
> > For me this is clearly a crypto driver and you are supposed to:
> > 1. Cc crypto maintaners,
> > 2. Put it actually into crypto and use crypto API.
> 
> added crypto maintainers for comments.
> IMO, as accel framework is designed to support any type of compute
> accelerators, the PKI crypto accelerator in accel framework is not
> completely out of place here, as also suggested at:
> https://lore.kernel.org/all/2025031352-gyration-deceit-5563@gregkh/

To be fair, Greg did suggest drivers/crypto/ as an alternative... :)

  "Great, then why isn't this in drivers/accel/ or drivers/crypto/ ?"
  https://lore.kernel.org/r/2025031236-siamese-graffiti-5b98@gregkh/

There are already six drivers for crypto accelerators in drivers/crypto/,
so that would seem to be a natural fit for your driver:

  aspeed/aspeed-acry.c
  caam/caampkc.c
  ccp/ccp-crypto-rsa.c <-- from AMD no less!
  hisilicon/hpre/hpre_crypto.c
  intel/qat/qat_common/qat_asym_algs.c
  starfive/jh7110-rsa.c

You can find these in the tree with:

  git grep 'cra_name = "rsa"'

So far there are only drivers to accelerate RSA encryption/decryption.
The kernel supports a single padding scheme, PKCS1, which is implemented
by crypto/rsa-pkcs1pad.c.  There is no support yet for OAEP.

So the padding of the hash (which is cheap) happens in software and then
crypto/rsa-pkcs1pad.c performs an RSA encrypt/decrypt operation which is
either performed in software by crypto/rsa.c, or in hardware if a crypto
accelerator is present.  Drivers for crypto accelerators register the
"rsa" algorithm with a higher cra_priority than the software
implementation, hence are generally preferred.

One benefit that you get from implementing a proper akcipher_alg in your
driver is that virtual machines may take advantage of the hardware
accelerator through the virtio support implemented by:
drivers/crypto/virtio/virtio_crypto_akcipher_algs.c

Note that the crypto subsystem currently does not support hardware
acceleration of signature generation/verification (crypto_sig),
but only encryption/decryption (crypto_akcipher).  One reason is
that signature generation/verification is generally a synchronous
operation and doesn't benefit as much from hardware acceleration
due to the overhead of interacting with the hardware.

So there's no support e.g. for generating or verifying ECDSA signatures
in hardware.  I think that would only really make sense if private keys
are kept in hardware and cannot be retrieved.  So the use case wouldn't
be acceleration, but security of private keys.

That said, for RSA specifically, signature generation/verification does
involve an encrypt/decrypt operation internally.  The padding is once
again done in software (by crypto/rsassa-pkcs1.c -- no PSS support yet).
But the actual encrypt/decrypt operation will be performed in
hardware if a crypto accelerator is present.

The user space interface Herbert referred to is a set of system calls
which are usable e.g. via the keyutils library and command line utility:
https://git.kernel.org/pub/scm/linux/kernel/git/dhowells/keyutils.git/

HTH,

Lukas

Re: [PATCH v2 1/2] drm/amdgpu: Fix double free in amdgpu_userq_fence_driver_alloc()

[Yadav, Arvind]

Reviewed-by:Reviewed-by:Arvind Yadav 

On 4/12/2025 8:09 PM, Dan Carpenter wrote:

The goto frees "fence_drv" so this is a double free bug.  There is no
need to call amdgpu_seq64_free(adev, fence_drv->va) since the seq64
allocation failed so change the goto to goto free_fence_drv.  Also
propagate the error code from amdgpu_seq64_alloc() instead of hard coding
it to -ENOMEM.

Fixes: e7cf21fbb277 ("drm/amdgpu: Few optimization and fixes for userq fence 
driver")
Signed-off-by: Dan Carpenter 
---
v2: No change.

  drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 7 ++-
  1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
index a4953d668972..b012fece91e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
@@ -84,11 +84,8 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device 
*adev,
/* Acquire seq64 memory */
r = amdgpu_seq64_alloc(adev, &fence_drv->va, &fence_drv->gpu_addr,
   &fence_drv->cpu_addr);
-   if (r) {
-   kfree(fence_drv);
-   r = -ENOMEM;
-   goto free_seq64;
-   }
+   if (r)
+   goto free_fence_drv;
  
  	memset(fence_drv->cpu_addr, 0, sizeof(u64));
  

Re: [PATCH v2 2/2] drm/amdgpu: Clean up error handling in amdgpu_userq_fence_driver_alloc()

[Yadav, Arvind]

Reviewed-by:Arvind Yadav 

On 4/12/2025 8:09 PM, Dan Carpenter wrote:

1) Checkpatch complains if we print an error message for kzalloc()
failure.  The kzalloc() failure already has it's own error messages
built in.  Also this allocation is small enough that it is guaranteed
to succeed.
2) Return directly instead of doing a goto free_fence_drv.  The
"fence_drv" is already NULL so no cleanup is necessary.

Signed-off-by: Dan Carpenter 
---
v2: New patch

  drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 7 ++-
  1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
index b012fece91e8..86eab5461162 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
@@ -75,11 +75,8 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device 
*adev,
int r;
  
  	fence_drv = kzalloc(sizeof(*fence_drv), GFP_KERNEL);

-   if (!fence_drv) {
-   DRM_ERROR("Failed to allocate memory for fence driver\n");
-   r = -ENOMEM;
-   goto free_fence_drv;
-   }
+   if (!fence_drv)
+   return -ENOMEM;
  
  	/* Acquire seq64 memory */

r = amdgpu_seq64_alloc(adev, &fence_drv->va, &fence_drv->gpu_addr,

Re: [PATCH v1 4/4] drm: panel: Add support for Renesas R69328 based MIPI DSI panel

[ALOK TIWARI]

On 13-04-2025 16:54, Svyatoslav Ryhel wrote:

From: Maxim Schwalm 

Driver adds support for panels with Renesas R69328 IC

Currently supported compatible is:
- jdi,dx12d100vm0eaa

Co-developed-by: Svyatoslav Ryhel 
Signed-off-by: Svyatoslav Ryhel 
Signed-off-by: Maxim Schwalm 
---
  drivers/gpu/drm/panel/Kconfig|  13 +
  drivers/gpu/drm/panel/Makefile   |   1 +
  drivers/gpu/drm/panel/panel-renesas-r69328.c | 282 +++
  3 files changed, 296 insertions(+)
  create mode 100644 drivers/gpu/drm/panel/panel-renesas-r69328.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index e8723f42cafb..86c66f818a11 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -618,6 +618,19 @@ config DRM_PANEL_RENESAS_R61307
  This panel controller can be found in LG Optimus Vu P895 smartphone
  in combination with LCD panel.
  
+config DRM_PANEL_RENESAS_R69328

+   tristate "Renesas R69328 720x1280 DSI video mode panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to enable support for JDI dx12d100vm0eaa
+ IPS-LCD module with Renesas R69328 IC. The panel has a 720x1280
+ resolution and uses 24 bit RGB per pixel.
+
+ This panel controller can be found in LG Optimus 4X P895 smartphone
+ in combination with LCD panel.
+
  config DRM_PANEL_RONBO_RB070D30
tristate "Ronbo Electronics RB070D30 panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 61d8853df1a7..37e4e13165a9 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += 
panel-raydium-rm68200.o
  obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM692E5) += panel-raydium-rm692e5.o
  obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM69380) += panel-raydium-rm69380.o
  obj-$(CONFIG_DRM_PANEL_RENESAS_R61307) += panel-renesas-r61307.o
+obj-$(CONFIG_DRM_PANEL_RENESAS_R69328) += panel-renesas-r69328.o
  obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o
  obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01) += panel-samsung-ams581vf01.o
  obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08) += panel-samsung-ams639rq08.o
diff --git a/drivers/gpu/drm/panel/panel-renesas-r69328.c 
b/drivers/gpu/drm/panel/panel-renesas-r69328.c
new file mode 100644
index ..207067b29473
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-renesas-r69328.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0


add Blank line


+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+
+#define R69328_MACP0xb0 /* Manufacturer Access CMD Protect */
+#define   R69328_MACP_ON   0x03
+#define   R69328_MACP_OFF  0x04


remove extra ' ' after #define


+
+#define R69328_GAMMA_SET_A 0xc8 /* Gamma Setting A */
+#define R69328_GAMMA_SET_B 0xc9 /* Gamma Setting B */
+#define R69328_GAMMA_SET_C 0xca /* Gamma Setting C */
+
+#define R69328_POWER_SET   0xd1
+
+struct renesas_r69328 {
+   struct drm_panel panel;
+   struct mipi_dsi_device *dsi;
+
+   struct regulator *vdd_supply;
+   struct regulator *vddio_supply;
+   struct gpio_desc *reset_gpio;
+
+   bool prepared;
+};
+
+static inline struct renesas_r69328 *to_renesas_r69328(struct drm_panel *panel)
+{
+   return container_of(panel, struct renesas_r69328, panel);
+}
+
+static void renesas_r69328_reset(struct renesas_r69328 *priv)
+{
+   gpiod_set_value_cansleep(priv->reset_gpio, 1);
+   usleep_range(1, 11000);
+   gpiod_set_value_cansleep(priv->reset_gpio, 0);
+   usleep_range(2000, 3000);
+}
+
+static int renesas_r69328_prepare(struct drm_panel *panel)
+{
+   struct renesas_r69328 *priv = to_renesas_r69328(panel);
+   struct device *dev = &priv->dsi->dev;
+   int ret;
+
+   if (priv->prepared)
+   return 0;
+
+   ret = regulator_enable(priv->vdd_supply);
+   if (ret) {
+   dev_err(dev, "failed to enable vdd power supply\n");
+   return ret;
+   }
+
+   usleep_range(1, 11000);
+
+   ret = regulator_enable(priv->vddio_supply);
+   if (ret < 0) {
+   dev_err(dev, "failed to enable vddio power supply\n");
+   return ret;
+   }
+
+   usleep_range(1, 11000);
+
+   renesas_r69328_reset(priv);
+
+   priv->prepared = true;


a '\n' before return


+   return 0;
+}
+
+static int renesas_r69328_enable(struct drm_panel *panel)
+{
+   struct renesas_r69328 *priv = to_renesas_r69328(panel);
+   struct mipi_dsi_multi_context ctx = { .dsi = priv->dsi };
+
+   /* Set address mode */
+   mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
+   mipi_dsi_dcs_set_pixel_format_multi(&ctx, MIPI_DCS_PIXEL

[PATCH 02/13] drm/dp: Add argument in drm_edp_backlight_init

[Suraj Kandpal]

Add bool argument in drm_edp_backlight init to provide the drivers
option to choose if they want to use luminance values to
manipulate brightness.

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/display/drm_dp_helper.c   | 7 ---
 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +-
 drivers/gpu/drm/nouveau/nouveau_backlight.c   | 2 +-
 include/drm/display/drm_dp_helper.h   | 2 +-
 4 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index 41de7a92d76d..99b27e5e3365 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -4231,6 +4231,7 @@ drm_edp_backlight_probe_state(struct drm_dp_aux *aux, 
struct drm_edp_backlight_i
  * @edp_dpcd: A cached copy of the eDP DPCD
  * @current_level: Where to store the probed brightness level, if any
  * @current_mode: Where to store the currently set backlight control mode
+ * @need_luminance: Tells us if a we want to manipulate backlight using 
luminance values
  *
  * Initializes a &drm_edp_backlight_info struct by probing @aux for it's 
backlight capabilities,
  * along with also probing the current and maximum supported brightness levels.
@@ -4243,7 +4244,7 @@ drm_edp_backlight_probe_state(struct drm_dp_aux *aux, 
struct drm_edp_backlight_i
 int
 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info 
*bl,
   u16 driver_pwm_freq_hz, const u8 
edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
-  u16 *current_level, u8 *current_mode)
+  u16 *current_level, u8 *current_mode, bool 
need_luminance)
 {
int ret;
 
@@ -4254,7 +4255,7 @@ drm_edp_backlight_init(struct drm_dp_aux *aux, struct 
drm_edp_backlight_info *bl
if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
bl->lsb_reg_used = true;
if ((edp_dpcd[0] & DP_EDP_15) && edp_dpcd[3] &
-   (DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE))
+   (DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) && need_luminance)
bl->luminance_set = true;
 
/* Sanity check caps */
@@ -4372,7 +4373,7 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, 
struct drm_dp_aux *aux)
bl->aux = aux;
 
ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
-¤t_level, ¤t_mode);
+¤t_level, ¤t_mode, false);
if (ret < 0)
return ret;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 20ab90acb351..d658e77b43d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -601,7 +601,7 @@ static int intel_dp_aux_vesa_setup_backlight(struct 
intel_connector *connector,
} else {
ret = drm_edp_backlight_init(&intel_dp->aux, 
&panel->backlight.edp.vesa.info,
 panel->vbt.backlight.pwm_freq_hz, 
intel_dp->edp_dpcd,
-¤t_level, ¤t_mode);
+¤t_level, ¤t_mode, 
false);
if (ret < 0)
return ret;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c 
b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index d47442125fa1..b938684a9422 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -262,7 +262,7 @@ nv50_backlight_init(struct nouveau_backlight *bl,
 nv_conn->base.name);
 
ret = drm_edp_backlight_init(&nv_conn->aux, 
&bl->edp_info, 0, edp_dpcd,
-¤t_level, 
¤t_mode);
+¤t_level, 
¤t_mode, false);
if (ret < 0)
return ret;
 
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index b8fdc09737fc..ef0786a0af4a 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -850,7 +850,7 @@ struct drm_edp_backlight_info {
 int
 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info 
*bl,
   u16 driver_pwm_freq_hz, const u8 
edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
-  u16 *current_level, u8 *current_mode);
+  u16 *current_level, u8 *current_mode, bool 
need_luminance);
 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
u16 level);
 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct 
drm_edp_backlight_info *bl,
-- 
2.34.1

[PATCH 12/13] drm/i915/backlight: Use drm helper to set edp backlight

[Suraj Kandpal]

Now that the drm helper sets the backlight using luminance
too we can use that. Remove the obselete function.

Signed-off-by: Suraj Kandpal 
---
 .../drm/i915/display/intel_dp_aux_backlight.c | 34 ++-
 1 file changed, 3 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 2eff9b545390..95b29d9af335 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -476,31 +476,6 @@ static u32 intel_dp_aux_vesa_get_backlight(struct 
intel_connector *connector, en
return connector->panel.backlight.level;
 }
 
-static int
-intel_dp_aux_vesa_set_luminance(struct intel_connector *connector, u32 level)
-{
-   struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
-   u8 buf[3];
-   int ret;
-
-   level = level * 1000;
-   level &= 0xff;
-   buf[0] = (level & 0xff);
-   buf[1] = (level & 0x00ff00) >> 8;
-   buf[2] = (level & 0xff) >> 16;
-
-   ret = drm_dp_dpcd_write(&intel_dp->aux, 
DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
-   buf, sizeof(buf));
-   if (ret != sizeof(buf)) {
-   drm_err(intel_dp->aux.drm_dev,
-   "%s: Failed to set VESA Aux Luminance: %d\n",
-   intel_dp->aux.name, ret);
-   return -EINVAL;
-   } else {
-   return 0;
-   }
-}
-
 static void
 intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, 
u32 level)
 {
@@ -508,11 +483,6 @@ intel_dp_aux_vesa_set_backlight(const struct 
drm_connector_state *conn_state, u3
struct intel_panel *panel = &connector->panel;
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
 
-   if (panel->backlight.edp.vesa.luminance_control_support) {
-   if (!intel_dp_aux_vesa_set_luminance(connector, level))
-   return;
-   }
-
if (!panel->backlight.edp.vesa.info.aux_set) {
const u32 pwm_level = intel_backlight_level_to_pwm(connector, 
level);
 
@@ -538,7 +508,9 @@ intel_dp_aux_vesa_enable_backlight(const struct 
intel_crtc_state *crtc_state,
if (ret == 1)
return;
 
-   if (!intel_dp_aux_vesa_set_luminance(connector, level))
+   if (!drm_edp_backlight_set_level(&intel_dp->aux,
+
&panel->backlight.edp.vesa.info,
+level))
return;
}
 
-- 
2.34.1

[PATCH v9 02/19] dt-bindings: display: imx: Add i.MX8qxp Display Controller blit engine

[Liu Ying]

i.MX8qxp Display Controller contains a blit engine for raster graphics.
It may read up to 3 source images from memory and computes one destination
image from it, which is written back to memory.

Signed-off-by: Liu Ying 
Reviewed-by: Rob Herring (Arm) 
---
v9:
* No change.

v8:
* Drop instance numbers from compatible strings. This means switching back to
  the patch in v4. So, add Rob's previous R-b tag back. (Dmitry)

v7:
* Add instance numbers to blit engine internal devices' compatible strings.
  (Rob)
* Drop Rob's R-b tag.

v6:
* No change.

v5:
* No change.

v4:
* Collect Rob's R-b tag.

v3:
* New patch. (Rob)

 .../imx/fsl,imx8qxp-dc-blit-engine.yaml   | 204 ++
 1 file changed, 204 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blit-engine.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blit-engine.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blit-engine.yaml
new file mode 100644
index ..45db6da39e20
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-blit-engine.yaml
@@ -0,0 +1,204 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blit-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Blit Engine
+
+description: |
+  A blit operation (block based image transfer) reads up to 3 source images
+  from memory and computes one destination image from it, which is written
+  back to memory. The following basic operations are supported:
+
+  * Buffer Fill
+Fills a buffer with constant color
+
+  * Buffer Copy
+Copies one source to a destination buffer.
+
+  * Image Blend
+Combines two source images by a blending equation and writes result to
+destination (which can be one of the sources).
+
+  * Image Rop2/3
+Combines up to three source images by a logical equation (raster operation)
+and writes result to destination (which can be one of the sources).
+
+  * Image Flip
+Mirrors the source image in horizontal and/or vertical direction.
+
+  * Format Convert
+Convert between the supported color and buffer formats.
+
+  * Color Transform
+Modify colors by linear or non-linear transformations.
+
+  * Image Scale
+Changes size of the source image.
+
+  * Image Rotate
+Rotates the source image by any angle.
+
+  * Image Filter
+Performs an FIR filter operation on the source image.
+
+  * Image Warp
+Performs a re-sampling of the source image with any pattern. The sample
+point positions are read from a compressed coordinate buffer.
+
+  * Buffer Pack
+Writes an image with color components stored in up to three different
+buffers (planar formats) into a single buffer (packed format).
+
+  * Chroma Resample
+Converts between different YUV formats that differ in chroma sampling rate
+(4:4:4, 4:2:2, 4:2:0).
+
+maintainers:
+  - Liu Ying 
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-blit-engine
+
+  reg:
+maxItems: 2
+
+  reg-names:
+items:
+  - const: pec
+  - const: cfg
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 1
+
+  ranges: true
+
+patternProperties:
+  "^blitblend@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-blitblend
+
+  "^clut@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-clut
+
+  "^fetchdecode@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-fetchdecode
+
+  "^fetcheco@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-fetcheco
+
+  "^fetchwarp@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-fetchwarp
+
+  "^filter@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-filter
+
+  "^hscaler@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-hscaler
+
+  "^matrix@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-matrix
+
+  "^rop@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-rop
+
+  "^store@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-store
+
+  "^vscaler@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  comp

[PATCH v9 05/19] dt-bindings: display: imx: Add i.MX8qxp Display Controller AXI performance counter

[Liu Ying]

i.MX8qxp Display Controller contains a AXI performance counter which allows
measurement of average bandwidth and latency during operation.

Signed-off-by: Liu Ying 
Reviewed-by: Rob Herring (Arm) 
---
v9:
* No change.

v8:
* No change.

v7:
* No change.

v6:
* No change.

v5:
* No change.

v4:
* Collect Rob's R-b tag.

v3:
* New patch. (Rob)

 ...sl,imx8qxp-dc-axi-performance-counter.yaml | 57 +++
 1 file changed, 57 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml
 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml
new file mode 100644
index ..1d6501afc7f2
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 
http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller AXI Performance Counter
+
+description: |
+  Performance counters are provided to allow measurement of average bandwidth
+  and latency during operation. The following features are supported:
+
+  * Manual and timer controlled measurement mode.
+
+  * Measurement counters:
+- GLOBAL_COUNTER for overall measurement time
+- BUSY_COUNTER for number of data bus busy cycles
+- DATA_COUNTER for number of data transfer cycles
+- TRANSFER_COUNTER for number of transfers
+- ADDRBUSY_COUNTER for number of address bus busy cycles
+- LATENCY_COUNTER for average latency
+
+  * Counter overflow detection.
+
+  * Outstanding Transfer Counters (OTC) which are used for latency measurement
+have to run immediately after reset, but can be disabled by software when
+there is no need for latency measurement.
+
+maintainers:
+  - Liu Ying 
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-axi-performance-counter
+
+  reg:
+maxItems: 1
+
+  clocks:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+pmu@5618f000 {
+compatible = "fsl,imx8qxp-dc-axi-performance-counter";
+reg = <0x5618f000 0x90>;
+clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
+};
-- 
2.34.1

[DO NOT MERGE PATCH v9 16/19] arm64: dts: imx8qxp: Add display controller subsystem

[Liu Ying]

Add display controller subsystem in i.MX8qxp SoC.

Signed-off-by: Liu Ying 
---
v9:
* No change.

v8:
* Drop instance numbers from display controller internal devices' compatible
  strings. (Dmitry)

v7:
* Add instance numbers to display controller internal devices' compatible
  strings.
* Drop aliases.

v6:
* No change.

v5:
* No change.

v4:
* No change.

v3:
* No change.

v2:
* New patch. (Krzysztof)

 .../arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 408 ++
 .../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 236 ++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi|   4 +-
 3 files changed, 647 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi 
b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi
new file mode 100644
index ..0db345204b89
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include 
+#include 
+#include 
+
+dc0_axi_ext_clk: clock-dc0-axi-ext {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <8>;
+   clock-output-names = "dc0_axi_ext_clk";
+};
+
+dc0_axi_int_clk: clock-dc0-axi-int {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <4>;
+   clock-output-names = "dc0_axi_int_clk";
+};
+
+dc0_cfg_clk: clock-dc0-cfg {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <1>;
+   clock-output-names = "dc0_cfg_clk";
+};
+
+dc0_subsys: bus@5600 {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0x5600 0x0 0x5600 0x100>;
+
+   dc0_irqsteer: interrupt-controller@5600 {
+   compatible = "fsl,imx-irqsteer";
+   reg = <0x5600 0x1000>;
+   interrupt-controller;
+   interrupt-parent = <&gic>;
+   #interrupt-cells = <1>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   clocks = <&dc0_lis_lpcg IMX_LPCG_CLK_4>;
+   clock-names = "ipg";
+   fsl,channel = <0>;
+   fsl,num-irqs = <512>;
+   };
+
+   dc0_disp_lpcg: clock-controller@5601 {
+   reg = <0x5601 0x4>;
+   #clock-cells = <1>;
+   clocks = <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
+<&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>;
+   clock-indices = , ;
+   clock-output-names = "dc0_disp0_lpcg_clk", "dc0_disp1_lpcg_clk";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   };
+
+   dc0_lis_lpcg: clock-controller@56010004 {
+   reg = <0x56010004 0x4>;
+   #clock-cells = <1>;
+   clocks = <&dc0_cfg_clk>;
+   clock-indices = ;
+   clock-output-names = "dc0_lis_lpcg_ipg_clk";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   };
+
+   dc0_disp_ctrl_link_mst0_lpcg: clock-controller@56010008 {
+   reg = <0x56010008 0x4>;
+   #clock-cells = <1>;
+   clocks = <&dc0_cfg_clk>;
+   clock-indices = ;
+   clock-output-names = "dc0_disp_ctrl_link_mst0_lpcg_msi_clk";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   };
+
+   dc0_pixel_combiner_lpcg: clock-controller@56010010 {
+   reg = <0x56010010 0x4>;
+   #clock-cells = <1>;
+   clocks = <&dc0_cfg_clk>;
+   clock-indices = ;
+   clock-output-names = "dc0_pixel_combiner_lpcg_apb_clk";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   };
+
+   dc0_lpcg: clock-controller@56010014 {
+   reg = <0x56010014 0x4>;
+   #clock-cells = <1>;
+   clocks = <&dc0_cfg_clk>, <&dc0_axi_int_clk>;
+   clock-indices = , ;
+   clock-output-names = "dc0_lpcg_cfg_clk",
+"dc0_lpcg_axi_clk";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   };
+
+   dc0_pc: pixel-combiner@5602 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x5602 0x1>;
+   clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
+   clock-names = "apb";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   status = "disabled";
+
+   channel@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+   

[DO NOT MERGE PATCH v9 19/19] arm64: dts: imx8qxp-mek: Add MX8-DLVDS-LCD1 display module support

[Liu Ying]

MX8-DLVDS-LCD1 display module integrates a KOE TX26D202VM0BWA LCD panel
and a touch IC.  Add an overlay to support the LCD panel on i.MX8qxp
MEK.  mipi_lvds_0_ldb channel0 and mipi_lvds_1_ldb channel1 send odd
and even pixels to the panel respectively.

Signed-off-by: Liu Ying 
---
v9:
* Rebase on v6.15-rc1.

v8:
* No change.

v7:
* No change.

v6:
* No change.

v5:
* No change.

v4:
* No change.

v3:
* No change.

v2:
* New patch. (Francesco)

 arch/arm64/boot/dts/freescale/Makefile|   2 +
 .../imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso | 183 ++
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts |  30 +++
 3 files changed, 215 insertions(+)
 create mode 100644 
arch/arm64/boot/dts/freescale/imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso

diff --git a/arch/arm64/boot/dts/freescale/Makefile 
b/arch/arm64/boot/dts/freescale/Makefile
index b6d3fe26d621..ec3f786b15ce 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -284,7 +284,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
 
+imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd-dtbs += imx8qxp-mek.dtb 
imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtbo
 imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx8qxp-mek-pcie-ep.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb
 
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
diff --git 
a/arch/arm64/boot/dts/freescale/imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso 
b/arch/arm64/boot/dts/freescale/imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso
new file mode 100644
index ..7ddd90e68754
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include 
+
+&{/} {
+   panel-lvds0 {
+   compatible = "koe,tx26d202vm0bwa";
+   backlight = <&backlight_lvds1>;
+   power-supply = <®_vcc_per_3v3>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dual-lvds-odd-pixels;
+
+   panel_lvds0_in: endpoint {
+   remote-endpoint = <&lvds0_out>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dual-lvds-even-pixels;
+
+   panel_lvds1_in: endpoint {
+   remote-endpoint = <&lvds1_out>;
+   };
+   };
+   };
+   };
+};
+
+&backlight_lvds1 {
+   status = "okay";
+};
+
+&dc0_framegen0 {
+   assigned-clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>;
+   assigned-clock-parents = <0>,
+<&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>;
+   assigned-clock-rates = <94032>;
+};
+
+&dc0_pixel_link0 {
+   status = "okay";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@1 {
+   reg = <1>;
+
+   status = "okay";
+   };
+   };
+};
+
+&dc0_pc {
+   status = "okay";
+
+   channel@0 {
+   status = "okay";
+   };
+};
+
+&mipi_lvds_0_ldb {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   fsl,companion-ldb = <&mipi_lvds_1_ldb>;
+   status = "okay";
+
+   channel@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+   status = "okay";
+
+   port@1 {
+   reg = <1>;
+
+   lvds0_out: endpoint {
+   remote-endpoint = <&panel_lvds0_in>;
+   };
+   };
+   };
+};
+
+&mipi_lvds_0_phy {
+   status = "okay";
+};
+
+&mipi_lvds_0_pxl2dpi {
+   fsl,companion-pxl2dpi = <&mipi_lvds_1_pxl2dpi>;
+   status = "okay";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+
+   mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
+   status = "okay";
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+
+   mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+   status = "okay";
+   };
+   };
+   };
+};
+
+&mipi_lvds_1_ldb {
+ 

[DO NOT MERGE PATCH v9 15/19] dt-bindings: firmware: imx: Add SCU controlled display pixel link nodes

[Liu Ying]

Document SCU controlled display pixel link child nodes.

Signed-off-by: Liu Ying 
---
v9:
* No change.

v8:
* No change.

v7:
* No change.

v6:
* No change.

v5:
* No change.

v4:
* No change.

v3:
* No change.

v2:
* New patch as needed by display controller subsystem device tree.

 .../devicetree/bindings/firmware/fsl,scu.yaml | 20 +++
 1 file changed, 20 insertions(+)

diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml 
b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
index f9ba18f06369..e3b9e7e2d040 100644
--- a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
+++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
@@ -30,6 +30,26 @@ properties:
   Clock controller node that provides the clocks controlled by the SCU
 $ref: /schemas/clock/fsl,scu-clk.yaml
 
+  dc0-pixel-link0:
+description:
+  Display pixel link0 in display controller subsystem0 controlled by the 
SCU
+$ref: /schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml
+
+  dc0-pixel-link1:
+description:
+  Display pixel link1 in display controller subsystem0 controlled by the 
SCU
+$ref: /schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml
+
+  dc1-pixel-link0:
+description:
+  Display pixel link0 in display controller subsystem1 controlled by the 
SCU
+$ref: /schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml
+
+  dc1-pixel-link1:
+description:
+  Display pixel link1 in display controller subsystem1 controlled by the 
SCU
+$ref: /schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml
+
   gpio:
 description:
   Control the GPIO PINs on SCU domain over the firmware APIs
-- 
2.34.1

[PATCH v9 09/19] drm/imx: Add i.MX8qxp Display Controller display engine

[Liu Ying]

i.MX8qxp Display Controller display engine consists of all processing
units that operate in a display clock domain.  Add minimal feature
support with FrameGen and TCon so that the engine can output display
timings.  The FrameGen driver, TCon driver and display engine driver
are components to be aggregated by a master registered in the upcoming
DRM driver.

Reviewed-by: Maxime Ripard 
Signed-off-by: Liu Ying 
Reviewed-by: Dmitry Baryshkov 
---
v9:
* Add Dmitry's R-b tag.

v8:
* Get DE/FG/TC device instance numbers through register start addresses of the
  devices, instead of compatible strings. (Dmitry)
* s/shdld/shdload/ for DE IRQs. (Dmitry)
* Drop id member from struct dc_de. (Dmitry)
* Add dc_de_post_bind(), to avoid dependency on the component helper's way of
  implementing component binding order. (Dmitry)

v7:
* Add kernel doc for struct dc_drm_device. (Dmitry)
* Fix regmap_config definitions by correcting name field, correcting read
  ranges and setting max_register field.
* Get instance numbers from device data(compatible strings) instead of OF
  aliases.
* Collect Maxime's R-b tag.
* Trivial tweaks.

v6:
* No change.

v5:
* Replace .remove_new with .remove in dc-{de,fg,tc}.c. (Uwe)
* Select REGMAP and REGMAP_MMIO Kconfig options.
* Fix commit message to state that display engine driver is a component driver
  instead of a master/aggregate driver.

v4:
* Use regmap to define register map for all registers. (Dmitry)
* Use regmap APIs to access registers. (Dmitry)
* Inline some small functions. (Dmitry)
* Move dc_fg_displaymode() and dc_fg_panic_displaymode() function calls from
  KMS routine to initialization stage. (Dmitry)
* Use devm_kzalloc() to drmm_kzalloc() to allocate dc_* data strutures.
* Drop unnecessary private struct dc_*_priv.
* Set suppress_bind_attrs driver flag to true to avoid unnecessary sys
  interfaces to bind/unbind the drivers.

v3:
* No change.

v2:
* Use OF alias id to get instance id.
* Add dev member to struct dc_tc.

 drivers/gpu/drm/imx/Kconfig |   1 +
 drivers/gpu/drm/imx/Makefile|   1 +
 drivers/gpu/drm/imx/dc/Kconfig  |   7 +
 drivers/gpu/drm/imx/dc/Makefile |   5 +
 drivers/gpu/drm/imx/dc/dc-de.c  | 177 +++
 drivers/gpu/drm/imx/dc/dc-de.h  |  56 +
 drivers/gpu/drm/imx/dc/dc-drv.c |  32 +++
 drivers/gpu/drm/imx/dc/dc-drv.h |  57 +
 drivers/gpu/drm/imx/dc/dc-fg.c  | 376 
 drivers/gpu/drm/imx/dc/dc-tc.c  | 141 
 10 files changed, 853 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dc/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dc/Makefile
 create mode 100644 drivers/gpu/drm/imx/dc/dc-de.c
 create mode 100644 drivers/gpu/drm/imx/dc/dc-de.h
 create mode 100644 drivers/gpu/drm/imx/dc/dc-drv.c
 create mode 100644 drivers/gpu/drm/imx/dc/dc-drv.h
 create mode 100644 drivers/gpu/drm/imx/dc/dc-fg.c
 create mode 100644 drivers/gpu/drm/imx/dc/dc-tc.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 03535a15dd8f..3e8c6edbc17c 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
+source "drivers/gpu/drm/imx/dc/Kconfig"
 source "drivers/gpu/drm/imx/dcss/Kconfig"
 source "drivers/gpu/drm/imx/ipuv3/Kconfig"
 source "drivers/gpu/drm/imx/lcdc/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 86f38e7c7422..c7b317640d71 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
+obj-$(CONFIG_DRM_IMX8_DC) += dc/
 obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
 obj-$(CONFIG_DRM_IMX) += ipuv3/
 obj-$(CONFIG_DRM_IMX_LCDC) += lcdc/
diff --git a/drivers/gpu/drm/imx/dc/Kconfig b/drivers/gpu/drm/imx/dc/Kconfig
new file mode 100644
index ..e1ef76d82830
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/Kconfig
@@ -0,0 +1,7 @@
+config DRM_IMX8_DC
+   tristate "Freescale i.MX8 Display Controller Graphics"
+   depends on DRM && COMMON_CLK && OF && (ARCH_MXC || COMPILE_TEST)
+   select REGMAP
+   select REGMAP_MMIO
+   help
+ enable Freescale i.MX8 Display Controller(DC) graphics support
diff --git a/drivers/gpu/drm/imx/dc/Makefile b/drivers/gpu/drm/imx/dc/Makefile
new file mode 100644
index ..56de82d53d4d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+imx8-dc-drm-objs := dc-de.o dc-drv.o dc-fg.o dc-tc.o
+
+obj-$(CONFIG_DRM_IMX8_DC) += imx8-dc-drm.o
diff --git a/drivers/gpu/drm/imx/dc/dc-de.c b/drivers/gpu/drm/imx/dc/dc-de.c
new file mode 100644
index ..5a3125596fdf
--- /dev/null
+++ b/drivers/gpu/drm/imx/dc/dc-de.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "dc-de.h"
+#include "dc-drv.h"
+
+#define POLARITYCTRL   0xc
+#define  POLEN_HIGHB

[DO NOT MERGE PATCH v9 17/19] arm64: dts: imx8qxp: Add MIPI-LVDS combo subsystems

[Liu Ying]

The MIPI-LVDS combo subsystems are peripherals of pixel link MSI
bus in i.MX8qxp display controller subsystem.  Add the MIPI-LVDS
combo subsystems.

Signed-off-by: Liu Ying 
---
v9:
* No change.

v8:
* No change.

v7:
* No change.

v6:
* No change.

v5:
* No change.

v4:
* No change.

v3:
* No change.

v2:
* New patch. (Francesco)

 .../boot/dts/freescale/imx8qxp-ss-dc.dtsi |   4 +
 .../dts/freescale/imx8qxp-ss-mipi-lvds.dtsi   | 437 ++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi|   3 +
 3 files changed, 444 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi 
b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
index 299720d8c99e..94c46a20597c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
@@ -152,10 +152,12 @@ port@1 {
 
dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 
{
reg = <0>;
+   remote-endpoint = 
<&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
};
 
dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 
{
reg = <1>;
+   remote-endpoint = 
<&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
};
};
 
@@ -207,10 +209,12 @@ port@1 {
 
dc0_pixel_link1_mipi_lvds_1_pxl2dpi: endpoint@0 
{
reg = <0>;
+   remote-endpoint = 
<&mipi_lvds_1_pxl2dpi_dc0_pixel_link1>;
};
 
dc0_pixel_link1_mipi_lvds_0_pxl2dpi: endpoint@1 
{
reg = <1>;
+   remote-endpoint = 
<&mipi_lvds_0_pxl2dpi_dc0_pixel_link1>;
};
};
 
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi 
b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi
new file mode 100644
index ..fa7e7c33518e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include 
+#include 
+
+/ {
+   mipi_lvds_0_ipg_clk: clock-mipi-lvds0-ipg {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <12000>;
+   clock-output-names = "mipi_lvds_0_ipg_clk";
+   };
+
+   mipi_lvds_1_ipg_clk: clock-mipi-lvds1-ipg {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <12000>;
+   clock-output-names = "mipi_lvds_1_ipg_clk";
+   };
+};
+
+&dc0_pl_msi_bus {
+   mipi_lvds_0_irqsteer: interrupt-controller@5622 {
+   compatible = "fsl,imx-irqsteer";
+   reg = <0x5622 0x1000>;
+   interrupts = ;
+   interrupt-controller;
+   interrupt-parent = <&gic>;
+   #interrupt-cells = <1>;
+   clocks = <&mipi_lvds_0_lis_lpcg IMX_LPCG_CLK_4>;
+   clock-names = "ipg";
+   fsl,channel = <0>;
+   fsl,num-irqs = <32>;
+   };
+
+   mipi_lvds_0_csr: syscon@56221000 {
+   compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", 
"simple-mfd";
+   reg = <0x56221000 0x1000>;
+   clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
+   clock-names = "ipg";
+
+   mipi_lvds_0_pxl2dpi: pxl2dpi {
+   compatible = "fsl,imx8qxp-pxl2dpi";
+   fsl,sc-resource = ;
+   power-domains = <&pd IMX_SC_R_MIPI_0>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   mipi_lvds_0_pxl2dpi_dc0_pixel_link0: 
endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
+   status = "disabled";
+   };
+
+   mipi_lvds_0_pxl2dpi_dc0_pixel_link1: 
endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<&dc0_pixel_link1_m

[PATCH v9 06/19] dt-bindings: display: imx: Add i.MX8qxp Display Controller command sequencer

[Liu Ying]

i.MX8qxp Display Controller contains a command sequencer is designed to
autonomously process command lists.

Signed-off-by: Liu Ying 
Reviewed-by: Rob Herring (Arm) 
---
v9:
* Add Rob's R-b tag.

v8:
* No change.

v7:
* No change.

v6:
* No change.

v5:
* No change.

v4:
* Replace "fsl,iram" property with standard "sram" property. (Rob)

v3:
* New patch. (Rob)

 .../imx/fsl,imx8qxp-dc-command-sequencer.yaml | 67 +++
 1 file changed, 67 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml
 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml
new file mode 100644
index ..27118f4c0d28
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 
http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Command Sequencer
+
+description: |
+  The Command Sequencer is designed to autonomously process command lists.
+  By that it can load setups into the DC configuration and synchronize to
+  hardware events.  This releases a system's CPU from workload, because it
+  does not need to wait for certain events.  Also it simplifies SW 
architecture,
+  because no interrupt handlers are required.  Setups are read via AXI bus,
+  while write access to configuration registers occurs directly via an internal
+  bus.  This saves bandwidth for the AXI interconnect and improves the system
+  architecture in terms of safety aspects.
+
+maintainers:
+  - Liu Ying 
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-command-sequencer
+
+  reg:
+maxItems: 1
+
+  clocks:
+maxItems: 1
+
+  interrupts:
+maxItems: 5
+
+  interrupt-names:
+items:
+  - const: error
+  - const: sw0
+  - const: sw1
+  - const: sw2
+  - const: sw3
+
+  sram:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: phandle pointing to the mmio-sram device node
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-names
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+command-sequencer@56180400 {
+compatible = "fsl,imx8qxp-dc-command-sequencer";
+reg = <0x56180400 0x1a4>;
+clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
+interrupt-parent = <&dc0_intc>;
+interrupts = <36>, <37>, <38>, <39>, <40>;
+interrupt-names = "error", "sw0", "sw1", "sw2", "sw3";
+};
-- 
2.34.1

[PATCH v9 04/19] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine

[Liu Ying]

i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain.  Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.

Signed-off-by: Liu Ying 
Reviewed-by: Rob Herring (Arm) 
---
v9:
* No change.

v8:
* Drop instance numbers from compatible strings. This means switching back to
  the patch in v4. So, add Rob's previous R-b tag back. (Dmitry)

v7:
* Add instance numbers to pixel engine internal devices' compatible strings.
  (Rob)
* Drop Rob's R-b tag.

v6:
* No change.

v5:
* No change.

v4:
* Collect Rob's R-b tag.

v3:
* No change.

v2:
* Drop fsl,dc-*-id DT properties from example. (Krzysztof)
* Fix register range sizes in example.

 .../imx/fsl,imx8qxp-dc-pixel-engine.yaml  | 250 ++
 1 file changed, 250 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
new file mode 100644
index ..633443a6cc38
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
@@ -0,0 +1,250 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 
http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Pixel Engine
+
+description:
+  All Processing Units that operate in the AXI bus clock domain. Pixel
+  pipelines have the ability to stall when a destination is busy. Implements
+  all communication to memory resources and most of the image processing
+  functions. Interconnection of Processing Units is re-configurable.
+
+maintainers:
+  - Liu Ying 
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-pixel-engine
+
+  reg:
+maxItems: 1
+
+  clocks:
+maxItems: 1
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 1
+
+  ranges: true
+
+patternProperties:
+  "^blit-engine@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-blit-engine
+
+  "^constframe@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-constframe
+
+  "^extdst@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-extdst
+
+  "^fetchdecode@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-fetchdecode
+
+  "^fetcheco@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-fetcheco
+
+  "^fetchlayer@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-fetchlayer
+
+  "^fetchwarp@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-fetchwarp
+
+  "^hscaler@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-hscaler
+
+  "^layerblend@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-layerblend
+
+  "^matrix@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-matrix
+
+  "^safety@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-safety
+
+  "^vscaler@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+  compatible:
+const: fsl,imx8qxp-dc-vscaler
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+pixel-engine@56180800 {
+compatible = "fsl,imx8qxp-dc-pixel-engine";
+reg = <0x56180800 0xac00>;
+clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+constframe@56180960 {
+compatible = "fsl,imx8qxp-dc-constframe";
+reg = <0x56180960 0xc>, <0x56184400 0x20>;
+reg-names = "pec", "cfg";
+};
+
+extdst@56180980 {
+compatible = "fsl,imx8qxp-dc-extdst";
+reg = <0x56180980 0x1c>, <0x56184800 0x28>;
+reg-names = "pec", "cfg";
+interrupt-parent = <&dc0_intc>;
+interrupts = <3>, <4>, <5>;
+interrupt-names = "shdload", "framecomplete"

Re: [PATCH 1/7] drm/bridge: analogix_dp: drop extra calls to analogix_dp_prepare_panel()

[Damon Ding]

Hi Dmitry,

On 2025/4/1 13:11, Dmitry Baryshkov wrote:

The analogix_dp_prepare_panel() returns immediately if there is no
attached panel. Drop several calls to this function which are performed
when dp->plat_data->panel is NULL.

Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 22 +-
  1 file changed, 1 insertion(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 
042154e2d8ccd74ac2dc27fe527e810a50e08a09..ab1cfc340aa95bbf13fe021bd33227b565a5458d
 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1005,17 +1005,11 @@ static int analogix_dp_get_modes(struct drm_connector 
*connector)
  {
struct analogix_dp_device *dp = to_dp(connector);
const struct drm_edid *drm_edid;
-   int ret, num_modes = 0;
+   int num_modes = 0;
  
  	if (dp->plat_data->panel) {

num_modes += drm_panel_get_modes(dp->plat_data->panel, 
connector);
} else {
-   ret = analogix_dp_prepare_panel(dp, true, false);
-   if (ret) {
-   DRM_ERROR("Failed to prepare panel (%d)\n", ret);
-   return 0;
-   }
-
drm_edid = drm_edid_read_ddc(connector, &dp->aux.ddc);
  
  		drm_edid_connector_update(&dp->connector, drm_edid);

@@ -1024,10 +1018,6 @@ static int analogix_dp_get_modes(struct drm_connector 
*connector)
num_modes += 
drm_edid_connector_add_modes(&dp->connector);
drm_edid_free(drm_edid);
}
-
-   ret = analogix_dp_prepare_panel(dp, false, false);
-   if (ret)
-   DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
}
  
  	if (dp->plat_data->get_modes)

@@ -1087,19 +1077,9 @@ analogix_dp_detect(struct drm_connector *connector, bool 
force)
if (dp->plat_data->panel)
return connector_status_connected;
  
-	ret = analogix_dp_prepare_panel(dp, true, false);

-   if (ret) {
-   DRM_ERROR("Failed to prepare panel (%d)\n", ret);
-   return connector_status_disconnected;
-   }
-
if (!analogix_dp_detect_hpd(dp))
status = connector_status_connected;
  
-	ret = analogix_dp_prepare_panel(dp, false, false);

-   if (ret)
-   DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
-
return status;
  }
  



With the patch series:
https://patchwork.kernel.org/project/linux-rockchip/list/?series=942183

When I verify this patch, there will be a small warning:
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c:1075:6: warning: 
unused variable 'ret' [-Wunused-variable]

int ret;
^

It should be better to remove the unused 'ret'.

Best regards,
Damon

[PATCH v3] drm/amd/display: Add error check for avi and vendor infoframe setup function

[Wentao Liang]

The function fill_stream_properties_from_drm_display_mode() calls the
function drm_hdmi_avi_infoframe_from_display_mode() and the
function drm_hdmi_vendor_infoframe_from_display_mode(), but does
not check its return value. Log the error messages to prevent silent
failure if either function fails.

Signed-off-by: Wentao Liang 
---
v3: Fix error-logging function error
v2: Fix code diff error

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5f216d626cbb..cdf1a07aa8af 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6104,6 +6104,7 @@ static void fill_stream_properties_from_drm_display_mode(
struct amdgpu_dm_connector *aconnector = NULL;
struct hdmi_vendor_infoframe hv_frame;
struct hdmi_avi_infoframe avi_frame;
+   ssize_t err;
 
if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
aconnector = to_amdgpu_dm_connector(connector);
@@ -6150,9 +6151,17 @@ static void fill_stream_properties_from_drm_display_mode(
}
 
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
-   drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct 
drm_connector *)connector, mode_in);
+   err = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame,
+  (struct 
drm_connector *)connector,
+  mode_in);
+   if (err < 0)
+   drm_err(connector->dev, "Failed to setup avi infoframe: 
%zd\n", err);
timing_out->vic = avi_frame.video_code;
-   drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct 
drm_connector *)connector, mode_in);
+   err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame,
+ (struct 
drm_connector *)connector,
+ mode_in);
+   if (err < 0)
+   drm_err(connector->dev, "Failed to setup vendor 
infoframe: %zd\n", err);
timing_out->hdmi_vic = hv_frame.vic;
}
 
-- 
2.42.0.windows.2