Re: [Discuss-gnuradio] Linux version of Quartus II kit?

2005-11-11 Thread Uwe Bonnes
> "Daniel" == Daniel O'Connor <[EMAIL PROTECTED]> writes:

Daniel> On Fri, 11 Nov 2005 11:40, David R. Palchak wrote:
>> Am I right in assuming that a modified FPGA design needs to be
>> compiled using the Quartus II toolchain?  I ask because as near as I
>> can tell, the only free version of the Quartus II software requires a
>> windows setup (which I don't have).  Has anyone found an alternative
>> solution?

Daniel> It might work under Wine.

I tried several times, but in most cases wine hang with creating the licence
server. One reason for that is know (detect a broken pipe) and a test case
showing the missbehaviour is in the wine test suite, but the problem is hard
to tackle. I'll nag some more capable wine developpers about that.

Bye
-- 
Uwe Bonnes[EMAIL PROTECTED]

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
- Tel. 06151 162516  Fax. 06151 164321 --


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Re: [Discuss-gnuradio] Using USRP w/o Daughterboard's

2005-11-11 Thread Eric Blossom
On Thu, Nov 10, 2005 at 05:18:26PM -0700, Robitaille, Michael wrote:
> Thanks Eric, I got my direct interface to the USRP working and the
> usrp_oscope.py and ursp_fft.py examples work.  I am very glad that the
> software defaults to a Basix Rx DB configuration when it finds no DB.
> 
> One item that I am trying to chase down is that when I input a square wave
> at low frequencies (1 kHz to 10 kHz) I see a droop in the amplitude.  The
> signal at the AD9862 input pins looks good.  Can the droop be cause by the
> decimation filter? 
> 

Did you turn off the DC removal control loop in the FPGA?

Eric


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Re: [Discuss-gnuradio] using 2nd Basic-RX board ?

2005-11-11 Thread Chuck Swiger

At 07:58 PM 11/10/2005 -0800, you wrote:

On Thu, Nov 10, 2005 at 06:23:57PM -0500, cswiger wrote:
>
> But when I try to use it in my script I get a flatline:
>
> self.dut_out = usrp.source_c(0, decim, 4, gru.hexint(0xf0f2f1f0),

The FPGA contains only 2 instance of the DDC, not 4, hence your problem...


OK - I just remembered that while waking up. Actually it is better to use
two receive channels and switch the ports with the mux - they don't
have to run concurrently. It just saves from having to move test jig
cables around.  Changing mux shouldn't change ddc phase.

Tks

--Chuck



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Re: [Discuss-gnuradio] Using USRP w/o Daughterboard's

2005-11-11 Thread [EMAIL PROTECTED]
No I have not yet made that change.  I have been trying to figure out how
to use it.  I don't understand the brief description

  /*!
   * \brief Enable/disable automatic DC offset removal control loop in FPGA
   *
   * \param bits  which control loops to enable
   * \param mask  which \p bits to pay attention to
   *
   * If the corresponding bit is set, enable the automatic DC
   * offset correction control loop.
   *
   * 
   * The 4 low bits are significant:
   *
   *   ADC0 = (1 << 0)
   *   ADC1 = (1 << 1)
   *   ADC2 = (1 << 2)
   *   ADC3 = (1 << 3)
   * 
   *
   * By default the control loop is enabled on all ADC's.
   */

I don't know what to use for bit or mask values.  Is this like the mux
values?
Please explain how you determine the bit and mask values to use?

Mike

Original Message:
-
From: Eric Blossom [EMAIL PROTECTED]
Date: Fri, 11 Nov 2005 01:47:29 -0800
To: [EMAIL PROTECTED], discuss-gnuradio@gnu.org
Subject: Re: [Discuss-gnuradio] Using USRP w/o Daughterboard's


On Thu, Nov 10, 2005 at 05:18:26PM -0700, Robitaille, Michael wrote:
> Thanks Eric, I got my direct interface to the USRP working and the
> usrp_oscope.py and ursp_fft.py examples work.  I am very glad that the
> software defaults to a Basix Rx DB configuration when it finds no DB.
> 
> One item that I am trying to chase down is that when I input a square wave
> at low frequencies (1 kHz to 10 kHz) I see a droop in the amplitude.  The
> signal at the AD9862 input pins looks good.  Can the droop be cause by the
> decimation filter? 
> 

Did you turn off the DC removal control loop in the FPGA?

Eric


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[Discuss-gnuradio] Reducing the ADC sample rate

2005-11-11 Thread [EMAIL PROTECTED]
I would like to reduce the ADC sample rate from the default 62.5 MS/s.  I
have found the set_adc_clk_div in the usrp0_rx class.  Is this still
usable.  I tried to use it in the follow:

u = usrp.source_c()

u.set_adc_clk_div(6)

and I get errors?

I did 'from gnuradio import usrp0' and still get the error.  I also tried

u = usrp0.source_c()

Mike


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Re: [Discuss-gnuradio] Reducing the ADC sample rate

2005-11-11 Thread Eric Blossom
On Fri, Nov 11, 2005 at 12:09:13PM -0500, [EMAIL PROTECTED] wrote:
> I would like to reduce the ADC sample rate from the default 62.5 MS/s.  I
> have found the set_adc_clk_div in the usrp0_rx class.  Is this still
> usable.  I tried to use it in the follow:

No.  That was only implemented in the Rev 0 USRP.

FYI, the ADC sample rate on the current boards is 64MS/sec.

> I did 'from gnuradio import usrp0' and still get the error.  I also tried
> 
> u = usrp0.source_c()
> 

You don't have a usrp0, so this is moot.

Eric


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[Discuss-gnuradio] A/D converters and related expriments

2005-11-11 Thread mIB
Can I ask if there is a beginners list for electronics? 
I need to know the subject of Hispeed A/D bit deep
and esentials.  




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