[dpdk-dev] [PATCH] eal: sPAPR IOMMU support in pci probing for vfio-pci in ppc64le
From: Gowrishankar Muthukrishnan
Below changes adds pci probing support for vfio-pci devices in power8.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Chao Zhu
---
lib/librte_eal/linuxapp/eal/eal_vfio.c | 88 ++
lib/librte_eal/linuxapp/eal/eal_vfio.h | 1 +
2 files changed, 89 insertions(+)
diff --git a/lib/librte_eal/linuxapp/eal/eal_vfio.c
b/lib/librte_eal/linuxapp/eal/eal_vfio.c
index 702f7a2..1d4fea6 100644
--- a/lib/librte_eal/linuxapp/eal/eal_vfio.c
+++ b/lib/librte_eal/linuxapp/eal/eal_vfio.c
@@ -50,12 +50,15 @@
static struct vfio_config vfio_cfg;
static int vfio_type1_dma_map(int);
+static int vfio_spapr_dma_map(int);
static int vfio_noiommu_dma_map(int);
/* IOMMU types we support */
static const struct vfio_iommu_type iommu_types[] = {
/* x86 IOMMU, otherwise known as type 1 */
{ RTE_VFIO_TYPE1, "Type 1", &vfio_type1_dma_map},
+ /* ppc64 IOMMU, otherwise known as spapr */
+ { RTE_VFIO_SPAPR, "sPAPR", &vfio_spapr_dma_map},
/* IOMMU-less mode */
{ RTE_VFIO_NOIOMMU, "No-IOMMU", &vfio_noiommu_dma_map},
};
@@ -540,6 +543,91 @@ int vfio_setup_device(const char *sysfs_base, const char
*dev_addr,
}
static int
+vfio_spapr_dma_map(int vfio_container_fd)
+{
+ const struct rte_memseg *ms = rte_eal_get_physmem_layout();
+ int i, ret;
+
+ struct vfio_iommu_spapr_register_memory reg = {
+ .argsz = sizeof(reg),
+ .flags = 0
+ };
+ struct vfio_iommu_spapr_tce_info info = {
+ .argsz = sizeof(info),
+ };
+ struct vfio_iommu_spapr_tce_create create = {
+ .argsz = sizeof(create),
+ };
+ struct vfio_iommu_spapr_tce_remove remove = {
+ .argsz = sizeof(remove),
+ };
+
+ /* query spapr iommu info */
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_GET_INFO, &info);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot get iommu info, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ /* remove default DMA of 32 bit window */
+ remove.start_addr = info.dma32_window_start;
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_REMOVE, &remove);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot remove default DMA window, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ /* calculate window size based on number of hugepages configured */
+ create.window_size = rte_eal_get_physmem_size();
+ create.page_shift = __builtin_ctzll(ms->hugepage_sz);
+ create.levels = 2;
+
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_CREATE, &create);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot create new DMA window, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ /* map all DPDK segments for DMA. use 1:1 PA to IOVA mapping */
+ for (i = 0; i < RTE_MAX_MEMSEG; i++) {
+ struct vfio_iommu_type1_dma_map dma_map;
+
+ if (ms[i].addr == NULL)
+ break;
+
+ reg.vaddr = (uintptr_t) ms[i].addr;
+ reg.size = ms[i].len;
+ ret = ioctl(vfio_container_fd,
VFIO_IOMMU_SPAPR_REGISTER_MEMORY, ®);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot register vaddr for IOMMU, "
+ "error %i (%s)\n", errno,
strerror(errno));
+ return -1;
+ }
+
+ memset(&dma_map, 0, sizeof(dma_map));
+ dma_map.argsz = sizeof(struct vfio_iommu_type1_dma_map);
+ dma_map.vaddr = ms[i].addr_64;
+ dma_map.size = ms[i].len;
+ dma_map.iova = ms[i].phys_addr;
+ dma_map.flags = VFIO_DMA_MAP_FLAG_READ |
VFIO_DMA_MAP_FLAG_WRITE;
+
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_MAP_DMA, &dma_map);
+
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot set up DMA remapping, "
+ "error %i (%s)\n", errno,
strerror(errno));
+ return -1;
+ }
+
+ }
+
+ return 0;
+}
+
+static int
vfio_noiommu_dma_map(int __rte_unused vfio_container_fd)
{
/* No-IOMMU mode does not need DMA mapping */
diff --git a/lib/librte_eal/linuxapp/eal/eal_vfio.h
b/lib/librte_eal/linuxapp/eal/eal_vfio.h
index 29f7f3e..533b854 100644
--- a/lib/librte_eal/linuxapp/eal/eal_vfio.h
+++ b/lib/librte_eal/linuxapp/eal/eal_vfio.h
@@ -53,6 +53,7 @@
#endif
#define RTE_VFIO_TYPE1 VFIO_TYPE1_IOMMU
+#define RTE_VFIO_SPAPR VFIO_SPAPR_TCE_v2_IOMMU
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)
#define RTE_VFIO_NOIOMMU 8
--
1.9.1
[dpdk-dev] [PATCH v2] net/bonding: support bifurcated driver in eal cli using --vdev
From: Gowrishankar Muthukrishnan
At present, creating bonding devices using --vdev is broken for PMD like
mlx5 as it is neither UIO nor VFIO based and hence PMD driver is unknown
to find_port_id_by_pci_addr(), as below.
testpmd --vdev 'net_bonding0,mode=1,slave=,socket_id=0'
PMD: bond_ethdev_parse_slave_port_kvarg(150) - Invalid slave port value
() specified
EAL: Failed to parse slave ports for bonded device net_bonding0
This patch fixes parsing PCI ID from bonding device params by verifying
it in RTE PCI bus, rather than checking dev->kdrv.
Changes:
v2 - revisit fix by iterating rte_pci_bus
Signed-off-by: Gowrishankar Muthukrishnan
---
drivers/net/bonding/rte_eth_bond_args.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/net/bonding/rte_eth_bond_args.c
b/drivers/net/bonding/rte_eth_bond_args.c
index c718e61..180586c 100644
--- a/drivers/net/bonding/rte_eth_bond_args.c
+++ b/drivers/net/bonding/rte_eth_bond_args.c
@@ -40,6 +40,8 @@
#include "rte_eth_bond.h"
#include "rte_eth_bond_private.h"
+extern struct rte_pci_bus rte_pci_bus;
+
const char *pmd_bond_init_valid_arguments[] = {
PMD_BOND_SLAVE_PORT_KVARG,
PMD_BOND_PRIMARY_SLAVE_KVARG,
@@ -59,16 +61,6 @@
unsigned i;
for (i = 0; i < rte_eth_dev_count(); i++) {
-
- /* Currently populated by rte_eth_copy_pci_info().
-*
-* TODO: Once the PCI bus has arrived we should have a better
-* way to test for being a PCI device or not.
-*/
- if (rte_eth_devices[i].data->kdrv == RTE_KDRV_UNKNOWN ||
- rte_eth_devices[i].data->kdrv == RTE_KDRV_NONE)
- continue;
-
pci_dev = RTE_ETH_DEV_TO_PCI(&rte_eth_devices[i]);
eth_pci_addr = &pci_dev->addr;
@@ -103,12 +95,18 @@
static inline int
parse_port_id(const char *port_str)
{
+ struct rte_pci_device *dev;
struct rte_pci_addr dev_addr;
- int port_id;
+ int port_id = -1;
/* try parsing as pci address, physical devices */
if (eal_parse_pci_DomBDF(port_str, &dev_addr) == 0) {
- port_id = find_port_id_by_pci_addr(&dev_addr);
+ FOREACH_DEVICE_ON_PCIBUS(dev) {
+ if (rte_eal_compare_pci_addr(&dev->addr, &dev_addr))
+ continue;
+
+ port_id = find_port_id_by_pci_addr(&dev_addr);
+ }
if (port_id < 0)
return -1;
} else {
--
1.9.1
[dpdk-dev] [PATCH] mlx5: fix get link settings call for speed and duplex values
From: Gowrishankar Muthukrishnan
mlx5 pmd does not correctly retrieve link speed and duplex values
in linksetting struct through ETHTOOL_GLINKSETTINGS ioctl call.
Due to which pktgen application could not correctly calculate tx/rx
rate and hence, very few packets (of count 32) only sent all the time.
Link settings can be derived through ETHTOOL_GLINKSETTINGS ioctl
only after updating ethtool_link_settings struct with appropriate
link mode bitmask words returned by its kernel side implementation.
With this patch, pktgen app is able to tx/rx packets on mlx5 ports.
Signed-off-by: Gowrishankar Muthukrishnan
---
drivers/net/mlx5/mlx5_ethdev.c | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index b70b7b9..003cef3 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -119,6 +119,7 @@ struct ethtool_link_settings {
#define ETHTOOL_LINK_MODE_10baseCR4_Full_BIT 38
#define ETHTOOL_LINK_MODE_10baseLR4_ER4_Full_BIT 39
#endif
+#define ETHTOOL_LINK_MODE_MASK_MAX_KERNEL_NU32 (SCHAR_MAX)
/**
* Return private structure associated with an Ethernet device.
@@ -807,9 +808,11 @@ struct priv *
mlx5_link_update_unlocked_gs(struct rte_eth_dev *dev, int wait_to_complete)
{
struct priv *priv = mlx5_get_priv(dev);
- struct ethtool_link_settings edata = {
- .cmd = ETHTOOL_GLINKSETTINGS,
- };
+ struct {
+ struct ethtool_link_settings edata;
+ __u32 link_mode_data[3 *
ETHTOOL_LINK_MODE_MASK_MAX_KERNEL_NU32];
+ } ecmd;
+
struct ifreq ifr;
struct rte_eth_link dev_link;
uint64_t sc;
@@ -822,15 +825,23 @@ struct priv *
memset(&dev_link, 0, sizeof(dev_link));
dev_link.link_status = ((ifr.ifr_flags & IFF_UP) &&
(ifr.ifr_flags & IFF_RUNNING));
- ifr.ifr_data = (void *)&edata;
+ memset(&ecmd, 0, sizeof(ecmd));
+ ecmd.edata.cmd = ETHTOOL_GLINKSETTINGS;
+ ifr.ifr_data = (void *)&ecmd;
if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
DEBUG("ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS) failed: %s",
strerror(errno));
return -1;
}
- dev_link.link_speed = edata.speed;
- sc = edata.link_mode_masks[0] |
- ((uint64_t)edata.link_mode_masks[1] << 32);
+ ecmd.edata.link_mode_masks_nwords = -ecmd.edata.link_mode_masks_nwords;
+ if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
+ DEBUG("ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS) failed: %s",
+ strerror(errno));
+ return -1;
+ }
+ dev_link.link_speed = ecmd.edata.speed;
+ sc = ecmd.edata.link_mode_masks[0] |
+ ((uint64_t)ecmd.edata.link_mode_masks[1] << 32);
priv->link_speed_capa = 0;
if (sc & ETHTOOL_LINK_MODE_Autoneg_BIT)
priv->link_speed_capa |= ETH_LINK_SPEED_AUTONEG;
@@ -866,7 +877,7 @@ struct priv *
ETHTOOL_LINK_MODE_10baseCR4_Full_BIT |
ETHTOOL_LINK_MODE_10baseLR4_ER4_Full_BIT))
priv->link_speed_capa |= ETH_LINK_SPEED_100G;
- dev_link.link_duplex = ((edata.duplex == DUPLEX_HALF) ?
+ dev_link.link_duplex = ((ecmd.edata.duplex == DUPLEX_HALF) ?
ETH_LINK_HALF_DUPLEX : ETH_LINK_FULL_DUPLEX);
dev_link.link_autoneg = !(dev->data->dev_conf.link_speeds &
ETH_LINK_SPEED_FIXED);
--
1.9.1
[dpdk-dev] [PATCH v2] net/mlx5: fix get link settings call for speed and duplex values
From: Gowrishankar Muthukrishnan
ETHTOOL_GLINKSETTINGS ioctl call in mlx5 pmd returns inconsistent
link status due to which any application relying on it would not
function correctly.
Changes:
v2 - coding style update
Fixes: 188408719888 ("net/mlx5: fix support for newer link speeds")
Cc: sta...@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan
---
drivers/net/mlx5/mlx5_ethdev.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index b70b7b9..3ceb13a 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -119,6 +119,7 @@ struct ethtool_link_settings {
#define ETHTOOL_LINK_MODE_10baseCR4_Full_BIT 38
#define ETHTOOL_LINK_MODE_10baseLR4_ER4_Full_BIT 39
#endif
+#define ETHTOOL_LINK_MODE_MASK_MAX_KERNEL_NU32 (SCHAR_MAX)
/**
* Return private structure associated with an Ethernet device.
@@ -807,9 +808,12 @@ struct priv *
mlx5_link_update_unlocked_gs(struct rte_eth_dev *dev, int wait_to_complete)
{
struct priv *priv = mlx5_get_priv(dev);
- struct ethtool_link_settings edata = {
- .cmd = ETHTOOL_GLINKSETTINGS,
- };
+ struct {
+ struct ethtool_link_settings edata;
+ __u32 link_mode_data[
+ 3 * ETHTOOL_LINK_MODE_MASK_MAX_KERNEL_NU32];
+ } ecmd;
+
struct ifreq ifr;
struct rte_eth_link dev_link;
uint64_t sc;
@@ -822,15 +826,23 @@ struct priv *
memset(&dev_link, 0, sizeof(dev_link));
dev_link.link_status = ((ifr.ifr_flags & IFF_UP) &&
(ifr.ifr_flags & IFF_RUNNING));
- ifr.ifr_data = (void *)&edata;
+ memset(&ecmd, 0, sizeof(ecmd));
+ ecmd.edata.cmd = ETHTOOL_GLINKSETTINGS;
+ ifr.ifr_data = (void *)&ecmd;
if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
DEBUG("ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS) failed: %s",
strerror(errno));
return -1;
}
- dev_link.link_speed = edata.speed;
- sc = edata.link_mode_masks[0] |
- ((uint64_t)edata.link_mode_masks[1] << 32);
+ ecmd.edata.link_mode_masks_nwords = -ecmd.edata.link_mode_masks_nwords;
+ if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
+ DEBUG("ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS) failed: %s",
+ strerror(errno));
+ return -1;
+ }
+ dev_link.link_speed = ecmd.edata.speed;
+ sc = ecmd.edata.link_mode_masks[0] |
+ ((uint64_t)ecmd.edata.link_mode_masks[1] << 32);
priv->link_speed_capa = 0;
if (sc & ETHTOOL_LINK_MODE_Autoneg_BIT)
priv->link_speed_capa |= ETH_LINK_SPEED_AUTONEG;
@@ -866,7 +878,7 @@ struct priv *
ETHTOOL_LINK_MODE_10baseCR4_Full_BIT |
ETHTOOL_LINK_MODE_10baseLR4_ER4_Full_BIT))
priv->link_speed_capa |= ETH_LINK_SPEED_100G;
- dev_link.link_duplex = ((edata.duplex == DUPLEX_HALF) ?
+ dev_link.link_duplex = ((ecmd.edata.duplex == DUPLEX_HALF) ?
ETH_LINK_HALF_DUPLEX : ETH_LINK_FULL_DUPLEX);
dev_link.link_autoneg = !(dev->data->dev_conf.link_speeds &
ETH_LINK_SPEED_FIXED);
--
1.9.1
[dpdk-dev] [PATCH] net/mlx5: fix inconsistent link status query
From: Gowrishankar Muthukrishnan
ETHTOOL_GLINKSETTINGS ioctl call in mlx5 pmd returns inconsistent
link status due to which any application relying on it would not
function correctly.
Fixes: 188408719888 ("net/mlx5: fix support for newer link speeds")
Cc: sta...@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan
---
v3:
- stick with C standard for uint32_t
drivers/net/mlx5/mlx5_ethdev.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index b70b7b9..01f881e 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -119,6 +119,7 @@ struct ethtool_link_settings {
#define ETHTOOL_LINK_MODE_10baseCR4_Full_BIT 38
#define ETHTOOL_LINK_MODE_10baseLR4_ER4_Full_BIT 39
#endif
+#define ETHTOOL_LINK_MODE_MASK_MAX_KERNEL_NU32 (SCHAR_MAX)
/**
* Return private structure associated with an Ethernet device.
@@ -807,9 +808,12 @@ struct priv *
mlx5_link_update_unlocked_gs(struct rte_eth_dev *dev, int wait_to_complete)
{
struct priv *priv = mlx5_get_priv(dev);
- struct ethtool_link_settings edata = {
- .cmd = ETHTOOL_GLINKSETTINGS,
- };
+ struct {
+ struct ethtool_link_settings edata;
+ uint32_t link_mode_data[3 *
+ ETHTOOL_LINK_MODE_MASK_MAX_KERNEL_NU32];
+ } ecmd;
+
struct ifreq ifr;
struct rte_eth_link dev_link;
uint64_t sc;
@@ -822,15 +826,23 @@ struct priv *
memset(&dev_link, 0, sizeof(dev_link));
dev_link.link_status = ((ifr.ifr_flags & IFF_UP) &&
(ifr.ifr_flags & IFF_RUNNING));
- ifr.ifr_data = (void *)&edata;
+ memset(&ecmd, 0, sizeof(ecmd));
+ ecmd.edata.cmd = ETHTOOL_GLINKSETTINGS;
+ ifr.ifr_data = (void *)&ecmd;
if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
DEBUG("ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS) failed: %s",
strerror(errno));
return -1;
}
- dev_link.link_speed = edata.speed;
- sc = edata.link_mode_masks[0] |
- ((uint64_t)edata.link_mode_masks[1] << 32);
+ ecmd.edata.link_mode_masks_nwords = -ecmd.edata.link_mode_masks_nwords;
+ if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
+ DEBUG("ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS) failed: %s",
+ strerror(errno));
+ return -1;
+ }
+ dev_link.link_speed = ecmd.edata.speed;
+ sc = ecmd.edata.link_mode_masks[0] |
+ ((uint64_t)ecmd.edata.link_mode_masks[1] << 32);
priv->link_speed_capa = 0;
if (sc & ETHTOOL_LINK_MODE_Autoneg_BIT)
priv->link_speed_capa |= ETH_LINK_SPEED_AUTONEG;
@@ -866,7 +878,7 @@ struct priv *
ETHTOOL_LINK_MODE_10baseCR4_Full_BIT |
ETHTOOL_LINK_MODE_10baseLR4_ER4_Full_BIT))
priv->link_speed_capa |= ETH_LINK_SPEED_100G;
- dev_link.link_duplex = ((edata.duplex == DUPLEX_HALF) ?
+ dev_link.link_duplex = ((ecmd.edata.duplex == DUPLEX_HALF) ?
ETH_LINK_HALF_DUPLEX : ETH_LINK_FULL_DUPLEX);
dev_link.link_autoneg = !(dev->data->dev_conf.link_speeds &
ETH_LINK_SPEED_FIXED);
--
1.9.1
[dpdk-dev] [PATCH v4] net/mlx5: fix inconsistent link status query
From: Gowrishankar Muthukrishnan
ETHTOOL_GLINKSETTINGS ioctl call in mlx5 pmd returns inconsistent
link status due to which any application relying on it would not
function correctly.
Fixes: 188408719888 ("net/mlx5: fix support for newer link speeds")
Cc: sta...@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan
---
v4:
- use __extension__ for GNU C standard (struct in struct)
drivers/net/mlx5/mlx5_ethdev.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index b70b7b9..1644546 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -119,6 +119,7 @@ struct ethtool_link_settings {
#define ETHTOOL_LINK_MODE_10baseCR4_Full_BIT 38
#define ETHTOOL_LINK_MODE_10baseLR4_ER4_Full_BIT 39
#endif
+#define ETHTOOL_LINK_MODE_MASK_MAX_KERNEL_NU32 (SCHAR_MAX)
/**
* Return private structure associated with an Ethernet device.
@@ -807,9 +808,12 @@ struct priv *
mlx5_link_update_unlocked_gs(struct rte_eth_dev *dev, int wait_to_complete)
{
struct priv *priv = mlx5_get_priv(dev);
- struct ethtool_link_settings edata = {
- .cmd = ETHTOOL_GLINKSETTINGS,
- };
+ __extension__ struct {
+ struct ethtool_link_settings edata;
+ uint32_t link_mode_data[3 *
+ ETHTOOL_LINK_MODE_MASK_MAX_KERNEL_NU32];
+ } ecmd;
+
struct ifreq ifr;
struct rte_eth_link dev_link;
uint64_t sc;
@@ -822,15 +826,23 @@ struct priv *
memset(&dev_link, 0, sizeof(dev_link));
dev_link.link_status = ((ifr.ifr_flags & IFF_UP) &&
(ifr.ifr_flags & IFF_RUNNING));
- ifr.ifr_data = (void *)&edata;
+ memset(&ecmd, 0, sizeof(ecmd));
+ ecmd.edata.cmd = ETHTOOL_GLINKSETTINGS;
+ ifr.ifr_data = (void *)&ecmd;
if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
DEBUG("ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS) failed: %s",
strerror(errno));
return -1;
}
- dev_link.link_speed = edata.speed;
- sc = edata.link_mode_masks[0] |
- ((uint64_t)edata.link_mode_masks[1] << 32);
+ ecmd.edata.link_mode_masks_nwords = -ecmd.edata.link_mode_masks_nwords;
+ if (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {
+ DEBUG("ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS) failed: %s",
+ strerror(errno));
+ return -1;
+ }
+ dev_link.link_speed = ecmd.edata.speed;
+ sc = ecmd.edata.link_mode_masks[0] |
+ ((uint64_t)ecmd.edata.link_mode_masks[1] << 32);
priv->link_speed_capa = 0;
if (sc & ETHTOOL_LINK_MODE_Autoneg_BIT)
priv->link_speed_capa |= ETH_LINK_SPEED_AUTONEG;
@@ -866,7 +878,7 @@ struct priv *
ETHTOOL_LINK_MODE_10baseCR4_Full_BIT |
ETHTOOL_LINK_MODE_10baseLR4_ER4_Full_BIT))
priv->link_speed_capa |= ETH_LINK_SPEED_100G;
- dev_link.link_duplex = ((edata.duplex == DUPLEX_HALF) ?
+ dev_link.link_duplex = ((ecmd.edata.duplex == DUPLEX_HALF) ?
ETH_LINK_HALF_DUPLEX : ETH_LINK_FULL_DUPLEX);
dev_link.link_autoneg = !(dev->data->dev_conf.link_speeds &
ETH_LINK_SPEED_FIXED);
--
1.9.1
[dpdk-dev] [PATCH v2] net/bonding: enable bonding pmd in ppc64le
From: Gowrishankar Muthukrishnan Earlier bonding pmd was disabled in default config for ppc64le. Hence, removing it as it has been verified. Signed-off-by: Gowrishankar Muthukrishnan --- v2: - remove configuration variable for default enablement config/defconfig_ppc_64-power8-linuxapp-gcc | 1 - 1 file changed, 1 deletion(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index 71e4c35..a52e22e 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -51,7 +51,6 @@ CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n CONFIG_RTE_LIBRTE_IXGBE_PMD=n CONFIG_RTE_LIBRTE_VIRTIO_PMD=y CONFIG_RTE_LIBRTE_VMXNET3_PMD=n -CONFIG_RTE_LIBRTE_PMD_BOND=n CONFIG_RTE_LIBRTE_ENIC_PMD=n CONFIG_RTE_LIBRTE_FM10K_PMD=n CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n -- 1.9.1
[dpdk-dev] [PATCH] i40e: implement vector PMD for altivec
From: Gowrishankar Muthukrishnan This patch enables i40e driver in powerpc along with its altivec intrinsic support. Signed-off-by: Gowrishankar Muthukrishnan --- MAINTAINERS | 1 + config/defconfig_ppc_64-power8-linuxapp-gcc | 2 +- doc/guides/nics/features/i40e.ini | 1 + doc/guides/nics/features/i40e_vec.ini | 1 + drivers/net/i40e/Makefile | 2 + drivers/net/i40e/i40e_rxtx_vec_altivec.c| 628 6 files changed, 634 insertions(+), 1 deletion(-) create mode 100644 drivers/net/i40e/i40e_rxtx_vec_altivec.c diff --git a/MAINTAINERS b/MAINTAINERS index 065397b..a380b5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -166,6 +166,7 @@ IBM POWER M: Chao Zhu F: lib/librte_eal/common/arch/ppc_64/ F: lib/librte_eal/common/include/arch/ppc_64/ +F: drivers/net/i40e/i40e_rxtx_vec_altivec.c Intel x86 M: Bruce Richardson diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index f953e61..e8e5e58 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -49,7 +49,7 @@ CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n # Note: Initially, all of the PMD drivers compilation are turned off on Power # Will turn on them only after the successful testing on Power CONFIG_RTE_LIBRTE_IXGBE_PMD=n -CONFIG_RTE_LIBRTE_I40E_PMD=n +CONFIG_RTE_LIBRTE_I40E_PMD=y CONFIG_RTE_LIBRTE_VIRTIO_PMD=y CONFIG_RTE_LIBRTE_VMXNET3_PMD=n CONFIG_RTE_LIBRTE_PMD_BOND=n diff --git a/doc/guides/nics/features/i40e.ini b/doc/guides/nics/features/i40e.ini index 0d143bc..6fad048 100644 --- a/doc/guides/nics/features/i40e.ini +++ b/doc/guides/nics/features/i40e.ini @@ -46,3 +46,4 @@ Linux VFIO = Y x86-32 = Y x86-64 = Y ARMv8= Y +PPC_64 = Y diff --git a/doc/guides/nics/features/i40e_vec.ini b/doc/guides/nics/features/i40e_vec.ini index edd6b71..f653446 100644 --- a/doc/guides/nics/features/i40e_vec.ini +++ b/doc/guides/nics/features/i40e_vec.ini @@ -38,3 +38,4 @@ Linux VFIO = Y x86-32 = Y x86-64 = Y ARMv8= Y +PPC_64 = Y diff --git a/drivers/net/i40e/Makefile b/drivers/net/i40e/Makefile index 13085fb..9c9a867 100644 --- a/drivers/net/i40e/Makefile +++ b/drivers/net/i40e/Makefile @@ -99,6 +99,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_rxtx.c ifeq ($(CONFIG_RTE_ARCH_ARM64),y) SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_neon.c +else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y) +SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_altivec.c else SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_sse.c endif diff --git a/drivers/net/i40e/i40e_rxtx_vec_altivec.c b/drivers/net/i40e/i40e_rxtx_vec_altivec.c new file mode 100644 index 000..12cf53f --- /dev/null +++ b/drivers/net/i40e/i40e_rxtx_vec_altivec.c @@ -0,0 +1,628 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * Copyright(c) 2016 IBM Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include "base/i40e_prototype.h" +#include "base/i40e_type.h" +#include "i40e_ethdev.h
[dpdk-dev] [PATCH v2] i40e: implement vector PMD for altivec
From: Gowrishankar Muthukrishnan Changes: v2 - minor corrections for gcc strict aliasing and coding style standard. This patch enables i40e driver in powerpc along with its altivec intrinsic support. Signed-off-by: Gowrishankar Muthukrishnan --- MAINTAINERS | 1 + config/defconfig_ppc_64-power8-linuxapp-gcc | 2 +- doc/guides/nics/features/i40e.ini | 1 + doc/guides/nics/features/i40e_vec.ini | 1 + drivers/net/i40e/Makefile | 2 + drivers/net/i40e/i40e_rxtx_vec_altivec.c| 651 6 files changed, 657 insertions(+), 1 deletion(-) create mode 100644 drivers/net/i40e/i40e_rxtx_vec_altivec.c diff --git a/MAINTAINERS b/MAINTAINERS index 065397b..a380b5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -166,6 +166,7 @@ IBM POWER M: Chao Zhu F: lib/librte_eal/common/arch/ppc_64/ F: lib/librte_eal/common/include/arch/ppc_64/ +F: drivers/net/i40e/i40e_rxtx_vec_altivec.c Intel x86 M: Bruce Richardson diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index f953e61..e8e5e58 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -49,7 +49,7 @@ CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n # Note: Initially, all of the PMD drivers compilation are turned off on Power # Will turn on them only after the successful testing on Power CONFIG_RTE_LIBRTE_IXGBE_PMD=n -CONFIG_RTE_LIBRTE_I40E_PMD=n +CONFIG_RTE_LIBRTE_I40E_PMD=y CONFIG_RTE_LIBRTE_VIRTIO_PMD=y CONFIG_RTE_LIBRTE_VMXNET3_PMD=n CONFIG_RTE_LIBRTE_PMD_BOND=n diff --git a/doc/guides/nics/features/i40e.ini b/doc/guides/nics/features/i40e.ini index 0d143bc..6fad048 100644 --- a/doc/guides/nics/features/i40e.ini +++ b/doc/guides/nics/features/i40e.ini @@ -46,3 +46,4 @@ Linux VFIO = Y x86-32 = Y x86-64 = Y ARMv8= Y +PPC_64 = Y diff --git a/doc/guides/nics/features/i40e_vec.ini b/doc/guides/nics/features/i40e_vec.ini index edd6b71..f653446 100644 --- a/doc/guides/nics/features/i40e_vec.ini +++ b/doc/guides/nics/features/i40e_vec.ini @@ -38,3 +38,4 @@ Linux VFIO = Y x86-32 = Y x86-64 = Y ARMv8= Y +PPC_64 = Y diff --git a/drivers/net/i40e/Makefile b/drivers/net/i40e/Makefile index 13085fb..9c9a867 100644 --- a/drivers/net/i40e/Makefile +++ b/drivers/net/i40e/Makefile @@ -99,6 +99,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_rxtx.c ifeq ($(CONFIG_RTE_ARCH_ARM64),y) SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_neon.c +else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y) +SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_altivec.c else SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_sse.c endif diff --git a/drivers/net/i40e/i40e_rxtx_vec_altivec.c b/drivers/net/i40e/i40e_rxtx_vec_altivec.c new file mode 100644 index 000..28c65b1 --- /dev/null +++ b/drivers/net/i40e/i40e_rxtx_vec_altivec.c @@ -0,0 +1,651 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * Copyright(c) 2016 IBM Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include "base/i40e_prototype.h&q
[dpdk-dev] [PATCH v3] i40e: implement vector PMD for altivec
From: Gowrishankar Muthukrishnan Changes: v3 - minor corrections for coding style standard. v2 - minor corrections for gcc strict aliasing and coding style standard. This patch enables i40e driver in powerpc along with its altivec intrinsic support. Signed-off-by: Gowrishankar Muthukrishnan --- MAINTAINERS | 1 + config/defconfig_ppc_64-power8-linuxapp-gcc | 2 +- doc/guides/nics/features/i40e.ini | 1 + doc/guides/nics/features/i40e_vec.ini | 1 + drivers/net/i40e/Makefile | 2 + drivers/net/i40e/i40e_rxtx_vec_altivec.c| 654 6 files changed, 660 insertions(+), 1 deletion(-) create mode 100644 drivers/net/i40e/i40e_rxtx_vec_altivec.c diff --git a/MAINTAINERS b/MAINTAINERS index 065397b..a380b5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -166,6 +166,7 @@ IBM POWER M: Chao Zhu F: lib/librte_eal/common/arch/ppc_64/ F: lib/librte_eal/common/include/arch/ppc_64/ +F: drivers/net/i40e/i40e_rxtx_vec_altivec.c Intel x86 M: Bruce Richardson diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index f953e61..e8e5e58 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -49,7 +49,7 @@ CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n # Note: Initially, all of the PMD drivers compilation are turned off on Power # Will turn on them only after the successful testing on Power CONFIG_RTE_LIBRTE_IXGBE_PMD=n -CONFIG_RTE_LIBRTE_I40E_PMD=n +CONFIG_RTE_LIBRTE_I40E_PMD=y CONFIG_RTE_LIBRTE_VIRTIO_PMD=y CONFIG_RTE_LIBRTE_VMXNET3_PMD=n CONFIG_RTE_LIBRTE_PMD_BOND=n diff --git a/doc/guides/nics/features/i40e.ini b/doc/guides/nics/features/i40e.ini index 0d143bc..6fad048 100644 --- a/doc/guides/nics/features/i40e.ini +++ b/doc/guides/nics/features/i40e.ini @@ -46,3 +46,4 @@ Linux VFIO = Y x86-32 = Y x86-64 = Y ARMv8= Y +PPC_64 = Y diff --git a/doc/guides/nics/features/i40e_vec.ini b/doc/guides/nics/features/i40e_vec.ini index edd6b71..f653446 100644 --- a/doc/guides/nics/features/i40e_vec.ini +++ b/doc/guides/nics/features/i40e_vec.ini @@ -38,3 +38,4 @@ Linux VFIO = Y x86-32 = Y x86-64 = Y ARMv8= Y +PPC_64 = Y diff --git a/drivers/net/i40e/Makefile b/drivers/net/i40e/Makefile index 13085fb..9c9a867 100644 --- a/drivers/net/i40e/Makefile +++ b/drivers/net/i40e/Makefile @@ -99,6 +99,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_rxtx.c ifeq ($(CONFIG_RTE_ARCH_ARM64),y) SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_neon.c +else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y) +SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_altivec.c else SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_sse.c endif diff --git a/drivers/net/i40e/i40e_rxtx_vec_altivec.c b/drivers/net/i40e/i40e_rxtx_vec_altivec.c new file mode 100644 index 000..2230e6f --- /dev/null +++ b/drivers/net/i40e/i40e_rxtx_vec_altivec.c @@ -0,0 +1,654 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * Copyright(c) 2016 IBM Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include
[dpdk-dev] [PATCH v4] i40e: implement vector PMD for altivec
From: Gowrishankar Muthukrishnan This patch enables i40e driver in powerpc along with its altivec intrinsic support. Changes: v4 - docs and config update. v3 - minor corrections for coding style standard. v2 - minor corrections for gcc strict aliasing and coding style standard. Signed-off-by: Gowrishankar Muthukrishnan --- MAINTAINERS | 1 + config/defconfig_ppc_64-power8-linuxapp-gcc | 1 - doc/guides/nics/features/i40e.ini | 1 + doc/guides/nics/features/i40e_vec.ini | 1 + doc/guides/rel_notes/release_17_05.rst | 3 + drivers/net/i40e/Makefile | 2 + drivers/net/i40e/i40e_rxtx_vec_altivec.c| 654 7 files changed, 662 insertions(+), 1 deletion(-) create mode 100644 drivers/net/i40e/i40e_rxtx_vec_altivec.c diff --git a/MAINTAINERS b/MAINTAINERS index 24e0eff..8da7573 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -166,6 +166,7 @@ IBM POWER M: Chao Zhu F: lib/librte_eal/common/arch/ppc_64/ F: lib/librte_eal/common/include/arch/ppc_64/ +F: drivers/net/i40e/i40e_rxtx_vec_altivec.c Intel x86 M: Bruce Richardson diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index 35f7fb6..ceddd41 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -49,7 +49,6 @@ CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n # Note: Initially, all of the PMD drivers compilation are turned off on Power # Will turn on them only after the successful testing on Power CONFIG_RTE_LIBRTE_IXGBE_PMD=n -CONFIG_RTE_LIBRTE_I40E_PMD=n CONFIG_RTE_LIBRTE_VIRTIO_PMD=y CONFIG_RTE_LIBRTE_VMXNET3_PMD=n CONFIG_RTE_LIBRTE_PMD_BOND=n diff --git a/doc/guides/nics/features/i40e.ini b/doc/guides/nics/features/i40e.ini index 6d11cce..7030015 100644 --- a/doc/guides/nics/features/i40e.ini +++ b/doc/guides/nics/features/i40e.ini @@ -48,3 +48,4 @@ Linux VFIO = Y x86-32 = Y x86-64 = Y ARMv8= Y +Power8 = Y diff --git a/doc/guides/nics/features/i40e_vec.ini b/doc/guides/nics/features/i40e_vec.ini index edd6b71..5ec4088 100644 --- a/doc/guides/nics/features/i40e_vec.ini +++ b/doc/guides/nics/features/i40e_vec.ini @@ -38,3 +38,4 @@ Linux VFIO = Y x86-32 = Y x86-64 = Y ARMv8= Y +Power8 = Y diff --git a/doc/guides/rel_notes/release_17_05.rst b/doc/guides/rel_notes/release_17_05.rst index e25ea9f..b8600a0 100644 --- a/doc/guides/rel_notes/release_17_05.rst +++ b/doc/guides/rel_notes/release_17_05.rst @@ -41,6 +41,9 @@ New Features Also, make sure to start the actual text at the margin. = +* **Added powerpc support for i40e and its vector PMD .** + + i40e PMD and its vector PMD enabled by default in powerpc. Resolved Issues --- diff --git a/drivers/net/i40e/Makefile b/drivers/net/i40e/Makefile index 94482cf..ad97441 100644 --- a/drivers/net/i40e/Makefile +++ b/drivers/net/i40e/Makefile @@ -99,6 +99,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_rxtx.c ifeq ($(CONFIG_RTE_ARCH_ARM64),y) SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_neon.c +else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y) +SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_altivec.c else SRCS-$(CONFIG_RTE_LIBRTE_I40E_INC_VECTOR) += i40e_rxtx_vec_sse.c endif diff --git a/drivers/net/i40e/i40e_rxtx_vec_altivec.c b/drivers/net/i40e/i40e_rxtx_vec_altivec.c new file mode 100644 index 000..40d1929 --- /dev/null +++ b/drivers/net/i40e/i40e_rxtx_vec_altivec.c @@ -0,0 +1,654 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * Copyright(c) 2017 IBM Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. I
[dpdk-dev] [PATCH v2] eal: sPAPR IOMMU support in pci probing for vfio-pci in ppc64le
From: Gowrishankar Muthukrishnan
Below changes adds pci probing support for vfio-pci devices in power8.
Changes:
v2 - kernel version checked and doc updated
Signed-off-by: Gowrishankar Muthukrishnan
---
doc/guides/rel_notes/release_17_05.rst | 4 ++
lib/librte_eal/linuxapp/eal/eal_vfio.c | 90 ++
lib/librte_eal/linuxapp/eal/eal_vfio.h | 6 +++
3 files changed, 100 insertions(+)
diff --git a/doc/guides/rel_notes/release_17_05.rst
b/doc/guides/rel_notes/release_17_05.rst
index e25ea9f..4b90036 100644
--- a/doc/guides/rel_notes/release_17_05.rst
+++ b/doc/guides/rel_notes/release_17_05.rst
@@ -42,6 +42,10 @@ New Features
=
+* **Added powerpc support in pci probing for vfio-pci devices.**
+
+ sPAPR IOMMU based pci probing enabled for vfio-pci devices.
+
Resolved Issues
---
diff --git a/lib/librte_eal/linuxapp/eal/eal_vfio.c
b/lib/librte_eal/linuxapp/eal/eal_vfio.c
index 702f7a2..9377a66 100644
--- a/lib/librte_eal/linuxapp/eal/eal_vfio.c
+++ b/lib/librte_eal/linuxapp/eal/eal_vfio.c
@@ -50,12 +50,15 @@
static struct vfio_config vfio_cfg;
static int vfio_type1_dma_map(int);
+static int vfio_spapr_dma_map(int);
static int vfio_noiommu_dma_map(int);
/* IOMMU types we support */
static const struct vfio_iommu_type iommu_types[] = {
/* x86 IOMMU, otherwise known as type 1 */
{ RTE_VFIO_TYPE1, "Type 1", &vfio_type1_dma_map},
+ /* ppc64 IOMMU, otherwise known as spapr */
+ { RTE_VFIO_SPAPR, "sPAPR", &vfio_spapr_dma_map},
/* IOMMU-less mode */
{ RTE_VFIO_NOIOMMU, "No-IOMMU", &vfio_noiommu_dma_map},
};
@@ -540,6 +543,93 @@ int vfio_setup_device(const char *sysfs_base, const char
*dev_addr,
}
static int
+vfio_spapr_dma_map(int vfio_container_fd)
+{
+ const struct rte_memseg *ms = rte_eal_get_physmem_layout();
+ int i, ret;
+
+ struct vfio_iommu_spapr_register_memory reg = {
+ .argsz = sizeof(reg),
+ .flags = 0
+ };
+ struct vfio_iommu_spapr_tce_info info = {
+ .argsz = sizeof(info),
+ };
+ struct vfio_iommu_spapr_tce_create create = {
+ .argsz = sizeof(create),
+ };
+ struct vfio_iommu_spapr_tce_remove remove = {
+ .argsz = sizeof(remove),
+ };
+
+ /* query spapr iommu info */
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_GET_INFO, &info);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot get iommu info, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ /* remove default DMA of 32 bit window */
+ remove.start_addr = info.dma32_window_start;
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_REMOVE, &remove);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot remove default DMA window, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ /* calculate window size based on number of hugepages configured */
+ create.window_size = rte_eal_get_physmem_size();
+ create.page_shift = __builtin_ctzll(ms->hugepage_sz);
+ create.levels = 2;
+
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_CREATE, &create);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot create new DMA window, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ /* map all DPDK segments for DMA. use 1:1 PA to IOVA mapping */
+ for (i = 0; i < RTE_MAX_MEMSEG; i++) {
+ struct vfio_iommu_type1_dma_map dma_map;
+
+ if (ms[i].addr == NULL)
+ break;
+
+ reg.vaddr = (uintptr_t) ms[i].addr;
+ reg.size = ms[i].len;
+ ret = ioctl(vfio_container_fd,
+ VFIO_IOMMU_SPAPR_REGISTER_MEMORY, ®);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot register vaddr for IOMMU, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ memset(&dma_map, 0, sizeof(dma_map));
+ dma_map.argsz = sizeof(struct vfio_iommu_type1_dma_map);
+ dma_map.vaddr = ms[i].addr_64;
+ dma_map.size = ms[i].len;
+ dma_map.iova = ms[i].phys_addr;
+ dma_map.flags = VFIO_DMA_MAP_FLAG_READ |
+VFIO_DMA_MAP_FLAG_WRITE;
+
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_MAP_DMA, &dma_map);
+
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot set up DMA remapping, "
+
[dpdk-dev] [PATCH v3] eal: sPAPR IOMMU support in pci probing for vfio-pci in ppc64le
From: Gowrishankar Muthukrishnan
Below changes adds pci probing support for vfio-pci devices in power8.
v3 - better validation for kernel not implementing few iocts called
v2 - kernel version checked and doc updated
Signed-off-by: Gowrishankar Muthukrishnan
---
doc/guides/rel_notes/release_17_05.rst | 4 ++
lib/librte_eal/linuxapp/eal/eal_vfio.c | 90 ++
lib/librte_eal/linuxapp/eal/eal_vfio.h | 25 ++
3 files changed, 119 insertions(+)
diff --git a/doc/guides/rel_notes/release_17_05.rst
b/doc/guides/rel_notes/release_17_05.rst
index e25ea9f..4b90036 100644
--- a/doc/guides/rel_notes/release_17_05.rst
+++ b/doc/guides/rel_notes/release_17_05.rst
@@ -42,6 +42,10 @@ New Features
=
+* **Added powerpc support in pci probing for vfio-pci devices.**
+
+ sPAPR IOMMU based pci probing enabled for vfio-pci devices.
+
Resolved Issues
---
diff --git a/lib/librte_eal/linuxapp/eal/eal_vfio.c
b/lib/librte_eal/linuxapp/eal/eal_vfio.c
index 702f7a2..9377a66 100644
--- a/lib/librte_eal/linuxapp/eal/eal_vfio.c
+++ b/lib/librte_eal/linuxapp/eal/eal_vfio.c
@@ -50,12 +50,15 @@
static struct vfio_config vfio_cfg;
static int vfio_type1_dma_map(int);
+static int vfio_spapr_dma_map(int);
static int vfio_noiommu_dma_map(int);
/* IOMMU types we support */
static const struct vfio_iommu_type iommu_types[] = {
/* x86 IOMMU, otherwise known as type 1 */
{ RTE_VFIO_TYPE1, "Type 1", &vfio_type1_dma_map},
+ /* ppc64 IOMMU, otherwise known as spapr */
+ { RTE_VFIO_SPAPR, "sPAPR", &vfio_spapr_dma_map},
/* IOMMU-less mode */
{ RTE_VFIO_NOIOMMU, "No-IOMMU", &vfio_noiommu_dma_map},
};
@@ -540,6 +543,93 @@ int vfio_setup_device(const char *sysfs_base, const char
*dev_addr,
}
static int
+vfio_spapr_dma_map(int vfio_container_fd)
+{
+ const struct rte_memseg *ms = rte_eal_get_physmem_layout();
+ int i, ret;
+
+ struct vfio_iommu_spapr_register_memory reg = {
+ .argsz = sizeof(reg),
+ .flags = 0
+ };
+ struct vfio_iommu_spapr_tce_info info = {
+ .argsz = sizeof(info),
+ };
+ struct vfio_iommu_spapr_tce_create create = {
+ .argsz = sizeof(create),
+ };
+ struct vfio_iommu_spapr_tce_remove remove = {
+ .argsz = sizeof(remove),
+ };
+
+ /* query spapr iommu info */
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_GET_INFO, &info);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot get iommu info, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ /* remove default DMA of 32 bit window */
+ remove.start_addr = info.dma32_window_start;
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_REMOVE, &remove);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot remove default DMA window, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ /* calculate window size based on number of hugepages configured */
+ create.window_size = rte_eal_get_physmem_size();
+ create.page_shift = __builtin_ctzll(ms->hugepage_sz);
+ create.levels = 2;
+
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_CREATE, &create);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot create new DMA window, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ /* map all DPDK segments for DMA. use 1:1 PA to IOVA mapping */
+ for (i = 0; i < RTE_MAX_MEMSEG; i++) {
+ struct vfio_iommu_type1_dma_map dma_map;
+
+ if (ms[i].addr == NULL)
+ break;
+
+ reg.vaddr = (uintptr_t) ms[i].addr;
+ reg.size = ms[i].len;
+ ret = ioctl(vfio_container_fd,
+ VFIO_IOMMU_SPAPR_REGISTER_MEMORY, ®);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot register vaddr for IOMMU, "
+ "error %i (%s)\n", errno, strerror(errno));
+ return -1;
+ }
+
+ memset(&dma_map, 0, sizeof(dma_map));
+ dma_map.argsz = sizeof(struct vfio_iommu_type1_dma_map);
+ dma_map.vaddr = ms[i].addr_64;
+ dma_map.size = ms[i].len;
+ dma_map.iova = ms[i].phys_addr;
+ dma_map.flags = VFIO_DMA_MAP_FLAG_READ |
+VFIO_DMA_MAP_FLAG_WRITE;
+
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_MAP_DMA, &dma_map);
+
+ if (ret) {
[dpdk-dev] [PATCH v7 1/9] lpm: add altivec intrinsics for dpdk lpm on ppc_64
From: Gowrishankar Muthukrishnan
This patch adds ppc64le port for LPM library in DPDK.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Chao Zhu
---
app/test/test_xmmt_ops.h | 16 +++
config/defconfig_ppc_64-power8-linuxapp-gcc| 1 -
.../common/include/arch/ppc_64/rte_vect.h | 60
lib/librte_lpm/Makefile| 2 +
lib/librte_lpm/rte_lpm.h | 2 +
lib/librte_lpm/rte_lpm_altivec.h | 154 +
6 files changed, 234 insertions(+), 1 deletion(-)
create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
create mode 100644 lib/librte_lpm/rte_lpm_altivec.h
diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
index de9c16f..42174d2 100644
--- a/app/test/test_xmmt_ops.h
+++ b/app/test/test_xmmt_ops.h
@@ -62,6 +62,22 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
#define vect_set_epi32(i3, i2, i1, i0) _mm_set_epi32(i3, i2, i1, i0)
+#elif defined(RTE_ARCH_PPC_64)
+
+/* vect_* abstraction implementation using ALTIVEC */
+
+/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
+#define vect_loadu_sil128(p) vec_ld(0, p)
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static inline xmm_t __attribute__((always_inline))
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+ xmm_t data = (xmm_t){i0, i1, i2, i3};
+
+ return data;
+}
+
#endif
#endif /* _TEST_XMMT_OPS_H_ */
diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc
b/config/defconfig_ppc_64-power8-linuxapp-gcc
index bef8f49..9ddf3c5 100644
--- a/config/defconfig_ppc_64-power8-linuxapp-gcc
+++ b/config/defconfig_ppc_64-power8-linuxapp-gcc
@@ -57,7 +57,6 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n
CONFIG_RTE_LIBRTE_FM10K_PMD=n
# This following libraries are not available on Power. So they're turned off.
-CONFIG_RTE_LIBRTE_LPM=n
CONFIG_RTE_LIBRTE_ACL=n
CONFIG_RTE_LIBRTE_SCHED=n
CONFIG_RTE_LIBRTE_PORT=n
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
b/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
new file mode 100644
index 000..05209e5
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
@@ -0,0 +1,60 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) IBM Corporation 2016.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of IBM Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_VECT_PPC_64_H_
+#define _RTE_VECT_PPC_64_H_
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef vector signed int xmm_t;
+
+#defineXMM_SIZE(sizeof(xmm_t))
+#defineXMM_MASK(XMM_SIZE - 1)
+
+typedef union rte_xmm {
+ xmm_tx;
+ uint8_t u8[XMM_SIZE / sizeof(uint8_t)];
+ uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
+ uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
+ uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
+ double pd[XMM_SIZE / sizeof(double)];
+} __attribute__((aligned(16))) rte_xmm_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_VECT_PPC_64_H_ */
diff --git a/lib/librte_lpm/Makefile b/lib/librte_lpm/Makefile
index 656ade2..3dc549d 100644
--- a/lib/librte_lpm/Makefile
+++ b/lib/librte_lpm/Makefile
@@ -51,6 +51,8 @@ ifneq ($(filter y,$(CONFIG_RTE_ARCH_ARM)
$(CONFIG_RTE_ARCH_ARM64)),)
SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include +=
[dpdk-dev] [PATCH v7 2/9] acl: add altivec intrinsics for dpdk acl on ppc_64
From: Gowrishankar Muthukrishnan
This patch adds port for ACL library in ppc64le.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Konstantin Ananyev
Acked-by: Chao Zhu
---
app/test-acl/main.c | 4 +
config/defconfig_ppc_64-power8-linuxapp-gcc | 1 -
lib/librte_acl/Makefile | 2 +
lib/librte_acl/acl.h| 4 +
lib/librte_acl/acl_run.h| 2 +
lib/librte_acl/acl_run_altivec.c| 47
lib/librte_acl/acl_run_altivec.h| 329
lib/librte_acl/rte_acl.c| 13 ++
lib/librte_acl/rte_acl.h| 1 +
9 files changed, 402 insertions(+), 1 deletion(-)
create mode 100644 lib/librte_acl/acl_run_altivec.c
create mode 100644 lib/librte_acl/acl_run_altivec.h
diff --git a/app/test-acl/main.c b/app/test-acl/main.c
index d366981..1b2b176 100644
--- a/app/test-acl/main.c
+++ b/app/test-acl/main.c
@@ -105,6 +105,10 @@ static const struct acl_alg acl_alg[] = {
.name = "neon",
.alg = RTE_ACL_CLASSIFY_NEON,
},
+ {
+ .name = "altivec",
+ .alg = RTE_ACL_CLASSIFY_ALTIVEC,
+ },
};
static struct {
diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc
b/config/defconfig_ppc_64-power8-linuxapp-gcc
index 9ddf3c5..dede34f 100644
--- a/config/defconfig_ppc_64-power8-linuxapp-gcc
+++ b/config/defconfig_ppc_64-power8-linuxapp-gcc
@@ -57,7 +57,6 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n
CONFIG_RTE_LIBRTE_FM10K_PMD=n
# This following libraries are not available on Power. So they're turned off.
-CONFIG_RTE_LIBRTE_ACL=n
CONFIG_RTE_LIBRTE_SCHED=n
CONFIG_RTE_LIBRTE_PORT=n
CONFIG_RTE_LIBRTE_TABLE=n
diff --git a/lib/librte_acl/Makefile b/lib/librte_acl/Makefile
index 9803e9d..d05be66 100644
--- a/lib/librte_acl/Makefile
+++ b/lib/librte_acl/Makefile
@@ -52,6 +52,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_scalar.c
ifneq ($(filter y,$(CONFIG_RTE_ARCH_ARM) $(CONFIG_RTE_ARCH_ARM64)),)
SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_neon.c
CFLAGS_acl_run_neon.o += -flax-vector-conversions -Wno-maybe-uninitialized
+else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y)
+SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_altivec.c
else
SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c
#check if flag for SSE4.1 is already on, if not set it up manually
diff --git a/lib/librte_acl/acl.h b/lib/librte_acl/acl.h
index 09d6784..6664a55 100644
--- a/lib/librte_acl/acl.h
+++ b/lib/librte_acl/acl.h
@@ -234,6 +234,10 @@ int
rte_acl_classify_neon(const struct rte_acl_ctx *ctx, const uint8_t **data,
uint32_t *results, uint32_t num, uint32_t categories);
+int
+rte_acl_classify_altivec(const struct rte_acl_ctx *ctx, const uint8_t **data,
+ uint32_t *results, uint32_t num, uint32_t categories);
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/lib/librte_acl/acl_run.h b/lib/librte_acl/acl_run.h
index b2fc42c..024f393 100644
--- a/lib/librte_acl/acl_run.h
+++ b/lib/librte_acl/acl_run.h
@@ -39,7 +39,9 @@
#define MAX_SEARCHES_AVX16 16
#define MAX_SEARCHES_SSE8 8
+#define MAX_SEARCHES_ALTIVEC8 8
#define MAX_SEARCHES_SSE4 4
+#define MAX_SEARCHES_ALTIVEC4 4
#define MAX_SEARCHES_SCALAR2
#define GET_NEXT_4BYTES(prm, idx) \
diff --git a/lib/librte_acl/acl_run_altivec.c b/lib/librte_acl/acl_run_altivec.c
new file mode 100644
index 000..3523526
--- /dev/null
+++ b/lib/librte_acl/acl_run_altivec.c
@@ -0,0 +1,47 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright (C) IBM Corporation 2016.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVE
[dpdk-dev] [PATCH v7 3/9] l3fwd: add altivec support for em_hash_key
From: Gowrishankar Muthukrishnan
This patch adds ppc64le port for em_mask_key function.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Chao Zhu
---
examples/l3fwd/l3fwd_em.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index def5a02..6053a62 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -259,8 +259,16 @@ em_mask_key(void *key, xmm_t mask)
return vandq_s32(data, mask);
}
+#elif defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+ xmm_t data = vec_ld(0, (xmm_t *)(key));
+
+ return vec_and(data, mask);
+}
#else
-#error No vector engine (SSE, NEON) available, check your toolchain
+#error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
#endif
static inline uint8_t
--
1.9.1
[dpdk-dev] [PATCH v7 4/9] table: enable table library for ppc64le
From: Gowrishankar Muthukrishnan This patch enables librte_table in ppc64le. Signed-off-by: Gowrishankar Muthukrishnan Acked-by: Chao Zhu --- config/defconfig_ppc_64-power8-linuxapp-gcc | 1 - 1 file changed, 1 deletion(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index dede34f..41f67d5 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -59,5 +59,4 @@ CONFIG_RTE_LIBRTE_FM10K_PMD=n # This following libraries are not available on Power. So they're turned off. CONFIG_RTE_LIBRTE_SCHED=n CONFIG_RTE_LIBRTE_PORT=n -CONFIG_RTE_LIBRTE_TABLE=n CONFIG_RTE_LIBRTE_PIPELINE=n -- 1.9.1
[dpdk-dev] [PATCH v7 6/9] port: enable port library for ppc64le
From: Gowrishankar Muthukrishnan This patch enables librte_port in ppc64le. Signed-off-by: Gowrishankar Muthukrishnan Acked-by: Chao Zhu --- config/defconfig_ppc_64-power8-linuxapp-gcc | 1 - 1 file changed, 1 deletion(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index 0c7060f..1fc8df2 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -57,5 +57,4 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n CONFIG_RTE_LIBRTE_FM10K_PMD=n # This following libraries are not available on Power. So they're turned off. -CONFIG_RTE_LIBRTE_PORT=n CONFIG_RTE_LIBRTE_PIPELINE=n -- 1.9.1
[dpdk-dev] [PATCH v7 7/9] pipeline: enable pipeline library for ppc64le
From: Gowrishankar Muthukrishnan This patch enables librte_pipeline for ppc64le. Signed-off-by: Gowrishankar Muthukrishnan Acked-by: Chao Zhu --- config/defconfig_ppc_64-power8-linuxapp-gcc | 2 -- 1 file changed, 2 deletions(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index 1fc8df2..f953e61 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -56,5 +56,3 @@ CONFIG_RTE_LIBRTE_PMD_BOND=n CONFIG_RTE_LIBRTE_ENIC_PMD=n CONFIG_RTE_LIBRTE_FM10K_PMD=n -# This following libraries are not available on Power. So they're turned off. -CONFIG_RTE_LIBRTE_PIPELINE=n -- 1.9.1
[dpdk-dev] [PATCH v7 8/9] ip_pipeline: fix lcore mapping for varying SMT threads as in ppc64
From: Gowrishankar Muthukrishnan
This patch fixes ip_pipeline panic in app_init_core_map while preparing cpu
core map in powerpc with SMT off. cpu_core_map_compute_linux currently prepares
core mapping based on file existence in sysfs ie.
/sys/devices/system/cpu/cpu/topology/physical_package_id
/sys/devices/system/cpu/cpu/topology/core_id
These files do not exist for lcores which are offline for any reason (as in
powerpc, while SMT is off). In this situation, this function should further
continue preparing map for other online lcores instead of returning with -1
for a first unavailable lcore.
Also, in SMT=off scenario for powerpc, lcore ids can not be always indexed from
0 upto 'number of cores present' (/sys/devices/system/cpu/present). For eg, for
an online lcore 32, core_id returned in sysfs is 112 where online lcores are
10 (as in one configuration), hence sysfs lcore id can not be checked with
indexing lcore number before positioning lcore map array.
Signed-off-by: Gowrishankar Muthukrishnan
Acked by: Cristian Dumitrescu
Acked-by: Chao Zhu
---
examples/ip_pipeline/cpu_core_map.c | 8
1 file changed, 8 insertions(+)
diff --git a/examples/ip_pipeline/cpu_core_map.c
b/examples/ip_pipeline/cpu_core_map.c
index cb088b1..dd8f678 100644
--- a/examples/ip_pipeline/cpu_core_map.c
+++ b/examples/ip_pipeline/cpu_core_map.c
@@ -351,8 +351,10 @@ cpu_core_map_compute_linux(struct cpu_core_map *map)
int lcore_socket_id =
cpu_core_map_get_socket_id_linux(lcore_id);
+#if !defined(RTE_ARCH_PPC_64)
if (lcore_socket_id < 0)
return -1;
+#endif
if (((uint32_t) lcore_socket_id) == socket_id)
n_detected++;
@@ -368,6 +370,7 @@ cpu_core_map_compute_linux(struct cpu_core_map *map)
cpu_core_map_get_socket_id_linux(
lcore_id);
+#if !defined(RTE_ARCH_PPC_64)
if (lcore_socket_id < 0)
return -1;
@@ -377,9 +380,14 @@ cpu_core_map_compute_linux(struct cpu_core_map *map)
if (lcore_core_id < 0)
return -1;
+#endif
+#if !defined(RTE_ARCH_PPC_64)
if (((uint32_t) lcore_socket_id == socket_id) &&
((uint32_t) lcore_core_id == core_id)) {
+#else
+ if (((uint32_t) lcore_socket_id == socket_id)) {
+#endif
uint32_t pos = cpu_core_map_pos(map,
socket_id,
core_id_contig,
--
1.9.1
[dpdk-dev] [PATCH v7 9/9] table: fix verification on hash bucket header alignment
From: Gowrishankar Muthukrishnan
In powerpc systems, rte table hash structs rte_bucket_4_8, rte_bucket_4_16 and
rte_bucket_4_32 are not cache aligned and hence verification on same would fail.
Instead of checking alignment on cpu cacheline, it could equally be tested as
multiple of 64 bytes.
Signed-off-by: Gowrishankar Muthukrishnan
---
lib/librte_table/rte_table_hash_key16.c | 4 ++--
lib/librte_table/rte_table_hash_key32.c | 4 ++--
lib/librte_table/rte_table_hash_key8.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/lib/librte_table/rte_table_hash_key16.c
b/lib/librte_table/rte_table_hash_key16.c
index b7e000f..08d4d77 100644
--- a/lib/librte_table/rte_table_hash_key16.c
+++ b/lib/librte_table/rte_table_hash_key16.c
@@ -130,7 +130,7 @@ rte_table_hash_create_key16_lru(void *params,
/* Check input parameters */
if ((check_params_create_lru(p) != 0) ||
((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||
- ((sizeof(struct rte_bucket_4_16) % RTE_CACHE_LINE_SIZE) != 0))
+ ((sizeof(struct rte_bucket_4_16) % 64) != 0))
return NULL;
n_entries_per_bucket = 4;
key_size = 16;
@@ -344,7 +344,7 @@ rte_table_hash_create_key16_ext(void *params,
/* Check input parameters */
if ((check_params_create_ext(p) != 0) ||
((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||
- ((sizeof(struct rte_bucket_4_16) % RTE_CACHE_LINE_SIZE) != 0))
+ ((sizeof(struct rte_bucket_4_16) % 64) != 0))
return NULL;
n_entries_per_bucket = 4;
diff --git a/lib/librte_table/rte_table_hash_key32.c
b/lib/librte_table/rte_table_hash_key32.c
index a7aba49..161f6b7 100644
--- a/lib/librte_table/rte_table_hash_key32.c
+++ b/lib/librte_table/rte_table_hash_key32.c
@@ -129,7 +129,7 @@ rte_table_hash_create_key32_lru(void *params,
/* Check input parameters */
if ((check_params_create_lru(p) != 0) ||
((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||
- ((sizeof(struct rte_bucket_4_32) % RTE_CACHE_LINE_SIZE) != 0)) {
+ ((sizeof(struct rte_bucket_4_32) % 64) != 0)) {
return NULL;
}
n_entries_per_bucket = 4;
@@ -337,7 +337,7 @@ rte_table_hash_create_key32_ext(void *params,
/* Check input parameters */
if ((check_params_create_ext(p) != 0) ||
((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||
- ((sizeof(struct rte_bucket_4_32) % RTE_CACHE_LINE_SIZE) != 0))
+ ((sizeof(struct rte_bucket_4_32) % 64) != 0))
return NULL;
n_entries_per_bucket = 4;
diff --git a/lib/librte_table/rte_table_hash_key8.c
b/lib/librte_table/rte_table_hash_key8.c
index e2e2bdc..b04f60d 100644
--- a/lib/librte_table/rte_table_hash_key8.c
+++ b/lib/librte_table/rte_table_hash_key8.c
@@ -125,7 +125,7 @@ rte_table_hash_create_key8_lru(void *params, int socket_id,
uint32_t entry_size)
/* Check input parameters */
if ((check_params_create_lru(p) != 0) ||
((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||
- ((sizeof(struct rte_bucket_4_8) % RTE_CACHE_LINE_SIZE) != 0)) {
+ ((sizeof(struct rte_bucket_4_8) % 64) != 0)) {
return NULL;
}
n_entries_per_bucket = 4;
@@ -332,7 +332,7 @@ rte_table_hash_create_key8_ext(void *params, int socket_id,
uint32_t entry_size)
/* Check input parameters */
if ((check_params_create_ext(p) != 0) ||
((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||
- ((sizeof(struct rte_bucket_4_8) % RTE_CACHE_LINE_SIZE) != 0))
+ ((sizeof(struct rte_bucket_4_8) % 64) != 0))
return NULL;
n_entries_per_bucket = 4;
--
1.9.1
[dpdk-dev] [PATCH v7 0/9] enable lpm, acl and other missing libraries in ppc64le
From: Gowrishankar Muthukrishnan This patchset enables LPM, ACL and other few missing libs in ppc64le and also address few patches in related examples (ip_pipeline and l3fwd). Test report: 1. LPM and ACL unit tests passed. Steps: compile test app and run (with any needed params) lpm_autotest acl_autotest table_autotest test_table_lpm_combined fails same as in intel in current master. 2. Example ip_pipeline application verified for port forwarding. compile examples/ip_pipeline (adjust app_init_core_map param for ht to 1 in case of ppc64le in SMT=off mode). modify config/l3fwd.cfg as per enabled PMD ports. run ip_pipeline with config file option and check packets fwd. v7 changes: - removed enforcing cache alignment for table hash structs and instead check only for multiples of 64 bytes. v6 changes: - added cache alignment fix for rte hash table structs. v5 changes: - no change in lpm lib enablement - no change in acl lib enablement - config file changes individually for sched,table,port,pipeline lib enablement - ip_pipeline patch description and changes flagged only for ppc64le. app_init_core_map changes removed (due to bug found and under investigation only on ppc64le/smt=off case). v4 changes: - fix transition4 in acl_run_altivec.h for gcc strict-aliasing error. Thanks to Chao Zhu for bringing up. v3 changes: - rebase over master to fix conflict in examples/l3fwd/l3fwd_em.c v2 changes: - enabling libs in config included as part of lib changes itself. Gowrishankar Muthukrishnan (9): lpm: add altivec intrinsics for dpdk lpm on ppc_64 acl: add altivec intrinsics for dpdk acl on ppc_64 l3fwd: add altivec support for em_hash_key table: enable table library for ppc64le sched: enable sched library for ppc64le port: enable port library for ppc64le pipeline: enable pipeline library for ppc64le ip_pipeline: fix lcore mapping for varying SMT threads as in ppc64 table: fix verification on hash bucket header alignment app/test-acl/main.c| 4 + app/test/test_xmmt_ops.h | 16 + config/defconfig_ppc_64-power8-linuxapp-gcc| 7 - examples/ip_pipeline/cpu_core_map.c| 8 + examples/l3fwd/l3fwd_em.c | 10 +- lib/librte_acl/Makefile| 2 + lib/librte_acl/acl.h | 4 + lib/librte_acl/acl_run.h | 2 + lib/librte_acl/acl_run_altivec.c | 47 +++ lib/librte_acl/acl_run_altivec.h | 329 + lib/librte_acl/rte_acl.c | 13 + lib/librte_acl/rte_acl.h | 1 + .../common/include/arch/ppc_64/rte_vect.h | 60 lib/librte_lpm/Makefile| 2 + lib/librte_lpm/rte_lpm.h | 2 + lib/librte_lpm/rte_lpm_altivec.h | 154 ++ lib/librte_table/rte_table_hash_key16.c| 4 +- lib/librte_table/rte_table_hash_key32.c| 4 +- lib/librte_table/rte_table_hash_key8.c | 4 +- 19 files changed, 659 insertions(+), 14 deletions(-) create mode 100644 lib/librte_acl/acl_run_altivec.c create mode 100644 lib/librte_acl/acl_run_altivec.h create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_vect.h create mode 100644 lib/librte_lpm/rte_lpm_altivec.h -- 1.9.1
[dpdk-dev] [PATCH v7 5/9] sched: enable sched library for ppc64le
From: Gowrishankar Muthukrishnan This patch enables librte_sched in ppc64le. Signed-off-by: Gowrishankar Muthukrishnan Acked-by: Chao Zhu --- config/defconfig_ppc_64-power8-linuxapp-gcc | 1 - 1 file changed, 1 deletion(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index 41f67d5..0c7060f 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -57,6 +57,5 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n CONFIG_RTE_LIBRTE_FM10K_PMD=n # This following libraries are not available on Power. So they're turned off. -CONFIG_RTE_LIBRTE_SCHED=n CONFIG_RTE_LIBRTE_PORT=n CONFIG_RTE_LIBRTE_PIPELINE=n -- 1.9.1
[dpdk-dev] [PATCH] examples: fix ip_pipeline to load PMD driver correctly
From: Gowrishankar Muthukrishnan
There is typo in init.c of ip_pipeline example due to which,
invalid file path is added to -d option of EAL i.e path starting
with =.
Signed-off-by: Gowrishankar Muthukrishnan
---
examples/ip_pipeline/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/ip_pipeline/init.c b/examples/ip_pipeline/init.c
index cd167f6..27b0aa7 100644
--- a/examples/ip_pipeline/init.c
+++ b/examples/ip_pipeline/init.c
@@ -236,7 +236,7 @@ app_init_eal(struct app_params *app)
}
if (p->add_driver) {
- snprintf(buffer, sizeof(buffer), "-d=%s", p->add_driver);
+ snprintf(buffer, sizeof(buffer), "-d %s", p->add_driver);
app->eal_argv[n_args++] = strdup(buffer);
}
--
1.9.1
[dpdk-dev] [PATCH] net/bonding: enable bonding pmd in ppc64le
From: Gowrishankar Muthukrishnan Earlier bonding pmd was disabled in default config for ppc64le. Same has been verified, with active-backup mode for an instance (to bond two VFs in each phy port): testpmd-bonding-cmd.txt: create bonded device 1 0 create bonded device 1 0 add bonding slave 0 4 add bonding slave 1 4 add bonding slave 2 5 add bonding slave 3 5 set bonding primary 0 4 set bonding primary 2 5 port start 4 port start 5 show bonding config 4 show bonding config 5 set portlist 4,5 ./ppc_64-power8-linuxapp-gcc/app/testpmd -l 0,8,16 -b 0002:01:00.0 -b 0002:01:00.1 --socket-mem 512,512 -- -i --cmdline-file=../testpmd-bonding-cmd.txt EAL: PCI device 0002:01:00.0 on NUMA socket 1 EAL: Device is blacklisted, not initializing EAL: PCI device 0002:01:00.1 on NUMA socket 1 EAL: Device is blacklisted, not initializing EAL: PCI device 0002:01:00.2 on NUMA socket 1 EAL: probe driver: 15b3:1014 net_mlx5 PMD: net_mlx5: PCI information matches, using device "mlx5_2" (SR-IOV: true, MPS: false) PMD: net_mlx5: 1 port(s) detected PMD: net_mlx5: MPS is disabled PMD: net_mlx5: port 1 MAC address is 00:22:33:44:55:02 EAL: PCI device 0002:01:00.3 on NUMA socket 1 EAL: probe driver: 15b3:1014 net_mlx5 PMD: net_mlx5: PCI information matches, using device "mlx5_3" (SR-IOV: true, MPS: false) PMD: net_mlx5: 1 port(s) detected PMD: net_mlx5: MPS is disabled PMD: net_mlx5: port 1 MAC address is 00:22:33:44:55:03 EAL: PCI device 0002:01:00.6 on NUMA socket 1 EAL: probe driver: 15b3:1014 net_mlx5 PMD: net_mlx5: PCI information matches, using device "mlx5_4" (SR-IOV: true, MPS: false) PMD: net_mlx5: 1 port(s) detected PMD: net_mlx5: MPS is disabled PMD: net_mlx5: port 1 MAC address is 00:22:33:44:55:06 EAL: PCI device 0002:01:00.7 on NUMA socket 1 EAL: probe driver: 15b3:1014 net_mlx5 PMD: net_mlx5: PCI information matches, using device "mlx5_5" (SR-IOV: true, MPS: false) PMD: net_mlx5: 1 port(s) detected PMD: net_mlx5: MPS is disabled PMD: net_mlx5: port 1 MAC address is 00:22:33:44:55:07 Interactive-mode selected CLI commands to be read from ../testpmd-bonding-cmd.txt USER1: create a new mbuf pool : n=163456, size=2176, socket=0 USER1: create a new mbuf pool : n=163456, size=2176, socket=1 Configuring Port 0 (socket 1) PMD: net_mlx5: 0x33518f80: TX queues number update: 0 -> 1 PMD: net_mlx5: 0x33518f80: RX queues number update: 0 -> 1 Port 0: 00:22:33:44:55:02 Configuring Port 1 (socket 1) PMD: net_mlx5: 0x3351d000: TX queues number update: 0 -> 1 PMD: net_mlx5: 0x3351d000: RX queues number update: 0 -> 1 Port 1: 00:22:33:44:55:03 Configuring Port 2 (socket 1) PMD: net_mlx5: 0x33521080: TX queues number update: 0 -> 1 PMD: net_mlx5: 0x33521080: RX queues number update: 0 -> 1 Port 2: 00:22:33:44:55:06 Configuring Port 3 (socket 1) PMD: net_mlx5: 0x33525100: TX queues number update: 0 -> 1 PMD: net_mlx5: 0x33525100: RX queues number update: 0 -> 1 Port 3: 00:22:33:44:55:07 Checking link statuses... Done EAL: Initializing pmd_bond for net_bond_testpmd_0 EAL: Create bonded device net_bond_testpmd_0 on port 4 in mode 1 on socket 0. Created new bonded device net_bond_testpmd_0 on (port 4). EAL: Initializing pmd_bond for net_bond_testpmd_1 EAL: Create bonded device net_bond_testpmd_1 on port 5 in mode 1 on socket 0. Created new bonded device net_bond_testpmd_1 on (port 5). Configuring Port 4 (socket 0) Port 4: LSC event Port 4: 00:22:33:44:55:02 Checking link statuses... Done Configuring Port 5 (socket 0) Port 5: LSC event Port 5: 00:22:33:44:55:06 Checking link statuses... Done Bonding mode: 1 Slaves (2): [0 1] Active Slaves (2): [0 1] Primary: [0] Bonding mode: 1 Slaves (2): [2 3] Active Slaves (2): [2 3] Primary: [2] previous number of forwarding ports 4 - changed to number of configured ports 2 Read CLI commands from ../testpmd-bonding-cmd.txt testpmd> start Signed-off-by: Gowrishankar Muthukrishnan --- config/defconfig_ppc_64-power8-linuxapp-gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index 71e4c35..4fce585 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -51,7 +51,7 @@ CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n CONFIG_RTE_LIBRTE_IXGBE_PMD=n CONFIG_RTE_LIBRTE_VIRTIO_PMD=y CONFIG_RTE_LIBRTE_VMXNET3_PMD=n -CONFIG_RTE_LIBRTE_PMD_BOND=n +CONFIG_RTE_LIBRTE_PMD_BOND=y CONFIG_RTE_LIBRTE_ENIC_PMD=n CONFIG_RTE_LIBRTE_FM10K_PMD=n CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n -- 1.9.1
[dpdk-dev] [PATCH] net/bonding: support bifurcated driver in eal cli using --vdev
From: Gowrishankar Muthukrishnan
At present, creating bonding devices using --vdev is broken for PMD like
mlx5 as it is neither UIO nor VFIO based and hence PMD driver is unknown
to find_port_id_by_pci_addr(), as below.
testpmd --vdev 'net_bonding0,mode=1,slave=,socket_id=0'
PMD: bond_ethdev_parse_slave_port_kvarg(150) - Invalid slave port value
() specified
EAL: Failed to parse slave ports for bonded device net_bonding0
This patch adds RTE_KDRV_BIFURCATED in rte_kernel_driver for the PMD
driver like mlx5 to be a known one.
Signed-off-by: Gowrishankar Muthukrishnan
---
lib/librte_eal/common/include/rte_pci.h | 1 +
lib/librte_eal/linuxapp/eal/eal_pci.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/lib/librte_eal/common/include/rte_pci.h
b/lib/librte_eal/common/include/rte_pci.h
index b82ab9e..bbfd50d 100644
--- a/lib/librte_eal/common/include/rte_pci.h
+++ b/lib/librte_eal/common/include/rte_pci.h
@@ -126,6 +126,7 @@ enum rte_kernel_driver {
RTE_KDRV_VFIO,
RTE_KDRV_UIO_GENERIC,
RTE_KDRV_NIC_UIO,
+ RTE_KDRV_BIFURCATED,
RTE_KDRV_NONE,
};
diff --git a/lib/librte_eal/linuxapp/eal/eal_pci.c
b/lib/librte_eal/linuxapp/eal/eal_pci.c
index 595622b..a222ec3 100644
--- a/lib/librte_eal/linuxapp/eal/eal_pci.c
+++ b/lib/librte_eal/linuxapp/eal/eal_pci.c
@@ -351,6 +351,8 @@
dev->kdrv = RTE_KDRV_IGB_UIO;
else if (!strcmp(driver, "uio_pci_generic"))
dev->kdrv = RTE_KDRV_UIO_GENERIC;
+ else if (!strcmp(driver, "mlx5_core"))
+ dev->kdrv = RTE_KDRV_BIFURCATED;
else
dev->kdrv = RTE_KDRV_UNKNOWN;
} else
--
1.9.1
[dpdk-dev] [PATCH] net/i40e: fix compilation error in ppc64le
From: Gowrishankar Muthukrishnan
A typo introduced in i40e_rxtx_vec_altivec.c from commit 67f038076657
("net/i40e: enable per-device packet type mapping"). This patch is to
address compilation error in ppc64le.
Signed-off-by: Gowrishankar Muthukrishnan
---
drivers/net/i40e/i40e_rxtx_vec_altivec.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/i40e/i40e_rxtx_vec_altivec.c
b/drivers/net/i40e/i40e_rxtx_vec_altivec.c
index 07de31b..f4036ea 100644
--- a/drivers/net/i40e/i40e_rxtx_vec_altivec.c
+++ b/drivers/net/i40e/i40e_rxtx_vec_altivec.c
@@ -208,13 +208,13 @@
ptype1 = vec_sr(ptype1, (vector unsigned long){30, 30});
rx_pkts[0]->packet_type =
- ptype_tbl[(*(vector unsigned char *)&ptype0)[0])];
+ ptype_tbl[(*(vector unsigned char *)&ptype0)[0]];
rx_pkts[1]->packet_type =
- ptype_tbl[(*(vector unsigned char *)&ptype0)[8])];
+ ptype_tbl[(*(vector unsigned char *)&ptype0)[8]];
rx_pkts[2]->packet_type =
- ptype_tbl[(*(vector unsigned char *)&ptype1)[0])];
+ ptype_tbl[(*(vector unsigned char *)&ptype1)[0]];
rx_pkts[3]->packet_type =
- ptype_tbl[(*(vector unsigned char *)&ptype1)[8])];
+ ptype_tbl[(*(vector unsigned char *)&ptype1)[8]];
}
/* Notice:
--
1.9.1
[dpdk-dev] [PATCH] usertools: fix cpu_layout script for multithreads of more than 2
From: Gowrishankar Muthukrishnan
Current usertools/cpu_layout.py is broken to handle multithreads of count more
than 2 as in IBM powerpc P8 servers. Below patch addressed this issue. Also,
added minor exception catch on failing to open unavailable sys file in case of
multithread=off configuration in server.
Patch has been verified not to break existing topology configurations
and also not changing anything in current output.
Signed-off-by: Gowrishankar Muthukrishnan
---
usertools/cpu_layout.py | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/usertools/cpu_layout.py b/usertools/cpu_layout.py
index 5735891..99152a2 100755
--- a/usertools/cpu_layout.py
+++ b/usertools/cpu_layout.py
@@ -46,6 +46,8 @@
for cpu in xrange(max_cpus + 1):
try:
fd = open("{}/cpu{}/topology/core_id".format(base_path, cpu))
+except IOError:
+continue
except:
break
core = int(fd.read())
@@ -70,7 +72,10 @@
print("")
max_processor_len = len(str(len(cores) * len(sockets) * 2 - 1))
-max_core_map_len = max_processor_len * 2 + len('[, ]') + len('Socket ')
+max_thread_count = len(core_map.values()[0])
+max_core_map_len = (max_processor_len * max_thread_count) \
+ + len(", ") * (max_thread_count - 1) \
+ + len('[]') + len('Socket ')
max_core_id_len = len(str(max(cores)))
output = " ".ljust(max_core_id_len + len('Core '))
@@ -87,5 +92,8 @@
for c in cores:
output = "Core %s" % str(c).ljust(max_core_id_len)
for s in sockets:
-output += " " + str(core_map[(s, c)]).ljust(max_core_map_len)
+if core_map.has_key((s,c)):
+output += " " + str(core_map[(s, c)]).ljust(max_core_map_len)
+else:
+output += " " * (max_core_map_len + 1)
print(output)
--
1.9.1
[dpdk-dev] [PATCH] kni: add new mbuf in alloc_q only based on its empty slots
From: Gowrishankar Muthukrishnan
In kni_allocate_mbufs(), we attempt to add max_burst (32) count of mbuf always
into alloc_q, which is excessively leading too many rte_pktmbuf_free() when
alloc_q is contending at high packet rate (for eg 10Gig data). In a situation
when alloc_q fifo can only accommodate very few (or zero) mbuf, create only
what needed and add in fifo.
With this patch, we could stop random network stall in KNI at higher packet
rate (eg 1G or 10G data between vEth0 and PMD) sufficiently exhausting alloc_q
on above condition. I tested i40e PMD for this purpose in ppc64le.
Signed-off-by: Gowrishankar Muthukrishnan
---
lib/librte_kni/rte_kni.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/lib/librte_kni/rte_kni.c b/lib/librte_kni/rte_kni.c
index c3f9208..7e0e9a6 100644
--- a/lib/librte_kni/rte_kni.c
+++ b/lib/librte_kni/rte_kni.c
@@ -624,6 +624,7 @@ struct rte_kni *
int i, ret;
struct rte_mbuf *pkts[MAX_MBUF_BURST_NUM];
void *phys[MAX_MBUF_BURST_NUM];
+ int allocq_free;
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pool) !=
offsetof(struct rte_kni_mbuf, pool));
@@ -646,7 +647,9 @@ struct rte_kni *
return;
}
- for (i = 0; i < MAX_MBUF_BURST_NUM; i++) {
+ allocq_free = (kni->alloc_q->read - kni->alloc_q->write - 1) \
+ & MAX_MBUF_BURST_NUM;
+ for (i = 0; i < allocq_free; i++) {
pkts[i] = rte_pktmbuf_alloc(kni->pktmbuf_pool);
if (unlikely(pkts[i] == NULL)) {
/* Out of memory */
--
1.9.1
[dpdk-dev] [PATCH v2] kni: add new mbuf in alloc_q only based on its empty slots
From: Gowrishankar Muthukrishnan
In kni_allocate_mbufs(), we attempt to add max_burst (32) count of mbuf
always into alloc_q, which is excessively leading too many rte_pktmbuf_
free() when alloc_q is contending at high packet rate (for eg 10Gig data).
In a situation when alloc_q fifo can only accommodate very few (or zero)
mbuf, create only what needed and add in fifo.
With this patch, we could stop random network stall in KNI at higher packet
rate (eg 1G or 10G data between vEth0 and PMD) sufficiently exhausting
alloc_q on above condition. I tested i40e PMD for this purpose in ppc64le.
Changes:
v2 - alloc_q free count calculation corrected.
line wrap fixed for commit message.
Signed-off-by: Gowrishankar Muthukrishnan
---
lib/librte_kni/rte_kni.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/lib/librte_kni/rte_kni.c b/lib/librte_kni/rte_kni.c
index c3f9208..9c5d485 100644
--- a/lib/librte_kni/rte_kni.c
+++ b/lib/librte_kni/rte_kni.c
@@ -624,6 +624,7 @@ struct rte_kni *
int i, ret;
struct rte_mbuf *pkts[MAX_MBUF_BURST_NUM];
void *phys[MAX_MBUF_BURST_NUM];
+ int allocq_free;
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pool) !=
offsetof(struct rte_kni_mbuf, pool));
@@ -646,7 +647,9 @@ struct rte_kni *
return;
}
- for (i = 0; i < MAX_MBUF_BURST_NUM; i++) {
+ allocq_free = (kni->alloc_q->read - kni->alloc_q->write - 1) \
+ & (MAX_MBUF_BURST_NUM - 1);
+ for (i = 0; i < allocq_free; i++) {
pkts[i] = rte_pktmbuf_alloc(kni->pktmbuf_pool);
if (unlikely(pkts[i] == NULL)) {
/* Out of memory */
--
1.9.1
[dpdk-dev] [PATCH 0/2] eal/malloc: fix wrong heap initialization over multiple memsegs
From: Gowrishankar Muthukrishnan When there are multiple memsegs (each per hugepage), there are couple of problems observed: 1. Same heap size index is always chosen to add new malloc_elems again and again, while there is an increasing heap size actually. Hence, when there is memalloc request for size *more than* elem->size available in free heap, malloc_heap_alloc would fail. In elem_start_pt(), we are actually relying on elem->size at the best, for finding suitable element, which is lower than requested size, in this case. Hence, patch 1 in this series addresses this by merging contiguous malloc_elem (by virt addresses), so that there is better chance of finding suitable elem for the requested size. 2. Even after resizing the heap malloc_elems, its free_head index is still the same, as the memsegs are just added in every malloc_ elem. If larger memory is requested in rte_malloc, in a way that, heap index of requested size is beyond the slot where the entire heap is available, malloc_heap_alloc would fail. Because, at the time of heap init, only the lower index is always chosen to fill up memsegs. Hence, patch 2 addresses this by moving the list of malloc_elems into new slot in heap, as its size grows. We encountered these situations as we run ip_reassembly example app, when multiple segments are created in VA (when overcommit hugepages set in powerpc arch). These problems are found only in the current releases (until v18.05 which carries new implementation for dynamic memory allocation). These patches are tested with unit tests as well as some of the examples apps. I request more testing if possible, on other archs as these are problems in available LTS codes as well. Signed-off-by: Gowrishankar Muthukrishnan Gowrishankar Muthukrishnan (2): eal/malloc: merge malloc_elems in heap if they are contiguous eal/malloc: fix heap index to correctly insert memseg lib/librte_eal/common/malloc_heap.c | 52 - 1 file changed, 51 insertions(+), 1 deletion(-) -- 1.9.1
[dpdk-dev] [PATCH 1/2] eal/malloc: merge malloc_elems in heap if they are contiguous
From: Gowrishankar Muthukrishnan
During malloc heap init, if there are malloc_elems contiguous in
virt addresses, they could be merged so that, merged malloc_elem
would guarantee larger free memory size than its actual hugepage
size, it was created for.
Fixes: fafcc11985 ("mem: rework memzone to be allocated by malloc")
Cc: sta...@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan
---
lib/librte_eal/common/malloc_heap.c | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/lib/librte_eal/common/malloc_heap.c
b/lib/librte_eal/common/malloc_heap.c
index 267a4c6..1cacf7f 100644
--- a/lib/librte_eal/common/malloc_heap.c
+++ b/lib/librte_eal/common/malloc_heap.c
@@ -213,7 +213,9 @@
{
struct rte_mem_config *mcfg = rte_eal_get_configuration()->mem_config;
unsigned ms_cnt;
- struct rte_memseg *ms;
+ struct rte_memseg *ms, *prev_ms = NULL;
+ struct malloc_elem *elem, *prev_elem;
+ int ret;
if (mcfg == NULL)
return -1;
@@ -222,6 +224,32 @@
(ms_cnt < RTE_MAX_MEMSEG) && (ms->len > 0);
ms_cnt++, ms++) {
malloc_heap_add_memseg(&mcfg->malloc_heaps[ms->socket_id], ms);
+ elem = (struct malloc_elem *)ms->addr;
+ if (prev_ms != NULL && \
+ (ms->socket_id == prev_ms->socket_id)) {
+ prev_elem = (struct malloc_elem *)prev_ms->addr;
+
+ /* prev_elem and elem to be contiguous for the resize.
+ Other wise look for prev_elem in iterations */
+ if (elem != RTE_PTR_ADD(prev_elem,
+ prev_elem->size + MALLOC_ELEM_OVERHEAD)) {
+ prev_ms = ms;
+ continue;
+ }
+ /* end BUSY elem pointed by prev_elem can be merged
+ with prev_elem itself, as it expands it size now.
+*/
+ prev_elem->size += MALLOC_ELEM_OVERHEAD;
+
+ /* preserve end BUSY elem that points to current elem,
+ or else free_list will be broken */
+ ret = malloc_elem_resize(prev_elem,
+ prev_elem->size + elem->size -
MALLOC_ELEM_OVERHEAD);
+ if (ret < 0)
+ prev_elem = elem;
+ } else {
+ prev_ms = ms;
+ }
}
return 0;
--
1.9.1
[dpdk-dev] [PATCH 2/2] eal/malloc: fix heap index to correctly insert memseg
From: Gowrishankar Muthukrishnan
When there are multiple memsegs created and adding new memseg would
cause bigger heap size, its index in free_head list should be based
on new size of heap. Currently, only the size of elem is accounted
as in malloc_elem_free_list_insert. As heap total size gets bigger,
list of those memsegs should be at the right index, so that
malloc_heap_alloc would find suitable element for the requested
memory size by applications.
Fixes: b0489e7bca ("malloc: fix linear complexity")
Cc: sta...@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan
---
Eg. Below heap is in one numa socket, for the size of 1G (i.e 64*16MB).
All corresponding malloc_elem are always added in heap index 8,
as their size is always 16MB (and due to which, index is also 8 always).
free_head = {{lh_first = 0x0}, {lh_first = 0x0}, {lh_first = 0x0}, {
lh_first = 0x0}, {lh_first = 0x0}, {lh_first = 0x0}, {lh_first =
0x0}, {
lh_first = 0x0}, {lh_first = 0x7efd3f00}, {lh_first = 0x0},
{lh_first = 0x0}, {
lh_first = 0x0}, {lh_first = 0x0}},
alloc_count = 6, total_size = 1073733632},
Ideally, this list of memsegs should ideally be at slot 12, as they grow heap
for 1G.
---
lib/librte_eal/common/malloc_heap.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/lib/librte_eal/common/malloc_heap.c
b/lib/librte_eal/common/malloc_heap.c
index 1cacf7f..f686e5e 100644
--- a/lib/librte_eal/common/malloc_heap.c
+++ b/lib/librte_eal/common/malloc_heap.c
@@ -105,10 +105,32 @@
ms->len - MALLOC_ELEM_OVERHEAD);
end_elem = RTE_PTR_ALIGN_FLOOR(end_elem, RTE_CACHE_LINE_SIZE);
const size_t elem_size = (uintptr_t)end_elem - (uintptr_t)start_elem;
+ size_t cur_idx, new_idx, heap_size;
malloc_elem_init(start_elem, heap, ms, elem_size);
malloc_elem_mkend(end_elem, start_elem);
+
+ /* Compare heap index based on its current size as well as
+* its new size with memseg added. If new size needs new index
+* move its free_head to the new slot.
+*/
+ cur_idx = malloc_elem_free_list_index(heap->total_size);
+ heap_size = heap->total_size + elem_size;
+ new_idx = malloc_elem_free_list_index(heap_size);
+ if (cur_idx != new_idx) {
+ heap->free_head[new_idx] = heap->free_head[cur_idx];
+ memset(&heap->free_head[cur_idx],
+ 0, sizeof(heap->free_head[cur_idx]));
+ }
+
+ /* malloc_elem_free_list_insert calculates index based on
+* elem->size, hence we set elem->size as new heap size,
+* while inserting this elem. After that, we reset elem->size
+* to its original value. A minor hack though!.
+*/
+ start_elem->size = heap_size;
malloc_elem_free_list_insert(start_elem);
+ start_elem->size = elem_size;
heap->total_size += elem_size;
}
--
1.9.1
[dpdk-dev] [PATCH] bus/fslmc: use PRIu64 instead of llX in format specifier
From: Gowrishankar Muthukrishnan
Instead of llX, use C99 standard "PRIu64" in format specifier. Former one
breaks compile in ppc64le.
Fixes: c2c167fdb3 ("bus/fslmc: support memory event callbacks for VFIO")
Signed-off-by: Gowrishankar Muthukrishnan
--
In file included from dpdk/drivers/bus/fslmc/fslmc_vfio.c:37:0:
dpdk/drivers/bus/fslmc/fslmc_vfio.c: In function ‘fslmc_map_dma’:
dpdk/drivers/bus/fslmc/fslmc_logs.h:18:44: error: format ‘%llX’ expects
argument of type ‘long long unsigned int’, but argument 5 has type ‘__u64 {aka
long unsigned int}’ [-Werror=format=]
rte_log(RTE_LOG_DEBUG, dpaa2_logtype_bus, "fslmc: %s(): " fmt "\n", \
^
dpdk/drivers/bus/fslmc/fslmc_vfio.c:272:2: note: in expansion of macro
‘DPAA2_BUS_DEBUG’
DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
^~~
dpdk/drivers/bus/fslmc/fslmc_vfio.c:272:39: note: format string is defined here
DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
~~~^
%lX
drivers/bus/fslmc/fslmc_vfio.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index 4036e82..a003a7d 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -270,7 +270,7 @@ static int vfio_map_irq_region(struct fslmc_vfio_group
*group)
return -1;
}
- DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
+ DPAA2_BUS_DEBUG("--> Map address: %"PRIu64", size: 0x%"PRIu64"",
dma_map.vaddr, dma_map.size);
ret = ioctl(group->container->fd, VFIO_IOMMU_MAP_DMA, &dma_map);
if (ret) {
@@ -303,7 +303,7 @@ static int vfio_map_irq_region(struct fslmc_vfio_group
*group)
return -1;
}
- DPAA2_BUS_DEBUG("--> Unmap address: %llX, size: 0x%llX",
+ DPAA2_BUS_DEBUG("--> Unmap address: %"PRIu64", size: 0x%"PRIu64"",
dma_unmap.iova, dma_unmap.size);
ret = ioctl(group->container->fd, VFIO_IOMMU_UNMAP_DMA, &dma_unmap);
if (ret) {
@@ -401,7 +401,7 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group
*group, char *mcp_obj)
goto MC_FAILURE;
}
- DPAA2_BUS_DEBUG("Region offset = %llx , region size = %llx",
+ DPAA2_BUS_DEBUG("Region offset = %"PRIu64" , region size = %"PRIu64"",
reg_info.offset, reg_info.size);
v_addr = (size_t)mmap(NULL, reg_info.size,
--
1.9.1
[dpdk-dev] [PATCH] event/dpaa: fix integer overflow on max_event_ports at compile time
From: Gowrishankar Muthukrishnan
dev_info->max_event_ports is uint8_t. dpaa_event_dev_info_get assigns
DPAA_EVENT_MAX_EVENT_PORT (which is RTE_MAX_LCORE, upto 256 in ppc64le)
into this variable, which breaks compile in ppc64le.
Fixes: 9caac5dd1e ("event/dpaa: introduce PMD")
Signed-off-by: Gowrishankar Muthukrishnan
--
dpdk/drivers/event/dpaa/dpaa_eventdev.c: In function ‘dpaa_event_dev_info_get’:
dpdk/ppc_64-power8-linuxapp-gcc/include/rte_config.h:23:23: error: large
integer implicitly truncated to unsigned type [-Werror=overflow]
#define RTE_MAX_LCORE 256
^
dpdk/drivers/event/dpaa/dpaa_eventdev.h:29:36: note: in expansion of macro
‘RTE_MAX_LCORE’
#define DPAA_EVENT_MAX_EVENT_PORT RTE_MAX_LCORE
^
dpdk/drivers/event/dpaa/dpaa_eventdev.c:197:3: note: in expansion of macro
‘DPAA_EVENT_MAX_EVENT_PORT’
DPAA_EVENT_MAX_EVENT_PORT;
^
drivers/event/dpaa/dpaa_eventdev.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/event/dpaa/dpaa_eventdev.h
b/drivers/event/dpaa/dpaa_eventdev.h
index 918fe35..583e46c 100644
--- a/drivers/event/dpaa/dpaa_eventdev.h
+++ b/drivers/event/dpaa/dpaa_eventdev.h
@@ -26,7 +26,7 @@
#define DPAA_EVENT_MAX_QUEUE_FLOWS 2048
#define DPAA_EVENT_MAX_QUEUE_PRIORITY_LEVELS 8
#define DPAA_EVENT_MAX_EVENT_PRIORITY_LEVELS 0
-#define DPAA_EVENT_MAX_EVENT_PORT RTE_MAX_LCORE
+#define DPAA_EVENT_MAX_EVENT_PORT RTE_MIN(RTE_MAX_LCORE, INT8_MAX)
#define DPAA_EVENT_MAX_PORT_DEQUEUE_DEPTH 8
#define DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_NS 100UL
#define DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_INVALID((uint64_t)-1)
--
1.9.1
[dpdk-dev] [PATCH v2] bus/fslmc: use PRIu64 instead of llX in format specifier
From: Gowrishankar Muthukrishnan
Instead of llX, use C99 standard "PRIu64" in format specifier. Former one
breaks compile in ppc64le.
Fixes: c2c167fdb3 ("bus/fslmc: support memory event callbacks for VFIO")
Signed-off-by: Gowrishankar Muthukrishnan
--
v2:
- corrected format specifier wrt address and size.
In file included from dpdk/drivers/bus/fslmc/fslmc_vfio.c:37:0:
dpdk/drivers/bus/fslmc/fslmc_vfio.c: In function ‘fslmc_map_dma’:
dpdk/drivers/bus/fslmc/fslmc_logs.h:18:44: error: format ‘%llX’ expects
argument of type ‘long long unsigned int’, but argument 5 has type ‘__u64 {aka
long unsigned int}’ [-Werror=format=]
rte_log(RTE_LOG_DEBUG, dpaa2_logtype_bus, "fslmc: %s(): " fmt "\n", \
^
dpdk/drivers/bus/fslmc/fslmc_vfio.c:272:2: note: in expansion of macro
‘DPAA2_BUS_DEBUG’
DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
^~~
dpdk/drivers/bus/fslmc/fslmc_vfio.c:272:39: note: format string is defined here
DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
~~~^
%lX
---
drivers/bus/fslmc/fslmc_vfio.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index 4036e82..80c64d2 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -270,7 +270,7 @@ static int vfio_map_irq_region(struct fslmc_vfio_group
*group)
return -1;
}
- DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
+ DPAA2_BUS_DEBUG("--> Map address: %"PRIx64", size: 0x%"PRIu64"",
dma_map.vaddr, dma_map.size);
ret = ioctl(group->container->fd, VFIO_IOMMU_MAP_DMA, &dma_map);
if (ret) {
@@ -303,7 +303,7 @@ static int vfio_map_irq_region(struct fslmc_vfio_group
*group)
return -1;
}
- DPAA2_BUS_DEBUG("--> Unmap address: %llX, size: 0x%llX",
+ DPAA2_BUS_DEBUG("--> Unmap address: %"PRIx64", size: 0x%"PRIu64"",
dma_unmap.iova, dma_unmap.size);
ret = ioctl(group->container->fd, VFIO_IOMMU_UNMAP_DMA, &dma_unmap);
if (ret) {
@@ -401,7 +401,7 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group
*group, char *mcp_obj)
goto MC_FAILURE;
}
- DPAA2_BUS_DEBUG("Region offset = %llx , region size = %llx",
+ DPAA2_BUS_DEBUG("Region offset = %"PRIx64" , region size = %"PRIu64"",
reg_info.offset, reg_info.size);
v_addr = (size_t)mmap(NULL, reg_info.size,
--
1.9.1
[dpdk-dev] [PATCH v2] bus/fslmc: use PRIu64 instead of llX in format specifier
From: Gowrishankar Muthukrishnan
Instead of llX, use C99 standard "PRIu64" in format specifier. Former one
breaks compile in ppc64le.
Fixes: c2c167fdb3 ("bus/fslmc: support memory event callbacks for VFIO")
Signed-off-by: Gowrishankar Muthukrishnan
--
v2:
- corrected format specifier wrt address and size.
Thanks Shreyansh, Hemant and Thomas.
In file included from dpdk/drivers/bus/fslmc/fslmc_vfio.c:37:0:
dpdk/drivers/bus/fslmc/fslmc_vfio.c: In function ‘fslmc_map_dma’:
dpdk/drivers/bus/fslmc/fslmc_logs.h:18:44: error: format ‘%llX’ expects
argument of type ‘long long unsigned int’, but argument 5 has type ‘__u64 {aka
long unsigned int}’ [-Werror=format=]
rte_log(RTE_LOG_DEBUG, dpaa2_logtype_bus, "fslmc: %s(): " fmt "\n", \
^
dpdk/drivers/bus/fslmc/fslmc_vfio.c:272:2: note: in expansion of macro
‘DPAA2_BUS_DEBUG’
DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
^~~
dpdk/drivers/bus/fslmc/fslmc_vfio.c:272:39: note: format string is defined here
DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
~~~^
%lX
---
drivers/bus/fslmc/fslmc_vfio.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index 4036e82..93c20f3 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -270,8 +270,8 @@ static int vfio_map_irq_region(struct fslmc_vfio_group
*group)
return -1;
}
- DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
- dma_map.vaddr, dma_map.size);
+ DPAA2_BUS_DEBUG("--> Map address: %"PRIx64", size: 0x%"PRIu64"",
+ (uint64_t)dma_map.vaddr, (uint64_t)dma_map.size);
ret = ioctl(group->container->fd, VFIO_IOMMU_MAP_DMA, &dma_map);
if (ret) {
DPAA2_BUS_ERR("VFIO_IOMMU_MAP_DMA API(errno = %d)",
@@ -303,8 +303,8 @@ static int vfio_map_irq_region(struct fslmc_vfio_group
*group)
return -1;
}
- DPAA2_BUS_DEBUG("--> Unmap address: %llX, size: 0x%llX",
- dma_unmap.iova, dma_unmap.size);
+ DPAA2_BUS_DEBUG("--> Unmap address: %"PRIx64", size: 0x%"PRIu64"",
+ (uint64_t)dma_unmap.iova, (uint64_t)dma_unmap.size);
ret = ioctl(group->container->fd, VFIO_IOMMU_UNMAP_DMA, &dma_unmap);
if (ret) {
DPAA2_BUS_ERR("VFIO_IOMMU_UNMAP_DMA API(errno = %d)",
@@ -401,8 +401,8 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group
*group, char *mcp_obj)
goto MC_FAILURE;
}
- DPAA2_BUS_DEBUG("Region offset = %llx , region size = %llx",
- reg_info.offset, reg_info.size);
+ DPAA2_BUS_DEBUG("Region offset = %"PRIx64" , region size = %"PRIu64"",
+ (uint64_t)reg_info.offset, (uint64_t)reg_info.size);
v_addr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
--
1.9.1
[dpdk-dev] [PATCH v3] bus/fslmc: use PRIu64 instead of llX in format specifier
From: Gowrishankar Muthukrishnan
Instead of llX, use C99 standard "PRIu64" in format specifier. Former one
breaks compile in ppc64le.
Fixes: c2c167fdb3 ("bus/fslmc: support memory event callbacks for VFIO")
Signed-off-by: Gowrishankar Muthukrishnan
--
v3:
- correction to prefix address with 0x
v2:
- corrected format specifier wrt address and size.
Thanks Shreyansh, Hemant and Thomas.
In file included from dpdk/drivers/bus/fslmc/fslmc_vfio.c:37:0:
dpdk/drivers/bus/fslmc/fslmc_vfio.c: In function ‘fslmc_map_dma’:
dpdk/drivers/bus/fslmc/fslmc_logs.h:18:44: error: format ‘%llX’ expects
argument of type ‘long long unsigned int’, but argument 5 has type ‘__u64 {aka
long unsigned int}’ [-Werror=format=]
rte_log(RTE_LOG_DEBUG, dpaa2_logtype_bus, "fslmc: %s(): " fmt "\n", \
^
dpdk/drivers/bus/fslmc/fslmc_vfio.c:272:2: note: in expansion of macro
‘DPAA2_BUS_DEBUG’
DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
^~~
dpdk/drivers/bus/fslmc/fslmc_vfio.c:272:39: note: format string is defined here
DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
~~~^
%lX
---
drivers/bus/fslmc/fslmc_vfio.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index 4036e82..675d160 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -270,8 +270,8 @@ static int vfio_map_irq_region(struct fslmc_vfio_group
*group)
return -1;
}
- DPAA2_BUS_DEBUG("--> Map address: %llX, size: 0x%llX",
- dma_map.vaddr, dma_map.size);
+ DPAA2_BUS_DEBUG("--> Map address: 0x%"PRIx64", size: %"PRIu64"",
+ (uint64_t)dma_map.vaddr, (uint64_t)dma_map.size);
ret = ioctl(group->container->fd, VFIO_IOMMU_MAP_DMA, &dma_map);
if (ret) {
DPAA2_BUS_ERR("VFIO_IOMMU_MAP_DMA API(errno = %d)",
@@ -303,8 +303,8 @@ static int vfio_map_irq_region(struct fslmc_vfio_group
*group)
return -1;
}
- DPAA2_BUS_DEBUG("--> Unmap address: %llX, size: 0x%llX",
- dma_unmap.iova, dma_unmap.size);
+ DPAA2_BUS_DEBUG("--> Unmap address: 0x%"PRIx64", size: %"PRIu64"",
+ (uint64_t)dma_unmap.iova, (uint64_t)dma_unmap.size);
ret = ioctl(group->container->fd, VFIO_IOMMU_UNMAP_DMA, &dma_unmap);
if (ret) {
DPAA2_BUS_ERR("VFIO_IOMMU_UNMAP_DMA API(errno = %d)",
@@ -401,8 +401,8 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group
*group, char *mcp_obj)
goto MC_FAILURE;
}
- DPAA2_BUS_DEBUG("Region offset = %llx , region size = %llx",
- reg_info.offset, reg_info.size);
+ DPAA2_BUS_DEBUG("Region offset = 0x%"PRIx64" , region size =
%"PRIu64"",
+ (uint64_t)reg_info.offset, (uint64_t)reg_info.size);
v_addr = (size_t)mmap(NULL, reg_info.size,
PROT_WRITE | PROT_READ, MAP_SHARED,
--
1.9.1
[dpdk-dev] [PATCH v2 24/41] vfio: allow to map other memory regions
From: Gowrishankar Muthukrishnan
Below patch adds powerpc arch specific changes.
Signed-off-by: Gowrishankar Muthukrishnan
---
lib/librte_eal/linuxapp/eal/eal_vfio.c | 63 +-
1 file changed, 47 insertions(+), 16 deletions(-)
diff --git a/lib/librte_eal/linuxapp/eal/eal_vfio.c
b/lib/librte_eal/linuxapp/eal/eal_vfio.c
index 4e9e296..063982c 100644
--- a/lib/librte_eal/linuxapp/eal/eal_vfio.c
+++ b/lib/librte_eal/linuxapp/eal/eal_vfio.c
@@ -24,6 +24,7 @@
static int vfio_type1_dma_map(int);
static int vfio_type1_dma_mem_map(int, uint64_t, uint64_t, uint64_t, int);
static int vfio_spapr_dma_map(int);
+static int vfio_spapr_dma_mem_map(int, uint64_t, uint64_t, uint64_t, int);
static int vfio_noiommu_dma_map(int);
static int vfio_noiommu_dma_mem_map(int, uint64_t, uint64_t, uint64_t, int);
@@ -41,8 +42,7 @@
.type_id = RTE_VFIO_SPAPR,
.name = "sPAPR",
.dma_map_func = &vfio_spapr_dma_map,
- .dma_user_map_func = NULL
- // TODO: work with PPC64 people on enabling this, window size!
+ .dma_user_map_func = &vfio_spapr_dma_mem_map
},
/* IOMMU-less mode */
{
@@ -801,10 +801,51 @@ struct spapr_create_window_walk_param {
}
static int
+vfio_spapr_dma_mem_map(int vfio_container_fd, uint64_t vaddr, uint64_t iova,
+ uint64_t len, int do_map)
+{
+ struct vfio_iommu_type1_dma_map dma_map;
+ struct vfio_iommu_type1_dma_unmap dma_unmap;
+ int ret;
+
+ if (do_map != 0) {
+ memset(&dma_map, 0, sizeof(dma_map));
+ dma_map.argsz = sizeof(struct vfio_iommu_type1_dma_map);
+ dma_map.vaddr = vaddr;
+ dma_map.size = len;
+ dma_map.iova = iova;
+ dma_map.flags = VFIO_DMA_MAP_FLAG_READ |
+ VFIO_DMA_MAP_FLAG_WRITE;
+
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_MAP_DMA, &dma_map);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot set up DMA remapping, error
%i (%s)\n",
+ errno, strerror(errno));
+ return -1;
+ }
+
+ } else {
+ memset(&dma_unmap, 0, sizeof(dma_unmap));
+ dma_unmap.argsz = sizeof(struct vfio_iommu_type1_dma_unmap);
+ dma_unmap.size = len;
+ dma_unmap.iova = iova;
+
+ ret = ioctl(vfio_container_fd, VFIO_IOMMU_UNMAP_DMA,
+ &dma_unmap);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot clear DMA remapping, error
%i (%s)\n",
+ errno, strerror(errno));
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static int
vfio_spapr_dma_map_walk(const struct rte_memseg_list *msl __rte_unused,
const struct rte_memseg *ms, void *arg)
{
- struct vfio_iommu_type1_dma_map dma_map;
struct vfio_iommu_spapr_register_memory reg = {
.argsz = sizeof(reg),
.flags = 0
@@ -828,17 +869,8 @@ struct spapr_create_window_walk_param {
return -1;
}
- memset(&dma_map, 0, sizeof(dma_map));
- dma_map.argsz = sizeof(struct vfio_iommu_type1_dma_map);
- dma_map.vaddr = addr;
- dma_map.size = len;
- dma_map.iova = hw_addr;
- dma_map.flags = VFIO_DMA_MAP_FLAG_READ |
- VFIO_DMA_MAP_FLAG_WRITE;
-
- ret = ioctl(*vfio_container_fd, VFIO_IOMMU_MAP_DMA,
- &dma_map);
-
+ ret = vfio_spapr_dma_mem_map(*vfio_container_fd, addr,
+ hw_addr, len, 1);
if (ret) {
RTE_LOG(ERR, EAL, " cannot set up DMA remapping, error %i
(%s)\n",
errno, strerror(errno));
@@ -852,7 +884,6 @@ struct spapr_create_window_walk_param {
vfio_spapr_dma_map(int vfio_container_fd)
{
int ret;
- uint64_t hugepage_sz = 0;
struct spapr_create_window_walk_param wa;
struct vfio_iommu_spapr_tce_info info = {
@@ -890,7 +921,7 @@ struct spapr_create_window_walk_param {
/* sPAPR requires window size to be a power of 2 */
create.window_size = rte_align64pow2(create.window_size);
- create.page_shift = __builtin_ctzll(hugepage_sz);
+ create.page_shift = __builtin_ctzll(wa.hugepage_sz);
create.levels = 1;
ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_CREATE, &create);
--
1.9.1
[dpdk-dev] [PATCH v2 24/41] vfio: allow to map other memory regions
From: Gowrishankar Muthukrishnan
Below patch adds powerpc arch specific changes.
Signed-off-by: Gowrishankar Muthukrishnan
---
lib/librte_eal/linuxapp/eal/eal_vfio.c | 110 +++--
1 file changed, 105 insertions(+), 5 deletions(-)
diff --git a/lib/librte_eal/linuxapp/eal/eal_vfio.c
b/lib/librte_eal/linuxapp/eal/eal_vfio.c
index 4e9e296..985acf4 100644
--- a/lib/librte_eal/linuxapp/eal/eal_vfio.c
+++ b/lib/librte_eal/linuxapp/eal/eal_vfio.c
@@ -24,6 +24,7 @@
static int vfio_type1_dma_map(int);
static int vfio_type1_dma_mem_map(int, uint64_t, uint64_t, uint64_t, int);
static int vfio_spapr_dma_map(int);
+static int vfio_spapr_dma_mem_map(int, uint64_t, uint64_t, uint64_t, int);
static int vfio_noiommu_dma_map(int);
static int vfio_noiommu_dma_mem_map(int, uint64_t, uint64_t, uint64_t, int);
@@ -41,8 +42,7 @@
.type_id = RTE_VFIO_SPAPR,
.name = "sPAPR",
.dma_map_func = &vfio_spapr_dma_map,
- .dma_user_map_func = NULL
- // TODO: work with PPC64 people on enabling this, window size!
+ .dma_user_map_func = &vfio_spapr_dma_mem_map
},
/* IOMMU-less mode */
{
@@ -838,7 +838,6 @@ struct spapr_create_window_walk_param {
ret = ioctl(*vfio_container_fd, VFIO_IOMMU_MAP_DMA,
&dma_map);
-
if (ret) {
RTE_LOG(ERR, EAL, " cannot set up DMA remapping, error %i
(%s)\n",
errno, strerror(errno));
@@ -852,7 +851,6 @@ struct spapr_create_window_walk_param {
vfio_spapr_dma_map(int vfio_container_fd)
{
int ret;
- uint64_t hugepage_sz = 0;
struct spapr_create_window_walk_param wa;
struct vfio_iommu_spapr_tce_info info = {
@@ -890,7 +888,7 @@ struct spapr_create_window_walk_param {
/* sPAPR requires window size to be a power of 2 */
create.window_size = rte_align64pow2(create.window_size);
- create.page_shift = __builtin_ctzll(hugepage_sz);
+ create.page_shift = __builtin_ctzll(wa.hugepage_sz);
create.levels = 1;
ret = ioctl(vfio_container_fd, VFIO_IOMMU_SPAPR_TCE_CREATE, &create);
@@ -912,6 +910,108 @@ struct spapr_create_window_walk_param {
}
static int
+vfio_spapr_dma_mem_map(int vfio_container_fd, uint64_t vaddr, uint64_t iova,
+ uint64_t len, int do_map)
+{
+ int ret;
+ struct spapr_create_window_walk_param wa = {
+ .hugepage_sz = 0,
+ };
+ struct vfio_iommu_spapr_tce_create create = {
+ .argsz = sizeof(create),
+ };
+
+ /* check if DMA window is from 0 to max(phys_addr + len) */
+ wa.create = &create;
+ rte_memseg_walk(vfio_spapr_create_window_walk, &wa);
+ create.window_size = rte_align64pow2(create.window_size);
+ if (iova > create.window_size) {
+ struct vfio_iommu_spapr_tce_info info = {
+ .argsz = sizeof(info),
+ };
+ struct vfio_iommu_spapr_tce_remove remove = {
+ .argsz = sizeof(remove),
+ };
+
+ /* query spapr iommu info */
+ ret = ioctl(vfio_container_fd,
+ VFIO_IOMMU_SPAPR_TCE_GET_INFO, &info);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot get iommu info, "
+ "error %i (%s)\n", errno,
strerror(errno));
+ return -1;
+ }
+
+ /* remove old DMA window */
+ remove.start_addr = info.dma32_window_start;
+ ret = ioctl(vfio_container_fd,
+ VFIO_IOMMU_SPAPR_TCE_REMOVE, &remove);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot remove default DMA window, "
+ "error %i (%s)\n", errno,
strerror(errno));
+ return -1;
+ }
+ create.page_shift = __builtin_ctzll(wa.hugepage_sz);
+ create.levels = 1;
+
+ ret = ioctl(vfio_container_fd,
+ VFIO_IOMMU_SPAPR_TCE_CREATE, &create);
+ if (ret) {
+ RTE_LOG(ERR, EAL, " cannot create new DMA window, "
+ "error %i (%s)\n", errno,
strerror(errno));
+ return -1;
+ }
+
+ if (create.start_addr != 0) {
+ RTE_LOG(ERR, EAL, " DMA window start address != 0\n");
+ return -1;
+ }
+
+ }
+
+ if (do_map != 0) {
+ if (rte_memseg_walk(vfio_spapr_dma_map_walk,
&vfio_container_fd))
+ return -1;
+
[dpdk-dev] [PATCH v3] net/bonding: support bifurcated driver in eal cli using --vdev
From: Gowrishankar Muthukrishnan
At present, creating bonding devices using --vdev is broken for PMD like
mlx5 as it is neither UIO nor VFIO based and hence PMD driver is unknown
to find_port_id_by_pci_addr(), as below.
testpmd --vdev 'net_bonding0,mode=1,slave=,socket_id=0'
PMD: bond_ethdev_parse_slave_port_kvarg(150) - Invalid slave port value
() specified
EAL: Failed to parse slave ports for bonded device net_bonding0
This patch fixes parsing PCI ID from bonding device params by verifying
it in RTE PCI bus, rather than checking dev->kdrv.
Fixes: eac901ce ("ethdev: decouple from PCI device")
Signed-off-by: Gowrishankar Muthukrishnan
---
v3:
- adapt rte_bus API (with suggestions from Declan and Ga??tan)
drivers/net/bonding/rte_eth_bond_args.c | 35 ++---
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/net/bonding/rte_eth_bond_args.c
b/drivers/net/bonding/rte_eth_bond_args.c
index bb634c6..7c65dda 100644
--- a/drivers/net/bonding/rte_eth_bond_args.c
+++ b/drivers/net/bonding/rte_eth_bond_args.c
@@ -61,16 +61,6 @@
unsigned i;
for (i = 0; i < rte_eth_dev_count(); i++) {
-
- /* Currently populated by rte_eth_copy_pci_info().
-*
-* TODO: Once the PCI bus has arrived we should have a better
-* way to test for being a PCI device or not.
-*/
- if (rte_eth_devices[i].data->kdrv == RTE_KDRV_UNKNOWN ||
- rte_eth_devices[i].data->kdrv == RTE_KDRV_NONE)
- continue;
-
pci_dev = RTE_ETH_DEV_TO_PCI(&rte_eth_devices[i]);
eth_pci_addr = &pci_dev->addr;
@@ -98,6 +88,16 @@
return -1;
}
+static inline int
+pci_addr_cmp(const struct rte_device *dev, const void *_pci_addr)
+{
+ struct rte_pci_device *pdev;
+ const struct rte_pci_addr *paddr = _pci_addr;
+
+ pdev = RTE_DEV_TO_PCI(*(struct rte_device **)(void *)&dev);
+ return rte_eal_compare_pci_addr(&pdev->addr, paddr);
+}
+
/**
* Parses a port identifier string to a port id by pci address, then by name,
* and finally port id.
@@ -106,10 +106,23 @@
parse_port_id(const char *port_str)
{
struct rte_pci_addr dev_addr;
+ struct rte_bus *pci_bus;
+ struct rte_device *dev;
int port_id;
+ pci_bus = rte_bus_find_by_name("pci");
+ if (pci_bus == NULL) {
+ RTE_LOG(ERR, PMD, "unable to find PCI bus\n");
+ return -1;
+ }
+
/* try parsing as pci address, physical devices */
- if (eal_parse_pci_DomBDF(port_str, &dev_addr) == 0) {
+ if (pci_bus->parse(port_str, &dev_addr) == 0) {
+ dev = pci_bus->find_device(NULL, pci_addr_cmp, &dev_addr);
+ if (dev == NULL) {
+ RTE_LOG(ERR, PMD, "unable to find PCI device\n");
+ return -1;
+ }
port_id = find_port_id_by_pci_addr(&dev_addr);
if (port_id < 0)
return -1;
--
1.9.1
[dpdk-dev] [PATCH] examples/l3fwd: optimised packet processing on powerpc
From: Gowrishankar Muthukrishnan
This patch adds altivec support for lpm packet processing in powerpc.
Signed-off-by: Gowrishankar Muthukrishnan
---
examples/l3fwd/l3fwd_altivec.h | 279 +
examples/l3fwd/l3fwd_lpm.c | 4 +-
examples/l3fwd/l3fwd_lpm_altivec.h | 155 +
3 files changed, 437 insertions(+), 1 deletion(-)
create mode 100644 examples/l3fwd/l3fwd_altivec.h
create mode 100644 examples/l3fwd/l3fwd_lpm_altivec.h
diff --git a/examples/l3fwd/l3fwd_altivec.h b/examples/l3fwd/l3fwd_altivec.h
new file mode 100644
index 000..732a461
--- /dev/null
+++ b/examples/l3fwd/l3fwd_altivec.h
@@ -0,0 +1,279 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ * Copyright(c) 2017 IBM Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _L3FWD_ALTIVEC_H_
+#define _L3FWD_ALTIVEC_H_
+
+#include "l3fwd.h"
+#include "l3fwd_common.h"
+
+/*
+ * Update source and destination MAC addresses in the ethernet header.
+ * Perform RFC1812 checks and updates for IPV4 packets.
+ */
+static inline void
+processx4_step3(struct rte_mbuf *pkt[FWDSTEP], uint16_t dst_port[FWDSTEP])
+{
+ vector unsigned int te[FWDSTEP];
+ vector unsigned int ve[FWDSTEP];
+ vector unsigned int *p[FWDSTEP];
+
+ p[0] = rte_pktmbuf_mtod(pkt[0], vector unsigned int *);
+ p[1] = rte_pktmbuf_mtod(pkt[1], vector unsigned int *);
+ p[2] = rte_pktmbuf_mtod(pkt[2], vector unsigned int *);
+ p[3] = rte_pktmbuf_mtod(pkt[3], vector unsigned int *);
+
+ ve[0] = (vector unsigned int)val_eth[dst_port[0]];
+ te[0] = *p[0];
+
+ ve[1] = (vector unsigned int)val_eth[dst_port[1]];
+ te[1] = *p[1];
+
+ ve[2] = (vector unsigned int)val_eth[dst_port[2]];
+ te[2] = *p[2];
+
+ ve[3] = (vector unsigned int)val_eth[dst_port[3]];
+ te[3] = *p[3];
+
+ /* Update first 12 bytes, keep rest bytes intact. */
+ te[0] = (vector unsigned int)vec_sel(
+ (vector unsigned short)ve[0],
+ (vector unsigned short)te[0],
+ (vector unsigned short){0,0,0,0,0,0,0x,0x});
+
+ te[1] = (vector unsigned int)vec_sel(
+ (vector unsigned short)ve[1],
+ (vector unsigned short)te[1],
+ (vector unsigned short){0,0,0,0,0,0,0x,0x});
+
+ te[2] = (vector unsigned int)vec_sel(
+ (vector unsigned short)ve[2],
+ (vector unsigned short)te[2],
+ (vector unsigned short){0,0,0,0,0,0,0x,0x});
+
+ te[3] = (vector unsigned int)vec_sel(
+ (vector unsigned short)ve[3],
+ (vector unsigned short)te[3],
+ (vector unsigned short){0,0,0,0,0,0,0x,0x});
+
+ *p[0] = te[0];
+ *p[1] = te[1];
+ *p[2] = te[2];
+ *p[3] = te[3];
+
+ rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[0] + 1),
+ &dst_port[0], pkt[0]->packet_type);
+ rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[1] + 1),
+ &dst_port[1], pkt[1]->packet_type);
+ rfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[2] + 1),
+
[dpdk-dev] [PATCH v2] examples/l3fwd: optimised packet processing on powerpc
From: Gowrishankar Muthukrishnan
This patch adds altivec support for lpm packet processing in powerpc.
Signed-off-by: Gowrishankar Muthukrishnan
---
v2:
* coding style standards
MAINTAINERS| 1 +
examples/l3fwd/l3fwd_altivec.h | 284 +
examples/l3fwd/l3fwd_lpm.c | 5 +-
examples/l3fwd/l3fwd_lpm_altivec.h | 164 +
4 files changed, 453 insertions(+), 1 deletion(-)
create mode 100644 examples/l3fwd/l3fwd_altivec.h
create mode 100644 examples/l3fwd/l3fwd_lpm_altivec.h
diff --git a/MAINTAINERS b/MAINTAINERS
index a0cd75e..0010b6c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -168,6 +168,7 @@ M: Chao Zhu
F: lib/librte_eal/common/arch/ppc_64/
F: lib/librte_eal/common/include/arch/ppc_64/
F: drivers/net/i40e/i40e_rxtx_vec_altivec.c
+F: examples/l3fwd/*altivec.h
Intel x86
M: Bruce Richardson
diff --git a/examples/l3fwd/l3fwd_altivec.h b/examples/l3fwd/l3fwd_altivec.h
new file mode 100644
index 000..29c2627
--- /dev/null
+++ b/examples/l3fwd/l3fwd_altivec.h
@@ -0,0 +1,284 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ * Copyright(c) 2017 IBM Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _L3FWD_ALTIVEC_H_
+#define _L3FWD_ALTIVEC_H_
+
+#include "l3fwd.h"
+#include "l3fwd_common.h"
+
+/*
+ * Update source and destination MAC addresses in the ethernet header.
+ * Perform RFC1812 checks and updates for IPV4 packets.
+ */
+static inline void
+processx4_step3(struct rte_mbuf *pkt[FWDSTEP], uint16_t dst_port[FWDSTEP])
+{
+ vector unsigned int te[FWDSTEP];
+ vector unsigned int ve[FWDSTEP];
+ vector unsigned int *p[FWDSTEP];
+
+ p[0] = rte_pktmbuf_mtod(pkt[0], vector unsigned int *);
+ p[1] = rte_pktmbuf_mtod(pkt[1], vector unsigned int *);
+ p[2] = rte_pktmbuf_mtod(pkt[2], vector unsigned int *);
+ p[3] = rte_pktmbuf_mtod(pkt[3], vector unsigned int *);
+
+ ve[0] = (vector unsigned int)val_eth[dst_port[0]];
+ te[0] = *p[0];
+
+ ve[1] = (vector unsigned int)val_eth[dst_port[1]];
+ te[1] = *p[1];
+
+ ve[2] = (vector unsigned int)val_eth[dst_port[2]];
+ te[2] = *p[2];
+
+ ve[3] = (vector unsigned int)val_eth[dst_port[3]];
+ te[3] = *p[3];
+
+ /* Update first 12 bytes, keep rest bytes intact. */
+ te[0] = (vector unsigned int)vec_sel(
+ (vector unsigned short)ve[0],
+ (vector unsigned short)te[0],
+ (vector unsigned short) {0, 0, 0, 0,
+ 0, 0, 0x, 0x});
+
+ te[1] = (vector unsigned int)vec_sel(
+ (vector unsigned short)ve[1],
+ (vector unsigned short)te[1],
+ (vector unsigned short) {0, 0, 0, 0,
+ 0, 0, 0x, 0x});
+
+ te[2] = (vector unsigned int)vec_sel(
+ (vector unsigned short)ve[2],
+ (vector unsigned short)te[2],
+ (vector unsigned short) {0, 0, 0, 0, 0,
+ 0, 0x, 0x});
+
+ te[3] = (vector unsigned int)vec_sel(
+ (vector unsigned short)ve[3],
+
[dpdk-dev] [PATCH] eal: fix TSC resolution in hz for ppc_64 architecture
From: Gowrishankar Muthukrishnan
In ppc_64, rte_rdtsc() returns timebase register value which increments
at independent timebase frequency and hence not related to lcore cpu
frequency to derive into. In this patch, we fix get_tsc_freq() to not
depend upon rte_rdtsc(), but obtain cpu current frequency from sysfs.
Signed-off-by: Gowrishankar Muthukrishnan
---
Note:
* This patch would need minor port as per below patch (yet to upstream):
http://dpdk.org/dev/patchwork/patch/27527/
lib/librte_eal/linuxapp/eal/eal_timer.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/lib/librte_eal/linuxapp/eal/eal_timer.c
b/lib/librte_eal/linuxapp/eal/eal_timer.c
index afa32f5..b8775cc 100644
--- a/lib/librte_eal/linuxapp/eal/eal_timer.c
+++ b/lib/librte_eal/linuxapp/eal/eal_timer.c
@@ -55,8 +55,10 @@
#include "eal_private.h"
#include "eal_internal_cfg.h"
+#include "eal_filesystem.h"
enum timer_source eal_timer_source = EAL_TIMER_HPET;
+static const char sys_cpu_dir[] = "/sys/devices/system/cpu";
#ifdef RTE_LIBEAL_USE_HPET
@@ -269,6 +271,17 @@ struct eal_hpet_regs {
uint64_t
get_tsc_freq(void)
{
+#ifdef RTE_ARCH_PPC_64
+ unsigned long cpu_hz;
+ char path[PATH_MAX];
+
+ snprintf(path, sizeof(path), "%s/cpu%d/cpufreq/cpuinfo_cur_freq",
+ sys_cpu_dir, rte_get_master_lcore());
+ if (eal_parse_sysfs_value(path, &cpu_hz) < 0)
+ RTE_LOG(WARNING, EAL, "Unable to parse %s\n",
+ path);
+ return cpu_hz*1000;
+#else
#ifdef CLOCK_MONOTONIC_RAW
#define NS_PER_SEC 1E9
@@ -290,6 +303,7 @@ struct eal_hpet_regs {
return tsc_hz;
}
#endif
+#endif
return 0;
}
--
1.9.1
[dpdk-dev] [PATCH v2 2/5] eal/ppc64: define architecture specific rdtsc hz
From: Jerin Jacob
In ppc_64, rte_rdtsc() returns timebase register value which increments
at independent timebase frequency and hence not related to lcore cpu
frequency to derive TSC hz. Hence, we stick with master lcore frequency.
CC: Chao Zhu
Signed-off-by: Jerin Jacob
Signed-off-by: Gowrishankar Muthukrishnan
---
v2:
* add ppc_64 specific implementation
.../common/include/arch/ppc_64/rte_cycles.h| 24 ++
1 file changed, 24 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h
b/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h
index 8fa6fc6..1b36587 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h
@@ -38,9 +38,13 @@
#endif
#include "generic/rte_cycles.h"
+#include "../../lib/librte_eal/common/eal_filesystem.h"
#include
#include
+#include
+
+static const char sys_cpu_dir[] = "/sys/devices/system/cpu";
/**
* Read the time base register.
@@ -79,6 +83,26 @@
return tsc.tsc_64;
}
+/**
+ * Get the number of rdtsc cycles in one second.
+ *
+ * @return
+ * The number of rdtsc cycles in one second.
+ */
+static inline uint64_t
+rte_rdtsc_arch_hz(void)
+{
+ unsigned long cpu_hz;
+ char path[PATH_MAX];
+
+ snprintf(path, sizeof(path), "%s/cpu%d/cpufreq/cpuinfo_cur_freq",
+ sys_cpu_dir, rte_get_master_lcore());
+ if (eal_parse_sysfs_value(path, &cpu_hz) < 0)
+ RTE_LOG(WARNING, EAL, "Unable to parse %s\n", path);
+
+ return cpu_hz*1000;
+}
+
static inline uint64_t
rte_rdtsc_precise(void)
{
--
1.9.1
[dpdk-dev] [PATCH v2 0/5] improve tsc frequency calibration
From: Gowrishankar Muthukrishnan Some architecture like armv8 provides an architecture specific function to get the rdtsc frequency. The existing rdtsc calibration scheme uses OS serivce like sleep(1) to calibrate the frequency which may not produce the accurate result. Introducing an architecture specific hook to get the rdtsc frequency if architecture provides it. If not, use the exiting the calibrate scheme to get the rdtsc frequency. Jerin Jacob (5): eal/x86: define architecture specific rdtsc hz eal/ppc64: define architecture specific rdtsc hz eal/armv7: define architecture specific rdtsc hz eal/armv8: define architecture specific rdtsc hz eal/timer: honor architecture specific rdtsc hz function lib/librte_eal/common/eal_common_timer.c | 5 +++- .../common/include/arch/arm/rte_cycles_32.h| 13 ++ .../common/include/arch/arm/rte_cycles_64.h| 30 ++ .../common/include/arch/ppc_64/rte_cycles.h| 24 + .../common/include/arch/x86/rte_cycles.h | 13 ++ 5 files changed, 84 insertions(+), 1 deletion(-) -- 1.9.1
[dpdk-dev] [PATCH v2 4/5] eal/armv8: define architecture specific rdtsc hz
From: Jerin Jacob
Use cntvct_el0 system register to get the system counter frequency.
If the system is configured with RTE_ARM_EAL_RDTSC_USE_PMU then
return 0(let the common code calibrate the tsc frequency).
CC: Jianbo Liu
Signed-off-by: Jerin Jacob
Acked-by: Jianbo Liu
---
.../common/include/arch/arm/rte_cycles_64.h| 30 ++
1 file changed, 30 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
index 1545769..5b95cb6 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
@@ -58,6 +58,23 @@
asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
return tsc;
}
+
+/**
+ * Get the number of rdtsc cycles in one second if the architecture supports.
+ *
+ * @return
+ * The number of rdtsc cycles in one second. Return zero if the architecture
+ * support is not available.
+ */
+static inline uint64_t
+rte_rdtsc_arch_hz(void)
+{
+ uint64_t freq;
+
+ asm volatile("mrs %0, cntfrq_el0" : "=r" (freq));
+ return freq;
+}
+
#else
/**
* This is an alternative method to enable rte_rdtsc() with high resolution
@@ -85,6 +102,19 @@
asm volatile("mrs %0, pmccntr_el0" : "=r"(tsc));
return tsc;
}
+
+/**
+ * Get the number of rdtsc cycles in one second if the architecture supports.
+ *
+ * @return
+ * The number of rdtsc cycles in one second. Return zero if the architecture
+ * support is not available.
+ */
+static inline uint64_t
+rte_rdtsc_arch_hz(void)
+{
+ return 0;
+}
#endif
static inline uint64_t
--
1.9.1
[dpdk-dev] [PATCH v2 5/5] eal/timer: honor architecture specific rdtsc hz function
From: Jerin Jacob
When calibrating the tsc frequency, first, probe the architecture specific
rdtsc hz function. if not available, use the existing calibrate scheme
to calibrate the tsc frequency.
Signed-off-by: Jerin Jacob
---
lib/librte_eal/common/eal_common_timer.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/lib/librte_eal/common/eal_common_timer.c
b/lib/librte_eal/common/eal_common_timer.c
index ed0b16d..978edae 100644
--- a/lib/librte_eal/common/eal_common_timer.c
+++ b/lib/librte_eal/common/eal_common_timer.c
@@ -80,8 +80,11 @@
void
set_tsc_freq(void)
{
- uint64_t freq = get_tsc_freq();
+ uint64_t freq;
+ freq = rte_rdtsc_arch_hz();
+ if (!freq)
+ freq = get_tsc_freq();
if (!freq)
freq = estimate_tsc_freq();
--
1.9.1
[dpdk-dev] [PATCH v2 3/5] eal/armv7: define architecture specific rdtsc hz
From: Jerin Jacob
CC: Jan Viktorin
CC: Jianbo Liu
Signed-off-by: Jerin Jacob
---
lib/librte_eal/common/include/arch/arm/rte_cycles_32.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
b/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
index 9c1be71..68d7462 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
@@ -104,6 +104,19 @@
#endif /* RTE_ARM_EAL_RDTSC_USE_PMU */
+/**
+ * Get the number of rdtsc cycles in one second if the architecture supports.
+ *
+ * @return
+ * The number of rdtsc cycles in one second. Return zero if the architecture
+ * support is not available.
+ */
+static inline uint64_t
+rte_rdtsc_arch_hz(void)
+{
+ return 0;
+}
+
static inline uint64_t
rte_rdtsc_precise(void)
{
--
1.9.1
[dpdk-dev] [PATCH v2 1/5] eal/x86: define architecture specific rdtsc hz
From: Jerin Jacob
CC: Bruce Richardson
CC: Konstantin Ananyev
Signed-off-by: Jerin Jacob
Acked-by: Anatoly Burakov
---
lib/librte_eal/common/include/arch/x86/rte_cycles.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cycles.h
b/lib/librte_eal/common/include/arch/x86/rte_cycles.h
index 1bb3e1d..e2661e2 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cycles.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cycles.h
@@ -77,6 +77,19 @@
return tsc.tsc_64;
}
+/**
+ * Get the number of rdtsc cycles in one second if the architecture supports.
+ *
+ * @return
+ * The number of rdtsc cycles in one second. Return zero if the architecture
+ * support is not available.
+ */
+static inline uint64_t
+rte_rdtsc_arch_hz(void)
+{
+ return 0;
+}
+
static inline uint64_t
rte_rdtsc_precise(void)
{
--
1.9.1
[dpdk-dev] [PATCH] net/tap: define __NR_bpf for powerpc
From: Gowrishankar Muthukrishnan
This patch defines __NR_bpf for powerpc architecture and hence,
fixes compiling tap driver for this architecture.
Fixes: b02d85e1 ("net/tap: add eBPF API")
Signed-off-by: Gowrishankar Muthukrishnan
---
drivers/net/tap/tap_bpf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index 8d6f9a2..06e9509 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -97,6 +97,8 @@ enum bpf_map_type {
# define __NR_bpf 349
# elif defined(__s390__)
# define __NR_bpf 351
+# elif defined(__powerpc__)
+# define __NR_bpf 361
# else
# error __NR_bpf not defined
# endif
--
1.9.1
[dpdk-dev] [PATCH] ring: fix compilation error with a broken else clause
From: Gowrishankar Muthukrishnan
Calling rte_smp_wmb macro expands into a compound block, which
would break compiling a else clause following it, if that calling
place has been terminated already with ";", as in below code.
This patch adds { } around this macro to allow compiling else too.
Fixes: git show c9fb3c6289 ("ring: move code in a new header file")
Signed-off-by: Gowrishankar Muthukrishnan
---
Error in compiling source:
In file included from /tmp/dpdk/lib/librte_ring/rte_ring.h:372:0,
from /tmp/dpdk/lib/librte_ring/rte_ring.c:90:
/tmp/dpdk/lib/librte_ring/rte_ring_generic.h: In function ‘update_tail’:
/tmp/dpdk/lib/librte_ring/rte_ring_generic.h:75:2: error: ‘else’ without a
previous ‘if’
else
^~~~
/tmp/dpdk/mk/internal/rte.compile-pre.mk:114: recipe for target 'rte_ring.o'
failed
lib/librte_ring/rte_ring_generic.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/librte_ring/rte_ring_generic.h
b/lib/librte_ring/rte_ring_generic.h
index 8c3e65b..a668489 100644
--- a/lib/librte_ring/rte_ring_generic.h
+++ b/lib/librte_ring/rte_ring_generic.h
@@ -70,8 +70,9 @@
update_tail(struct rte_ring_headtail *ht, uint32_t old_val, uint32_t new_val,
uint32_t single, uint32_t enqueue)
{
- if (enqueue)
+ if (enqueue) {
rte_smp_wmb();
+ }
else
rte_smp_rmb();
/*
--
1.9.1
[dpdk-dev] [PATCH] eal/ppc64: revert implement arch-specific TSC freq query
From: Gowrishankar Muthukrishnan
This reverts commit 15692396fd68932b6a81f00f12d4b0da12baa7d3
(eal/ppc64: implement arch-specific TSC freq query). We intended
to derive pkt/sec estimation with cpu clock frequency. As timebase
register serves the timer purpose, we need to stick with it for
calculating pkt/sec, hence reverting the change.
Fixes: 15692396fd (eal/ppc64: implement arch-specific TSC freq query)
Signed-off-by: Gowrishankar Muthukrishnan
---
lib/librte_eal/common/arch/ppc_64/rte_cycles.c | 47 +-
1 file changed, 1 insertion(+), 46 deletions(-)
diff --git a/lib/librte_eal/common/arch/ppc_64/rte_cycles.c
b/lib/librte_eal/common/arch/ppc_64/rte_cycles.c
index 69a9f74..851fd02 100644
--- a/lib/librte_eal/common/arch/ppc_64/rte_cycles.c
+++ b/lib/librte_eal/common/arch/ppc_64/rte_cycles.c
@@ -1,52 +1,7 @@
-/*
- * BSD LICENSE
- *
- * Copyright (C) IBM Corporation 2014.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of IBM Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include
-#include
-#include "eal_filesystem.h"
#include "eal_private.h"
-static const char sys_cpu_dir[] = "/sys/devices/system/cpu";
-
uint64_t
get_tsc_freq_arch(void)
{
- unsigned long cpu_hz;
- char path[PATH_MAX];
-
- snprintf(path, sizeof(path), "%s/cpu%d/cpufreq/cpuinfo_cur_freq",
- sys_cpu_dir, rte_get_master_lcore());
- if (eal_parse_sysfs_value(path, &cpu_hz) < 0)
- RTE_LOG(WARNING, EAL, "Unable to parse %s\n", path);
-
- return cpu_hz*1000;
+ return 0;
}
--
1.9.1
[dpdk-dev] [PATCH v2] eal/ppc: fix compilation error with a broken else clause
From: Gowrishankar Muthukrishnan
Calling rte_smp_{w/r}mb macro expands into a compound block, which
would break compiling a else clause following it, if that calling
place has been terminated already with ";", as in below code.
This patch adds { } around this macro to allow compiling else too.
Fixes: d23a6bd04d ("eal/ppc: fix memory barrier for IBM POWER")
Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power")
Signed-off-by: Gowrishankar Muthukrishnan
---
v2:
fixed ppc_64 atomic defines for a below error.
In file included from /tmp/dpdk/lib/librte_ring/rte_ring.h:372:0,
from /tmp/dpdk/lib/librte_ring/rte_ring.c:90:
/tmp/dpdk/lib/librte_ring/rte_ring_generic.h: In function ???update_tail???:
/tmp/dpdk/lib/librte_ring/rte_ring_generic.h:75:2: error: ???else??? without a
previous ???if???
else
^~~~
/tmp/dpdk/mk/internal/rte.compile-pre.mk:114: recipe for target 'rte_ring.o'
failed
lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index f38618f..39fce7b 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -64,9 +64,9 @@
* occur before the STORE operations generated after.
*/
#ifdef RTE_ARCH_64
-#definerte_wmb() {asm volatile("lwsync" : : : "memory"); }
+#definerte_wmb() asm volatile("lwsync" : : : "memory")
#else
-#definerte_wmb() {asm volatile("sync" : : : "memory"); }
+#definerte_wmb() asm volatile("sync" : : : "memory")
#endif
/**
@@ -76,9 +76,9 @@
* occur before the LOAD operations generated after.
*/
#ifdef RTE_ARCH_64
-#definerte_rmb() {asm volatile("lwsync" : : : "memory"); }
+#definerte_rmb() asm volatile("lwsync" : : : "memory")
#else
-#definerte_rmb() {asm volatile("sync" : : : "memory"); }
+#definerte_rmb() asm volatile("sync" : : : "memory")
#endif
#define rte_smp_mb() rte_mb()
--
1.9.1
[dpdk-dev] [PATCH] eal/ppc: fix rte_smp_mb for a compilation error with else clause
From: Gowrishankar Muthukrishnan
This patch fixes the compilation problem with rte_smp_mb,
when there is else clause following it, as in test_barrier.c.
Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power")
Cc: sta...@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan
---
lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index 39fce7b..1821774 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -55,7 +55,7 @@
* Guarantees that the LOAD and STORE operations generated before the
* barrier occur before the LOAD and STORE operations generated after.
*/
-#definerte_mb() {asm volatile("sync" : : : "memory"); }
+#definerte_mb() asm volatile("sync" : : : "memory")
/**
* Write memory barrier.
--
1.9.1
[dpdk-dev] [PATCH] net/bonding: avoid wrong casting on primary_slave_port_id from input param
From: Gowrishankar Muthukrishnan
primary_slave_port_id is uint16_t which needs to be correctly stored
with the same data type of input parameter in bond_ethdev_configure.
Fixes: f8244c6399 ("ethdev: increase port id range")
Cc: sta...@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan
---
In powerpc, creating bond pmd results in below error due to wrong
cast on input param. This is reproducible, only when using shared
libraries.
sudo -E LD_LIBRARY_PATH=$PWD/$RTE_TARGET/lib $RTE_TARGET/app/testpmd \
-l 0,8 --socket-mem=1024,1024 \
--vdev 'net_tap0,iface=dpdktap0' --vdev 'net_tap1,iface=dpdktap1' \
--vdev 'net_bonding0,mode=1,slave=0,slave=1,primary=0,socket_id=1' \
-d $RTE_TARGET/lib/librte_pmd_tap.so \
-d $RTE_TARGET/lib/librte_mempool_ring.so -- --forward-mode=rxonly
Configuring Port 0 (socket 0)
PMD: net_tap0: 0x70a854070280: TX configured queues number: 1
PMD: net_tap0: 0x70a854070280: RX configured queues number: 1
Port 0: 86:EA:6D:52:3E:DB
Configuring Port 1 (socket 0)
PMD: net_tap1: 0x70a854074300: TX configured queues number: 1
PMD: net_tap1: 0x70a854074300: RX configured queues number: 1
Port 1: 42:9A:B8:49:B6:00
Configuring Port 2 (socket 1)
EAL: Failed to set primary slave port 7424 on bonded device net_bonding0
Fail to configure port 2
EAL: Error - exiting with code: 1
Cause: Start ports failed
drivers/net/bonding/rte_eth_bond_args.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/bonding/rte_eth_bond_args.c
b/drivers/net/bonding/rte_eth_bond_args.c
index 27d3101..e99681e 100644
--- a/drivers/net/bonding/rte_eth_bond_args.c
+++ b/drivers/net/bonding/rte_eth_bond_args.c
@@ -244,7 +244,7 @@
if (primary_slave_port_id < 0)
return -1;
- *(uint8_t *)extra_args = (uint8_t)primary_slave_port_id;
+ *(uint16_t *)extra_args = (uint16_t)primary_slave_port_id;
return 0;
}
--
1.9.1
[dpdk-dev] linking error with dpdk
On Saturday 18 June 2016 01:13 PM, Raja Jayapal wrote: > Hi All, > > I am trying to install dpdk with ovs, but am getting the linking errors. > Downloaded and tried with dpdk 2.0/2.2/16.04 and latest ovs. > > DPDK : wget http://dpdk.org/browse/dpdk/snapshot/dpdk-2.0.0.tar.gz and wget > http://dpdk.org/browse/dpdk/snapshot/dpdk-2.2.0.tar.gz > OVS : git clone https://github.com/openvswitch/ovs.git > > ./configure --with-dpdk=/home/ubuntu/raja2/dpdk-2.2.0 > - - - - - - - > checking target hint for cgcc... x86_64 > checking whether make has GNU make $(if) extension... yes > checking whether dpdk datapath is enabled... yes > checking for /home/ubuntu/raja2/dpdk-2.2.0/include/rte_config.h... no > checking for /home/ubuntu/raja2/dpdk-2.2.0/include/dpdk/rte_config.h... no > configure: error: Could not find DPDK libraries in > /home/ubuntu/raja2/dpdk-2.2.0/lib You need to have CONFIG_RTE_BUILD_COMBINE_LIBS=y if you are trying dpdk-2.2.0 or less. As Ferruh replied earlier, refer to dpdk version what INSTALL.DPDK.md suggests. Thanks, Gowrishankar > ./configure --prefix=/usr --sysconfdir=/etc --localstatedir=/var > --with-dpdk=/home/ubuntu/raja1/dpdk-2.0.0/x86_64-native-linuxapp-gcc/ > --enable-ssl > - - - - - - - - - - > checking whether gcc -std=gnu99 accepts -Wno-unused-parameter... yes > checking target hint for cgcc... x86_64 > checking whether make has GNU make $(if) extension... yes > checking whether dpdk datapath is enabled... yes > checking for > /home/ubuntu/raja1/dpdk-2.0.0/x86_64-native-linuxapp-gcc//include/rte_config.h... > yes > configure: error: Could not find DPDK libraries in > /home/ubuntu/raja1/dpdk-2.0.0/x86_64-native-linuxapp-gcc//lib > ubuntu at 01HW462422:~/raja1/ovs$ > > Installed dpdk successfully, but when i build ovs with dpdk i am getting the > linking error in all the three versions of dpdk. > Is there any specific version in which the dpdk-ovs will only work, if so > please let me know. > > Thanks, > Raja > =-=-= > Notice: The information contained in this e-mail > message and/or attachments to it may contain > confidential or privileged information. If you are > not the intended recipient, any dissemination, use, > review, distribution, printing or copying of the > information contained in this e-mail message > and/or attachments to it are strictly prohibited. If > you have received this communication in error, > please notify us by reply e-mail or telephone and > immediately and permanently delete the message > and any attachments. Thank you > > >
[dpdk-dev] [PATCH] eal/ppc: fix secondary process to map hugepages in correct order
From: Gowri Shankar
For a secondary process address space to map hugepages from every segment of
primary process, hugepage_file entries has to be mapped reversely from the
list that primary process updated for every segment. This is for a reason that,
in ppc64, hugepages are sorted for decrementing addresses.
Signed-off-by: Gowrishankar
---
lib/librte_eal/linuxapp/eal/eal_memory.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/lib/librte_eal/linuxapp/eal/eal_memory.c
b/lib/librte_eal/linuxapp/eal/eal_memory.c
index 5b9132c..6aea5d0 100644
--- a/lib/librte_eal/linuxapp/eal/eal_memory.c
+++ b/lib/librte_eal/linuxapp/eal/eal_memory.c
@@ -1400,7 +1400,7 @@ rte_eal_hugepage_attach(void)
{
const struct rte_mem_config *mcfg =
rte_eal_get_configuration()->mem_config;
const struct hugepage_file *hp = NULL;
- unsigned num_hp = 0;
+ unsigned num_hp = 0, mapped_hp = 0;
unsigned i, s = 0; /* s used to track the segment number */
off_t size;
int fd, fd_zero = -1, fd_hugepage = -1;
@@ -1486,14 +1486,12 @@ rte_eal_hugepage_attach(void)
goto error;
}
- num_hp = size / sizeof(struct hugepage_file);
- RTE_LOG(DEBUG, EAL, "Analysing %u files\n", num_hp);
-
s = 0;
while (s < RTE_MAX_MEMSEG && mcfg->memseg[s].len > 0){
void *addr, *base_addr;
uintptr_t offset = 0;
size_t mapping_size;
+ unsigned int index;
#ifdef RTE_LIBRTE_IVSHMEM
/*
* if segment has ioremap address set, it's an IVSHMEM segment
and
@@ -1504,6 +1502,8 @@ rte_eal_hugepage_attach(void)
continue;
}
#endif
+ num_hp = mcfg->memseg[s].len / mcfg->memseg[s].hugepage_sz;
+ RTE_LOG(DEBUG, EAL, "Analysing %u files in segment %u\n",
num_hp, s);
/*
* free previously mapped memory so we can map the
* hugepages into the space
@@ -1514,18 +1514,23 @@ rte_eal_hugepage_attach(void)
/* find the hugepages for this segment and map them
* we don't need to worry about order, as the server sorted the
* entries before it did the second mmap of them */
+#ifdef RTE_ARCH_PPC_64
+ for (i = num_hp-1; i < num_hp && offset < mcfg->memseg[s].len;
i--){
+#else
for (i = 0; i < num_hp && offset < mcfg->memseg[s].len; i++){
- if (hp[i].memseg_id == (int)s){
- fd = open(hp[i].filepath, O_RDWR);
+#endif
+ index = i + mapped_hp;
+ if (hp[index].memseg_id == (int)s){
+ fd = open(hp[index].filepath, O_RDWR);
if (fd < 0) {
RTE_LOG(ERR, EAL, "Could not open %s\n",
- hp[i].filepath);
+ hp[index].filepath);
goto error;
}
#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS
- mapping_size = hp[i].size * hp[i].repeated;
+ mapping_size = hp[index].size *
hp[index].repeated;
#else
- mapping_size = hp[i].size;
+ mapping_size = hp[index].size;
#endif
addr = mmap(RTE_PTR_ADD(base_addr, offset),
mapping_size, PROT_READ |
PROT_WRITE,
@@ -1534,7 +1539,7 @@ rte_eal_hugepage_attach(void)
if (addr == MAP_FAILED ||
addr != RTE_PTR_ADD(base_addr,
offset)) {
RTE_LOG(ERR, EAL, "Could not mmap %s\n",
- hp[i].filepath);
+ hp[index].filepath);
goto error;
}
offset+=mapping_size;
@@ -1543,6 +1548,7 @@ rte_eal_hugepage_attach(void)
RTE_LOG(DEBUG, EAL, "Mapped segment %u of size 0x%llx\n", s,
(unsigned long long)mcfg->memseg[s].len);
s++;
+ mapped_hp += num_hp;
}
/* unmap the hugepage config file, since we are done using it */
munmap((void *)(uintptr_t)hp, size);
--
1.7.10.4
[dpdk-dev] [PATCH 1/6] config: enable lpm, port, table, pipeline, acl, sched libraries for ppc64le
From: gowrishankar In this patch, DPDK libraries such as LPM, port, table, pipeline, ACL, and sched are enabled for ppc64le. Signed-off-by: Gowrishankar --- config/defconfig_ppc_64-power8-linuxapp-gcc | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index 9eb0cc4..02d15bc 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -57,9 +57,9 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n CONFIG_RTE_LIBRTE_FM10K_PMD=n # This following libraries are not available on Power. So they're turned off. -CONFIG_RTE_LIBRTE_LPM=n -CONFIG_RTE_LIBRTE_ACL=n -CONFIG_RTE_LIBRTE_SCHED=n -CONFIG_RTE_LIBRTE_PORT=n -CONFIG_RTE_LIBRTE_TABLE=n -CONFIG_RTE_LIBRTE_PIPELINE=n +CONFIG_RTE_LIBRTE_LPM=y +CONFIG_RTE_LIBRTE_ACL=y +CONFIG_RTE_LIBRTE_SCHED=y +CONFIG_RTE_LIBRTE_PORT=y +CONFIG_RTE_LIBRTE_TABLE=y +CONFIG_RTE_LIBRTE_PIPELINE=y -- 1.9.1
[dpdk-dev] [PATCH 0/6] enable lpm, acl and other missing libraries in ppc64le
This patchset enables LPM, ACL and other few missing libs in ppc64le and also address few patches in related examples (ip_pipeline and l3fwd). Test report: LPM autotest test results as below. RTE>>lpm_autotest No. routes = 1076806 Route distribution per prefix width: DEPTHQUANTITY (PERCENT) --- 01 0 (0.00) 02 0 (0.00) 03 1 (0.00) 04 0 (0.00) 05 3 (0.00) 06 2 (0.00) 07 4 (0.00) 08201 (0.02) 09 37 (0.00) 10 55 (0.01) 11 97 (0.01) 12381 (0.04) 13775 (0.07) 14 2104 (0.20) 15 3712 (0.34) 16 69319 (6.44) 17 12983 (1.21) 18 23667 (2.20) 19 69068 (6.41) 20 62354 (5.79) 21 48531 (4.51) 22 72355 (6.72) 23 85427 (7.93) 24 583900 (54.23) 25 2654 (0.25) 26 5650 (0.52) 27 6467 (0.60) 28 7127 (0.66) 29 12936 (1.20) 30 5999 (0.56) 31 13 (0.00) 32984 (0.09) Unique added entries = 1039948 Used table 24 entries = 11343198 (67.6107%) 64 byte Cache entries used = 360735 (23087040 bytes) Average LPM Add: 110766 cycles Average LPM Lookup: 34.5 cycles (fails = 19.3%) BULK LPM Lookup: 31.5 cycles (fails = 19.3%) LPM LookupX4: 29.5 cycles (fails = 19.3%) Average LPM Delete: 63813.8 cycles Test OK RTE>> ACL autotest test results as below: .. ... ACL: trie 0: number of rules: 17, indexes: 4 ACL: trie 1: number of rules: 10, indexes: 5 ACL: Gen phase for ACL "acl_ctx": runtime memory footprint on socket -1: single nodes/bytes used: 8822/70576 quad nodes/vectors/bytes used: 12788/53374/426992 DFA nodes/group64/bytes used: 2175/4359/2233864 match nodes/bytes used: 24100/3084800 total: 5818432 bytes max limit: 18446744073709551615 bytes ACL: Build phase for ACL "acl_ctx": node limit for tree split: 16384 nodes created: 47885 memory consumed: 100663380 ACL: trie 0: number of rules: 22, indexes: 5 ACL: trie 1: number of rules: 5, indexes: 5 Test OK RTE>> Thanks.
[dpdk-dev] [PATCH 1/6] config: enable lpm, port, table, pipeline, acl, sched libraries for ppc64le
From: gowrishankar In this patch, DPDK libraries such as LPM, port, table, pipeline, ACL, and sched are enabled for ppc64le. Signed-off-by: Gowrishankar --- config/defconfig_ppc_64-power8-linuxapp-gcc | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index 9eb0cc4..02d15bc 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -57,9 +57,9 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n CONFIG_RTE_LIBRTE_FM10K_PMD=n # This following libraries are not available on Power. So they're turned off. -CONFIG_RTE_LIBRTE_LPM=n -CONFIG_RTE_LIBRTE_ACL=n -CONFIG_RTE_LIBRTE_SCHED=n -CONFIG_RTE_LIBRTE_PORT=n -CONFIG_RTE_LIBRTE_TABLE=n -CONFIG_RTE_LIBRTE_PIPELINE=n +CONFIG_RTE_LIBRTE_LPM=y +CONFIG_RTE_LIBRTE_ACL=y +CONFIG_RTE_LIBRTE_SCHED=y +CONFIG_RTE_LIBRTE_PORT=y +CONFIG_RTE_LIBRTE_TABLE=y +CONFIG_RTE_LIBRTE_PIPELINE=y -- 1.9.1
[dpdk-dev] [PATCH 2/6] lpm: add altivec intrinsics for dpdk lpm on ppc_64
From: gowrishankar
This patch adds ppc64le port for LPM library in DPDK.
Signed-off-by: Gowrishankar
---
app/test/test_xmmt_ops.h | 16 +++
.../common/include/arch/ppc_64/rte_vect.h | 60
lib/librte_lpm/Makefile| 2 +
lib/librte_lpm/rte_lpm.h | 2 +
lib/librte_lpm/rte_lpm_altivec.h | 154 +
5 files changed, 234 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
create mode 100644 lib/librte_lpm/rte_lpm_altivec.h
diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
index de9c16f..42174d2 100644
--- a/app/test/test_xmmt_ops.h
+++ b/app/test/test_xmmt_ops.h
@@ -62,6 +62,22 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
#define vect_set_epi32(i3, i2, i1, i0) _mm_set_epi32(i3, i2, i1, i0)
+#elif defined(RTE_ARCH_PPC_64)
+
+/* vect_* abstraction implementation using ALTIVEC */
+
+/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
+#define vect_loadu_sil128(p) vec_ld(0, p)
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static inline xmm_t __attribute__((always_inline))
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+ xmm_t data = (xmm_t){i0, i1, i2, i3};
+
+ return data;
+}
+
#endif
#endif /* _TEST_XMMT_OPS_H_ */
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
b/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
new file mode 100644
index 000..05209e5
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
@@ -0,0 +1,60 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) IBM Corporation 2016.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of IBM Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_VECT_PPC_64_H_
+#define _RTE_VECT_PPC_64_H_
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef vector signed int xmm_t;
+
+#defineXMM_SIZE(sizeof(xmm_t))
+#defineXMM_MASK(XMM_SIZE - 1)
+
+typedef union rte_xmm {
+ xmm_tx;
+ uint8_t u8[XMM_SIZE / sizeof(uint8_t)];
+ uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
+ uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
+ uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
+ double pd[XMM_SIZE / sizeof(double)];
+} __attribute__((aligned(16))) rte_xmm_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_VECT_PPC_64_H_ */
diff --git a/lib/librte_lpm/Makefile b/lib/librte_lpm/Makefile
index 656ade2..3dc549d 100644
--- a/lib/librte_lpm/Makefile
+++ b/lib/librte_lpm/Makefile
@@ -51,6 +51,8 @@ ifneq ($(filter y,$(CONFIG_RTE_ARCH_ARM)
$(CONFIG_RTE_ARCH_ARM64)),)
SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include += rte_lpm_neon.h
else ifeq ($(CONFIG_RTE_ARCH_X86),y)
SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include += rte_lpm_sse.h
+else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y)
+SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include += rte_lpm_altivec.h
endif
# this lib needs eal
diff --git a/lib/librte_lpm/rte_lpm.h b/lib/librte_lpm/rte_lpm.h
index 2df1d67..dbe5483 100644
--- a/lib/librte_lpm/rte_lpm.h
+++ b/lib/librte_lpm/rte_lpm.h
@@ -480,6 +480,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip,
uint32_t hop[4],
#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64)
#include "rte_lpm_neon.h"
+#elif defined(RTE_ARCH_PPC_64
[dpdk-dev] [PATCH 3/6] acl: add altivec intrinsics for dpdk acl on ppc_64
From: gowrishankar
This patch adds port for ACL library in ppc64le.
Signed-off-by: Gowrishankar
---
app/test-acl/main.c | 4 +
lib/librte_acl/Makefile | 2 +
lib/librte_acl/acl.h | 4 +
lib/librte_acl/acl_run.h | 2 +
lib/librte_acl/acl_run_altivec.c | 47 ++
lib/librte_acl/acl_run_altivec.h | 328 +++
lib/librte_acl/rte_acl.c | 13 ++
lib/librte_acl/rte_acl.h | 1 +
8 files changed, 401 insertions(+)
create mode 100644 lib/librte_acl/acl_run_altivec.c
create mode 100644 lib/librte_acl/acl_run_altivec.h
diff --git a/app/test-acl/main.c b/app/test-acl/main.c
index 0b0c093..3bee0de 100644
--- a/app/test-acl/main.c
+++ b/app/test-acl/main.c
@@ -105,6 +105,10 @@ static const struct acl_alg acl_alg[] = {
.name = "neon",
.alg = RTE_ACL_CLASSIFY_NEON,
},
+ {
+ .name = "altivec",
+ .alg = RTE_ACL_CLASSIFY_ALTIVEC,
+ },
};
static struct {
diff --git a/lib/librte_acl/Makefile b/lib/librte_acl/Makefile
index 2e394c9..6810552 100644
--- a/lib/librte_acl/Makefile
+++ b/lib/librte_acl/Makefile
@@ -52,6 +52,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_scalar.c
ifneq ($(filter y,$(CONFIG_RTE_ARCH_ARM) $(CONFIG_RTE_ARCH_ARM64)),)
SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_neon.c
CFLAGS_acl_run_neon.o += -flax-vector-conversions -Wno-maybe-uninitialized
+else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y)
+SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_altivec.c
else
SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c
#check if flag for SSE4.1 is already on, if not set it up manually
diff --git a/lib/librte_acl/acl.h b/lib/librte_acl/acl.h
index 09d6784..6664a55 100644
--- a/lib/librte_acl/acl.h
+++ b/lib/librte_acl/acl.h
@@ -234,6 +234,10 @@ int
rte_acl_classify_neon(const struct rte_acl_ctx *ctx, const uint8_t **data,
uint32_t *results, uint32_t num, uint32_t categories);
+int
+rte_acl_classify_altivec(const struct rte_acl_ctx *ctx, const uint8_t **data,
+ uint32_t *results, uint32_t num, uint32_t categories);
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/lib/librte_acl/acl_run.h b/lib/librte_acl/acl_run.h
index b2fc42c..024f393 100644
--- a/lib/librte_acl/acl_run.h
+++ b/lib/librte_acl/acl_run.h
@@ -39,7 +39,9 @@
#define MAX_SEARCHES_AVX16 16
#define MAX_SEARCHES_SSE8 8
+#define MAX_SEARCHES_ALTIVEC8 8
#define MAX_SEARCHES_SSE4 4
+#define MAX_SEARCHES_ALTIVEC4 4
#define MAX_SEARCHES_SCALAR2
#define GET_NEXT_4BYTES(prm, idx) \
diff --git a/lib/librte_acl/acl_run_altivec.c b/lib/librte_acl/acl_run_altivec.c
new file mode 100644
index 000..3523526
--- /dev/null
+++ b/lib/librte_acl/acl_run_altivec.c
@@ -0,0 +1,47 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright (C) IBM Corporation 2016.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "acl_run_altivec.h"
+
+int
+rte_acl_classify_altivec(const struct rte_acl_ctx *ctx, const uint8_t **data,
+ uint32_t *results, uint32_t num, uint32_t categories)
+{
+ if (likely(num >= MAX_SEARCHES_ALTIVEC8))
+ return search_altivec_8(ctx, data, results, num, categories);
+ else if (num >= MAX_SEARCHES_ALTIVEC4)
+ return search_altivec_4(ctx, data, results, num, categories);
+ else
+
[dpdk-dev] [PATCH 4/6] table: cache align rte_bucket_4_8
From: gowrishankar
Align rte_bucket_4_8 for cache line.
Signed-off-by: Gowrishankar
---
lib/librte_table/rte_table_hash_key8.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/librte_table/rte_table_hash_key8.c
b/lib/librte_table/rte_table_hash_key8.c
index e2e2bdc..4d5e0cd 100644
--- a/lib/librte_table/rte_table_hash_key8.c
+++ b/lib/librte_table/rte_table_hash_key8.c
@@ -68,7 +68,7 @@ struct rte_bucket_4_8 {
uint64_t key[4];
/* Cache line 1 */
- uint8_t data[0];
+ uint8_t data[0] __rte_cache_aligned;
};
struct rte_table_hash {
--
1.9.1
[dpdk-dev] [PATCH 5/6] ip_pipeline: fix lcore mapping for varying SMT threads as in ppc64
From: gowrishankar
offline lcore would still refer to original core id and this has to
be considered while creating cpu core mask.
Signed-off-by: Gowrishankar
---
examples/ip_pipeline/cpu_core_map.c | 12 +---
examples/ip_pipeline/init.c | 4
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/examples/ip_pipeline/cpu_core_map.c
b/examples/ip_pipeline/cpu_core_map.c
index cb088b1..482e68e 100644
--- a/examples/ip_pipeline/cpu_core_map.c
+++ b/examples/ip_pipeline/cpu_core_map.c
@@ -351,9 +351,6 @@ cpu_core_map_compute_linux(struct cpu_core_map *map)
int lcore_socket_id =
cpu_core_map_get_socket_id_linux(lcore_id);
- if (lcore_socket_id < 0)
- return -1;
-
if (((uint32_t) lcore_socket_id) == socket_id)
n_detected++;
}
@@ -368,18 +365,11 @@ cpu_core_map_compute_linux(struct cpu_core_map *map)
cpu_core_map_get_socket_id_linux(
lcore_id);
- if (lcore_socket_id < 0)
- return -1;
-
int lcore_core_id =
cpu_core_map_get_core_id_linux(
lcore_id);
- if (lcore_core_id < 0)
- return -1;
-
- if (((uint32_t) lcore_socket_id == socket_id) &&
- ((uint32_t) lcore_core_id == core_id)) {
+ if ((uint32_t) lcore_socket_id == socket_id) {
uint32_t pos = cpu_core_map_pos(map,
socket_id,
core_id_contig,
diff --git a/examples/ip_pipeline/init.c b/examples/ip_pipeline/init.c
index 83422e8..4acd38c 100644
--- a/examples/ip_pipeline/init.c
+++ b/examples/ip_pipeline/init.c
@@ -59,7 +59,11 @@ static void
app_init_core_map(struct app_params *app)
{
APP_LOG(app, HIGH, "Initializing CPU core map ...");
+#if defined(RTE_ARCH_PPC_64)
+ app->core_map = cpu_core_map_init(2, 5, 1, 0);
+#else
app->core_map = cpu_core_map_init(4, 32, 4, 0);
+#endif
if (app->core_map == NULL)
rte_panic("Cannot create CPU core map\n");
--
1.9.1
[dpdk-dev] [PATCH 6/6] l3fwd: add altivec support for em_hash_key
From: gowrishankar
This patch adds ppc64le port for em_mask_key function.
Signed-off-by: Gowrishankar
---
examples/l3fwd/l3fwd_em.c | 8
1 file changed, 8 insertions(+)
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index fc59243..3e261d1 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -259,6 +259,14 @@ em_mask_key(void *key, xmm_t mask)
return vandq_s32(data, mask);
}
+#elif defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+ xmm_t data = vec_ld(0, (xmm_t *)(key));
+
+ return vec_and(data, mask);
+}
#endif
static inline uint8_t
--
1.9.1
[dpdk-dev] [PATCH 1/6] config: enable lpm, port, table, pipeline, acl, sched libraries for ppc64le
Hi Thomas, On Friday 08 July 2016 06:27 PM, Thomas Monjalon wrote: > The comment and these lines can be removed and rely on default > enabling in config/common_base. I suggest to enable (remove disabling) > a feature at a time in the patch fixing the feature for PPC. Sure. So, do you suggest to send individual patchset (or patch) for each feature being enabled, one by one ?. Thanks, Gowrishankar
[dpdk-dev] [PATCH v2 0/6] enable lpm, acl and other missing libraries in ppc64le
From: gowrishankar This patchset enables LPM, ACL and other few missing libs in ppc64le and also address few patches in related examples (ip_pipeline and l3fwd). Test report: LPM and ACL unit tests verified as in patch set v1. Same results as before observed. v2 changes: - enabling libs in config included as part of lib changes itself. gowrishankar (6): lpm: add altivec intrinsics for dpdk lpm on ppc_64 acl: add altivec intrinsics for dpdk acl on ppc_64 ip_pipeline: fix lcore mapping for varying SMT threads as in ppc64 table: cache align rte_bucket_4_8 sched: enable sched library for ppc64le l3fwd: add altivec support for em_hash_key app/test-acl/main.c| 4 + app/test/test_xmmt_ops.h | 16 + config/defconfig_ppc_64-power8-linuxapp-gcc| 7 - examples/ip_pipeline/cpu_core_map.c| 12 +- examples/ip_pipeline/init.c| 4 + examples/l3fwd/l3fwd_em.c | 8 + lib/librte_acl/Makefile| 2 + lib/librte_acl/acl.h | 4 + lib/librte_acl/acl_run.h | 2 + lib/librte_acl/acl_run_altivec.c | 47 +++ lib/librte_acl/acl_run_altivec.h | 328 + lib/librte_acl/rte_acl.c | 13 + lib/librte_acl/rte_acl.h | 1 + .../common/include/arch/ppc_64/rte_vect.h | 60 lib/librte_lpm/Makefile| 2 + lib/librte_lpm/rte_lpm.h | 2 + lib/librte_lpm/rte_lpm_altivec.h | 154 ++ lib/librte_table/rte_table_hash_key8.c | 2 +- 18 files changed, 649 insertions(+), 19 deletions(-) create mode 100644 lib/librte_acl/acl_run_altivec.c create mode 100644 lib/librte_acl/acl_run_altivec.h create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_vect.h create mode 100644 lib/librte_lpm/rte_lpm_altivec.h -- 1.9.1
[dpdk-dev] [PATCH v2 1/6] lpm: add altivec intrinsics for dpdk lpm on ppc_64
From: gowrishankar
This patch adds ppc64le port for LPM library in DPDK.
Signed-off-by: Gowrishankar
---
app/test/test_xmmt_ops.h | 16 +++
config/defconfig_ppc_64-power8-linuxapp-gcc| 1 -
.../common/include/arch/ppc_64/rte_vect.h | 60
lib/librte_lpm/Makefile| 2 +
lib/librte_lpm/rte_lpm.h | 2 +
lib/librte_lpm/rte_lpm_altivec.h | 154 +
6 files changed, 234 insertions(+), 1 deletion(-)
create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
create mode 100644 lib/librte_lpm/rte_lpm_altivec.h
diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
index de9c16f..42174d2 100644
--- a/app/test/test_xmmt_ops.h
+++ b/app/test/test_xmmt_ops.h
@@ -62,6 +62,22 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
#define vect_set_epi32(i3, i2, i1, i0) _mm_set_epi32(i3, i2, i1, i0)
+#elif defined(RTE_ARCH_PPC_64)
+
+/* vect_* abstraction implementation using ALTIVEC */
+
+/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
+#define vect_loadu_sil128(p) vec_ld(0, p)
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static inline xmm_t __attribute__((always_inline))
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+ xmm_t data = (xmm_t){i0, i1, i2, i3};
+
+ return data;
+}
+
#endif
#endif /* _TEST_XMMT_OPS_H_ */
diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc
b/config/defconfig_ppc_64-power8-linuxapp-gcc
index 9eb0cc4..211ef18 100644
--- a/config/defconfig_ppc_64-power8-linuxapp-gcc
+++ b/config/defconfig_ppc_64-power8-linuxapp-gcc
@@ -57,7 +57,6 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n
CONFIG_RTE_LIBRTE_FM10K_PMD=n
# This following libraries are not available on Power. So they're turned off.
-CONFIG_RTE_LIBRTE_LPM=n
CONFIG_RTE_LIBRTE_ACL=n
CONFIG_RTE_LIBRTE_SCHED=n
CONFIG_RTE_LIBRTE_PORT=n
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
b/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
new file mode 100644
index 000..05209e5
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
@@ -0,0 +1,60 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) IBM Corporation 2016.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of IBM Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_VECT_PPC_64_H_
+#define _RTE_VECT_PPC_64_H_
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef vector signed int xmm_t;
+
+#defineXMM_SIZE(sizeof(xmm_t))
+#defineXMM_MASK(XMM_SIZE - 1)
+
+typedef union rte_xmm {
+ xmm_tx;
+ uint8_t u8[XMM_SIZE / sizeof(uint8_t)];
+ uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
+ uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
+ uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
+ double pd[XMM_SIZE / sizeof(double)];
+} __attribute__((aligned(16))) rte_xmm_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_VECT_PPC_64_H_ */
diff --git a/lib/librte_lpm/Makefile b/lib/librte_lpm/Makefile
index 656ade2..3dc549d 100644
--- a/lib/librte_lpm/Makefile
+++ b/lib/librte_lpm/Makefile
@@ -51,6 +51,8 @@ ifneq ($(filter y,$(CONFIG_RTE_ARCH_ARM)
$(CONFIG_RTE_ARCH_ARM64)),)
SYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include += rte_lpm_neon.h
else ifeq ($(CONFIG_
[dpdk-dev] [PATCH v2 2/6] acl: add altivec intrinsics for dpdk acl on ppc_64
From: gowrishankar
This patch adds port for ACL library in ppc64le.
Signed-off-by: Gowrishankar
---
app/test-acl/main.c | 4 +
config/defconfig_ppc_64-power8-linuxapp-gcc | 1 -
lib/librte_acl/Makefile | 2 +
lib/librte_acl/acl.h| 4 +
lib/librte_acl/acl_run.h| 2 +
lib/librte_acl/acl_run_altivec.c| 47
lib/librte_acl/acl_run_altivec.h| 328
lib/librte_acl/rte_acl.c| 13 ++
lib/librte_acl/rte_acl.h| 1 +
9 files changed, 401 insertions(+), 1 deletion(-)
create mode 100644 lib/librte_acl/acl_run_altivec.c
create mode 100644 lib/librte_acl/acl_run_altivec.h
diff --git a/app/test-acl/main.c b/app/test-acl/main.c
index 0b0c093..3bee0de 100644
--- a/app/test-acl/main.c
+++ b/app/test-acl/main.c
@@ -105,6 +105,10 @@ static const struct acl_alg acl_alg[] = {
.name = "neon",
.alg = RTE_ACL_CLASSIFY_NEON,
},
+ {
+ .name = "altivec",
+ .alg = RTE_ACL_CLASSIFY_ALTIVEC,
+ },
};
static struct {
diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc
b/config/defconfig_ppc_64-power8-linuxapp-gcc
index 211ef18..2ae26d9 100644
--- a/config/defconfig_ppc_64-power8-linuxapp-gcc
+++ b/config/defconfig_ppc_64-power8-linuxapp-gcc
@@ -57,7 +57,6 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n
CONFIG_RTE_LIBRTE_FM10K_PMD=n
# This following libraries are not available on Power. So they're turned off.
-CONFIG_RTE_LIBRTE_ACL=n
CONFIG_RTE_LIBRTE_SCHED=n
CONFIG_RTE_LIBRTE_PORT=n
CONFIG_RTE_LIBRTE_TABLE=n
diff --git a/lib/librte_acl/Makefile b/lib/librte_acl/Makefile
index 2e394c9..6810552 100644
--- a/lib/librte_acl/Makefile
+++ b/lib/librte_acl/Makefile
@@ -52,6 +52,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_scalar.c
ifneq ($(filter y,$(CONFIG_RTE_ARCH_ARM) $(CONFIG_RTE_ARCH_ARM64)),)
SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_neon.c
CFLAGS_acl_run_neon.o += -flax-vector-conversions -Wno-maybe-uninitialized
+else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y)
+SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_altivec.c
else
SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c
#check if flag for SSE4.1 is already on, if not set it up manually
diff --git a/lib/librte_acl/acl.h b/lib/librte_acl/acl.h
index 09d6784..6664a55 100644
--- a/lib/librte_acl/acl.h
+++ b/lib/librte_acl/acl.h
@@ -234,6 +234,10 @@ int
rte_acl_classify_neon(const struct rte_acl_ctx *ctx, const uint8_t **data,
uint32_t *results, uint32_t num, uint32_t categories);
+int
+rte_acl_classify_altivec(const struct rte_acl_ctx *ctx, const uint8_t **data,
+ uint32_t *results, uint32_t num, uint32_t categories);
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/lib/librte_acl/acl_run.h b/lib/librte_acl/acl_run.h
index b2fc42c..024f393 100644
--- a/lib/librte_acl/acl_run.h
+++ b/lib/librte_acl/acl_run.h
@@ -39,7 +39,9 @@
#define MAX_SEARCHES_AVX16 16
#define MAX_SEARCHES_SSE8 8
+#define MAX_SEARCHES_ALTIVEC8 8
#define MAX_SEARCHES_SSE4 4
+#define MAX_SEARCHES_ALTIVEC4 4
#define MAX_SEARCHES_SCALAR2
#define GET_NEXT_4BYTES(prm, idx) \
diff --git a/lib/librte_acl/acl_run_altivec.c b/lib/librte_acl/acl_run_altivec.c
new file mode 100644
index 000..3523526
--- /dev/null
+++ b/lib/librte_acl/acl_run_altivec.c
@@ -0,0 +1,47 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright (C) IBM Corporation 2016.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
[dpdk-dev] [PATCH v2 3/6] ip_pipeline: fix lcore mapping for varying SMT threads as in ppc64
From: gowrishankar
offline lcore would still refer to original core id and this has to
be considered while creating cpu core mask.
Signed-off-by: Gowrishankar
---
config/defconfig_ppc_64-power8-linuxapp-gcc | 3 ---
examples/ip_pipeline/cpu_core_map.c | 12 +---
examples/ip_pipeline/init.c | 4
3 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc
b/config/defconfig_ppc_64-power8-linuxapp-gcc
index 2ae26d9..94f09a7 100644
--- a/config/defconfig_ppc_64-power8-linuxapp-gcc
+++ b/config/defconfig_ppc_64-power8-linuxapp-gcc
@@ -58,6 +58,3 @@ CONFIG_RTE_LIBRTE_FM10K_PMD=n
# This following libraries are not available on Power. So they're turned off.
CONFIG_RTE_LIBRTE_SCHED=n
-CONFIG_RTE_LIBRTE_PORT=n
-CONFIG_RTE_LIBRTE_TABLE=n
-CONFIG_RTE_LIBRTE_PIPELINE=n
diff --git a/examples/ip_pipeline/cpu_core_map.c
b/examples/ip_pipeline/cpu_core_map.c
index cb088b1..482e68e 100644
--- a/examples/ip_pipeline/cpu_core_map.c
+++ b/examples/ip_pipeline/cpu_core_map.c
@@ -351,9 +351,6 @@ cpu_core_map_compute_linux(struct cpu_core_map *map)
int lcore_socket_id =
cpu_core_map_get_socket_id_linux(lcore_id);
- if (lcore_socket_id < 0)
- return -1;
-
if (((uint32_t) lcore_socket_id) == socket_id)
n_detected++;
}
@@ -368,18 +365,11 @@ cpu_core_map_compute_linux(struct cpu_core_map *map)
cpu_core_map_get_socket_id_linux(
lcore_id);
- if (lcore_socket_id < 0)
- return -1;
-
int lcore_core_id =
cpu_core_map_get_core_id_linux(
lcore_id);
- if (lcore_core_id < 0)
- return -1;
-
- if (((uint32_t) lcore_socket_id == socket_id) &&
- ((uint32_t) lcore_core_id == core_id)) {
+ if ((uint32_t) lcore_socket_id == socket_id) {
uint32_t pos = cpu_core_map_pos(map,
socket_id,
core_id_contig,
diff --git a/examples/ip_pipeline/init.c b/examples/ip_pipeline/init.c
index 83422e8..4acd38c 100644
--- a/examples/ip_pipeline/init.c
+++ b/examples/ip_pipeline/init.c
@@ -59,7 +59,11 @@ static void
app_init_core_map(struct app_params *app)
{
APP_LOG(app, HIGH, "Initializing CPU core map ...");
+#if defined(RTE_ARCH_PPC_64)
+ app->core_map = cpu_core_map_init(2, 5, 1, 0);
+#else
app->core_map = cpu_core_map_init(4, 32, 4, 0);
+#endif
if (app->core_map == NULL)
rte_panic("Cannot create CPU core map\n");
--
1.9.1
[dpdk-dev] [PATCH v2 4/6] table: cache align rte_bucket_4_8
From: gowrishankar
Align rte_bucket_4_8 for cache line.
Signed-off-by: Gowrishankar
---
lib/librte_table/rte_table_hash_key8.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/librte_table/rte_table_hash_key8.c
b/lib/librte_table/rte_table_hash_key8.c
index e2e2bdc..4d5e0cd 100644
--- a/lib/librte_table/rte_table_hash_key8.c
+++ b/lib/librte_table/rte_table_hash_key8.c
@@ -68,7 +68,7 @@ struct rte_bucket_4_8 {
uint64_t key[4];
/* Cache line 1 */
- uint8_t data[0];
+ uint8_t data[0] __rte_cache_aligned;
};
struct rte_table_hash {
--
1.9.1
[dpdk-dev] [PATCH v2 6/6] l3fwd: add altivec support for em_hash_key
From: gowrishankar
This patch adds ppc64le port for em_mask_key function.
Signed-off-by: Gowrishankar
---
examples/l3fwd/l3fwd_em.c | 8
1 file changed, 8 insertions(+)
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index fc59243..3e261d1 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -259,6 +259,14 @@ em_mask_key(void *key, xmm_t mask)
return vandq_s32(data, mask);
}
+#elif defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+ xmm_t data = vec_ld(0, (xmm_t *)(key));
+
+ return vec_and(data, mask);
+}
#endif
static inline uint8_t
--
1.9.1
[dpdk-dev] [PATCH v2 5/6] sched: enable sched library for ppc64le
From: gowrishankar This patch enables librte_sched in ppc64le. Signed-off-by: Gowrishankar --- config/defconfig_ppc_64-power8-linuxapp-gcc | 2 -- 1 file changed, 2 deletions(-) diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index 94f09a7..bbd5568 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -56,5 +56,3 @@ CONFIG_RTE_LIBRTE_PMD_BOND=n CONFIG_RTE_LIBRTE_ENIC_PMD=n CONFIG_RTE_LIBRTE_FM10K_PMD=n -# This following libraries are not available on Power. So they're turned off. -CONFIG_RTE_LIBRTE_SCHED=n -- 1.9.1
[dpdk-dev] [PATCH v2 0/6] enable lpm, acl and other missing libraries in ppc64le
Hi Chao, On Monday 11 July 2016 02:25 PM, Chao Zhu wrote: > Gowrishankar, > > Nice patches! Do you have some function test result? I need some time to > verify the patches. Please find below lpm and acl units tests (Test OK at the end of each tests). # ./app/test < EAL/PMD logs> APP: HPET is not enabled, using TSC as default timer RTE>>lpm_autotest No. routes = 1076806 Route distribution per prefix width: DEPTHQUANTITY (PERCENT) --- 01 0 (0.00) 02 0 (0.00) 03 1 (0.00) 04 0 (0.00) 05 3 (0.00) 06 2 (0.00) 07 4 (0.00) 08201 (0.02) 09 37 (0.00) 10 55 (0.01) 11 97 (0.01) 12381 (0.04) 13775 (0.07) 14 2104 (0.20) 15 3712 (0.34) 16 69319 (6.44) 17 12983 (1.21) 18 23667 (2.20) 19 69068 (6.41) 20 62354 (5.79) 21 48531 (4.51) 22 72355 (6.72) 23 85427 (7.93) 24 583900 (54.23) 25 2654 (0.25) 26 5650 (0.52) 27 6467 (0.60) 28 7127 (0.66) 29 12936 (1.20) 30 5999 (0.56) 31 13 (0.00) 32984 (0.09) Unique added entries = 1039948 Used table 24 entries = 11343198 (67.6107%) 64 byte Cache entries used = 360735 (23087040 bytes) Average LPM Add: 110820 cycles Average LPM Lookup: 34.5 cycles (fails = 19.3%) BULK LPM Lookup: 31.5 cycles (fails = 19.3%) LPM LookupX4: 29.5 cycles (fails = 19.3%) Average LPM Delete: 63841.6 cycles Test OK RTE>>acl_autotest ACL: allocation of 25166728 bytes on socket 33 for ACL_acl_ctx failed ACL: rte_acl_add_rules(acl_ctx): rule #1 is invalid ACL: rte_acl_ipv4vlan_add_rules: rule #1 is invalid ACL: rte_acl_ipv4vlan_add_rules: rule #1 is invalid ACL: rte_acl_ipv4vlan_add_rules: rule #1 is invalid ACL: rte_acl_ipv4vlan_add_rules: rule #1 is invalid ACL: rte_acl_add_rules(acl_ctx): rule #1 is invalid ACL: Gen phase for ACL "acl_ctx": runtime memory footprint on socket -1: single nodes/bytes used: 0/0 quad nodes/vectors/bytes used: 0/0/0 DFA nodes/group64/bytes used: 1/4/4104 match nodes/bytes used: 1/128 total: 6432 bytes max limit: 18446744073709551615 bytes ACL: Build phase for ACL "acl_ctx": node limit for tree split: 2048 nodes created: 2 memory consumed: 8388615 ACL: trie 0: number of rules: 16, indexes: 1 ACL: Gen phase for ACL "acl_ctx": runtime memory footprint on socket -1: single nodes/bytes used: 22/176 quad nodes/vectors/bytes used: 30/104/832 DFA nodes/group64/bytes used: 6/19/11784 match nodes/bytes used: 6/768 total: 15760 bytes max limit: 18446744073709551615 bytes ACL: Build phase for ACL "acl_ctx": node limit for tree split: 2048 nodes created: 64 memory consumed: 8388615 ACL: trie 0: number of rules: 6000, indexes: 4 acl context @0x3efded3b3400 socket_id=-1 alg=5 max_rules=196608 rule_size=128 num_rules=0 num_categories=0 num_tries=0 acl context @0x3efded3b3400 socket_id=-1 alg=5 max_rules=196608 rule_size=128 num_rules=0 num_categories=0 num_tries=0 ACL: Gen phase for ACL "acl_ctx": runtime memory footprint on socket -1: single nodes/bytes used: 974/7792 quad nodes/vectors/bytes used: 816/3211/25688 DFA nodes/group64/bytes used: 137/289/150024 match nodes/bytes used: 1181/151168 total: 336880 bytes max limit: 18446744073709551615 bytes ACL: Build phase for ACL "acl_ctx": node limit for tree split: 2048 nodes created: 3108 memory consumed: 8388615 ACL: trie 0: number of rules: 15, indexes: 4 ACL: trie 1: number of rules: 12, indexes: 5 ACL: Gen phase for ACL "acl_ctx": runtime memory footprint on socket -1: single nodes/bytes used: 974/7792 quad nodes/vectors/bytes used: 816/3211/25688 DFA nodes/group64/bytes used: 137/289/150024 match nodes/bytes used: 1181/151168 total: 336880 bytes max limit: 18446744073709551615 bytes ACL: Build phase for ACL "acl_ctx": node limit for tree split: 2048 nodes created: 3108 memory consumed: 8388615 ACL: trie 0: number of rules: 15, indexes: 4 ACL: trie 1: number of rules: 12, indexes: 5 ACL: Build phase for ACL "acl_ctx": node limit for tree split: 2048 nodes created: 0 memory consumed: 8388615 ACL: Gen phase for ACL "acl_ctx": runtime memory footprint on socket -1: single nodes/bytes used: 974/7792 quad nodes/vectors/bytes used: 816/3211/25688 DFA nodes/group64/bytes used: 137/289/150024 match nodes/bytes used: 1181/151168 total: 336880 bytes max limit: 18446744073709551615 bytes ACL: Build phase for ACL "acl_ctx": node limit for tree split: 2048 nodes created: 3108 memory consumed: 8388615 ACL: trie 0: number of rules: 15, indexes: 4 ACL: trie 1: number of rules: 12, indexes: 5 ACL: Gen phase for ACL "acl_ctx": runtime memory footprint on socket -1: single nodes/bytes used: 974/7792
[dpdk-dev] [PATCH v2 0/6] enable lpm, acl and other missing libraries in ppc64le
Hi Chao,
I did not face this error. Even I verified today with tip of master
6596554... .
However I had patch conflict for examples/l3fwd/l3fwd_em.c which is
fixed now and v3 patch set sent recently. Could you please check.
Thanks,
Gowrishankar
On Friday 15 July 2016 08:45 AM, Chao Zhu wrote:
> Gowrishankar,
>
> When I tried the patches, I got some compilation error:
>
> In file included from
> /root/test/sub/dpdk/lib/librte_acl/acl_run_altivec.c:34:0:
> /root/test/sub/dpdk/lib/librte_acl/acl_run_altivec.h: In function
> 'transition4':
> /root/test/sub/dpdk/lib/librte_acl/acl_run_altivec.h:198:2: error:
> dereferencing type-punned pointer will break strict-aliasing rules
> [-Werror=strict-aliasing]
>*indices1 = (xmm_t){((uint32_t *)&v)[0], ((uint32_t *)&v)[1],
>^
> /root/test/sub/dpdk/lib/librte_acl/acl_run_altivec.h:202:2: error:
> dereferencing type-punned pointer will break strict-aliasing rules
> [-Werror=strict-aliasing]
>*indices2 = (xmm_t){((uint32_t *)&v)[0], ((uint32_t *)&v)[1],
>
> Can you help to take a look?
>
>
> -Original Message-
> From: Gowrishankar [mailto:gowrishankar.m at linux.vnet.ibm.com]
> Sent: 2016?7?10? 15:51
> To: dev at dpdk.org
> Cc: Chao Zhu ; Bruce Richardson
> ; Konstantin Ananyev
> ; Thomas Monjalon 6wind.com>;
> Cristian Dumitrescu ; Pradeep
> ; gowrishankar
> Subject: [PATCH v2 0/6] enable lpm, acl and other missing libraries in
> ppc64le
>
> From: gowrishankar
>
> This patchset enables LPM, ACL and other few missing libs in ppc64le and
> also address few patches in related examples (ip_pipeline and l3fwd).
>
> Test report:
> LPM and ACL unit tests verified as in patch set v1.
> Same results as before observed.
>
> v2 changes:
> - enabling libs in config included as part of lib changes itself.
>
> gowrishankar (6):
>lpm: add altivec intrinsics for dpdk lpm on ppc_64
>acl: add altivec intrinsics for dpdk acl on ppc_64
>ip_pipeline: fix lcore mapping for varying SMT threads as in ppc64
>table: cache align rte_bucket_4_8
>sched: enable sched library for ppc64le
>l3fwd: add altivec support for em_hash_key
>
> app/test-acl/main.c| 4 +
> app/test/test_xmmt_ops.h | 16 +
> config/defconfig_ppc_64-power8-linuxapp-gcc| 7 -
> examples/ip_pipeline/cpu_core_map.c| 12 +-
> examples/ip_pipeline/init.c| 4 +
> examples/l3fwd/l3fwd_em.c | 8 +
> lib/librte_acl/Makefile| 2 +
> lib/librte_acl/acl.h | 4 +
> lib/librte_acl/acl_run.h | 2 +
> lib/librte_acl/acl_run_altivec.c | 47 +++
> lib/librte_acl/acl_run_altivec.h | 328
> +
> lib/librte_acl/rte_acl.c | 13 +
> lib/librte_acl/rte_acl.h | 1 +
> .../common/include/arch/ppc_64/rte_vect.h | 60
> lib/librte_lpm/Makefile| 2 +
> lib/librte_lpm/rte_lpm.h | 2 +
> lib/librte_lpm/rte_lpm_altivec.h | 154 ++
> lib/librte_table/rte_table_hash_key8.c | 2 +-
> 18 files changed, 649 insertions(+), 19 deletions(-) create mode 100644
> lib/librte_acl/acl_run_altivec.c create mode 100644
> lib/librte_acl/acl_run_altivec.h create mode 100644
> lib/librte_eal/common/include/arch/ppc_64/rte_vect.h
> create mode 100644 lib/librte_lpm/rte_lpm_altivec.h
>
> --
> 1.9.1
>
>
>
[dpdk-dev] librte_meter compilation fails on IBM Power8
I remember I came across this problem some time back (not sure on which tip of master), but certainly it is no more appearing now (atleast today tip 65965546 ..) Just an update. Thanks, Gowrishankar On Friday 24 June 2016 03:19 PM, Chao Zhu wrote: > I can repeat this problem by "export EXTRA_CFLAGS="-O0 -g"" on Power8. But > I'm not sure why this happens. The "-O3 -g" option works properly. I'll > investigate more. > > -Original Message- > From: Dumitrescu, Cristian [mailto:cristian.dumitrescu at intel.com] > Sent: 2016?6?24? 1:26 > To: N?lio Laranjeiro ; Chao Zhu linux. > vnet.ibm.com> > Cc: dev at dpdk.org > Subject: RE: librte_meter compilation fails on IBM Power8 > > > >> -Original Message- >> From: N?lio Laranjeiro [mailto:nelio.laranjeiro at 6wind.com] >> Sent: Wednesday, June 22, 2016 1:31 PM >> To: Dumitrescu, Cristian ; Chao Zhu >> >> Cc: dev at dpdk.org >> Subject: librte_meter compilation fails on IBM Power8 >> >> Hi Cristian, Chao, >> >> I have encountered a compilation failure on IBM Power8 when compiling >> master branch with EXTRA_CFLAGS='-O0 -g': >> >>/root/nl/dpdk.org/build/lib/librte_meter.a(rte_meter.o): In function >> `rte_meter_get_tb_params': >>/root/nl/dpdk.org/lib/librte_meter/rte_meter.c:57: undefined >> reference to `ceil' >> >> Seems related to commit 43f4364d. >> >> I don't have the time to search more deeply, I hope it can help. >> >> Regards, >> >> -- >> N?lio Laranjeiro >> 6WIND > I am not sure what the problem might be for IBM Power8. > > ceil() is a function defined in math library, we include math.h header file > in rte_meter.c and we also link the library properly in the Makefile by > using LDLIBS += -lm, therefore I do not see any issue in the library code. > > Thanks, > Cristian > > >
[dpdk-dev] [PATCH] eal/ppc: fix secondary process to map hugepages in correct order
Could this patch be reviewed please.
Thanks,
Gowrishankar
On Monday 07 March 2016 07:43 PM, Gowrishankar wrote:
> From: Gowri Shankar
>
> For a secondary process address space to map hugepages from every segment of
> primary process, hugepage_file entries has to be mapped reversely from the
> list that primary process updated for every segment. This is for a reason
> that,
> in ppc64, hugepages are sorted for decrementing addresses.
>
> Signed-off-by: Gowrishankar
> ---
> lib/librte_eal/linuxapp/eal/eal_memory.c | 26 --
> 1 file changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/lib/librte_eal/linuxapp/eal/eal_memory.c
> b/lib/librte_eal/linuxapp/eal/eal_memory.c
> index 5b9132c..6aea5d0 100644
> --- a/lib/librte_eal/linuxapp/eal/eal_memory.c
> +++ b/lib/librte_eal/linuxapp/eal/eal_memory.c
> @@ -1400,7 +1400,7 @@ rte_eal_hugepage_attach(void)
> {
> const struct rte_mem_config *mcfg =
> rte_eal_get_configuration()->mem_config;
> const struct hugepage_file *hp = NULL;
> - unsigned num_hp = 0;
> + unsigned num_hp = 0, mapped_hp = 0;
> unsigned i, s = 0; /* s used to track the segment number */
> off_t size;
> int fd, fd_zero = -1, fd_hugepage = -1;
> @@ -1486,14 +1486,12 @@ rte_eal_hugepage_attach(void)
> goto error;
> }
>
> - num_hp = size / sizeof(struct hugepage_file);
> - RTE_LOG(DEBUG, EAL, "Analysing %u files\n", num_hp);
> -
> s = 0;
> while (s < RTE_MAX_MEMSEG && mcfg->memseg[s].len > 0){
> void *addr, *base_addr;
> uintptr_t offset = 0;
> size_t mapping_size;
> + unsigned int index;
> #ifdef RTE_LIBRTE_IVSHMEM
> /*
>* if segment has ioremap address set, it's an IVSHMEM segment
> and
> @@ -1504,6 +1502,8 @@ rte_eal_hugepage_attach(void)
> continue;
> }
> #endif
> + num_hp = mcfg->memseg[s].len / mcfg->memseg[s].hugepage_sz;
> + RTE_LOG(DEBUG, EAL, "Analysing %u files in segment %u\n",
> num_hp, s);
> /*
>* free previously mapped memory so we can map the
>* hugepages into the space
> @@ -1514,18 +1514,23 @@ rte_eal_hugepage_attach(void)
> /* find the hugepages for this segment and map them
>* we don't need to worry about order, as the server sorted the
>* entries before it did the second mmap of them */
> +#ifdef RTE_ARCH_PPC_64
> + for (i = num_hp-1; i < num_hp && offset < mcfg->memseg[s].len;
> i--){
> +#else
> for (i = 0; i < num_hp && offset < mcfg->memseg[s].len; i++){
> - if (hp[i].memseg_id == (int)s){
> - fd = open(hp[i].filepath, O_RDWR);
> +#endif
> + index = i + mapped_hp;
> + if (hp[index].memseg_id == (int)s){
> + fd = open(hp[index].filepath, O_RDWR);
> if (fd < 0) {
> RTE_LOG(ERR, EAL, "Could not open %s\n",
> - hp[i].filepath);
> + hp[index].filepath);
> goto error;
> }
> #ifdef RTE_EAL_SINGLE_FILE_SEGMENTS
> - mapping_size = hp[i].size * hp[i].repeated;
> + mapping_size = hp[index].size *
> hp[index].repeated;
> #else
> - mapping_size = hp[i].size;
> + mapping_size = hp[index].size;
> #endif
> addr = mmap(RTE_PTR_ADD(base_addr, offset),
> mapping_size, PROT_READ |
> PROT_WRITE,
> @@ -1534,7 +1539,7 @@ rte_eal_hugepage_attach(void)
> if (addr == MAP_FAILED ||
> addr != RTE_PTR_ADD(base_addr,
> offset)) {
> RTE_LOG(ERR, EAL, "Could not mmap %s\n",
> - hp[i].filepath);
> + hp[index].filepath);
> goto error;
> }
> offset+=mapping_size;
> @@ -1543,6 +1548,7 @@ rte_eal_hugepage_attach(void)
> RTE_LOG(DEBUG, EAL, "Mapped segment %u of size 0x%llx\n", s,
> (unsigned long long)mcfg->memseg[s].len);
> s++;
> + mapped_hp += num_hp;
> }
> /* unmap the hugepage config file, since we are done using it */
> munmap((void *)(uintptr_t)hp, size);
[dpdk-dev] [PATCH v2] examples: fix ip_pipeline to load PMD driver correctly
From: Gowrishankar Muthukrishnan v2: minor correction in patch to avoid space between -d option and driver path Gowrishankar Muthukrishnan (1): examples: fix ip_pipeline to load PMD driver correctly examples/ip_pipeline/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1
[dpdk-dev] [PATCH v2] examples: fix ip_pipeline to load PMD driver correctly
From: Gowrishankar Muthukrishnan
There is typo in init.c of ip_pipeline example due to which,
invalid file path is added to -d option of EAL i.e path starting
with =.
Signed-off-by: Gowrishankar Muthukrishnan
---
examples/ip_pipeline/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/ip_pipeline/init.c b/examples/ip_pipeline/init.c
index 0dbc332..d580ddf 100644
--- a/examples/ip_pipeline/init.c
+++ b/examples/ip_pipeline/init.c
@@ -236,7 +236,7 @@ app_init_eal(struct app_params *app)
}
if (p->add_driver) {
- snprintf(buffer, sizeof(buffer), "-d=%s", p->add_driver);
+ snprintf(buffer, sizeof(buffer), "-d%s", p->add_driver);
app->eal_argv[n_args++] = strdup(buffer);
}
--
1.9.1
[dpdk-dev] [ovs-dev] dpdkvhostuser fail to alloc memory when receive packet from other host
On Wednesday 17 June 2015 03:19 PM, Du, Fan wrote:
> Hi,
>
> I'm playing dpdkvhostuser ports with latest DPDK and ovs master tree with
> iperf benchmarking.
> When kvm guest1(backed up dpdkvhostuser port)siting on HOST1 is receiving
> packets from either other physical HOST2,
> or similar kvm guest2 with dpdkvhostuser port siting on HOST2. The
> connectivity will break, iperf show no bandwidth and stall finally.
In my setup where kvm guest1 receives packets from phy host through ovs
switch (vhost-user),
I do not find this problem. I am on top of below commit fyi.
commit 7d1ced01772de541d6692c7d5604210e274bcd37 (ovs)
Btw, I checked tx case for guest as well. qemu I am using is of version
2.3.0. Is your qemu of version above 2.2
if allotting more than 1GB guest memory.
Could you also share hugepages params passed to kernel.
Regards,
Gowri Shankar
>
> Other test scenario like, two kvm guest sitting on one host, or a single kvm
> guest send packets to a physical host works like a charm.
>
> Swiitch debug option on, dpdk lib spit as below:
> VHOST_CONFIG: read message VHOST_USER_SET_VRING_CALL
> VHOST_CONFIG: vring call idx:0 file:62
> VHOST_CONFIG: read message VHOST_USER_SET_VRING_CALL
> VHOST_CONFIG: vring call idx:0 file:58
>
> VHOST_DATA: F0 Failed to allocate memory for mbuf. mbuf_pool:0x7fc7411ab5c0
> VHOST_DATA: F0 Failed to allocate memory for mbuf. mbuf_pool:0x7fc7411ab5c0
> VHOST_DATA: F0 Failed to allocate memory for mbuf. mbuf_pool:0x7fc7411ab5c0
> VHOST_DATA: F0 Failed to allocate memory for mbuf. mbuf_pool:0x7fc7411ab5c0
> VHOST_DATA: F0 Failed to allocate memory for mbuf. mbuf_pool:0x7fc7411ab5c0
> VHOST_DATA: F0 Failed to allocate memory for mbuf. mbuf_pool:0x7fc7411ab5c0
> VHOST_DATA: F0 Failed to allocate memory for mbuf. mbuf_pool:0x7fc7411ab5c0
> VHOST_DATA: F0 Failed to allocate memory for mbuf. mbuf_pool:0x7fc7411ab5c0
>
> After some tweaks of logging code, and looks like bad things happens within
> below code snippet:
> In lib/librte_vhost/vhost_rxtx.c function: rte_vhost_dequeue_burst
>
> 612 vb_offset = 0;
> 613 vb_avail = desc->len;
> 614 /* Allocate an mbuf and populate the structure. */
> 615 m = rte_pktmbuf_alloc(mbuf_pool);
> 616 if (unlikely(m == NULL)) {
> 617 RTE_LOG(ERR, VHOST_DATA,
> 618 "F0 Failed to allocate memory for mbuf.
> mbuf_pool:%p\n", mbuf_pool);
> 619 break;
> 620 }
> 621 seg_offset = 0;
> 622 seg_avail = m->buf_len - RTE_PKTMBUF_HEADROOM;
> 623 cpy_len = RTE_MIN(vb_avail, seg_avail);
>
>
>
> ___
> dev mailing list
> dev at openvswitch.org
> http://openvswitch.org/mailman/listinfo/dev
[PATCH v3 0/7] cryptodev: support digest message in SM2
This patch series fixes SM2 algorithm implementation to support digest message as input along with plain message as today. v3: - fixed minor issues in code rebase Gowrishankar Muthukrishnan (7): crypto/openssl: include SM2 in asymmetric capabilities cryptodev: add hash algorithms in asymmetric capability cryptodev: use generic EC xform params for SM2 cryptodev: set private and public keys in EC session cryptodev: add RNG capability in EC based xform crypto/cnxk: add SM2 support app/test: check asymmetric capabilities in SM2 test app/test/test_cryptodev_asym.c| 197 - app/test/test_cryptodev_sm2_test_vectors.h| 32 ++- doc/guides/cryptodevs/features/cn10k.ini | 1 + doc/guides/rel_notes/release_23_11.rst| 8 + drivers/common/cnxk/hw/cpt.h | 3 +- drivers/common/cnxk/roc_ae.c | 32 ++- drivers/common/cnxk/roc_ae.h | 21 +- drivers/common/cnxk/roc_ae_fpm_tables.c | 190 + drivers/common/cpt/cpt_mcode_defines.h| 18 ++ drivers/common/cpt/cpt_ucode_asym.h | 22 +- drivers/crypto/cnxk/cnxk_ae.h | 269 +- drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +- .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 17 ++ drivers/crypto/openssl/rte_openssl_pmd.c | 53 +--- drivers/crypto/openssl/rte_openssl_pmd_ops.c | 55 +++- drivers/crypto/qat/qat_asym.c | 6 +- examples/fips_validation/main.c | 14 +- lib/cryptodev/cryptodev_trace.h | 9 + lib/cryptodev/cryptodev_trace_points.c| 3 + lib/cryptodev/rte_crypto_asym.h | 33 +-- lib/cryptodev/rte_cryptodev.c | 16 ++ lib/cryptodev/rte_cryptodev.h | 25 ++ lib/cryptodev/version.map | 1 + 23 files changed, 831 insertions(+), 196 deletions(-) -- 2.25.1
[PATCH v3 1/7] crypto/openssl: include SM2 in asymmetric capabilities
Include SM2 algorithm in the asymmetric capabilities supported
by OpenSSL PMD.
Fixes: 3b7d638fb11f ("crypto/openssl: support asymmetric SM2")
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
index 85a4fa3e55..2eb450fcfd 100644
--- a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
+++ b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
@@ -593,6 +593,20 @@ static const struct rte_cryptodev_capabilities
openssl_pmd_capabilities[] = {
},
}
},
+ { /* SM2 */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_SM2,
+ .op_types =
+ ((1<
[PATCH v3 2/7] cryptodev: add hash algorithms in asymmetric capability
Most of the asymmetric operations start with hash of the input.
But a PMD might also support only plain input (eg openssl).
Add a new field in asymmetric capability to declare support
for hash operations that PMD can support for the asymmetric
operations. Application can skip computing hash if PMD already
supports it.
Signed-off-by: Gowrishankar Muthukrishnan
---
app/test/test_cryptodev_asym.c | 52 ++--
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 1 +
lib/cryptodev/cryptodev_trace.h | 9
lib/cryptodev/cryptodev_trace_points.c | 3 ++
lib/cryptodev/rte_cryptodev.c| 16 ++
lib/cryptodev/rte_cryptodev.h| 19 +++
lib/cryptodev/version.map| 1 +
7 files changed, 97 insertions(+), 4 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 9820b80f7e..61f65823df 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1810,8 +1810,10 @@ _test_sm2_sign(bool rnd_secret)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
+ const struct rte_cryptodev_asymmetric_xform_capability *capa;
struct rte_mempool *sess_mpool = ts_params->session_mpool;
struct rte_mempool *op_mpool = ts_params->op_mpool;
+ struct rte_cryptodev_asym_capability_idx idx;
uint8_t dev_id = ts_params->valid_devs[0];
struct rte_crypto_op *result_op = NULL;
uint8_t output_buf_r[TEST_DATA_SIZE];
@@ -1822,6 +1824,12 @@ _test_sm2_sign(bool rnd_secret)
int ret, status = TEST_SUCCESS;
void *sess = NULL;
+ /* Check SM2 capability */
+ idx.type = RTE_CRYPTO_ASYM_XFORM_SM2;
+ capa = rte_cryptodev_asym_capability_get(dev_id, &idx);
+ if (capa == NULL)
+ return -ENOTSUP;
+
/* Setup crypto op data structure */
op = rte_crypto_op_alloc(op_mpool, RTE_CRYPTO_OP_TYPE_ASYMMETRIC);
if (op == NULL) {
@@ -1838,7 +1846,10 @@ _test_sm2_sign(bool rnd_secret)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -1993,8 +2004,10 @@ test_sm2_verify(void)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
+ const struct rte_cryptodev_asymmetric_xform_capability *capa;
struct rte_mempool *sess_mpool = ts_params->session_mpool;
struct rte_mempool *op_mpool = ts_params->op_mpool;
+ struct rte_cryptodev_asym_capability_idx idx;
uint8_t dev_id = ts_params->valid_devs[0];
struct rte_crypto_op *result_op = NULL;
struct rte_crypto_asym_xform xform;
@@ -2003,6 +2016,12 @@ test_sm2_verify(void)
int ret, status = TEST_SUCCESS;
void *sess = NULL;
+ /* Check SM2 capability */
+ idx.type = RTE_CRYPTO_ASYM_XFORM_SM2;
+ capa = rte_cryptodev_asym_capability_get(dev_id, &idx);
+ if (capa == NULL)
+ return -ENOTSUP;
+
/* Setup crypto op data structure */
op = rte_crypto_op_alloc(op_mpool, RTE_CRYPTO_OP_TYPE_ASYMMETRIC);
if (op == NULL) {
@@ -2019,7 +2038,10 @@ test_sm2_verify(void)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2094,9 +2116,11 @@ _test_sm2_enc(bool rnd_secret)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
+ const struct rte_cryptodev_asymmetric_xform_capability *capa;
struct rte_mempool *sess_mpool = ts_params->session_mpool;
struct rte_mempool *op_mpool = ts_params->op_mpool;
uint8_t output_buf[TEST_DATA_SIZE], *pbuf = NULL;
+ struct rte_cryptodev_asym_capability_idx idx;
uint8_t dev_id = ts_params->valid_devs[0];
struct rte_crypto_op *result_op = NULL;
struct rte_crypto_asym_xform xform;
@@ -2105,6 +2129,12 @@ _test_sm2_enc(bool rnd_secr
[PATCH v3 3/7] cryptodev: use generic EC xform params for SM2
SM2 curve could use generic EC xform as it is yet another EC.
This would also require SM2 curve ID enumerated
along with other curves, as listed in:
https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
app/test/test_cryptodev_asym.c | 40
app/test/test_cryptodev_sm2_test_vectors.h | 4 +-
doc/guides/rel_notes/release_23_11.rst | 2 +
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 3 --
lib/cryptodev/rte_crypto_asym.h | 19 +++---
5 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 61f65823df..95fef9b42a 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1846,10 +1846,7 @@ _test_sm2_sign(bool rnd_secret)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
- else
- xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
+ xform.ec.curve_id = input_params.curve;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -1867,6 +1864,11 @@ _test_sm2_sign(bool rnd_secret)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_SIGN;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
+
asym_op->sm2.message.data = input_params.message.data;
asym_op->sm2.message.length = input_params.message.length;
asym_op->sm2.pkey.data = input_params.pkey.data;
@@ -2038,10 +2040,7 @@ test_sm2_verify(void)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
- else
- xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
+ xform.ec.curve_id = input_params.curve;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2059,6 +2058,11 @@ test_sm2_verify(void)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_VERIFY;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
+
asym_op->sm2.message.data = input_params.message.data;
asym_op->sm2.message.length = input_params.message.length;
asym_op->sm2.pkey.data = input_params.pkey.data;
@@ -2150,10 +2154,7 @@ _test_sm2_enc(bool rnd_secret)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
- else
- xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
+ xform.ec.curve_id = input_params.curve;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2171,6 +2172,11 @@ _test_sm2_enc(bool rnd_secret)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_ENCRYPT;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
+
asym_op->sm2.message.data = input_params.message.data;
asym_op->sm2.message.length = input_params.message.length;
asym_op->sm2.pkey.data = input_params.pkey.data;
@@ -2340,10 +2346,7 @@ test_sm2_dec(void)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
- else
- xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
+ xform.ec.curve_id = input_params.curve;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2361,6 +2364,11 @@ test_sm2_dec(void)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_DECRYPT;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+
[PATCH v3 4/7] cryptodev: set private and public keys in EC session
Set EC private and public keys into xform so that, it can be
maintained per session.
Signed-off-by: Gowrishankar Muthukrishnan
Change-Id: Ib8251987c805bc304f819bf13f94f310f225a0e3
---
app/test/test_cryptodev_asym.c | 60 ++--
drivers/common/cnxk/roc_ae.h | 18 ++
drivers/common/cpt/cpt_mcode_defines.h | 18 ++
drivers/common/cpt/cpt_ucode_asym.h | 22 +++
drivers/crypto/cnxk/cnxk_ae.h| 37
drivers/crypto/openssl/rte_openssl_pmd.c | 53 +
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 35
drivers/crypto/qat/qat_asym.c| 6 +-
examples/fips_validation/main.c | 14 +++--
lib/cryptodev/rte_crypto_asym.h | 18 ++
10 files changed, 158 insertions(+), 123 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 95fef9b42a..4c4bdb9861 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1503,6 +1503,12 @@ test_ecdsa_sign_verify(enum curve curve_id)
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA;
xform.ec.curve_id = input_params.curve;
+ xform.ec.pkey.data = input_params.pkey.data;
+ xform.ec.pkey.length = input_params.pkey.length;
+ xform.ec.q.x.data = input_params.pubkey_qx.data;
+ xform.ec.q.x.length = input_params.pubkey_qx.length;
+ xform.ec.q.y.data = input_params.pubkey_qy.data;
+ xform.ec.q.y.length = input_params.pubkey_qy.length;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -1524,8 +1530,6 @@ test_ecdsa_sign_verify(enum curve curve_id)
op->asym->ecdsa.message.length = input_params.digest.length;
op->asym->ecdsa.k.data = input_params.scalar.data;
op->asym->ecdsa.k.length = input_params.scalar.length;
- op->asym->ecdsa.pkey.data = input_params.pkey.data;
- op->asym->ecdsa.pkey.length = input_params.pkey.length;
/* Init out buf */
op->asym->ecdsa.r.data = output_buf_r;
@@ -1582,10 +1586,6 @@ test_ecdsa_sign_verify(enum curve curve_id)
/* Populate op with operational details */
op->asym->ecdsa.op_type = RTE_CRYPTO_ASYM_OP_VERIFY;
- op->asym->ecdsa.q.x.data = input_params.pubkey_qx.data;
- op->asym->ecdsa.q.x.length = input_params.pubkey_qx.length;
- op->asym->ecdsa.q.y.data = input_params.pubkey_qy.data;
- op->asym->ecdsa.q.y.length = input_params.pubkey_qx.length;
op->asym->ecdsa.r.data = asym_op->ecdsa.r.data;
op->asym->ecdsa.r.length = asym_op->ecdsa.r.length;
op->asym->ecdsa.s.data = asym_op->ecdsa.s.data;
@@ -1847,6 +1847,12 @@ _test_sm2_sign(bool rnd_secret)
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
xform.ec.curve_id = input_params.curve;
+ xform.ec.pkey.data = input_params.pkey.data;
+ xform.ec.pkey.length = input_params.pkey.length;
+ xform.ec.q.x.data = input_params.pubkey_qx.data;
+ xform.ec.q.x.length = input_params.pubkey_qx.length;
+ xform.ec.q.y.data = input_params.pubkey_qy.data;
+ xform.ec.q.y.length = input_params.pubkey_qy.length;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -1871,12 +1877,6 @@ _test_sm2_sign(bool rnd_secret)
asym_op->sm2.message.data = input_params.message.data;
asym_op->sm2.message.length = input_params.message.length;
- asym_op->sm2.pkey.data = input_params.pkey.data;
- asym_op->sm2.pkey.length = input_params.pkey.length;
- asym_op->sm2.q.x.data = input_params.pubkey_qx.data;
- asym_op->sm2.q.x.length = input_params.pubkey_qx.length;
- asym_op->sm2.q.y.data = input_params.pubkey_qy.data;
- asym_op->sm2.q.y.length = input_params.pubkey_qy.length;
asym_op->sm2.id.data = input_params.id.data;
asym_op->sm2.id.length = input_params.id.length;
if (rnd_secret) {
@@ -2041,6 +2041,12 @@ test_sm2_verify(void)
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
xform.ec.curve_id = input_params.curve;
+ xform.ec.pkey.data = input_params.pkey.data;
+ xform.ec.pkey.length = input_params.pkey.length;
+ xform.ec.q.x.data = input_params.pubkey_qx.data;
+ xform.ec.q.x.length = input_params.pubkey_qx.length;
+ xform.ec.q.y.data = input_params.pubkey_qy.data;
+ xform.ec.q.y.length = input_params.pubkey_qy.length;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2065,12 +2071,6 @@ test_sm2_verify(void)
asym_op->sm2.message.data = input_params
[PATCH v3 5/7] cryptodev: add RNG capability in EC based xform
Elliptic curve based asymmetric operations use cryptographically
secure random number in its computation. If PMD supports RNG
for such ops, the application could skip computing on its own.
This patch adds new field in asymmetric capability to declare
this capability.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 2 ++
lib/cryptodev/rte_cryptodev.h| 6 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
index 083ad63360..2862c294a9 100644
--- a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
+++ b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
@@ -604,6 +604,8 @@ static const struct rte_cryptodev_capabilities
openssl_pmd_capabilities[] = {
(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+ {.internal_rng = 1
+ }
}
}
}
diff --git a/lib/cryptodev/rte_cryptodev.h b/lib/cryptodev/rte_cryptodev.h
index 47c6fda25b..9f36e0323d 100644
--- a/lib/cryptodev/rte_cryptodev.h
+++ b/lib/cryptodev/rte_cryptodev.h
@@ -181,6 +181,12 @@ struct rte_cryptodev_asymmetric_xform_capability {
/**< Range of modulus length supported by modulus based xform.
* Value 0 mean implementation default
*/
+
+ uint8_t internal_rng;
+ /**< Availability of random number generator for Elliptic curve
based xform.
+* Value 0 means unavailable, and application should pass the
required
+* random value. Otherwise, PMD would internally compute the
random number.
+*/
};
uint64_t hash_algos;
--
2.25.1
[PATCH v3 7/7] app/test: check asymmetric capabilities in SM2 test
Check asymmetric capabilities such as SM3 hash support and
internal RNG and accordingly choose op params for SM2 test.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
app/test/test_cryptodev_asym.c | 77 +++---
app/test/test_cryptodev_sm2_test_vectors.h | 28 +---
2 files changed, 57 insertions(+), 48 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 4c4bdb9861..f16dcc01f7 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -608,6 +608,7 @@ static inline void print_asym_capa(
break;
case RTE_CRYPTO_ASYM_XFORM_ECDSA:
case RTE_CRYPTO_ASYM_XFORM_ECPM:
+ case RTE_CRYPTO_ASYM_XFORM_SM2:
default:
break;
}
@@ -1806,7 +1807,7 @@ test_ecpm_all_curve(void)
}
static int
-_test_sm2_sign(bool rnd_secret)
+test_sm2_sign(void)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
@@ -1875,11 +1876,19 @@ _test_sm2_sign(bool rnd_secret)
else
asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
- asym_op->sm2.message.data = input_params.message.data;
- asym_op->sm2.message.length = input_params.message.length;
- asym_op->sm2.id.data = input_params.id.data;
- asym_op->sm2.id.length = input_params.id.length;
- if (rnd_secret) {
+ if (asym_op->sm2.hash == RTE_CRYPTO_AUTH_SM3) {
+ asym_op->sm2.message.data = input_params.message.data;
+ asym_op->sm2.message.length = input_params.message.length;
+ asym_op->sm2.id.data = input_params.id.data;
+ asym_op->sm2.id.length = input_params.id.length;
+ } else {
+ asym_op->sm2.message.data = input_params.digest.data;
+ asym_op->sm2.message.length = input_params.digest.length;
+ asym_op->sm2.id.data = NULL;
+ asym_op->sm2.id.length = 0;
+ }
+
+ if (capa->internal_rng != 0) {
asym_op->sm2.k.data = NULL;
asym_op->sm2.k.length = 0;
} else {
@@ -1928,7 +1937,7 @@ _test_sm2_sign(bool rnd_secret)
debug_hexdump(stdout, "s:",
asym_op->sm2.s.data, asym_op->sm2.s.length);
- if (!rnd_secret) {
+ if (capa->internal_rng == 0) {
/* Verify sign (by comparison). */
if (memcmp(input_params.sign_r.data, asym_op->sm2.r.data,
asym_op->sm2.r.length) != 0) {
@@ -1989,18 +1998,6 @@ _test_sm2_sign(bool rnd_secret)
return status;
};
-static int
-test_sm2_sign_rnd_secret(void)
-{
- return _test_sm2_sign(true);
-}
-
-__rte_used static int
-test_sm2_sign_plain_secret(void)
-{
- return _test_sm2_sign(false);
-}
-
static int
test_sm2_verify(void)
{
@@ -2064,19 +2061,28 @@ test_sm2_verify(void)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_VERIFY;
+
if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
asym_op->sm2.hash = RTE_CRYPTO_AUTH_SM3;
else
asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
- asym_op->sm2.message.data = input_params.message.data;
- asym_op->sm2.message.length = input_params.message.length;
+ if (asym_op->sm2.hash == RTE_CRYPTO_AUTH_SM3) {
+ asym_op->sm2.message.data = input_params.message.data;
+ asym_op->sm2.message.length = input_params.message.length;
+ asym_op->sm2.id.data = input_params.id.data;
+ asym_op->sm2.id.length = input_params.id.length;
+ } else {
+ asym_op->sm2.message.data = input_params.digest.data;
+ asym_op->sm2.message.length = input_params.digest.length;
+ asym_op->sm2.id.data = NULL;
+ asym_op->sm2.id.length = 0;
+ }
+
asym_op->sm2.r.data = input_params.sign_r.data;
asym_op->sm2.r.length = input_params.sign_r.length;
asym_op->sm2.s.data = input_params.sign_s.data;
asym_op->sm2.s.length = input_params.sign_s.length;
- asym_op->sm2.id.data = input_params.id.data;
- asym_op->sm2.id.length = input_params.id.length;
RTE_LOG(DEBUG, USER1, "Process ASYM operation\n");
@@ -2116,7 +2122,7 @@ test_sm2_verify(void)
};
static int
-_test_sm2_enc(bool rnd_secret)
+test_sm2_enc(void)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
@@ -2185,7 +2191,8 @@ _test_sm2_enc(bool rnd_secret)
asym_op->sm2.message.data = input_params.message.data;
[PATCH v3 6/7] crypto/cnxk: add SM2 support
Add SM2 asymmetric algorithm support in cnxk PMD.
Signed-off-by: Gowrishankar Muthukrishnan
---
doc/guides/cryptodevs/features/cn10k.ini | 1 +
doc/guides/rel_notes/release_23_11.rst| 6 +
drivers/common/cnxk/hw/cpt.h | 3 +-
drivers/common/cnxk/roc_ae.c | 32 ++-
drivers/common/cnxk/roc_ae.h | 3 +-
drivers/common/cnxk/roc_ae_fpm_tables.c | 190 ++
drivers/crypto/cnxk/cnxk_ae.h | 232 +-
drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +-
.../crypto/cnxk/cnxk_cryptodev_capabilities.c | 17 ++
9 files changed, 481 insertions(+), 5 deletions(-)
diff --git a/doc/guides/cryptodevs/features/cn10k.ini
b/doc/guides/cryptodevs/features/cn10k.ini
index 55a1226965..15e2dd48a8 100644
--- a/doc/guides/cryptodevs/features/cn10k.ini
+++ b/doc/guides/cryptodevs/features/cn10k.ini
@@ -103,6 +103,7 @@ Modular Inversion =
Diffie-hellman =
ECDSA = Y
ECPM= Y
+SM2 = Y
;
; Supported Operating systems of the 'cn10k' crypto driver.
diff --git a/doc/guides/rel_notes/release_23_11.rst
b/doc/guides/rel_notes/release_23_11.rst
index e9afae8030..b21e78c7a0 100644
--- a/doc/guides/rel_notes/release_23_11.rst
+++ b/doc/guides/rel_notes/release_23_11.rst
@@ -72,12 +72,18 @@ New Features
Also, make sure to start the actual text at the margin.
===
+
* build: Enabling deprecated libraries is now done using the new
``enable_deprecated_libraries`` build option.
* build: Optional libraries can now be selected with the new ``enable_libs``
build option similarly to the existing ``enable_drivers`` build option.
+* **Updated CNXK crypto driver.**
+
+ * Added SM2 algorithm support in asymmetric crypto operations.
+
+
Removed Items
-
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index 5e1519e202..ce57de8788 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -79,7 +79,8 @@ union cpt_eng_caps {
uint64_t __io reserved_23_33 : 11;
uint64_t __io pdcp_chain : 1;
uint64_t __io sg_ver2 : 1;
- uint64_t __io reserved_36_63 : 28;
+ uint64_t __io sm2 : 1;
+ uint64_t __io reserved_37_63 : 27;
};
};
diff --git a/drivers/common/cnxk/roc_ae.c b/drivers/common/cnxk/roc_ae.c
index 336b927641..e6a013d7c4 100644
--- a/drivers/common/cnxk/roc_ae.c
+++ b/drivers/common/cnxk/roc_ae.c
@@ -149,7 +149,37 @@ const struct roc_ae_ec_group ae_ec_grp[ROC_AE_EC_ID_PMAX]
= {
0xBF, 0x07, 0x35, 0x73, 0xDF, 0x88, 0x3D, 0x2C,
0x34, 0xF1, 0xEF, 0x45, 0x1F, 0xD4, 0x6B, 0x50,
0x3F, 0x00},
- .length = 66}}};
+ .length = 66},
+ },
+ {},
+ {},
+ {},
+ {
+ .prime = {.data = {0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+ 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF},
+ .length = 32},
+ .order = {.data = {0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0x72, 0x03, 0xDF, 0x6B, 0x21,
+ 0xC6, 0x05, 0x2B, 0x53, 0xBB, 0xF4, 0x09,
+ 0x39, 0xD5, 0x41, 0x23},
+ .length = 32},
+ .consta = {.data = {0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+ 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFC},
+ .length = 32},
+ .constb = {.data = {0x28, 0xE9, 0xFA, 0x9E, 0x9D, 0x9F, 0x5E,
+ 0x34, 0x4D, 0x5A, 0x9E, 0x4B, 0xCF, 0x65,
+ 0x09, 0xA7, 0xF3, 0x97, 0x89, 0xF5, 0x15,
+ 0xAB, 0x8F, 0x92, 0xDD, 0xBC, 0xBD, 0x41,
+ 0x4D, 0x94, 0x0E, 0x93},
+ .length = 32},
+ }};
int
roc_ae_ec_grp_get(struct roc_ae_ec_group **tbl)
diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h
index d8ad0129b1..d459c5e680 100644
--- a/drivers/common/cnxk/roc_ae.h
+++ b/drivers/common/cnxk/roc_ae.h
@@ -34,7 +34,8 @@ typedef enum {
ROC_AE_EC_I
[PATCH v4 0/7] cryptodev: support digest message in SM2
This patch series fixes SM2 algorithm implementation to support digest message as input along with plain message as today. v4: - code rebase on next-crypto Gowrishankar Muthukrishnan (7): crypto/openssl: include SM2 in asymmetric capabilities cryptodev: add hash algorithms in asymmetric capability cryptodev: use generic EC xform params for SM2 cryptodev: set private and public keys in EC session cryptodev: add RNG capability in EC based xform crypto/cnxk: add SM2 support app/test: check asymmetric capabilities in SM2 test app/test/test_cryptodev_asym.c| 197 - app/test/test_cryptodev_sm2_test_vectors.h| 32 ++- doc/guides/cryptodevs/features/cn10k.ini | 1 + doc/guides/rel_notes/release_23_11.rst| 6 + drivers/common/cnxk/hw/cpt.h | 2 +- drivers/common/cnxk/roc_ae.c | 32 ++- drivers/common/cnxk/roc_ae.h | 21 +- drivers/common/cnxk/roc_ae_fpm_tables.c | 190 + drivers/common/cpt/cpt_mcode_defines.h| 18 ++ drivers/common/cpt/cpt_ucode_asym.h | 22 +- drivers/crypto/cnxk/cnxk_ae.h | 269 +- drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +- .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 17 ++ drivers/crypto/openssl/rte_openssl_pmd.c | 53 +--- drivers/crypto/openssl/rte_openssl_pmd_ops.c | 55 +++- drivers/crypto/qat/qat_asym.c | 6 +- examples/fips_validation/main.c | 14 +- lib/cryptodev/cryptodev_trace.h | 9 + lib/cryptodev/cryptodev_trace_points.c| 3 + lib/cryptodev/rte_crypto_asym.h | 33 +-- lib/cryptodev/rte_cryptodev.c | 16 ++ lib/cryptodev/rte_cryptodev.h | 25 ++ lib/cryptodev/version.map | 1 + 23 files changed, 828 insertions(+), 196 deletions(-) -- 2.25.1
[PATCH v4 1/7] crypto/openssl: include SM2 in asymmetric capabilities
Include SM2 algorithm in the asymmetric capabilities supported
by OpenSSL PMD.
Fixes: 3b7d638fb11f ("crypto/openssl: support asymmetric SM2")
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
index 85a4fa3e55..2eb450fcfd 100644
--- a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
+++ b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
@@ -593,6 +593,20 @@ static const struct rte_cryptodev_capabilities
openssl_pmd_capabilities[] = {
},
}
},
+ { /* SM2 */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_SM2,
+ .op_types =
+ ((1<
[PATCH v4 2/7] cryptodev: add hash algorithms in asymmetric capability
Most of the asymmetric operations start with hash of the input.
But a PMD might also support only plain input (eg openssl).
Add a new field in asymmetric capability to declare support
for hash operations that PMD can support for the asymmetric
operations. Application can skip computing hash if PMD already
supports it.
Signed-off-by: Gowrishankar Muthukrishnan
---
app/test/test_cryptodev_asym.c | 52 ++--
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 1 +
lib/cryptodev/cryptodev_trace.h | 9
lib/cryptodev/cryptodev_trace_points.c | 3 ++
lib/cryptodev/rte_cryptodev.c| 16 ++
lib/cryptodev/rte_cryptodev.h| 19 +++
lib/cryptodev/version.map| 1 +
7 files changed, 97 insertions(+), 4 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 39de0bdac5..af323e02d9 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1810,8 +1810,10 @@ _test_sm2_sign(bool rnd_secret)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
+ const struct rte_cryptodev_asymmetric_xform_capability *capa;
struct rte_mempool *sess_mpool = ts_params->session_mpool;
struct rte_mempool *op_mpool = ts_params->op_mpool;
+ struct rte_cryptodev_asym_capability_idx idx;
uint8_t dev_id = ts_params->valid_devs[0];
struct rte_crypto_op *result_op = NULL;
uint8_t output_buf_r[TEST_DATA_SIZE];
@@ -1822,6 +1824,12 @@ _test_sm2_sign(bool rnd_secret)
int ret, status = TEST_SUCCESS;
void *sess = NULL;
+ /* Check SM2 capability */
+ idx.type = RTE_CRYPTO_ASYM_XFORM_SM2;
+ capa = rte_cryptodev_asym_capability_get(dev_id, &idx);
+ if (capa == NULL)
+ return -ENOTSUP;
+
/* Setup crypto op data structure */
op = rte_crypto_op_alloc(op_mpool, RTE_CRYPTO_OP_TYPE_ASYMMETRIC);
if (op == NULL) {
@@ -1838,7 +1846,10 @@ _test_sm2_sign(bool rnd_secret)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -1993,8 +2004,10 @@ test_sm2_verify(void)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
+ const struct rte_cryptodev_asymmetric_xform_capability *capa;
struct rte_mempool *sess_mpool = ts_params->session_mpool;
struct rte_mempool *op_mpool = ts_params->op_mpool;
+ struct rte_cryptodev_asym_capability_idx idx;
uint8_t dev_id = ts_params->valid_devs[0];
struct rte_crypto_op *result_op = NULL;
struct rte_crypto_asym_xform xform;
@@ -2003,6 +2016,12 @@ test_sm2_verify(void)
int ret, status = TEST_SUCCESS;
void *sess = NULL;
+ /* Check SM2 capability */
+ idx.type = RTE_CRYPTO_ASYM_XFORM_SM2;
+ capa = rte_cryptodev_asym_capability_get(dev_id, &idx);
+ if (capa == NULL)
+ return -ENOTSUP;
+
/* Setup crypto op data structure */
op = rte_crypto_op_alloc(op_mpool, RTE_CRYPTO_OP_TYPE_ASYMMETRIC);
if (op == NULL) {
@@ -2019,7 +2038,10 @@ test_sm2_verify(void)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2094,9 +2116,11 @@ _test_sm2_enc(bool rnd_secret)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
+ const struct rte_cryptodev_asymmetric_xform_capability *capa;
struct rte_mempool *sess_mpool = ts_params->session_mpool;
struct rte_mempool *op_mpool = ts_params->op_mpool;
uint8_t output_buf[TEST_DATA_SIZE], *pbuf = NULL;
+ struct rte_cryptodev_asym_capability_idx idx;
uint8_t dev_id = ts_params->valid_devs[0];
struct rte_crypto_op *result_op = NULL;
struct rte_crypto_asym_xform xform;
@@ -2105,6 +2129,12 @@ _test_sm2_enc(bool rnd_secr
[PATCH v4 3/7] cryptodev: use generic EC xform params for SM2
SM2 curve could use generic EC xform as it is yet another EC.
This would also require SM2 curve ID enumerated
along with other curves, as listed in:
https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
app/test/test_cryptodev_asym.c | 40
app/test/test_cryptodev_sm2_test_vectors.h | 4 +-
doc/guides/rel_notes/release_23_11.rst | 2 +
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 3 --
lib/cryptodev/rte_crypto_asym.h | 19 +++---
5 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index af323e02d9..514ea96b8b 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1846,10 +1846,7 @@ _test_sm2_sign(bool rnd_secret)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
- else
- xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
+ xform.ec.curve_id = input_params.curve;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -1867,6 +1864,11 @@ _test_sm2_sign(bool rnd_secret)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_SIGN;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
+
asym_op->sm2.message.data = input_params.message.data;
asym_op->sm2.message.length = input_params.message.length;
asym_op->sm2.pkey.data = input_params.pkey.data;
@@ -2038,10 +2040,7 @@ test_sm2_verify(void)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
- else
- xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
+ xform.ec.curve_id = input_params.curve;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2059,6 +2058,11 @@ test_sm2_verify(void)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_VERIFY;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
+
asym_op->sm2.message.data = input_params.message.data;
asym_op->sm2.message.length = input_params.message.length;
asym_op->sm2.pkey.data = input_params.pkey.data;
@@ -2150,10 +2154,7 @@ _test_sm2_enc(bool rnd_secret)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
- else
- xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
+ xform.ec.curve_id = input_params.curve;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2171,6 +2172,11 @@ _test_sm2_enc(bool rnd_secret)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_ENCRYPT;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_SM3;
+ else
+ asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
+
asym_op->sm2.message.data = input_params.message.data;
asym_op->sm2.message.length = input_params.message.length;
asym_op->sm2.pkey.data = input_params.pkey.data;
@@ -2340,10 +2346,7 @@ test_sm2_dec(void)
/* Setup asym xform */
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
- if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
- xform.sm2.hash = RTE_CRYPTO_AUTH_SM3;
- else
- xform.sm2.hash = RTE_CRYPTO_AUTH_NULL;
+ xform.ec.curve_id = input_params.curve;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2361,6 +2364,11 @@ test_sm2_dec(void)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_DECRYPT;
+ if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
+
[PATCH v4 4/7] cryptodev: set private and public keys in EC session
Set EC private and public keys into xform so that, it can be
maintained per session.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Ciara Power
---
app/test/test_cryptodev_asym.c | 60 ++--
drivers/common/cnxk/roc_ae.h | 18 ++
drivers/common/cpt/cpt_mcode_defines.h | 18 ++
drivers/common/cpt/cpt_ucode_asym.h | 22 +++
drivers/crypto/cnxk/cnxk_ae.h| 37
drivers/crypto/openssl/rte_openssl_pmd.c | 53 +
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 35
drivers/crypto/qat/qat_asym.c| 6 +-
examples/fips_validation/main.c | 14 +++--
lib/cryptodev/rte_crypto_asym.h | 18 ++
10 files changed, 158 insertions(+), 123 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 514ea96b8b..a2bb1f9336 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1503,6 +1503,12 @@ test_ecdsa_sign_verify(enum curve curve_id)
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA;
xform.ec.curve_id = input_params.curve;
+ xform.ec.pkey.data = input_params.pkey.data;
+ xform.ec.pkey.length = input_params.pkey.length;
+ xform.ec.q.x.data = input_params.pubkey_qx.data;
+ xform.ec.q.x.length = input_params.pubkey_qx.length;
+ xform.ec.q.y.data = input_params.pubkey_qy.data;
+ xform.ec.q.y.length = input_params.pubkey_qy.length;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -1524,8 +1530,6 @@ test_ecdsa_sign_verify(enum curve curve_id)
op->asym->ecdsa.message.length = input_params.digest.length;
op->asym->ecdsa.k.data = input_params.scalar.data;
op->asym->ecdsa.k.length = input_params.scalar.length;
- op->asym->ecdsa.pkey.data = input_params.pkey.data;
- op->asym->ecdsa.pkey.length = input_params.pkey.length;
/* Init out buf */
op->asym->ecdsa.r.data = output_buf_r;
@@ -1582,10 +1586,6 @@ test_ecdsa_sign_verify(enum curve curve_id)
/* Populate op with operational details */
op->asym->ecdsa.op_type = RTE_CRYPTO_ASYM_OP_VERIFY;
- op->asym->ecdsa.q.x.data = input_params.pubkey_qx.data;
- op->asym->ecdsa.q.x.length = input_params.pubkey_qx.length;
- op->asym->ecdsa.q.y.data = input_params.pubkey_qy.data;
- op->asym->ecdsa.q.y.length = input_params.pubkey_qx.length;
op->asym->ecdsa.r.data = asym_op->ecdsa.r.data;
op->asym->ecdsa.r.length = asym_op->ecdsa.r.length;
op->asym->ecdsa.s.data = asym_op->ecdsa.s.data;
@@ -1847,6 +1847,12 @@ _test_sm2_sign(bool rnd_secret)
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
xform.ec.curve_id = input_params.curve;
+ xform.ec.pkey.data = input_params.pkey.data;
+ xform.ec.pkey.length = input_params.pkey.length;
+ xform.ec.q.x.data = input_params.pubkey_qx.data;
+ xform.ec.q.x.length = input_params.pubkey_qx.length;
+ xform.ec.q.y.data = input_params.pubkey_qy.data;
+ xform.ec.q.y.length = input_params.pubkey_qy.length;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -1871,12 +1877,6 @@ _test_sm2_sign(bool rnd_secret)
asym_op->sm2.message.data = input_params.message.data;
asym_op->sm2.message.length = input_params.message.length;
- asym_op->sm2.pkey.data = input_params.pkey.data;
- asym_op->sm2.pkey.length = input_params.pkey.length;
- asym_op->sm2.q.x.data = input_params.pubkey_qx.data;
- asym_op->sm2.q.x.length = input_params.pubkey_qx.length;
- asym_op->sm2.q.y.data = input_params.pubkey_qy.data;
- asym_op->sm2.q.y.length = input_params.pubkey_qy.length;
asym_op->sm2.id.data = input_params.id.data;
asym_op->sm2.id.length = input_params.id.length;
if (rnd_secret) {
@@ -2041,6 +2041,12 @@ test_sm2_verify(void)
xform.next = NULL;
xform.xform_type = RTE_CRYPTO_ASYM_XFORM_SM2;
xform.ec.curve_id = input_params.curve;
+ xform.ec.pkey.data = input_params.pkey.data;
+ xform.ec.pkey.length = input_params.pkey.length;
+ xform.ec.q.x.data = input_params.pubkey_qx.data;
+ xform.ec.q.x.length = input_params.pubkey_qx.length;
+ xform.ec.q.y.data = input_params.pubkey_qy.data;
+ xform.ec.q.y.length = input_params.pubkey_qy.length;
ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
if (ret < 0) {
@@ -2065,12 +2071,6 @@ test_sm2_verify(void)
asym_op->sm2.message.data = input_params.message.data;
asym_op->sm2.
[PATCH v4 5/7] cryptodev: add RNG capability in EC based xform
Elliptic curve based asymmetric operations use cryptographically
secure random number in its computation. If PMD supports RNG
for such ops, the application could skip computing on its own.
This patch adds new field in asymmetric capability to declare
this capability.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 2 ++
lib/cryptodev/rte_cryptodev.h| 6 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
index 083ad63360..2862c294a9 100644
--- a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
+++ b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
@@ -604,6 +604,8 @@ static const struct rte_cryptodev_capabilities
openssl_pmd_capabilities[] = {
(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+ {.internal_rng = 1
+ }
}
}
}
diff --git a/lib/cryptodev/rte_cryptodev.h b/lib/cryptodev/rte_cryptodev.h
index 3a1b4dc501..6c8f532797 100644
--- a/lib/cryptodev/rte_cryptodev.h
+++ b/lib/cryptodev/rte_cryptodev.h
@@ -181,6 +181,12 @@ struct rte_cryptodev_asymmetric_xform_capability {
/**< Range of modulus length supported by modulus based xform.
* Value 0 mean implementation default
*/
+
+ uint8_t internal_rng;
+ /**< Availability of random number generator for Elliptic curve
based xform.
+* Value 0 means unavailable, and application should pass the
required
+* random value. Otherwise, PMD would internally compute the
random number.
+*/
};
uint64_t hash_algos;
--
2.25.1
[PATCH v4 6/7] crypto/cnxk: add SM2 support
Add SM2 asymmetric algorithm support in cnxk PMD.
Signed-off-by: Gowrishankar Muthukrishnan
---
doc/guides/cryptodevs/features/cn10k.ini | 1 +
doc/guides/rel_notes/release_23_11.rst| 4 +
drivers/common/cnxk/hw/cpt.h | 2 +-
drivers/common/cnxk/roc_ae.c | 32 ++-
drivers/common/cnxk/roc_ae.h | 3 +-
drivers/common/cnxk/roc_ae_fpm_tables.c | 190 ++
drivers/crypto/cnxk/cnxk_ae.h | 232 +-
drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +-
.../crypto/cnxk/cnxk_cryptodev_capabilities.c | 17 ++
9 files changed, 478 insertions(+), 5 deletions(-)
diff --git a/doc/guides/cryptodevs/features/cn10k.ini
b/doc/guides/cryptodevs/features/cn10k.ini
index 53ee2a720e..4f542c6038 100644
--- a/doc/guides/cryptodevs/features/cn10k.ini
+++ b/doc/guides/cryptodevs/features/cn10k.ini
@@ -104,6 +104,7 @@ Modular Inversion =
Diffie-hellman =
ECDSA = Y
ECPM= Y
+SM2 = Y
;
; Supported Operating systems of the 'cn10k' crypto driver.
diff --git a/doc/guides/rel_notes/release_23_11.rst
b/doc/guides/rel_notes/release_23_11.rst
index 53639543a6..401230a1c0 100644
--- a/doc/guides/rel_notes/release_23_11.rst
+++ b/doc/guides/rel_notes/release_23_11.rst
@@ -96,6 +96,10 @@ New Features
Added support for DOCSIS security protocol through the ``rte_security`` API
callbacks.
+* **Updated CNXK crypto driver.**
+
+ Added SM2 algorithm support in asymmetric crypto operations.
+
Removed Items
-
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index cad4ed7e79..cf9046bbfb 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -78,7 +78,7 @@ union cpt_eng_caps {
uint64_t __io sm4 : 1;
uint64_t __io reserved_23_34 : 12;
uint64_t __io sg_ver2 : 1;
- uint64_t __io reserved36 : 1;
+ uint64_t __io sm2 : 1;
uint64_t __io pdcp_chain_zuc256 : 1;
uint64_t __io reserved_38_63 : 26;
};
diff --git a/drivers/common/cnxk/roc_ae.c b/drivers/common/cnxk/roc_ae.c
index 336b927641..e6a013d7c4 100644
--- a/drivers/common/cnxk/roc_ae.c
+++ b/drivers/common/cnxk/roc_ae.c
@@ -149,7 +149,37 @@ const struct roc_ae_ec_group ae_ec_grp[ROC_AE_EC_ID_PMAX]
= {
0xBF, 0x07, 0x35, 0x73, 0xDF, 0x88, 0x3D, 0x2C,
0x34, 0xF1, 0xEF, 0x45, 0x1F, 0xD4, 0x6B, 0x50,
0x3F, 0x00},
- .length = 66}}};
+ .length = 66},
+ },
+ {},
+ {},
+ {},
+ {
+ .prime = {.data = {0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+ 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF},
+ .length = 32},
+ .order = {.data = {0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0x72, 0x03, 0xDF, 0x6B, 0x21,
+ 0xC6, 0x05, 0x2B, 0x53, 0xBB, 0xF4, 0x09,
+ 0x39, 0xD5, 0x41, 0x23},
+ .length = 32},
+ .consta = {.data = {0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+ 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFC},
+ .length = 32},
+ .constb = {.data = {0x28, 0xE9, 0xFA, 0x9E, 0x9D, 0x9F, 0x5E,
+ 0x34, 0x4D, 0x5A, 0x9E, 0x4B, 0xCF, 0x65,
+ 0x09, 0xA7, 0xF3, 0x97, 0x89, 0xF5, 0x15,
+ 0xAB, 0x8F, 0x92, 0xDD, 0xBC, 0xBD, 0x41,
+ 0x4D, 0x94, 0x0E, 0x93},
+ .length = 32},
+ }};
int
roc_ae_ec_grp_get(struct roc_ae_ec_group **tbl)
diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h
index d8ad0129b1..d459c5e680 100644
--- a/drivers/common/cnxk/roc_ae.h
+++ b/drivers/common/cnxk/roc_ae.h
@@ -34,7 +34,8 @@ typedef enum {
ROC_AE_EC_ID_P160 = 5,
ROC_AE_EC_ID_P320 = 6,
ROC_AE_EC_ID_P512 = 7,
- ROC_AE_EC_ID_PMAX = 8
+ ROC_AE_EC_ID_SM2 = 8,
+ ROC_AE_EC_ID_PMAX
} roc_ae_ec_id;
/* Prime and order fields of built-in elliptic curves */
diff --git a/drivers/common/cnxk/roc_ae_fpm_t
[PATCH v4 7/7] app/test: check asymmetric capabilities in SM2 test
Check asymmetric capabilities such as SM3 hash support and
internal RNG and accordingly choose op params for SM2 test.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Arkadiusz Kusztal
---
app/test/test_cryptodev_asym.c | 77 +++---
app/test/test_cryptodev_sm2_test_vectors.h | 28 +---
2 files changed, 57 insertions(+), 48 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index a2bb1f9336..94bb091df3 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -608,6 +608,7 @@ static inline void print_asym_capa(
break;
case RTE_CRYPTO_ASYM_XFORM_ECDSA:
case RTE_CRYPTO_ASYM_XFORM_ECPM:
+ case RTE_CRYPTO_ASYM_XFORM_SM2:
default:
break;
}
@@ -1806,7 +1807,7 @@ test_ecpm_all_curve(void)
}
static int
-_test_sm2_sign(bool rnd_secret)
+test_sm2_sign(void)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
@@ -1875,11 +1876,19 @@ _test_sm2_sign(bool rnd_secret)
else
asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
- asym_op->sm2.message.data = input_params.message.data;
- asym_op->sm2.message.length = input_params.message.length;
- asym_op->sm2.id.data = input_params.id.data;
- asym_op->sm2.id.length = input_params.id.length;
- if (rnd_secret) {
+ if (asym_op->sm2.hash == RTE_CRYPTO_AUTH_SM3) {
+ asym_op->sm2.message.data = input_params.message.data;
+ asym_op->sm2.message.length = input_params.message.length;
+ asym_op->sm2.id.data = input_params.id.data;
+ asym_op->sm2.id.length = input_params.id.length;
+ } else {
+ asym_op->sm2.message.data = input_params.digest.data;
+ asym_op->sm2.message.length = input_params.digest.length;
+ asym_op->sm2.id.data = NULL;
+ asym_op->sm2.id.length = 0;
+ }
+
+ if (capa->internal_rng != 0) {
asym_op->sm2.k.data = NULL;
asym_op->sm2.k.length = 0;
} else {
@@ -1928,7 +1937,7 @@ _test_sm2_sign(bool rnd_secret)
debug_hexdump(stdout, "s:",
asym_op->sm2.s.data, asym_op->sm2.s.length);
- if (!rnd_secret) {
+ if (capa->internal_rng == 0) {
/* Verify sign (by comparison). */
if (memcmp(input_params.sign_r.data, asym_op->sm2.r.data,
asym_op->sm2.r.length) != 0) {
@@ -1989,18 +1998,6 @@ _test_sm2_sign(bool rnd_secret)
return status;
};
-static int
-test_sm2_sign_rnd_secret(void)
-{
- return _test_sm2_sign(true);
-}
-
-__rte_used static int
-test_sm2_sign_plain_secret(void)
-{
- return _test_sm2_sign(false);
-}
-
static int
test_sm2_verify(void)
{
@@ -2064,19 +2061,28 @@ test_sm2_verify(void)
/* Populate op with operational details */
asym_op->sm2.op_type = RTE_CRYPTO_ASYM_OP_VERIFY;
+
if (rte_cryptodev_asym_xform_capability_check_hash(capa,
RTE_CRYPTO_AUTH_SM3))
asym_op->sm2.hash = RTE_CRYPTO_AUTH_SM3;
else
asym_op->sm2.hash = RTE_CRYPTO_AUTH_NULL;
- asym_op->sm2.message.data = input_params.message.data;
- asym_op->sm2.message.length = input_params.message.length;
+ if (asym_op->sm2.hash == RTE_CRYPTO_AUTH_SM3) {
+ asym_op->sm2.message.data = input_params.message.data;
+ asym_op->sm2.message.length = input_params.message.length;
+ asym_op->sm2.id.data = input_params.id.data;
+ asym_op->sm2.id.length = input_params.id.length;
+ } else {
+ asym_op->sm2.message.data = input_params.digest.data;
+ asym_op->sm2.message.length = input_params.digest.length;
+ asym_op->sm2.id.data = NULL;
+ asym_op->sm2.id.length = 0;
+ }
+
asym_op->sm2.r.data = input_params.sign_r.data;
asym_op->sm2.r.length = input_params.sign_r.length;
asym_op->sm2.s.data = input_params.sign_s.data;
asym_op->sm2.s.length = input_params.sign_s.length;
- asym_op->sm2.id.data = input_params.id.data;
- asym_op->sm2.id.length = input_params.id.length;
RTE_LOG(DEBUG, USER1, "Process ASYM operation\n");
@@ -2116,7 +2122,7 @@ test_sm2_verify(void)
};
static int
-_test_sm2_enc(bool rnd_secret)
+test_sm2_enc(void)
{
struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
struct crypto_testsuite_sm2_params input_params = sm2_param_fp256;
@@ -2185,7 +2191,8 @@ _test_sm2_enc(bool rnd_secret)
asym_op->sm2.message.data = input_params.message.data;
[PATCH v2] test/cryptodev: add modexp group tests
Add modexp tests for groups 5, 14, 15, 16, 17 and 18.
Signed-off-by: Gowrishankar Muthukrishnan
---
v2:
- rebase on main
---
app/test/test_cryptodev_asym.c | 48 +
app/test/test_cryptodev_mod_test_vectors.h | 989 -
2 files changed, 1036 insertions(+), 1 deletion(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 94bb091df3..c6334380d7 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -2745,6 +2745,30 @@ static struct unit_test_suite
cryptodev_openssl_asym_testsuite = {
test_rsa_sign_verify_crt),
TEST_CASE_ST(ut_setup_asym, ut_teardown_asym, test_mod_inv),
TEST_CASE_ST(ut_setup_asym, ut_teardown_asym, test_mod_exp),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[0].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[0]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[1].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[1]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[2].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[2]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[3].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[3]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[4].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[4]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[5].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[5]),
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
@@ -2796,6 +2820,30 @@ static struct unit_test_suite
cryptodev_octeontx_asym_testsuite = {
TEST_CASE_ST(ut_setup_asym, ut_teardown_asym,
test_rsa_sign_verify_crt),
TEST_CASE_ST(ut_setup_asym, ut_teardown_asym, test_mod_exp),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[0].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[0]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[1].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[1]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[2].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[2]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[3].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[3]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[4].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[4]),
+ TEST_CASE_NAMED_WITH_DATA(
+ modex_group_test_cases[5].description,
+ ut_setup_asym, ut_teardown_asym,
+ modular_exponentiation, &modex_group_test_cases[5]),
TEST_CASE_ST(ut_setup_asym, ut_teardown_asym,
test_ecdsa_sign_verify_all_curve),
TEST_CASE_ST(ut_setup_asym, ut_teardown_asym, test_sm2_sign),
diff --git a/app/test/test_cryptodev_mod_test_vectors.h
b/app/test/test_cryptodev_mod_test_vectors.h
index 0ffc958037..c773c37018 100644
--- a/app/test/test_cryptodev_mod_test_vectors.h
+++ b/app/test/test_cryptodev_mod_test_vectors.h
@@ -6,7 +6,7 @@
#ifndef TEST_CRYPTODEV_MOD_TEST_VECTORS_H_
#define TEST_CRYPTODEV_MOD_TEST_VECTORS_H_
-#define DATA_SIZE 512
+#define DATA_SIZE 1024
struct modex_test_data {
enum rte_crypto_asym_xform_type xform_type;
@@ -269,4 +269,991 @@ struct rte_crypto_asym_xform modinv_xform = {
}
};
+static const struct
+modex_test_data modex_group_test_cases[] = {
+{
+ .description = "Modula
[PATCH v1 0/4] test/cryptodev: add ECDH tests
This patch series adds ECDH testsuite. It also enables ECDH support in CNXK PMD. Gowrishankar Muthukrishnan (4): test/cryptodev: add ECDH tests crypto/cnxk: use generic EC opcodes crypto/cnxk: change order of ECFPM params crypto/cnxk: add ECDH support app/test/test_cryptodev_asym.c| 729 ++ app/test/test_cryptodev_asym_util.h | 12 + app/test/test_cryptodev_ecdh_test_vectors.h | 577 ++ app/test/test_cryptodev_ecdsa_test_vectors.h | 3 + doc/guides/cryptodevs/features/cn10k.ini | 1 + doc/guides/cryptodevs/features/cn9k.ini | 1 + drivers/common/cnxk/roc_ae.h | 21 +- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 12 + drivers/crypto/cnxk/cnxk_ae.h | 240 -- drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +- .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 14 + 11 files changed, 1543 insertions(+), 69 deletions(-) create mode 100644 app/test/test_cryptodev_ecdh_test_vectors.h -- 2.25.1
[PATCH v1 1/4] test/cryptodev: add ECDH tests
Add ECDH tests.
Signed-off-by: Gowrishankar Muthukrishnan
---
app/test/test_cryptodev_asym.c | 729 +++
app/test/test_cryptodev_asym_util.h | 12 +
app/test/test_cryptodev_ecdh_test_vectors.h | 577 +++
app/test/test_cryptodev_ecdsa_test_vectors.h | 3 +
4 files changed, 1321 insertions(+)
create mode 100644 app/test/test_cryptodev_ecdh_test_vectors.h
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index c6334380d7..965e71d0bc 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -17,6 +17,7 @@
#include "test_cryptodev.h"
#include "test_cryptodev_dh_test_vectors.h"
#include "test_cryptodev_dsa_test_vectors.h"
+#include "test_cryptodev_ecdh_test_vectors.h"
#include "test_cryptodev_ecdsa_test_vectors.h"
#include "test_cryptodev_ecpm_test_vectors.h"
#include "test_cryptodev_mod_test_vectors.h"
@@ -1806,6 +1807,732 @@ test_ecpm_all_curve(void)
return overall_status;
}
+static int
+test_ecdh_priv_key_generate(enum curve curve_id)
+{
+ struct crypto_testsuite_params_asym *ts_params = &testsuite_params;
+ const struct rte_cryptodev_asymmetric_xform_capability *capa;
+ struct rte_mempool *sess_mpool = ts_params->session_mpool;
+ struct rte_mempool *op_mpool = ts_params->op_mpool;
+ struct rte_cryptodev_asym_capability_idx idx;
+ uint8_t dev_id = ts_params->valid_devs[0];
+ struct rte_crypto_asym_xform xform = {0};
+ struct rte_crypto_op *result_op = NULL;
+ uint8_t output_buf[TEST_DATA_SIZE];
+ struct rte_crypto_asym_op *asym_op;
+ struct rte_crypto_op *op = NULL;
+ int ret, status = TEST_SUCCESS;
+ uint16_t output_buflen = 0;
+ void *sess = NULL;
+ int curve;
+
+ /* Check ECDH capability */
+ idx.type = RTE_CRYPTO_ASYM_XFORM_ECDH;
+ capa = rte_cryptodev_asym_capability_get(dev_id, &idx);
+ if (capa == NULL)
+ return -ENOTSUP;
+
+ if (!(capa->op_types & (1 << RTE_CRYPTO_ASYM_KE_PRIV_KEY_GENERATE)))
+ return -ENOTSUP;
+
+ switch (curve_id) {
+ case SECP192R1:
+ curve = RTE_CRYPTO_EC_GROUP_SECP192R1;
+ output_buflen = 24;
+ break;
+ case SECP224R1:
+ curve = RTE_CRYPTO_EC_GROUP_SECP224R1;
+ output_buflen = 28;
+ break;
+ case SECP256R1:
+ curve = RTE_CRYPTO_EC_GROUP_SECP256R1;
+ output_buflen = 32;
+ break;
+ case SECP384R1:
+ curve = RTE_CRYPTO_EC_GROUP_SECP384R1;
+ output_buflen = 48;
+ break;
+ case SECP521R1:
+ curve = RTE_CRYPTO_EC_GROUP_SECP521R1;
+ output_buflen = 66;
+ break;
+ default:
+ RTE_LOG(ERR, USER1,
+ "line %u FAILED: %s", __LINE__,
+ "Unsupported curve id\n");
+ status = TEST_FAILED;
+ goto exit;
+ }
+
+ /* Setup crypto op data structure */
+ op = rte_crypto_op_alloc(op_mpool, RTE_CRYPTO_OP_TYPE_ASYMMETRIC);
+ if (op == NULL) {
+ RTE_LOG(ERR, USER1,
+ "line %u FAILED: %s", __LINE__,
+ "Failed to allocate asymmetric crypto "
+ "operation struct\n");
+ status = TEST_FAILED;
+ goto exit;
+ }
+ asym_op = op->asym;
+
+ /* Setup asym xform */
+ xform.next = NULL;
+ xform.xform_type = RTE_CRYPTO_ASYM_XFORM_ECDH;
+ xform.ec.curve_id = curve;
+
+ ret = rte_cryptodev_asym_session_create(dev_id, &xform, sess_mpool,
&sess);
+ if (ret < 0) {
+ RTE_LOG(ERR, USER1,
+ "line %u FAILED: %s", __LINE__,
+ "Session creation failed\n");
+ status = (ret == -ENOTSUP) ? TEST_SKIPPED : TEST_FAILED;
+ goto exit;
+ }
+
+ /* Attach asymmetric crypto session to crypto operations */
+ rte_crypto_op_attach_asym_session(op, sess);
+
+ /* Populate op with operational details */
+ asym_op->ecdh.ke_type = RTE_CRYPTO_ASYM_KE_PRIV_KEY_GENERATE;
+
+ /* Init out buf */
+ asym_op->ecdh.priv_key.data = output_buf;
+ asym_op->ecdh.priv_key.length = output_buflen;
+
+ RTE_LOG(DEBUG, USER1, "Process ASYM operation\n");
+
+ /* Process crypto operation */
+ if (rte_cryptodev_enqueue_burst(dev_id, 0, &op, 1) != 1) {
+ RTE_LOG(ERR, USER1,
+ "line %u FAILED: %s", __LINE__,
+
