[dpdk-dev] [PATCH] crypto/qat: fix memzone creation to use a fixed size string
Remove the dependency on dev->driver->pci_drv.name when
creating the memzone for the qat hardware queues.
The pci_drv.name may grow too large for RTE_MEMZONE_NAMESIZE.
Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
Signed-off-by: John Griffin
---
drivers/crypto/qat/qat_qp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c
index 5de47e3..a29ed66 100644
--- a/drivers/crypto/qat/qat_qp.c
+++ b/drivers/crypto/qat/qat_qp.c
@@ -300,7 +300,7 @@ qat_queue_create(struct rte_cryptodev *dev, struct
qat_queue *queue,
* Allocate a memzone for the queue - create a unique name.
*/
snprintf(queue->memz_name, sizeof(queue->memz_name), "%s_%s_%d_%d_%d",
- dev->driver->pci_drv.name, "qp_mem", dev->data->dev_id,
+ "qat_pmd", "qp_mem", dev->data->dev_id,
queue->hw_bundle_number, queue->hw_queue_number);
qp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes,
socket_id);
--
2.1.0
[dpdk-dev] [PATCH] crypto/qat: fix memzone creation to use a fixed size string
Hi Liu,
Comments embedded.
Rgds,
John.
On 05/09/16 04:23, Yuanhan Liu wrote:
> On Thu, Sep 01, 2016 at 11:21:38AM +0100, John Griffin wrote:
>> Remove the dependency on dev->driver->pci_drv.name when
>> creating the memzone for the qat hardware queues.
>> The pci_drv.name may grow too large for RTE_MEMZONE_NAMESIZE.
>
> Will the "may grow too large" cause any issues? If so, state it here. If
> not, marking this patch as a "fix" patch doesn't make sense to me then.
We discovered this when applying a future patch (2141c21966) and it
exposed this issue.
Problem is we create a memzone per hardware queue pair and if the
memzone name is too large, then this code will not produce a unique
name and two qps will end using the same memzone.
In retrospect, I'll wait for Pablo to apply that future patch and then
re-base a v2.
>
>>
>> Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
>>
>> Signed-off-by: John Griffin
>> ---
>> drivers/crypto/qat/qat_qp.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c
>> index 5de47e3..a29ed66 100644
>> --- a/drivers/crypto/qat/qat_qp.c
>> +++ b/drivers/crypto/qat/qat_qp.c
>> @@ -300,7 +300,7 @@ qat_queue_create(struct rte_cryptodev *dev, struct
>> qat_queue *queue,
>> * Allocate a memzone for the queue - create a unique name.
>> */
>> snprintf(queue->memz_name, sizeof(queue->memz_name), "%s_%s_%d_%d_%d",
>> -dev->driver->pci_drv.name, "qp_mem", dev->data->dev_id,
>> +"qat_pmd", "qp_mem", dev->data->dev_id,
>
> Besides that, why not putting "qat_pmd" and "qp_mem" inside the format
> string?
Fair point will send in the v2.
>
> --yliu
>
[dpdk-dev] [PATCH] crypto/qat: fix memzone creation to use a fixed size string
On 18/09/16 09:16, Yuanhan Liu wrote: > On Wed, Sep 14, 2016 at 04:32:46PM +0100, John Griffin wrote: >> Hi Liu, >> Comments embedded. >> >> Rgds, >> John. >> >> On 05/09/16 04:23, Yuanhan Liu wrote: >>> On Thu, Sep 01, 2016 at 11:21:38AM +0100, John Griffin wrote: >>>> Remove the dependency on dev->driver->pci_drv.name when >>>> creating the memzone for the qat hardware queues. >>>> The pci_drv.name may grow too large for RTE_MEMZONE_NAMESIZE. >>> >>> Will the "may grow too large" cause any issues? If so, state it here. If >>> not, marking this patch as a "fix" patch doesn't make sense to me then. >> We discovered this when applying a future patch (2141c21966) and it exposed >> this issue. >> Problem is we create a memzone per hardware queue pair and if the memzone >> name is too large, then this code will not produce a unique >> name and two qps will end using the same memzone. > > Thanks for the info, and I think you should put it in the commit log: it > helps people to really know what might go wrong without this fix. > > --yliu > No problem. Yes will add to the v2. Rgds, John.
[dpdk-dev] [PATCH] Adding maintainers for Intel QAT PMD
On 05/02/16 16:36, Fiona Trahe wrote: > Signed-off-by: Fiona Trahe Acked-by: John Griffin
[dpdk-dev] [PATCH] qat: addition of optimized content descriptor for AES128-SHA1-HMAC
Adding an optimized content descriptor for AES128-SHA1-HMAC to
improve thoughput performance.
Signed-off-by: John Griffin
---
drivers/crypto/qat/qat_adf/qat_algs.h| 7 ++
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 91
drivers/crypto/qat/qat_crypto.c | 64 +
drivers/crypto/qat/qat_crypto.h | 4 ++
4 files changed, 154 insertions(+), 12 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index b47dbc2..28fa111 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -127,4 +127,11 @@ void qat_alg_ablkcipher_init_dec(struct
qat_alg_ablkcipher_cd *cd,
int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
+int qat_crypto_sym_use_optimized_alg(struct qat_session *session);
+int qat_crypto_create_optimzed_session(struct qat_session *session,
+ uint8_t *cipherkey,
+ uint32_t cipherkeylen,
+ uint8_t *authkey,
+ uint32_t authkeylen,
+ uint32_t digestsize);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index aa108d4..8c1a801 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -444,6 +444,7 @@ int qat_alg_aead_session_create_content_desc_cipher(struct
qat_session *cdesc,
header->service_cmd_id = cdesc->qat_cmd;
ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
+
/* Configure the common header protocol flags */
ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags, proto);
cd_pars->u.s.content_desc_addr = cdesc->cd_paddr;
@@ -749,6 +750,96 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
return 0;
}
+/*
+ * Function which will return if it's possible to use the
+ * optimised content descriptor.
+ */
+int qat_crypto_sym_use_optimized_alg(struct qat_session *session)
+{
+ return ((session->qat_mode == ICP_QAT_HW_CIPHER_CBC_MODE)
+ && (session->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128)
+ && (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SHA1));
+}
+
+/*
+ * Function to create an optimised content descriptor for AES128 SHA1.
+ */
+int qat_crypto_create_optimzed_session(struct qat_session *session,
+ uint8_t *cipherkey,
+ uint32_t cipherkeylen,
+ uint8_t *authkey,
+ uint32_t authkeylen,
+ uint32_t digestsize)
+{
+ /* CFG_CIPH_AES128_CBC_ENCRYPT, CFG_AUTH_SHA1_MODE1_NO_NESTED */
+ uint32_t icp_qat_fw_aes128_cbc_sha1_encrypt[] = {0x21120202,
+ 0x422E, 0x1414, 0x18031800, 0};
+ /* CFG_CIPH_AES128_CBC_DECRYPT, CFG_AUTH_SHA1_MODE1_NO_NESTED */
+ uint32_t icp_qat_fw_aes128_cbc_sha1_decrypt[] = {0x41150202,
+ 0x122E, 0x1414, 0x18031800, 0};
+
+ register struct icp_qat_fw_la_bulk_req *qat_req;
+ uint8_t *cd_ptr = (uint8_t *)&session->cd;
+ uint16_t state2_size;
+ struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl;
+
+ /*
+* Setup the template for the request.
+*/
+ qat_req = &session->fw_req;
+
+ /*
+* Setup some hard coded values for the constant config table.
+*/
+ if (session->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
+ memcpy(&qat_req->cd_ctrl, icp_qat_fw_aes128_cbc_sha1_encrypt,
+ sizeof(icp_qat_fw_aes128_cbc_sha1_encrypt));
+ qat_req->comn_hdr.serv_specif_flags = 0x2c;
+ } else {
+ memcpy(&qat_req->cd_ctrl, icp_qat_fw_aes128_cbc_sha1_decrypt,
+ sizeof(icp_qat_fw_aes128_cbc_sha1_decrypt));
+ qat_req->comn_hdr.serv_specif_flags = 0x4c;
+ }
+
+ /*
+* Cope with a digest size != 0x14
+*/
+ if (digestsize != 0x14) {
+ hash_cd_ctrl = (struct icp_qat_fw_auth_cd_ctrl_hdr *)
+ &qat_req->cd_ctrl;
+ hash_cd_ctrl->inner_res_sz = digestsize;
+ hash_cd_ctrl->final_sz = digestsize;
+ struct icp_qat_fw_la_auth_req_params *auth_param =
+ (struct icp_qat_fw_la_auth_req_params *)
+ ((char *)&a
[dpdk-dev] [PATCH] app/test: fix for icc compilation error
On 22/06/16 17:13, Deepak Kumar Jain wrote:
> Icc complains about variable may be used without setting.
>
> Fixes: 97fe6461c7cbfb ("app/test: add SNOW 3G performance test)
>
> Signed-off-by: Deepak Kumar Jain
Acked-by: John Griffin
[dpdk-dev] [PATCH 0/3] AES GCM, AES CMAC fixes and addition of GCM tests for QAT.
This patchset solves an issue in QAT driver, that was giving invalid AES GCM results, due to incorrect IV setting. It adds unit tests to validate AES GCM in QAT. It also fixes the premature addition of AES CMAC support which was added to the code in error. AES CMAC will be added in a subsequent release when testing completes. AES CMAC was not advertised in the qat documentation. This patchset depends on patches: - aesni_gcm: PMD to support AES_GCM crypto operations (http://dpdk.org/dev/patchwork/patch/11201/) John Griffin (3): qat: fix AES GCM decryption app/test: add AES GCM tests for QAT qat: fixes premature addition of AES_CMAC in session app/test/test_cryptodev.c | 34 +- doc/guides/cryptodevs/qat.rst | 1 + doc/guides/rel_notes/release_16_04.rst | 5 + drivers/crypto/qat/qat_crypto.c| 24 4 files changed, 59 insertions(+), 5 deletions(-) -- 2.1.0
[dpdk-dev] [PATCH 1/3] qat: fix AES GCM decryption
AES GCM on the cryptodev API was giving invalid results
in some cases, due to an incorrect IV setting.
Added AES GCM in the QAT supported algorithms,
as encryption/decryption is fully functional.
Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
Signed-off-by: John Griffin
---
doc/guides/cryptodevs/qat.rst | 1 +
doc/guides/rel_notes/release_16_04.rst | 5 +
drivers/crypto/qat/qat_crypto.c| 22 +++---
3 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index af52047..ec4d6c6 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -48,6 +48,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_SYM_CIPHER_AES192_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_AES256_CBC``
* ``RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_AES_GCM``
Hash algorithms:
diff --git a/doc/guides/rel_notes/release_16_04.rst
b/doc/guides/rel_notes/release_16_04.rst
index d7a264a..ee8d141 100644
--- a/doc/guides/rel_notes/release_16_04.rst
+++ b/doc/guides/rel_notes/release_16_04.rst
@@ -99,6 +99,11 @@ Drivers
This made impossible the creation of more than one aesni_mb device
from command line.
+* **qat: Fixed AES GCM decryption.**
+
+ Allowed AES GCM on the cryptodev API, but in some cases gave invalid results
+ due to incorrect IV setting.
+
Libraries
~
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index cb16aae..48e810f 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -529,11 +529,27 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t
*out_msg)
auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
/* (GCM) aad length(240 max) will be at this location after precompute
*/
if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
- ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
- auth_param->u2.aad_sz =
- ALIGN_POW2_ROUNDUP(ctx->cd.hash.sha.state1[
+ ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
+ struct icp_qat_hw_auth_algo_blk *hash;
+
+ if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER)
+ hash = (struct icp_qat_hw_auth_algo_blk *)((char
*)&ctx->cd);
+ else
+ hash = (struct icp_qat_hw_auth_algo_blk *)((char
*)&ctx->cd +
+ sizeof(struct icp_qat_hw_cipher_algo_blk));
+
+ auth_param->u2.aad_sz = ALIGN_POW2_ROUNDUP(hash->sha.state1[
ICP_QAT_HW_GALOIS_128_STATE1_SZ +
ICP_QAT_HW_GALOIS_H_SZ + 3], 16);
+ if (op->sym->cipher.iv.length == 12) {
+ /*
+* For GCM a 12 bit IV is allowed,
+* but we need to inform the f/w
+*/
+ ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
+ qat_req->comn_hdr.serv_specif_flags,
+ ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
+ }
}
auth_param->hash_state_sz = (auth_param->u2.aad_sz) >> 3;
--
2.1.0
[dpdk-dev] [PATCH 2/3] app/test: add AES GCM tests for QAT
Signed-off-by: John Griffin
---
app/test/test_cryptodev.c | 34 +-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index d7e80c4..a5d4208 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -3420,6 +3420,39 @@ static struct unit_test_suite cryptodev_qat_testsuite =
{
TEST_CASE_ST(ut_setup, ut_teardown,
test_AES_CBC_HMAC_AES_XCBC_decrypt_digest_verify),
TEST_CASE_ST(ut_setup, ut_teardown, test_stats),
+
+ /** AES GCM Authenticated Encryption */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_encryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_encryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_encryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_encryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_encryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_encryption_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_encryption_test_case_7),
+
+ /** AES GCM Authenticated Decryption */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_decryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_decryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_decryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_decryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_decryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_decryption_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_authenticated_decryption_test_case_7),
+
/** Snow3G encrypt only (UEA2) */
TEST_CASE_ST(ut_setup, ut_teardown,
test_snow3g_encryption_test_case_1),
@@ -3432,7 +3465,6 @@ static struct unit_test_suite cryptodev_qat_testsuite = {
TEST_CASE_ST(ut_setup, ut_teardown,
test_snow3g_encryption_test_case_5),
-
/** Snow3G decrypt only (UEA2) */
TEST_CASE_ST(ut_setup, ut_teardown,
test_snow3g_decryption_test_case_1),
--
2.1.0
[dpdk-dev] [PATCH 3/3] qat: fixes premature addition of AES_CMAC in session creation
Remove support for AES CMAC support for which was added to
the code in error. AES CMAC will be added in a subsequent release
when testing completes.
Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
Signed-off-by: John Griffin
---
drivers/crypto/qat/qat_crypto.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 48e810f..366a064 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -295,7 +295,6 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev
*dev,
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
break;
case RTE_CRYPTO_AUTH_AES_GCM:
- case RTE_CRYPTO_AUTH_AES_GMAC:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
break;
case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
@@ -312,6 +311,7 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev
*dev,
case RTE_CRYPTO_AUTH_MD5:
case RTE_CRYPTO_AUTH_MD5_HMAC:
case RTE_CRYPTO_AUTH_AES_CCM:
+ case RTE_CRYPTO_AUTH_AES_GMAC:
case RTE_CRYPTO_AUTH_KASUMI_F9:
case RTE_CRYPTO_AUTH_AES_CMAC:
case RTE_CRYPTO_AUTH_AES_CBC_MAC:
--
2.1.0
[dpdk-dev] [PATCH v4] aesni_gcm: PMD to support AES_GCM crypto operations
On 10/03/16 16:41, Pablo de Lara wrote: > From: Declan Doherty > > This patch provides the implementation of an AES-NI accelerated crypto PMD > which is dependent on Intel's multi-buffer library, see the white paper > "Fast Multi-buffer IPsec Implementations on Intel? Architecture Processors" > > This PMD supports AES_GCM authenticated encryption and authenticated > decryption using > 128-bit AES keys > > The patch also contains the related unit tests functions for the implemented > functionality > > Signed-off-by: Declan Doherty > Signed-off-by: Pablo de Lara > -- Acked-by: John Griffin
[dpdk-dev] [PATCH 3/3] qat: fixes premature addition of AES_CMAC in session creation
On 11/03/16 00:16, Thomas Monjalon wrote: > 2016-03-08 16:22, John Griffin: >> Remove support for AES CMAC support for which was added to >> the code in error. AES CMAC will be added in a subsequent release >> when testing completes. > [...] >> case RTE_CRYPTO_AUTH_AES_GCM: >> -case RTE_CRYPTO_AUTH_AES_GMAC: > > CMAC or GMAC? Yes GMAC - thanks Pablo and Thomas.
[dpdk-dev] [PATCH v2 0/2] Out of place operations for symmetric crypto
On 29/03/16 15:14, Fiona Trahe wrote: > From: Arek Kusztal > > This patch adds out of place operations for qat symmetric crypto PMD, > i.e. the result of the operation can be written to the destination buffer > instead of overwriting the source buffer as done in "in-place" operation. > > v2: > - updated commit message to clarify out-of-place meaning > > > Arek Kusztal (2): >driver/crypto: out-of-place symmetric operations >app/test: added test for out-of-place symmetric operations > > app/test/test_cryptodev.c | 495 > ++- > doc/guides/cryptodevs/qat.rst |1 - > drivers/crypto/qat/qat_crypto.c | 22 +- > 3 files changed, 504 insertions(+), 14 deletions(-) > Acked-by: John Griffin
[dpdk-dev] [PATCH] qat: change the session structure to be variable sized
This patch changes the qat session data structure sent to qat from a
fixed size to a variable size which is dependent on the size of
the chosen algorithm.
This reduces the amount of bytes which are transferred across
PCIe and thus helps to increase qat performance when the
accelerator is bound by PCIe.
Signed-off-by: John Griffin
---
drivers/crypto/qat/qat_adf/qat_algs.h| 5 +-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 462 +--
drivers/crypto/qat/qat_crypto.c | 15 +-
3 files changed, 183 insertions(+), 299 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 243c1b4..6a86053 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -87,8 +87,10 @@ struct qat_session {
enum icp_qat_hw_cipher_mode qat_mode;
enum icp_qat_hw_auth_algo qat_hash_alg;
struct qat_alg_cd cd;
+ uint8_t *cd_cur_ptr;
phys_addr_t cd_paddr;
struct icp_qat_fw_la_bulk_req fw_req;
+ uint8_t aad_len;
struct qat_crypto_instance *inst;
uint8_t salt[ICP_QAT_HW_AES_BLK_SZ];
rte_spinlock_t lock;/* protects this struct */
@@ -115,7 +117,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
uint32_t digestsize,
unsigned int operation);
-void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);
+void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ uint16_t proto);
void qat_alg_ablkcipher_init_enc(struct qat_alg_ablkcipher_cd *cd,
int alg, const uint8_t *key,
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 185bb33..6de8919 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -344,7 +344,8 @@ static int qat_alg_do_precomputes(enum icp_qat_hw_auth_algo
hash_alg,
return 0;
}
-void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header)
+void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ uint16_t proto)
{
PMD_INIT_FUNC_TRACE();
header->hdr_flags =
@@ -358,7 +359,7 @@ void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr
*header)
ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(header->serv_specif_flags,
ICP_QAT_FW_CIPH_IV_16BYTE_DATA);
ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
- ICP_QAT_FW_LA_NO_PROTO);
+ proto);
ICP_QAT_FW_LA_UPDATE_STATE_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_NO_UPDATE_STATE);
}
@@ -375,127 +376,88 @@ int
qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
enum icp_qat_hw_cipher_convert key_convert;
+ uint32_t total_key_size;
uint16_t proto = ICP_QAT_FW_LA_NO_PROTO;/* no CCM/GCM/Snow3G */
- uint16_t cipher_offset = 0;
+ uint16_t cipher_offset, cd_size;
PMD_INIT_FUNC_TRACE();
- if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER &&
- cdesc->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
- cipher =
- (struct icp_qat_hw_cipher_algo_blk *)((char *)&cdesc->cd +
- sizeof(struct icp_qat_hw_auth_algo_blk));
- cipher_offset = sizeof(struct icp_qat_hw_auth_algo_blk);
- } else {
- cipher = (struct icp_qat_hw_cipher_algo_blk *)&cdesc->cd;
- cipher_offset = 0;
- }
- /* CD setup */
- if (cdesc->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
- ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
- ICP_QAT_FW_LA_RET_AUTH_RES);
- ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
- ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
- } else {
+ if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
+ cd_pars->u.s.content_desc_addr = cdesc->cd_paddr;
+ ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl,
+ ICP_QAT_FW_SLICE_CIPHER);
+ ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_NO_RET_AUTH_RES);
[dpdk-dev] [PATCH] qat: change the session structure to be variable sized
On 02/08/16 09:30, John Griffin wrote: > This patch changes the qat session data structure sent to qat from a > fixed size to a variable size which is dependent on the size of > the chosen algorithm. > This reduces the amount of bytes which are transferred across > PCIe and thus helps to increase qat performance when the > accelerator is bound by PCIe. > > Signed-off-by: John Griffin > --- > drivers/crypto/qat/qat_adf/qat_algs.h| 5 +- > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 462 > +-- > drivers/crypto/qat/qat_crypto.c | 15 +- > 3 files changed, 183 insertions(+), 299 deletions(-) > Self-Nack compile issue on icc - will fix and send again.
[dpdk-dev] [PATCH v1] crypto/qat: make the session struct variable in size
This patch changes the qat firmware session data structure from a fixed
size to a variable size which is dependent on the size of the chosen
algorithm.
This reduces the amount of bytes which are transferred across
PCIe and thus helps to increase qat performance when the
accelerator is bound by PCIe.
Signed-off-by: John Griffin
---
v1:
* Fixed a compile issue with icc.
drivers/crypto/qat/qat_adf/qat_algs.h| 5 +-
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 463 +--
drivers/crypto/qat/qat_crypto.c | 15 +-
3 files changed, 184 insertions(+), 299 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 243c1b4..6a86053 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -87,8 +87,10 @@ struct qat_session {
enum icp_qat_hw_cipher_mode qat_mode;
enum icp_qat_hw_auth_algo qat_hash_alg;
struct qat_alg_cd cd;
+ uint8_t *cd_cur_ptr;
phys_addr_t cd_paddr;
struct icp_qat_fw_la_bulk_req fw_req;
+ uint8_t aad_len;
struct qat_crypto_instance *inst;
uint8_t salt[ICP_QAT_HW_AES_BLK_SZ];
rte_spinlock_t lock;/* protects this struct */
@@ -115,7 +117,8 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
uint32_t digestsize,
unsigned int operation);
-void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);
+void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ uint16_t proto);
void qat_alg_ablkcipher_init_enc(struct qat_alg_ablkcipher_cd *cd,
int alg, const uint8_t *key,
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 185bb33..c658f6e 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -344,7 +344,8 @@ static int qat_alg_do_precomputes(enum icp_qat_hw_auth_algo
hash_alg,
return 0;
}
-void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header)
+void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ uint16_t proto)
{
PMD_INIT_FUNC_TRACE();
header->hdr_flags =
@@ -358,7 +359,7 @@ void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr
*header)
ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(header->serv_specif_flags,
ICP_QAT_FW_CIPH_IV_16BYTE_DATA);
ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
- ICP_QAT_FW_LA_NO_PROTO);
+ proto);
ICP_QAT_FW_LA_UPDATE_STATE_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_NO_UPDATE_STATE);
}
@@ -375,127 +376,88 @@ int
qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
enum icp_qat_hw_cipher_convert key_convert;
+ uint32_t total_key_size;
uint16_t proto = ICP_QAT_FW_LA_NO_PROTO;/* no CCM/GCM/Snow3G */
- uint16_t cipher_offset = 0;
+ uint16_t cipher_offset, cd_size;
PMD_INIT_FUNC_TRACE();
- if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER &&
- cdesc->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
- cipher =
- (struct icp_qat_hw_cipher_algo_blk *)((char *)&cdesc->cd +
- sizeof(struct icp_qat_hw_auth_algo_blk));
- cipher_offset = sizeof(struct icp_qat_hw_auth_algo_blk);
- } else {
- cipher = (struct icp_qat_hw_cipher_algo_blk *)&cdesc->cd;
- cipher_offset = 0;
- }
- /* CD setup */
- if (cdesc->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
- ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
- ICP_QAT_FW_LA_RET_AUTH_RES);
- ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
- ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
- } else {
+ if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
+ cd_pars->u.s.content_desc_addr = cdesc->cd_paddr;
+ ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl,
+ ICP_QAT_FW_SLICE_CIPHER);
+ ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_NO_RET
[dpdk-dev] [PATCH] crypto/qat: optimisation of request copy
On 04/08/16 13:00, Fiona Trahe wrote: > From: Fiona Trahe > > using rte_mov128 instead of structure assignment to copy > template request from session context into request > > Signed-off-by: Fiona Trahe > > --- > drivers/crypto/qat/qat_crypto.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: John Griffin
[dpdk-dev] [PATCH] Correcting upstream kernel version in driver
Fixing the version of the kernel required in the QAT documentation. Signed-off-by: John Griffin --- doc/guides/cryptodevs/qat.rst | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 1901842..23402b4 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -33,7 +33,7 @@ Quick Assist Crypto Poll Mode Driver The QAT PMD provides poll mode crypto driver support for **Intel QuickAssist Technology DH895xxC** hardware accelerator. -The QAT PMD has been tested on Fedora 21 64-bit with gcc and on the 4.3 +The QAT PMD has been tested on Fedora 21 64-bit with gcc and on the 4.4 kernel.org Linux kernel. @@ -73,9 +73,9 @@ Installation To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF devices exposed by this driver will be used by QAT PMD. -If you are running on kernel 4.3 or greater, see instructions for +If you are running on kernel 4.4 or greater, see instructions for `Installation using kernel.org driver`_ below. If you are on a kernel earlier -than 4.3, see `Installation using 01.org QAT driver`_. +than 4.4, see `Installation using 01.org QAT driver`_. Installation using 01.org QAT driver @@ -157,13 +157,13 @@ If the build or install fails due to mismatching kernel sources you may need to Installation using kernel.org driver -Assuming you are running on at least a 4.3 kernel, you can use the stock kernel.org QAT +Assuming you are running on at least a 4.4 kernel, you can use the stock kernel.org QAT driver to start the QAT hardware. The steps below assume you are: * Running DPDK on a platform with one ``DH895xCC`` device. -* On a kernel at least version 4.3. +* On a kernel at least version 4.4. In BIOS ensure that SRIOV is enabled and VT-d is disabled. @@ -190,7 +190,7 @@ Using the sysfs, enable the VFs:: echo 32 > /sys/bus/pci/drivers/dh895xcc/\:03\:00.0/sriov_numvfs -If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.3. +If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.4. To verify that the VFs are available for use - use ``lspci -d:443`` to confirm the bdf of the 32 VF devices are available per ``DH895xCC`` device. -- 2.1.0
[dpdk-dev] [PATCH] qat pmd:Fixing build issue on 32-bit systems
Fixing build issue on 32-bit systems.
Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
Signed-off-by: John Griffin
---
drivers/crypto/qat/qat_crypto.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 129e96d..828756b 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -342,7 +342,7 @@ qat_crypto_pkt_rx_burst(void *qp, struct rte_mbuf
**rx_pkts, uint16_t nb_pkts)
while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
msg_counter != nb_pkts) {
- rx_mbuf = (struct rte_mbuf *)(resp_msg->opaque_data);
+ rx_mbuf = (struct rte_mbuf *)(uintptr_t)(resp_msg->opaque_data);
ol = rte_pktmbuf_offload_get(rx_mbuf, RTE_PKTMBUF_OL_CRYPTO);
if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
@@ -405,7 +405,7 @@ qat_alg_write_mbuf_entry(struct rte_mbuf *mbuf, uint8_t
*out_msg)
ctx = (struct qat_session *)ol->op.crypto.session->_private;
qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
*qat_req = ctx->fw_req;
- qat_req->comn_mid.opaque_data = (uint64_t)mbuf;
+ qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)mbuf;
/*
* The following code assumes:
--
2.1.0
[dpdk-dev] [PATCH] qat pmd:Fixing build issue on 32-bit systems
Hi Pablo,
Sure - will resubmit a v2 with those modifications.
Thanks,
John.
On 16/02/16 15:52, De Lara Guarch, Pablo wrote:
> Hi John,
>
>> -Original Message-
>> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of John Griffin
>> Sent: Tuesday, February 16, 2016 9:45 AM
>> To: dev at dpdk.org
>> Subject: [dpdk-dev] [PATCH] qat pmd:Fixing build issue on 32-bit systems
>>
>> Fixing build issue on 32-bit systems.
>> Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
>>
>> Signed-off-by: John Griffin
> Acked-by: Pablo de Lara
>
> Could you include the error that you are fixing on this patch?
>
> For example:
>
> drivers/crypto/qat/qat_crypto.c:345:13:
> error: cast to pointer from integer of different size
> [-Werror=int-to-pointer-cast]
>
> Also, as a general rule, patch titles start with lowercase and do not include
> the name "issue" if we use "fix".
> e.g. (qat: fix build on 32-bit systems).
>
> Apart from this, patch looks OK to me, so you can leave the acknowledgment in
> the v2.
>
> Thanks!
> Pablo
>
[dpdk-dev] [PATCH v2] qat:fix build on 32-bit systems
Fixing build on 32-bit systems on quick assist driver - for example:
drivers/crypto/qat/qat_crypto.c: In function ?qat_alg_write_mbuf_entry?:
drivers/crypto/qat/qat_crypto.c:408:34: error: cast from pointer to integer of
different size [-Werror=pointer-to-int-cast]
Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
Signed-off-by: John Griffin
Acked-by: Pablo de Lara
---
v1->v2:
- Corrected subject text and included build failure.
drivers/crypto/qat/qat_crypto.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 129e96d..828756b 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -342,7 +342,7 @@ qat_crypto_pkt_rx_burst(void *qp, struct rte_mbuf
**rx_pkts, uint16_t nb_pkts)
while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
msg_counter != nb_pkts) {
- rx_mbuf = (struct rte_mbuf *)(resp_msg->opaque_data);
+ rx_mbuf = (struct rte_mbuf *)(uintptr_t)(resp_msg->opaque_data);
ol = rte_pktmbuf_offload_get(rx_mbuf, RTE_PKTMBUF_OL_CRYPTO);
if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
@@ -405,7 +405,7 @@ qat_alg_write_mbuf_entry(struct rte_mbuf *mbuf, uint8_t
*out_msg)
ctx = (struct qat_session *)ol->op.crypto.session->_private;
qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
*qat_req = ctx->fw_req;
- qat_req->comn_mid.opaque_data = (uint64_t)mbuf;
+ qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)mbuf;
/*
* The following code assumes:
--
2.1.0
[dpdk-dev] [PATCH v2] doc: add known issue on QAT PMD into release notes
On 10/11/16 17:27, Fiona Trahe wrote: > Issue is with the digest appended feature on QAT PMD. > A workaround is also documented. > > Signed-off-by: Fiona Trahe > Acked-by: John McNamara > --- > v2 > - fixed trailing whitespace checkpatch errors > Acked-by: John Griffin
[dpdk-dev] [PATCH] crypto: remove unused digest-appended feature
On 17/11/16 17:33, Fiona Trahe wrote: > The cryptodev API had specified that if the digest address field was > left empty on an authentication operation, then the PMD would assume > the digest was appended to the source or destination data. > This case was not handled at all by most PMDs and incorrectly handled > by the QAT PMD. > As no bugs were raised, it is assumed to be not needed, so this patch > removes it, rather than add handling for the case on all PMDs. > The digest can still be appended to the data, but its > address must now be provided in the op. > > Signed-off-by: Fiona Trahe > --- > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++ > drivers/crypto/qat/qat_crypto.c | 18 +- > lib/librte_cryptodev/rte_crypto_sym.h| 10 +- > 3 files changed, 4 insertions(+), 26 deletions(-) > Acked-by: John Griffin
