Re: [dpdk-dev] [PATCH] crypto: fix incorrect key setting
> -Original Message-
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Pablo de Lara
> Sent: Tuesday, February 7, 2017 10:50 PM
> To: dev@dpdk.org
> Cc: De Lara Guarch, Pablo ;
> sta...@dpdk.org
> Subject: [dpdk-dev] [PATCH] crypto: fix incorrect key setting
>
> When ciphering and authenticating in the same operation (cipher-then-auth
> or auth-then-cipher), the cipher key and authentication key was set with the
> same key, in SNOW3G, KASUMI and ZUC PMDs.
> They were using the key of the first transform structure, instead of using the
> keys of the two different transform structures.
>
> This is not a big issue, since usually, the same key is used for ciphering and
> authentication, but keys may be different.
>
> Fixes: 3aafc423cf4d ("snow3g: add driver for SNOW 3G library")
> Fixes: 2773c86d061a ("crypto/kasumi: add driver for KASUMI library")
> Fixes: cf7685d68f00 ("crypto/zuc: add driver for ZUC library")
>
> CC: sta...@dpdk.org
> Signed-off-by: Pablo de Lara
> ---
> drivers/crypto/kasumi/rte_kasumi_pmd.c | 4 ++--
> drivers/crypto/snow3g/rte_snow3g_pmd.c | 4 ++--
> drivers/crypto/zuc/rte_zuc_pmd.c | 6 --
> 3 files changed, 8 insertions(+), 6 deletions(-)
>
> --
> 2.7.4
Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] DPDK Accelaration Enhancement
HI Anthony, > -Original Message- > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ant loves honey > Sent: Saturday, December 24, 2016 10:56 PM > To: dev@dpdk.org > Subject: [dpdk-dev] DPDK Accelaration Enhancement > > Currently DPDK has the crypto PMD (.../drivers/crypto/qat/) and example > code (.../examples/dpdk_qat). > Intel QuickAssist Technology also supports compression along with > crypto. Last weekend, there is a proposed project to Intel Dev Mesh - "A > VPP plugin utilizing Intel QucikAssist Technology to perform hardware > assisted compression operations" > > https://devmesh.intel.com/projects/a-vpp-plugin-utilizing-intel-quickassist- > technology-to-perform-hardware-assisted-compression-operation > > Do we need a new PMD driver for compression or should we modify the > exiting crypto/qat driver to also support compression? There is still NO compression support in DPDK which utilizes Intel(R) QuickAssist Technology. > > The Intel QAT driver should be present in any Linux kernel greater than > version 4.4 > > I am trying to put the pieces together and hitting a roadblock. I am also > figuring how the PMD driver is interacting with the Intel QAT driver at the > code level. > Any pointer on how to move forward is greatly appreciated. > Please also let me know if I should modify the proposed project. > Have you gone through the Crypto Documentation on dpdk.org and release notes (qat.rst) for more information? > Merry Christmas and Happy New Year, > Anthony. Regards, Deepak
Re: [dpdk-dev] [PATCH] crypto/qat: fix typo
> -Original Message-
> From: De Lara Guarch, Pablo
> Sent: Thursday, June 29, 2017 12:16 PM
> To: Trahe, Fiona ; Griffin, John
> ; Jain, Deepak K
> Cc: dev@dpdk.org; De Lara Guarch, Pablo ;
> sta...@dpdk.org
> Subject: [PATCH] crypto/qat: fix typo
>
> Fixed a comment in QAT, referring to the IV size for AES-GCM, that should be
> in bytes, and not bits.
>
> Fixes: 53d8971cbe81 ("qat: fix AES-GCM decryption")
> CC: sta...@dpdk.org
>
> Signed-off-by: Pablo de Lara
> ---
> --
> 2.9.4
Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH] doc: announce crypto vdev init removal
> -Original Message- > From: De Lara Guarch, Pablo > Sent: Thursday, August 3, 2017 3:12 AM > To: tho...@monjalon.net; jerin.ja...@caviumnetworks.com; > akhil.go...@nxp.com; hemant.agra...@nxp.com; Trahe, Fiona > ; Jain, Deepak K ; > Griffin, John ; Doherty, Declan > ; Mcnamara, John > > Cc: dev@dpdk.org; De Lara Guarch, Pablo > Subject: [PATCH] doc: announce crypto vdev init removal > > In order to remove all dependencies on vdev for cryptodev, the > implementation of rte_cryptodev_vdev_pmd_init() function needs to be > moved to rte_cryptodev_vdev.h, and all crypto vdevs will include it, and > therefore, this function will be removed as a public API. > > Signed-off-by: Pablo de Lara > --- > doc/guides/rel_notes/deprecation.rst | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/doc/guides/rel_notes/deprecation.rst > b/doc/guides/rel_notes/deprecation.rst >be removed in 17.11: > >- ``rte_cryptodev_create_vdev`` > + > +* cryptodev: the following function will be static in 17.11 and > +included > + by all crypto drivers, therefore, will not be public: > + > + - ``rte_cryptodev_vdev_pmd_init`` > -- > 2.9.4 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH] doc: announce crypto vdev init removal
> -Original Message- > From: De Lara Guarch, Pablo > Sent: Thursday, August 3, 2017 3:12 AM > To: tho...@monjalon.net; jerin.ja...@caviumnetworks.com; > akhil.go...@nxp.com; hemant.agra...@nxp.com; Trahe, Fiona > ; Jain, Deepak K ; > Griffin, John ; Doherty, Declan > ; Mcnamara, John > > Cc: dev@dpdk.org; De Lara Guarch, Pablo > Subject: [PATCH] doc: announce crypto vdev init removal > > In order to remove all dependencies on vdev for cryptodev, the > implementation of rte_cryptodev_vdev_pmd_init() function needs to be > moved to rte_cryptodev_vdev.h, and all crypto vdevs will include it, and > therefore, this function will be removed as a public API. > > Signed-off-by: Pablo de Lara > --- > doc/guides/rel_notes/deprecation.rst | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/doc/guides/rel_notes/deprecation.rst > b/doc/guides/rel_notes/deprecation.rst > index f6bd910..63ffad1 100644 > --- a/doc/guides/rel_notes/deprecation.rst > +++ b/doc/guides/rel_notes/deprecation.rst > @@ -69,3 +69,8 @@ Deprecation Notices >be removed in 17.11: > >- ``rte_cryptodev_create_vdev`` > + > +* cryptodev: the following function will be static in 17.11 and > +included > + by all crypto drivers, therefore, will not be public: > + > + - ``rte_cryptodev_vdev_pmd_init`` > -- > 2.9.4 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH] doc: announce API change in crypto driver allocation
> -Original Message- > From: De Lara Guarch, Pablo > Sent: Thursday, August 3, 2017 2:03 AM > To: tho...@monjalon.net; jerin.ja...@caviumnetworks.com; > akhil.go...@nxp.com; hemant.agra...@nxp.com; Trahe, Fiona > ; Jain, Deepak K ; > Griffin, John ; Doherty, Declan > > Cc: dev@dpdk.org; De Lara Guarch, Pablo > Subject: [PATCH] doc: announce API change in crypto driver allocation > > rte_cryptodev_allocate_driver() function gets one parameter (rte_driver), as > the cryptodev_driver structure is allocated inside the function with > rte_malloc. > > This function is called from a constructor function, when crypto PMDs are > registered. > If malloc fails, there is no way to recover from it, so it is better to > allocate this > structure statically, in each PMD. > > Therefore, it is required to add an extra parameter in this function, to also > get a pointer to this structure. > >- ``rte_cryptodev_create_vdev`` > + > +* cryptodev: the following function will have an extra parameter, > +passing a > + statically allocated crypto driver structure, instead of calling > +malloc, > + in 17.11: > + > + - ``rte_cryptodev_allocate_driver`` > -- > 2.9.4 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH v2 1/3] crypto/qat: add support for Intel QAT device D15xx
> -Original Message- > From: Trahe, Fiona > Sent: Thursday, March 9, 2017 7:21 PM > To: dev@dpdk.org; De Lara Guarch, Pablo > ; Kusztal, ArkadiuszX > > Cc: Jain, Deepak K ; Trahe, Fiona > ; Griffin, John > Subject: [PATCH v2 1/3] crypto/qat: add support for Intel QAT device D15xx > > Add support for Intel QuickAssist Technology device D15xx > > Signed-off-by: Fiona Trahe > --- > drivers/crypto/qat/rte_qat_cryptodev.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/crypto/qat/rte_qat_cryptodev.c > b/drivers/crypto/qat/rte_qat_cryptodev.c > 2.5.0 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH v3 1/3] crypto/qat: add support for Intel QAT device D15xx
> -Original Message-
> From: Trahe, Fiona
> Sent: Monday, April 3, 2017 3:13 PM
> To: dev@dpdk.org; De Lara Guarch, Pablo
> Cc: Trahe, Fiona ; Jain, Deepak K
> ; Mcnamara, John
> Subject: [PATCH v3 1/3] crypto/qat: add support for Intel QAT device D15xx
>
> Add support for Intel QuickAssist Technology device D15xx
>
> Signed-off-by: Fiona Trahe
> ---
> drivers/crypto/qat/rte_qat_cryptodev.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/crypto/qat/rte_qat_cryptodev.c
> b/drivers/crypto/qat/rte_qat_cryptodev.c
> index 5b34f5e..386a449 100644
> --- a/drivers/crypto/qat/rte_qat_cryptodev.c
> +++ b/drivers/crypto/qat/rte_qat_cryptodev.c
> @@ -77,6 +77,9 @@ static const struct rte_pci_id pci_id_qat_map[] = {
> {
> RTE_PCI_DEVICE(0x8086, 0x19e3),
> },
> + {
> + RTE_PCI_DEVICE(0x8086, 0x6f55),
> + },
> {.device_id = 0},
> };
>
> --
> 2.5.0
Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH] doc: clarify Multi-Buffer library version support
> -Original Message- > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Pablo de Lara > Sent: Friday, February 10, 2017 12:34 PM > To: dec...@intel.com; Mcnamara, John > Cc: dev@dpdk.org; De Lara Guarch, Pablo > Subject: [dpdk-dev] [PATCH] doc: clarify Multi-Buffer library version support > > AES-NI MB PMD uses external Multi-Buffer library, which is hosted in github, > but the version was not specified in the documentation. > > Signed-off-by: Pablo de Lara > --- > doc/guides/cryptodevs/aesni_mb.rst | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/doc/guides/cryptodevs/aesni_mb.rst > b/doc/guides/cryptodevs/aesni_mb.rst > index 8b18eba..a492b6f 100644 > --- a/doc/guides/cryptodevs/aesni_mb.rst > +++ b/doc/guides/cryptodevs/aesni_mb.rst > @@ -70,9 +70,11 @@ Limitations > Installation > > > -To build DPDK with the AESNI_MB_PMD the user is required to download > -- > 2.7.4 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH v2] cryptodev: enable BPI for Cablelabs DOCSIS security spec
> -Original Message- > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Pablo de Lara > Sent: Thursday, February 23, 2017 2:03 PM > To: Doherty, Declan ; Trahe, Fiona > > Cc: dev@dpdk.org; De Lara Guarch, Pablo > Subject: [dpdk-dev] [PATCH v2] cryptodev: enable BPI for Cablelabs DOCSIS > security spec > > Extend the DPDK cryptodev API to enable processing of packets according to > the Baseline Privacy Interface Plus (BPI+) Specification described in the > security specification of the Cablelabs Data-over-Cable Service Interface > Specification (DOCSIS). > > Two new elements are added to the enum rte_crypto_cipher_algorithm. > Note elements of this enum are actually a combination of an algorithm (AES, > 3DES, etc) and mode (CBC, CTR, etc). The new DOCSISBPI mode is used to > convey to the PMD that the mode applied should be the specific combination > of CBC and CFB required by the DOCSIS Baseline Privacy Plus Spec. > > Signed-off-by: Fiona Trahe > Signed-off-by: Pablo de Lara > --- > 2.7.4 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH v2] crypto/openssl: add DES DOCSIS BPI support
> -Original Message- > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Pablo de Lara > Sent: Thursday, February 23, 2017 3:22 PM > To: Doherty, Declan > Cc: dev@dpdk.org; De Lara Guarch, Pablo > Subject: [dpdk-dev] [PATCH v2] crypto/openssl: add DES DOCSIS BPI support > > Adds support in OpenSSL for algorithm following the DOCSIS specification, > which combines DES-CBC for full DES blocks (8 bytes) and DES-CFB for last > runt block (less than 8 bytes). > > Signed-off-by: Pablo de Lara > --- > This patch depends on patch http://dpdk.org/dev/patchwork/patch/20691/. > > Changes in v2: > - Added patch dependency note > - Fixed the commit message > -- > 2.7.4 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH 1/4] crypto/qat: adding docsisbpi mode support
> -Original Message- > From: Trahe, Fiona > Sent: Thursday, March 2, 2017 1:03 PM > To: dev@dpdk.org; De Lara Guarch, Pablo > Cc: Jain, Deepak K ; Trahe, Fiona > > Subject: [PATCH 1/4] crypto/qat: adding docsisbpi mode support > > DOCSISPBI mode is handled in the QAT PMD by sending full blocks to the > hardware device for encryption and using openssl libcrypto for pre- or post- > processing of any partial blocks. > > Signed-off-by: Fiona Trahe > --- > doc/guides/cryptodevs/overview.rst | 2 + > doc/guides/cryptodevs/qat.rst| 2 + > doc/guides/rel_notes/release_17_05.rst | 6 + > drivers/crypto/qat/qat_adf/qat_algs.h| 4 + > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 34 ++- > drivers/crypto/qat/qat_crypto.c | 305 > ++- > 6 files changed, 350 insertions(+), 3 deletions(-) > > -- > 2.5.0 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH 2/4] test: add AES DOCSIS tests for QAT PMD
> -Original Message- > From: Trahe, Fiona > Sent: Thursday, March 2, 2017 1:03 PM > To: dev@dpdk.org; De Lara Guarch, Pablo > Cc: Jain, Deepak K ; Trahe, Fiona > > Subject: [PATCH 2/4] test: add AES DOCSIS tests for QAT PMD > > Extend test suite to run AES DOCSIS tests on Intel QuickAssist PMD. > > Signed-off-by: Fiona Trahe > --- > app/test/test_cryptodev.c | 18 ++ > app/test/test_cryptodev_aes_test_vectors.h | 18 -- > 2 files changed, 30 insertions(+), 6 deletions(-) > > -- > 2.5.0 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH 4/4] test: added crypto OOP tests
> -Original Message- > From: Trahe, Fiona > Sent: Thursday, March 2, 2017 1:03 PM > To: dev@dpdk.org; De Lara Guarch, Pablo > Cc: Jain, Deepak K ; Trahe, Fiona > > Subject: [PATCH 4/4] test: added crypto OOP tests > > Added out-of-place (OOP) tests for AES-CBC, AES-DOCSIS and DES-DOCSIS to > tests suites for QuickAssist and openssl PMDs. > > Signed-off-by: Fiona Trahe > -- > 2.5.0 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH 3/4] test: add DES DOCSIS tests for QAT PMD
> -Original Message- > From: Trahe, Fiona > Sent: Thursday, March 2, 2017 1:03 PM > To: dev@dpdk.org; De Lara Guarch, Pablo > Cc: Jain, Deepak K ; Trahe, Fiona > > Subject: [PATCH 3/4] test: add DES DOCSIS tests for QAT PMD > > Extend test suite to run DES DOCSIS tests on Intel > QuickAssist PMD. > Is there an extra space above? Otherwise > Signed-off-by: Fiona Trahe > --- > app/test/test_cryptodev.c | 18 ++ > app/test/test_cryptodev_des_test_vectors.h | 18 -- > -- > 2.5.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] openssl pmd: rename SW crypto device from libcrypto to openssl
> -Original Message-
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Slawomir
> Mrozowicz
> Sent: Tuesday, October 18, 2016 12:36 PM
> To: Doherty, Declan
> Cc: dev at dpdk.org; Mrozowicz, SlawomirX
>
> Subject: [dpdk-dev] [PATCH] openssl pmd: rename SW crypto device from
> libcrypto to openssl
>
> This patch replaces name "libcrypto" to "openssl" from file directories,
> symbol prefixes and sub-names connected with old name.
> Renamed poll mode driver files, test files, and documentations.
> It is done to better name association with library because
> the cryptography operations are using Openssl library crypto API.
>
> Fixes: d61f70b4c918 ("crypto/libcrypto: add driver for OpenSSL library")
>
> Signed-off-by: Slawomir Mrozowicz
> ---
> MAINTAINERS|6 +-
> app/test/test_cryptodev.c | 56 +-
> app/test/test_cryptodev_aes_test_vectors.h | 62 +-
> app/test/test_cryptodev_blockcipher.c |6 +-
> app/test/test_cryptodev_blockcipher.h |2 +-
> app/test/test_cryptodev_des_test_vectors.h | 56 +-
> app/test/test_cryptodev_hash_test_vectors.h| 48 +-
> app/test/test_cryptodev_perf.c | 52 +-
> config/common_base |4 +-
> delete mode 100644
> drivers/crypto/libcrypto/rte_pmd_libcrypto_version.map
> create mode 100644 drivers/crypto/openssl/Makefile
> create mode 100644 drivers/crypto/openssl/rte_openssl_pmd.c
> create mode 100644 drivers/crypto/openssl/rte_openssl_pmd_ops.c
> create mode 100644 drivers/crypto/openssl/rte_openssl_pmd_private.h
> create mode 100644 drivers/crypto/openssl/rte_pmd_openssl_version.map
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8f5fa82..af47e04 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> --
> 2.5.0
Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH 1/2] crypto/qat: rework request builder for performance
> -Original Message- > From: Trahe, Fiona > Sent: Monday, October 24, 2016 1:00 PM > To: dev at dpdk.org > Cc: De Lara Guarch, Pablo ; Trahe, Fiona > ; Griffin, John ; Jain, > Deepak K ; Kusztal, ArkadiuszX > > Subject: [PATCH 1/2] crypto/qat: rework request builder for performance > > QAT PMD adjusts the buffer start address and offsets passed to the device > so that the DMAs in and out of the device are 64-byte aligned. > This gives more consistent throughput, which had been variable depending > on how the application set up the mbuf. > The message builder code had to be considerably re-factored to do this > efficiently. > > Signed-off-by: Fiona Trahe > --- > drivers/crypto/qat/qat_adf/icp_qat_hw.h | 5 + > drivers/crypto/qat/qat_adf/qat_algs.h| 1 + > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 + > drivers/crypto/qat/qat_crypto.c | 239 > --- > 4 files changed, 176 insertions(+), 71 deletions(-) > > diff --git a/drivers/crypto/qat/qat_adf/icp_qat_hw.h > b/drivers/crypto/qat/qat_adf/icp_qat_hw.h > index a08094f..ebe245f 100644 > --- a/drivers/crypto/qat/qat_adf/icp_qat_hw.h > -- > 2.5.0 Acked-By: Deepak Kumar Jain
[dpdk-dev] [PATCH 2/2] app/test: use correct offsets in AES perf test
> -Original Message- > From: Trahe, Fiona > Sent: Monday, October 24, 2016 1:00 PM > To: dev at dpdk.org > Cc: De Lara Guarch, Pablo ; Trahe, Fiona > ; Griffin, John ; Jain, > Deepak K ; Kusztal, ArkadiuszX > > Subject: [PATCH 2/2] app/test: use correct offsets in AES perf test > > offsets for digest and data need to be adjusted to take prepended IV into > account > > Signed-off-by: Fiona Trahe > --- > app/test/test_cryptodev_perf.c | 15 --- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/app/test/test_cryptodev_perf.c > b/app/test/test_cryptodev_perf.c index e05e11b..53dd8f5 100644 > --- a/app/test/test_cryptodev_perf.c > +++ b/app/test/test_cryptodev_perf.c > @@ -2714,26 +2714,27 @@ test_perf_set_crypto_op_aes(struct > rte_crypto_op *op, struct rte_mbuf *m, > > -- > 2.5.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] doc/guides: add more info re VT-d/iommu settings for QAT
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Fiona Trahe > Sent: Wednesday, October 26, 2016 4:20 PM > To: dev at dpdk.org > Subject: [dpdk-dev] [PATCH] doc/guides: add more info re VT-d/iommu > settings for QAT > > add more info re VT-d/iommu settings for QAT remove limitation re > performance tuning > > Signed-off-by: Fiona Trahe > --- > doc/guides/cryptodevs/qat.rst | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst > index 70bc2b1..bbe0b12 100644 > --- a/doc/guides/cryptodevs/qat.rst > +++ b/doc/guides/cryptodevs/qat.rst > > -- > 2.5.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH 0/2] add aes-sha224-hmac support to Intel QAT driver
HI Pablo, > -Original Message- > From: De Lara Guarch, Pablo > Sent: Wednesday, September 7, 2016 7:00 PM > To: Jain, Deepak K ; Trahe, Fiona > ; Griffin, John > Cc: dev at dpdk.org > Subject: RE: [PATCH 0/2] add aes-sha224-hmac support to Intel QAT driver > > Hi Deepak, > > > -Original Message- > > From: Jain, Deepak K > > Sent: Thursday, August 18, 2016 6:18 AM > > To: De Lara Guarch, Pablo; Trahe, Fiona; Griffin, John > > Cc: dev at dpdk.org; Jain, Deepak K > > Subject: [PATCH 0/2] add aes-sha224-hmac support to Intel QAT driver > > > > This patchset adds support of aes-sha224-hmac in Intel(R) QuickAssist > > Technology driver. > > > > This patchset depends on following patchset: > > "crypto/qat: add MD5 HMAC capability to Intel QAT driver" > > (http://dpdk.org/dev/patchwork/patch/15165/) > > > > Jain, Deepak K (2): > > crypto/qat: add aes-sha224-hmac capability to Intel QAT driver > > app/test: add test cases for aes-sha224-hmac for Intel QAT driver > > > > app/test/test_cryptodev_aes.c| 6 +++-- > > doc/guides/cryptodevs/qat.rst| 1 + > > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 > > > > drivers/crypto/qat/qat_crypto.c | 4 ++- > > 4 files changed, 41 insertions(+), 3 deletions(-) > > > > -- > > 2.5.5 > > Could you send a v2 with a release notes update? > Agreed. I will send v2 with release notes. > Thanks, > Pablo
[dpdk-dev] [PATCH 0/2] add NULL crypto support in Intel QAT driver
HI Pablo, > -Original Message- > From: De Lara Guarch, Pablo > Sent: Wednesday, September 7, 2016 7:05 PM > To: Jain, Deepak K ; Trahe, Fiona > ; Griffin, John > Cc: dev at dpdk.org > Subject: RE: [PATCH 0/2] add NULL crypto support in Intel QAT driver > > Hi Deepak, > > > -Original Message- > > From: Jain, Deepak K > > Sent: Thursday, August 18, 2016 6:34 AM > > To: De Lara Guarch, Pablo; Trahe, Fiona; Griffin, John > > Cc: dev at dpdk.org; Jain, Deepak K > > Subject: [PATCH 0/2] add NULL crypto support in Intel QAT driver > > > > This patchset adds support of NULL crypto in Intel(R) QuickAssist > > Technology driver. > > > > This patchset depends on following patchset: > > "crypto/qat: add aes-sha384-hmac capability to Intel QAT driver" > > (http://dpdk.org/dev/patchwork/patch/15228/) > > > > Deepak Kumar Jain (2): > > crypto/qat: add NULL capability to Intel QAT driver > > app/test: add test cases for NULL for Intel QAT driver > > > > app/test/test_cryptodev.c| 10 ++ > > doc/guides/cryptodevs/qat.rst| 3 ++- > > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++ > > drivers/crypto/qat/qat_crypto.c | 4 > > 4 files changed, 18 insertions(+), 1 deletion(-) > > > > -- > > 2.5.5 > > Could you send a v2 with a release notes update? > Agreed. I will send v2 with release notes. > Thanks, > Pablo
[dpdk-dev] [PATCH 0/4] add kasumi in Intel(R) QuickAssist driver
Hi Pablo, > -Original Message- > From: De Lara Guarch, Pablo > Sent: Wednesday, September 7, 2016 7:07 PM > To: Jain, Deepak K ; Trahe, Fiona > ; Griffin, John > Cc: dev at dpdk.org > Subject: RE: [PATCH 0/4] add kasumi in Intel(R) QuickAssist driver > > Hi Deepak, > > > -Original Message- > > From: Jain, Deepak K > > Sent: Tuesday, August 23, 2016 2:36 PM > > To: De Lara Guarch, Pablo; Trahe, Fiona; Griffin, John > > Cc: dev at dpdk.org; Jain, Deepak K > > Subject: [PATCH 0/4] add kasumi in Intel(R) QuickAssist driver > > > > This patchset contains patches to enable kasumi cipher only and hash > > only functionality in Intel(R) QuickAsisst Technology Driver. > > > > This patchset depends on following patch: > > "crypto/qat: add NULL capability to Intel QAT driver" > > (http://dpdk.org/dev/patchwork/patch/15230/) > > > > Deepak Kumar Jain (4): > > crypto/qat: enable Kasumi F9 support in QAT driver > > app/test: add Kasumi f9 tests in QAT test suite > > crypto/qat: enable support of Kasumi F8 in QAT cryptodev > > app/test: add kasumi f8 test into QAT testsuite > > > > app/test/test_cryptodev.c | 16 + > > app/test/test_cryptodev_kasumi_hash_test_vectors.h | 43 > + > > drivers/crypto/qat/qat_adf/qat_algs.h | 10 ++- > > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 74 > > -- > > drivers/crypto/qat/qat_crypto.c| 69 > > ++-- > > 5 files changed, 201 insertions(+), 11 deletions(-) > > > > -- > > 2.5.5 > > Could you send a v2 with a release notes update? > Agreed. I will send v2 with release notes. > Thanks, > Pablo
[dpdk-dev] [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver
HI Pablo, > -Original Message- > From: De Lara Guarch, Pablo > Sent: Wednesday, September 7, 2016 7:02 PM > To: Jain, Deepak K ; Trahe, Fiona > ; Griffin, John > Cc: dev at dpdk.org > Subject: RE: [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver > > Hi Deepak, > > > -Original Message- > > From: Jain, Deepak K > > Sent: Thursday, August 18, 2016 6:26 AM > > To: De Lara Guarch, Pablo; Trahe, Fiona; Griffin, John > > Cc: dev at dpdk.org; Jain, Deepak K > > Subject: [PATCH 0/2] add aes-sha384-hmac support to Intel QAT driver > > > > This patchset adds support of aes-sha384-hmac in Intel(R) QuickAssist > > Technology driver. > > > > This patchset depends on following patchset: > > "crypto/qat: add aes-sha224-hmac capability to Intel QAT driver" > > (http://dpdk.org/dev/patchwork/patch/15226/) > > > > Jain, Deepak K (2): > > crypto/qat: add aes-sha384-hmac capability to Intel QAT driver > > app/test: add test cases for aes-sha384-hmac for Intel QAT driver > > > > app/test/test_cryptodev_aes.c| 6 +++-- > > doc/guides/cryptodevs/qat.rst| 1 + > > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 33 > > > > drivers/crypto/qat/qat_crypto.c | 10 --- > > 4 files changed, 44 insertions(+), 6 deletions(-) > > > > -- > > 2.5.5 > > Could you send a v2 with a release notes update? > Agreed. I will send v2 with release notes. > Thanks, > Pablo
[dpdk-dev] [PATCH] crypto/qat: add Intel QuickAssist C62x device
HI Pablo, > -Original Message- > From: De Lara Guarch, Pablo > Sent: Wednesday, September 7, 2016 7:07 PM > To: Jain, Deepak K ; Trahe, Fiona > ; Griffin, John > Cc: dev at dpdk.org > Subject: RE: [PATCH] crypto/qat: add Intel QuickAssist C62x device > > Hi Deepak, > > > -Original Message- > > From: Jain, Deepak K > > Sent: Tuesday, August 23, 2016 7:54 AM > > To: De Lara Guarch, Pablo; Trahe, Fiona; Griffin, John > > Cc: dev at dpdk.org; Jain, Deepak K > > Subject: [PATCH] crypto/qat: add Intel QuickAssist C62x device > > > > Signed-off-by: Deepak Kumar Jain > > Could you send a v2 with a release notes update? > Agreed. I will send v2 with release notes. > Thanks, > Pablo
[dpdk-dev] [PATCH] crypto/qat: add Intel(R) QuickAssist C3xxx device
HI Pablo, > -Original Message- > From: De Lara Guarch, Pablo > Sent: Wednesday, September 7, 2016 7:08 PM > To: Jain, Deepak K ; Trahe, Fiona > ; Griffin, John > Cc: dev at dpdk.org > Subject: RE: [PATCH] crypto/qat: add Intel(R) QuickAssist C3xxx device > > Hi Deepak, > > > -Original Message- > > From: Jain, Deepak K > > Sent: Friday, August 26, 2016 5:28 AM > > To: Trahe, Fiona; Griffin, John; De Lara Guarch, Pablo > > Cc: dev at dpdk.org; Jain, Deepak K > > Subject: [PATCH] crypto/qat: add Intel(R) QuickAssist C3xxx device > > > > Signed-off-by: Deepak Kumar Jain > > Could you send a v2 with a release notes update? > Agreed. I will send v2 with release notes. > Thanks, > Pablo
[dpdk-dev] [PATCH v2] doc/guides: add info on how to enable QAT
> -Original Message- > From: Thomas Monjalon [mailto:thomas.monjalon at 6wind.com] > Sent: Tuesday, September 13, 2016 12:51 PM > To: Jain, Deepak K > Cc: dev at dpdk.org; De Lara Guarch, Pablo intel.com>; > Breen, Eoin > Subject: Re: [dpdk-dev] [PATCH v2] doc/guides: add info on how to enable > QAT > > 2016-09-13 11:47, Deepak Kumar Jain: > > +#. ``make config T=x86_64-native-linuxapp-gcc`` #. Open the > > +``./build/.config`` file #. Replace ``CONFIG_RTE_LIBRTE_PMD_QAT=n`` > > +with ``CONFIG_RTE_LIBRTE_PMD_QAT=y`` > > It is better to put commands after "code-block:: console" > Then I suggest this command: > sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT\)=n,\1=y,' build/.config Thanks. I will update and send v3 of the patch. > > +#. ``make`` >
[dpdk-dev] [PATCH v3 1/3] app/test: cleanup of test code for kasumi
Hi Pablo, > -Original Message- > From: De Lara Guarch, Pablo > Sent: Saturday, September 17, 2016 2:00 AM > To: Jain, Deepak K ; dev at dpdk.org > Subject: RE: [PATCH v3 1/3] app/test: cleanup of test code for kasumi > > Hi Deepak, > > > -Original Message- > > From: Jain, Deepak K > > Sent: Thursday, September 15, 2016 3:04 AM > > To: dev at dpdk.org > > Cc: De Lara Guarch, Pablo; Jain, Deepak K > > Subject: [PATCH v3 1/3] app/test: cleanup of test code for kasumi > > > > Cleanup for easier kasumi enabling. > > Changed name of funcitons for clear understanding. > > Typo in "funcitons". > > Could you split this patch in two? One for the rename the functions and > another one for the rest. > Actually, are you doing something else apart from cleanup/reordering? Yes I can split the patch into two. One with name changes and one with reordering. Other than this, cleaner usage of Additional Authentication data is included in the code. Motivation behind this is to have code consistency across the wireless specific algorithms. Will send another version with comments incorporated. > > > > > Signed-off-by: Deepak Kumar Jain > > --- > > app/test/test_cryptodev.c | 117 > > ++ > > 1 file changed, 55 insertions(+), 62 deletions(-) > > > > diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c > > index 67ca912..89d627f 100644 > > --- a/app/test/test_cryptodev.c > > +++ b/app/test/test_cryptodev.c > > @@ -1448,74 +1448,67 @@ > > create_snow3g_kasumi_cipher_hash_operation(const uint8_t *auth_tag, > > ... > > > TEST_ASSERT_NOT_NULL(sym_op->auth.aad.data, > > "no room to prepend aad"); > > sym_op->auth.aad.phys_addr = rte_pktmbuf_mtophys( > > ut_params->ibuf); > > sym_op->auth.aad.length = aad_len; > > - > > - memset(sym_op->auth.aad.data, 0, aad_buffer_len); > > + memset(sym_op->auth.aad.data, 0, aad_buffer_len); > > No need to include extra tab. > > > rte_memcpy(sym_op->auth.aad.data, aad, aad_len); > > + TEST_HEXDUMP(stdout, "aad:", > > + sym_op->auth.aad.data, aad_len); > > No need to include extra tab. > > > > > - TEST_HEXDUMP(stdout, "aad:", > > - sym_op->auth.aad.data, aad_len); > > - > > - /* digest */ > > - sym_op->auth.digest.data = (uint8_t *)rte_pktmbuf_append( > > - ut_params->ibuf, auth_tag_len); > > ... > > > @@ -2714,12 +2707,12 @@ test_snow3g_authenticated_encryption(const > > struct snow3g_test_data *tdata) > > ut_params->obuf = ut_params->op->sym->m_src; > > if (ut_params->obuf) > > ciphertext = rte_pktmbuf_mtod(ut_params->obuf, uint8_t > *) > > - + tdata->iv.len; > > + + tdata->iv.len + tdata->aad.len; > > else > > ciphertext = plaintext; > > > > TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, plaintext_len); > > - > > + TEST_HEXDUMP(stdout, "OUTPUT BUFFER:", ut_params->obuf, 512); > > Magic number? What are you showing here? > > > /* Validate obuf */ > > TEST_ASSERT_BUFFERS_ARE_EQUAL_BIT( > > ciphertext, > > @@ -2728,7 +2721,7 @@ test_snow3g_authenticated_encryption(const > > struct snow3g_test_data *tdata) > > "Snow3G Ciphertext data not as expected"); > >
[dpdk-dev] [PATCH v3 1/2] crypto/qat: code cleanup
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Fiona Trahe > Sent: Friday, September 16, 2016 3:20 PM > To: dev at dpdk.org > Cc: De Lara Guarch, Pablo ; Trahe, Fiona > > Subject: [dpdk-dev] [PATCH v3 1/2] crypto/qat: code cleanup > > Cleanup of unused code. > Rename and simplify a badly named struct element, was aes, but used for all > types of ciphers Print correct error msg (Unsupported rather than > Undefined) for all ciphers not supported by qat PMD. > > Signed-off-by: Fiona Trahe > --- > drivers/crypto/qat/qat_adf/icp_qat_hw.h | 10 ++-- > drivers/crypto/qat/qat_adf/qat_algs.h| 1 - > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 63 > +++- > drivers/crypto/qat/qat_crypto.c | 6 ++- > 4 files changed, 16 insertions(+), 64 deletions(-) > > -- > 2.5.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH v3 2/2] crypto/qat: adding support for 3DES cipher algorithm
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Fiona Trahe > Sent: Friday, September 16, 2016 3:20 PM > To: dev at dpdk.org > Cc: De Lara Guarch, Pablo ; Trahe, Fiona > > Subject: [dpdk-dev] [PATCH v3 2/2] crypto/qat: adding support for 3DES > cipher algorithm > > 3DES support added to QuickAssist PMD > With CTR and CBC mode. > Both cipher-only and chained with HMAC_SHAx > > This patch depends on following patch : > crypto/qat: enable support of Kasumi F8 in QAT cryptodev > http://dpdk.org/dev/patchwork/patch/15813/ > > Signed-off-by: Fiona Trahe > --- > doc/guides/cryptodevs/qat.rst| 4 +- > doc/guides/rel_notes/release_16_11.rst | 1 + > drivers/crypto/qat/qat_adf/qat_algs.h| 5 ++ > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 25 +- > drivers/crypto/qat/qat_crypto.c | 59 > +++- > 5 files changed, 89 insertions(+), 5 deletions(-) > > diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst > index 3528499..16e5937 100644 > --- a/doc/guides/cryptodevs/qat.rst > +++ b/doc/guides/cryptodevs/qat.rst > @@ -42,6 +42,8 @@ The QAT PMD has support for: > -- > 2.5.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH v4] tools: add crypto device details
> -Original Message- > From: De Lara Guarch, Pablo > Sent: Tuesday, September 20, 2016 1:05 AM > To: dev at dpdk.org > Cc: Jain, Deepak K ; Eoin Breen > ; De Lara Guarch, Pablo > > Subject: [PATCH v4] tools: add crypto device details > > From: Eoin Breen > > Adding the support to bind/unbind crypto devices with dpdk-devbind.py > script, as now it is not restricted to network devices anymore. > > Signed-off-by: Eoin Breen > Signed-off-by: Pablo de Lara > --- > Changes since v3: > * Modified setup.sh script to show crypto details > * Added script usage in qat.rst doc > * Modified help script, to include crypto references > > Changes since v2: > * Removed network specific parameters from crypto parameters > > Changes since v1: > * Resolved coding issues > > doc/guides/cryptodevs/qat.rst | 5 +++ > tools/dpdk-devbind.py | 94 > ++- > tools/dpdk-setup.sh | 32 +++ > 3 files changed, 105 insertions(+), 26 deletions(-) > -- > 2.7.4 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH 1/2] snow3g: rename some SNOW 3G references
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara > Sent: Wednesday, September 21, 2016 2:45 AM > To: dev at dpdk.org > Cc: Doherty, Declan ; De Lara Guarch, Pablo > > Subject: [dpdk-dev] [PATCH 1/2] snow3g: rename some SNOW 3G > references > > SNOW 3G algorithm has all uppercase letters in its name and a space > between SNOW and 3G, but some references of it had some lowercase > letters or no space. > > Signed-off-by: Pablo de Lara > --- > app/test/test_cryptodev.c| 74 > > app/test/test_cryptodev_perf.c | 2 +- > doc/guides/cryptodevs/qat.rst| 8 +-- > doc/guides/cryptodevs/snow3g.rst | 6 +- > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 4 +- > drivers/crypto/qat/qat_crypto.c | 10 ++-- > drivers/crypto/snow3g/rte_snow3g_pmd.c | 2 +- > drivers/crypto/snow3g/rte_snow3g_pmd_ops.c | 6 +- > examples/l2fwd-crypto/main.c | 4 +- > lib/librte_cryptodev/rte_crypto_sym.h| 20 +++ > 10 files changed, 68 insertions(+), 68 deletions(-) > > 2.7.4 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH 2/2] kasumi: rename all KASUMI references
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara > Sent: Wednesday, September 21, 2016 2:45 AM > To: dev at dpdk.org > Cc: Doherty, Declan ; De Lara Guarch, Pablo > > Subject: [dpdk-dev] [PATCH 2/2] kasumi: rename all KASUMI references > > KASUMI 3G algorithm has all uppercase letters, but some references of it had > some lowercase letters. > > Signed-off-by: Pablo de Lara > --- > drivers/crypto/qat/qat_adf/qat_algs.h | 2 +- > drivers/crypto/qat/qat_crypto.c | 2 +- > lib/librte_cryptodev/rte_crypto_sym.h | 8 > 3 files changed, 6 insertions(+), 6 deletions(-) > > -- > 2.7.4 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] app/test: add AES GCM performance test to cryptodev
> -Original Message- > From: Yuanhan Liu [mailto:yuanhan.liu at linux.intel.com] > Sent: Friday, September 23, 2016 7:33 AM > To: Kusztal, ArkadiuszX > Cc: dev at dpdk.org; Trahe, Fiona ; Jain, Deepak K > ; De Lara Guarch, Pablo > ; Griffin, John > Subject: Re: [dpdk-dev] [PATCH] app/test: add AES GCM performance test > to cryptodev > > On Thu, Sep 22, 2016 at 04:54:57PM +0100, Arek Kusztal wrote: > > This patch adds AES Galois Counter Mode test case for cryptodev QAT > > tests. Test is performed with different buffer sizes, burst size of 32 > > and 128b key. Test vectors are placed in > > app/test/test_cryptodev_perf_vectors.h file. > > > > This patch depends on the following patches/patchsets: > > > > "app/test: fix linkage scope of gmac plaintext array" > > (http://dpdk.org/dev/patchwork/patch/16023/) > > > > Signed-off-by: Arek Kusztal > > FYI, > > My robot caught a build error when this patch applied. > > --yliu > > --- > test_cryptodev.o:(.data+0x1be0): multiple definition of `gmac_plaintext' > test_cryptodev_perf.o:(.data+0x4a0): first defined here > collect2: error: ld returned 1 exit status Seems like this patch : http://dpdk.org/dev/patchwork/patch/16023/ was not applied when you tested this patch. Please apply the dependent patch and then test this patch.
[dpdk-dev] [PATCH] app/test: fix compilation error when debug mode enabled
> -Original Message-
> From: Kusztal, ArkadiuszX
> Sent: Monday, September 26, 2016 2:53 PM
> To: dev at dpdk.org
> Cc: Trahe, Fiona ; Jain, Deepak K
> ; De Lara Guarch, Pablo
> ; Griffin, John intel.com>;
> Kusztal, ArkadiuszX
> Subject: [PATCH] app/test: fix compilation error when debug mode enabled
>
> This patch fixes compilation error in test_cryptodev.c when
> RTE_LOG_DEBUG is specified
>
> Fixes: ba0dda7a7100 ("app/test: add GMAC authentication tests to
> cryptodev tests")
>
> Signed-off-by: Arek Kusztal
> ---
> app/test/test_cryptodev.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c index
> d744b37..609908b 100644
> --- a/app/test/test_cryptodev.c
> +++ b/app/test/test_cryptodev.c
> @@ -4288,7 +4288,7 @@ static int create_gmac_session(uint8_t dev_id,
> ut_params->cipher_xform.cipher.key.data = cipher_key;
> ut_params->cipher_xform.cipher.key.length = tdata->key.len;
>
> - TEST_HEXDUMP(stdout, "key:", key, key_len);
> + TEST_HEXDUMP(stdout, "key:", cipher_key, tdata->key.len);
>
> ut_params->auth_xform.type = RTE_CRYPTO_SYM_XFORM_AUTH;
> >gmac_tag.len);
> -
> return 0;
>
> }
> --
> 2.1.0
Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH v2] app/test: add AES GCM performance test to cryptodev
> -Original Message- > From: Kusztal, ArkadiuszX > Sent: Friday, September 23, 2016 11:30 AM > To: dev at dpdk.org > Cc: Trahe, Fiona ; Jain, Deepak K > ; De Lara Guarch, Pablo > ; Griffin, John intel.com>; > Kusztal, ArkadiuszX > Subject: [PATCH v2] app/test: add AES GCM performance test to cryptodev > > This patch adds AES Galois Counter Mode performance test case for > cryptodev QAT tests. Test is performed with different buffer sizes, burst size > of 32 and 128b key. Test vectors are placed in > app/test/test_cryptodev_perf_vectors.h file. > > This patch depends on the following patches/patchsets: > > "app/test: fix linkage scope of gmac plaintext array" > (http://dpdk.org/dev/patchwork/patch/16023/) > > Signed-off-by: Arek Kusztal > --- > v2: > * Fixed 32b build problem in test_cryptodev_perf.c > --- > app/test/test_cryptodev_gcm_test_vectors.h | 636 > + > app/test/test_cryptodev_perf.c | 431 ++- > 2 files changed, 1064 insertions(+), 3 deletions(-) > > -- > 2.1.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] app/test: remove unnecessary hexdump from test_cryptodev.c
> -Original Message- > From: Kusztal, ArkadiuszX > Sent: Tuesday, September 27, 2016 10:21 AM > To: dev at dpdk.org > Cc: Trahe, Fiona ; Jain, Deepak K > ; De Lara Guarch, Pablo > ; Griffin, John intel.com>; > Kusztal, ArkadiuszX > Subject: [PATCH] app/test: remove unnecessary hexdump from > test_cryptodev.c > > This patch removes unnecesssary hexdump calls from GMAC related > functions in test_cryptodev.c which hinder compilation when > RTE_LOG_DEBUG is specified > > Signed-off-by: Arek Kusztal > --- > app/test/test_cryptodev.c | 4 > 1 file changed, 4 deletions(-) > > > } > -- > 2.1.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH v2 1/4] crypto/zuc: add driver for ZUC library
> -Original Message-
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara
> Sent: Thursday, September 29, 2016 4:00 AM
> To: dev at dpdk.org
> Cc: Doherty, Declan ; De Lara Guarch, Pablo
>
> Subject: [dpdk-dev] [PATCH v2 1/4] crypto/zuc: add driver for ZUC library
>
> Added new SW PMD which makes use of the libsso SW library, which
> provides wireless algorithms ZUC EEA3 and EIA3 in software.
>
> This PMD supports cipher-only, hash-only and chained operations ("cipher
> then hash" and "hash then cipher") of the following
> algorithms:
> - RTE_CRYPTO_SYM_CIPHER_ZUC_EEA3
> - RTE_CRYPTO_SYM_AUTH_ZUC_EIA3
>
> The ZUC hash and cipher algorithms, which are enabled by this crypto PMD
> are implemented by Intel's libsso software library.
>
> Signed-off-by: Pablo de Lara
> ---
> MAINTAINERS| 5 +
> config/common_base | 6 +
> config/defconfig_i686-native-linuxapp-gcc | 5 +
> config/defconfig_i686-native-linuxapp-icc | 5 +
> doc/guides/cryptodevs/index.rst| 1 +
> doc/guides/cryptodevs/zuc.rst | 108 ++
> drivers/crypto/Makefile| 1 +
> drivers/crypto/zuc/Makefile| 69
> drivers/crypto/zuc/rte_pmd_zuc_version.map | 3 +
> drivers/crypto/zuc/rte_zuc_pmd.c | 551
> +
> drivers/crypto/zuc/rte_zuc_pmd_ops.c | 342 ++
> drivers/crypto/zuc/rte_zuc_pmd_private.h | 108 ++
> lib/librte_cryptodev/rte_crypto_sym.h | 20 +-
> lib/librte_cryptodev/rte_cryptodev.h | 3 +
> mk/rte.app.mk | 2 +
> scripts/test-build.sh | 4 +
> --
> 2.7.4
Acked-by: Deepak Kumar Jain >deepak.k.jain at intel.com>
[dpdk-dev] [PATCH v2 2/4] app/test: rename some functions
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara > Sent: Thursday, September 29, 2016 4:00 AM > To: dev at dpdk.org > Cc: Doherty, Declan ; De Lara Guarch, Pablo > > Subject: [dpdk-dev] [PATCH v2 2/4] app/test: rename some functions > > Before adding the new ZUC tests, since they will use the existing common > functions for SNOW3G and KASUMI, these functions are renamed to > *_wireless_algo_*, instead of *_snow3g_kasumi_*, as they are common > functions for all the three wireless algorithms. > > Signed-off-by: Pablo de Lara > --- > app/test/test_cryptodev.c | 86 +++-- > -- > -- > 2.7.4 Acked-by: Deepak Kumar Jain >deepak.k.jain at intel.com>
[dpdk-dev] [PATCH v2 4/4] examples/l2fwd-crypto: enable ZUC EEA3 and EIA3 algos
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara > Sent: Thursday, September 29, 2016 4:00 AM > To: dev at dpdk.org > Cc: Doherty, Declan ; De Lara Guarch, Pablo > > Subject: [dpdk-dev] [PATCH v2 4/4] examples/l2fwd-crypto: enable ZUC > EEA3 and EIA3 algos > > This patch enables ZUC EEA3 cipher algorithm and ZUC EIA3 authentication > algorithm support to l2fwd-crypto sample application. > > Signed-off-by: Pablo de Lara > --- > examples/l2fwd-crypto/main.c | 12 > 1 file changed, 8 insertions(+), 4 deletions(-) > > -- > 2.7.4 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH v2 3/4] app/test: add test cases for ZUC PMD
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara > Sent: Thursday, September 29, 2016 4:00 AM > To: dev at dpdk.org > Cc: Doherty, Declan ; De Lara Guarch, Pablo > > Subject: [dpdk-dev] [PATCH v2 3/4] app/test: add test cases for ZUC PMD > > Add cipher and authentication ZUC algorithm tests. > > Signed-off-by: Pablo de Lara > --- > app/test/test_cryptodev.c | 245 ++ > app/test/test_cryptodev_zuc_hash_test_vectors.h | 359 > +++ > app/test/test_cryptodev_zuc_test_vectors.h | 582 > > 3 files changed, 1186 insertions(+) > create mode 100644 app/test/test_cryptodev_zuc_hash_test_vectors.h > create mode 100644 app/test/test_cryptodev_zuc_test_vectors.h > > -- > 2.7.4 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH] crypto/qat: fix capabilities for D15xx device
> -Original Message-
> From: Kusztal, ArkadiuszX
> Sent: Monday, April 10, 2017 2:20 PM
> To: dev@dpdk.org
> Cc: Trahe, Fiona ; De Lara Guarch, Pablo
> ; Griffin, John ;
> Jain, Deepak K ; Kusztal, ArkadiuszX
>
> Subject: [PATCH] crypto/qat: fix capabilities for D15xx device
>
> This commit fixes capabilities for Intel(R) QuickAssist Technology D15xx
> device
>
> Fixes: 259310f3a984 ("crypto/qat: support device D15xx")
>
> Signed-off-by: Arek Kusztal
> ---
> drivers/crypto/qat/rte_qat_cryptodev.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/crypto/qat/rte_qat_cryptodev.c
default:
> --
> 2.7.4
Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH] crypto/qat: fix AES-GCM authentication length
> -Original Message-
> From: Kusztal, ArkadiuszX
> Sent: Thursday, April 13, 2017 10:29 AM
> To: dev@dpdk.org
> Cc: Trahe, Fiona ; De Lara Guarch, Pablo
> ; Griffin, John ;
> Jain, Deepak K ; Kusztal, ArkadiuszX
>
> Subject: [PATCH] crypto/qat: fix AES-GCM authentication length
>
> This commit fixes AES-GCM length of authentication input data, cipher length
> is used instead
>
> Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
>
> Signed-off-by: Arek Kusztal
> ---
> drivers/crypto/qat/qat_crypto.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/crypto/qat/qat_crypto.c
> 2.1.0
Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH] crypto/qat: fix IV zero physical address
> -Original Message-
> From: Kusztal, ArkadiuszX
> Sent: Friday, April 14, 2017 9:09 AM
> To: dev@dpdk.org
> Cc: Trahe, Fiona ; De Lara Guarch, Pablo
> ; Griffin, John ;
> Jain, Deepak K ; Kusztal, ArkadiuszX
>
> Subject: [PATCH] crypto/qat: fix IV zero physical address
>
> This commit fixes zero physical address when IV not set
>
> Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
>
> Signed-off-by: Arek Kusztal
> ---
> drivers/crypto/qat/qat_crypto.c | 29 ++---
> 1 file changed, 18 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/crypto/qat/qat_crypto.c
> b/drivers/crypto/qat/qat_crypto.c index b9baf36..362eb9d 100644
> --
> 2.1.0
Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH] doc/crypto: add clarification about chained mbuf feature
> -Original Message- > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Fiona Trahe > Sent: Thursday, May 3, 2018 2:33 PM > > diff --git a/doc/guides/cryptodevs/overview.rst > b/doc/guides/cryptodevs/overview.rst > index b3cb6ca..493cd5f 100644 > --- a/doc/guides/cryptodevs/overview.rst > +++ b/doc/guides/cryptodevs/overview.rst > @@ -11,6 +11,16 @@ Supported Feature Flags > > .. include:: overview_feature_table.txt > > +Note, the mbuf scatter gather feature (aka chained mbufs, > +scatter-gather-lists or SGLs) indicate all following combinations are > +supported unless otherwise called out in the Limitations section of each > PMD. > + > +* In place operation, input buffer as multiple segments, same buffer > +used for output > +* Out of place operation, input buffer as single segment and output as > +multiple segments > +* Out of place operation, input buffer as multiple segments and output > +as single segment > +* Out of place operation, input buffer as multiple segments and output > +as multiple segments > + > + > Supported Cipher Algorithms > --- > > -- > 1.7.0.7 Acked-By: Deepak Kumar Jain
Re: [dpdk-dev] [PATCH v5 0/6] Cryptodev API/ABI deprecation notices
> -Original Message- > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Pablo de Lara > Sent: Monday, May 21, 2018 2:09 PM > To: Doherty, Declan ; akhil.go...@nxp.com; > shally.ve...@cavium.com > Cc: dev@dpdk.org; De Lara Guarch, Pablo > Subject: [dpdk-dev] [PATCH v5 0/6] Cryptodev API/ABI deprecation notices > > v5: > - Renamed rte_cryptodev_get_header_session_size with > rte_cryptodev_sym_get_header_session_size, and > rte_cryptodev_get_private_session_size with > rte_cryptodev_sym_get_private_session_size. > > v4: > - Fixed DPDK versions called out to deprecate/remove API. > - Removed rte_cryptodev_queue_pair_attach_sym_session call > from the IPSec gw app, since the function is deprecated now. > - Added patch announcing a replacement of some of the crypto > feature flags > - Added patch renaming two symmetric specific functions > from *_session_* to *_sym_session_*. > > v3: > - Added an extra deprecation announcement (replacing rte_pci_device > with rte_device) > - Rebased against latest DPDK code > > v2: > - Added an extra deprecation announcement > - Bonded the other two deprecation notices with the new one in a > patchset > > Pablo de Lara (6): > doc: announce ABI change for crypto sym info struct > doc: announce ABI change for crypto info struct > doc: announce deprecation for attach/detach crypto session > doc: announce deprecation in crypto queue pair start/stop > doc: announce deprecation in crypto feature flags > cryptodev: rename get session size API > > app/test-crypto-perf/main.c | 2 +- > doc/guides/prog_guide/cryptodev_lib.rst | 6 ++-- > doc/guides/rel_notes/deprecation.rst | 25 + > drivers/crypto/aesni_gcm/aesni_gcm_pmd.c | 2 +- > drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c| 2 +- > drivers/crypto/armv8/rte_armv8_pmd.c | 2 +- > drivers/crypto/kasumi/rte_kasumi_pmd.c| 2 +- > drivers/crypto/openssl/rte_openssl_pmd.c | 2 +- > drivers/crypto/snow3g/rte_snow3g_pmd.c| 2 +- > drivers/crypto/zuc/rte_zuc_pmd.c | 2 +- > examples/ipsec-secgw/ipsec-secgw.c| 2 +- > examples/ipsec-secgw/ipsec.c | 12 --- > examples/l2fwd-crypto/main.c | 2 +- > examples/vhost_crypto/main.c | 2 +- > lib/librte_cryptodev/rte_cryptodev.c | 12 +++ > lib/librte_cryptodev/rte_cryptodev.h | 35 +++ > .../rte_cryptodev_version.map | 8 + > test/test/test_cryptodev.c| 6 ++-- > test/test/test_event_crypto_adapter.c | 2 +- > 19 files changed, 99 insertions(+), 29 deletions(-) > > -- > 2.17.0 Series Acked-by: Deepak Kumar Jain
[dpdk-dev] DPDK Community Survey 2017
Hi All, As part of our ongoing efforts to improve DPDK, we'd like to hear your feedback! We have created a number of DPDK-related questions here. https://www.surveymonkey.com/r/DPDK_Community_Survey_2017 and want to hear your views!! The survey will close at midnight GMT on Sunday October 1st, 2017. Thanks in advance for your feedback - the more responses we get the more data we have to drive further features, improvements, etc. So please respond!!! Regards Deepak
[dpdk-dev] [dpdk-announce] DPDK Community Survey 2017
Hi All, As part of our ongoing efforts to improve DPDK, we'd like to hear your feedback! We have created a number of DPDK-related questions here. https://www.surveymonkey.com/r/DPDK_Community_Survey_2017 and want to hear your views!! The survey will close at midnight GMT on Sunday October 1st, 2017. Thanks in advance for your feedback - the more responses we get the more data we have to drive further features, improvements, etc. So please respond!!! Regards Deepak
Re: [dpdk-dev] DPDK Community Survey 2017
HI, As earlier agreed in DPDK Userspace, the closure date for this survey has been extended by a week. Survey will now close at midnight GMT on Sunday October 8th 2017. Gentle reminder in case you have not filled the survey. Many thanks, Deepak From: Jain, Deepak K Sent: Friday, September 22, 2017 2:18 PM To: annou...@dpdk.org Subject: DPDK Community Survey 2017 Hi All, As part of our ongoing efforts to improve DPDK, we'd like to hear your feedback! We have created a number of DPDK-related questions here. https://www.surveymonkey.com/r/DPDK_Community_Survey_2017 and want to hear your views!! The survey will close at midnight GMT on Sunday October 1st, 2017. Thanks in advance for your feedback - the more responses we get the more data we have to drive further features, improvements, etc. So please respond!!! Regards Deepak
Re: [dpdk-dev] DPDK Community Survey 2017
Just a gentle reminder to all that deadline for completing the survey is this Sunday midnight GMT ( October 8th, 2017). Please feel free to forward the link to all your colleagues who can provide feedback on dpdk. Thanks, Deepak From: Jain, Deepak K Sent: Friday, September 22, 2017 2:18 PM To: annou...@dpdk.org<mailto:annou...@dpdk.org> Subject: DPDK Community Survey 2017 Hi All, As part of our ongoing efforts to improve DPDK, we'd like to hear your feedback! We have created a number of DPDK-related questions here. https://www.surveymonkey.com/r/DPDK_Community_Survey_2017 and want to hear your views!! The survey will close at midnight GMT on Sunday October 8th, 2017. Thanks in advance for your feedback - the more responses we get the more data we have to drive further features, improvements, etc. So please respond!!! Regards Deepak
Re: [dpdk-dev] DPDK Community Survey 2017
Hi All, Just wanted to say big Thank you for filling the DPDK Survey and providing valuable feedback. In total, survey received 190 responses. I am compiling the results/feedback and will share them in due course. Thanks again, Deepak From: Jain, Deepak K Sent: Thursday, October 5, 2017 2:04 PM To: 'annou...@dpdk.org' ; 'us...@dpdk.org' ; 'dev@dpdk.org' Cc: 'Thomas Monjalon' Subject: RE: DPDK Community Survey 2017 Just a gentle reminder to all that deadline for completing the survey is this Sunday midnight GMT ( October 8th, 2017). Please feel free to forward the link to all your colleagues who can provide feedback on dpdk. Thanks, Deepak From: Jain, Deepak K Sent: Friday, September 22, 2017 2:18 PM To: annou...@dpdk.org<mailto:annou...@dpdk.org> Subject: DPDK Community Survey 2017 Hi All, As part of our ongoing efforts to improve DPDK, we'd like to hear your feedback! We have created a number of DPDK-related questions here. https://www.surveymonkey.com/r/DPDK_Community_Survey_2017 and want to hear your views!! The survey will close at midnight GMT on Sunday October 8th, 2017. Thanks in advance for your feedback - the more responses we get the more data we have to drive further features, improvements, etc. So please respond!!! Regards Deepak
Re: [dpdk-dev] [PATCH v1] doc: add note in proc info for stats retrieval
> -Original Message- > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Marko Kovacevic > Sent: Wednesday, January 24, 2018 4:47 PM > To: dev@dpdk.org > Cc: Mcnamara, John ; Varghese, Vipin > ; Kovacevic, Marko > > Subject: [dpdk-dev] [PATCH v1] doc: add note in proc info for stats retrieval > > Note added to outline that using > proc_info for virtual devices is not supported > > Signed-off-by: Marko Kovacevic > --- > doc/guides/tools/proc_info.rst | 3 +++ > 1 file changed, 3 insertions(+) > > **-m**: Print DPDK memory information. > + > +.. NOTE:: > + NOTE: Stats retrieval using ``proc_info`` is not supported for > +virtual devices like PCAP and TAP > -- > 2.9.5 Acked-by: Deepak Kumar Jain
Re: [dpdk-dev] [RFC v3] Compression API in DPDK :SW ZLIB PMD
Hi Shally, > -Original Message- > From: Verma, Shally [mailto:shally.ve...@cavium.com] > Sent: Friday, February 2, 2018 11:27 AM > To: Trahe, Fiona ; dev@dpdk.org > Cc: Gupta, Ashish ; Sahu, Sunila > ; Challa, Mahipal ; > Athreya, Narayana Prasad ; De Lara > Guarch, Pablo ; Jain, Deepak K > ; Roy Pledge ; Youri > Querry ; Hemant Agrawal > ; Ahmed Mansour > ; De Lara Guarch, Pablo > > Subject: RE: [RFC v3] Compression API in DPDK :SW ZLIB PMD >; Roy Pledge ; Youri > >Querry ; Hemant Agrawal > >; Ahmed Mansour > ; De > >Lara Guarch, Pablo > >Subject: RE: [RFC v3] Compression API in DPDK :SW ZLIB PMD > > > >Hi Fiona > > > >> I think a common draft repo would be the best way forward. Let's talk to > the maintainers about getting one set up. > >Sure. Please share us details when it is available. I assume it will be > >created > once API spec move from RFC to 1st version? > > > [Shally] Any update on this? We're available with sample SW ZLIB based > implementation (currently proof-concepted for stateless only) . So, if any > repo is available, we can upload it there. We are working towards getting final internal approvals and will have more info. on this early next week. > > >Thanks > >Shally > > > >From: Trahe, Fiona [mailto:fiona.tr...@intel.com] > >Sent: 12 January 2018 00:31 > >To: Verma, Shally ; dev@dpdk.org > >Cc: Gupta, Ashish ; Sahu, Sunila > >; Challa, Mahipal > ; > >Athreya, Narayana Prasad ; De > Lara > >Guarch, Pablo ; Jain, Deepak K > >; Roy Pledge ; Youri > >Querry ; Hemant Agrawal > >; Ahmed Mansour > ; Trahe, > >Fiona ; De Lara Guarch, Pablo > > > >Subject: RE: [RFC v3] Compression API in DPDK :SW ZLIB PMD > > > >Hi Shally, > > > > > >From: Verma, Shally [mailto:shally.ve...@cavium.com] > >Sent: Wednesday, January 10, 2018 8:33 AM > >To: Trahe, Fiona <mailto:fiona.tr...@intel.com>; mailto:dev@dpdk.org > >Cc: Gupta, Ashish <mailto:ashish.gu...@cavium.com>; Sahu, Sunila > ><mailto:sunila.s...@cavium.com>; Challa, Mahipal > ><mailto:mahipal.cha...@cavium.com>; Athreya, Narayana Prasad > ><mailto:narayanaprasad.athr...@cavium.com>; De Lara Guarch, Pablo > ><mailto:pablo.de.lara.gua...@intel.com>; Jain, Deepak K > ><mailto:deepak.k.j...@intel.com>; Roy Pledge > ><mailto:roy.ple...@nxp.com>; Youri Querry > ><mailto:youri.querr...@nxp.com>; Hemant Agrawal > ><mailto:hemant.agra...@nxp.com>; Ahmed Mansour > ><mailto:ahmed.mans...@nxp.com> > >Subject: [RFC v3] Compression API in DPDK :SW ZLIB PMD > > > >Hi Fiona > > > >We are planning to implement ZLIB based SW PMD to proof-concept DPDK > >compression RFC v3 API spec internally. However, would like to check If > >you're working upon similar in parallel and if yes, then what's your > >development roadmap / strategy so that we could see if we could leverage > joint effort. > >Depending upon your feedback, we can see if we can have some common > repo for joint development or send it as RFC patch. > > > >Let me know your opinion on same. > >[Fiona] We have not started a zlib based SW PMD, and would be delighted > >if you would do this, I agree it's a good way to prove out the API. > >We are writing some unit tests against the API, we would be happy to > >share these with you, and continue to develop these jointly so the same > test sets can be targeted against all PMDs. > >I think a common draft repo would be the best way forward. Let's talk to > the maintainers about getting one set up. > > > >Thanks > >Shally
Re: [dpdk-dev] FW: [RFC v1 1/1] lib/cryptodev: add support of asymmetric crypto
HI Shally, > -Original Message- > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Verma, Shally > Subject: [dpdk-dev] FW: [RFC v1 1/1] lib/cryptodev: add support of > asymmetric crypto > > Hi Pablo/Fiona > > Could you please provide your input on this RFC. Your feedback is awaited. Many thanks for sending the RFC. We are looking into this and will provide feedback by end of business next week. > > Thanks > Shally > > -Original Message- > From: Verma, Shally > Sent: 23 January 2018 15:24 > To: declan.dohe...@intel.com > Cc: dev@dpdk.org; Athreya, Narayana Prasad > ; Murthy, Nidadavolu > ; Sahu, Sunila > ; Gupta, Ashish ; > Verma, Shally > Subject: [RFC v1 1/1] lib/cryptodev: add support of asymmetric crypto > > From: Shally Verma > > Add support for asymmetric crypto operations in DPDK lib cryptodev > > Key feature include: > - Only session based asymmetric crypto operations > - new get and set APIs for symmetric and asymmetric session private > data and other informations > - APIs to create, configure and attch queue pair to asymmetric sessions > - new capabilities in struct device_info to indicate > -- number of dedicated queue pairs available for symmetric and > asymmetric operations, if any > -- number of asymmetric sessions possible per qp > > Proposed asymmetric cryptographic operations are: > - rsa > - dsa > - deffie-hellman key pair generation and shared key computation > - ecdeffie-hellman > - fundamental elliptic curve operations > - elliptic curve DSA > - modular exponentiation and inversion > > This patch primarily defines PMD operations and device capabilities > to perform asymmetric crypto ops on queue pairs and intend to > invite feedbacks on current proposal so as to ensure it encompass > all kind of crypto devices with different capabilities and queue > pair management. > > List of TBDs: > - Currently, patch only updated for RSA xform and associated params. > Other algoritms to be added in subsequent versions. > - per-service stats update > > Signed-off-by: Shally Verma > --- > > It is derivative of RFC v2 asymmetric crypto patch series initiated by > Umesh Kartha(mailto:umesh.kar...@caviumnetworks.com): > > http://dpdk.org/dev/patchwork/patch/24245/ > http://dpdk.org/dev/patchwork/patch/24246/ > http://dpdk.org/dev/patchwork/patch/24247/ > > And inclusive of all review comments given on RFC v2. > ( See complete discussion thread here: > http://dev.dpdk.narkive.com/yqTFFLHw/dpdk-dev-rfc-specifications-for- > asymmetric-crypto-algorithms#post12) > > Some of the RFCv2 Review comments pending for closure: > > " [Fiona] The count fn isn't used at all for sym - probably no need to add > > for > asym > better instead to remove the sym fn." > > It is still present in dpdk-next-crypto for sym, so what has been > decision > on it? > > >"[Fiona] if each qp can handle only a specific service, i.e. a subset off the > capabilities > Indicated by the device capability list, there's a need for a new API to > query > the capability of a qp." > > Current proposal doesn’t distinguish between device capability and qp > capability. > It rather leave such differences handling internal to PMDs. Thus no > capability > or API added for qp in current version. It is subject to revisit based on > review > feedback on current proposal. > > - Sessionless Support. > Current proposal only support Session-based because: > 1. All one-time setup i.e. algos and associated params, such as, public- > private keys > or modulus length can be done in control path using session-init API > 2. it’s an easier way to dedicate qp to do specific service (using > queue_pair_attach()) > which cannot be case in sessionless > 3. Couldn’t find any significant advantage going sessionless way. Also > existing most of PMDs are session-based. > > It could be added in subsequent versions, if requirement is identified, > based on review comment > on this RFC. > > Summary > --- > > This section provides an overview of key feature enabled in current > specification. > It comprise of key design challenges as have been identified on RFCv2 and > summary description of new interfaces and definitions added to handle > same. > > Description > --- > > This API set assumes that the max_nb_queue_pairs on a > device can be allocated to any mix of sym or asym. Some devices > may have a fixed max per service. Thus, rte_cryptodev_info > is updated with max_sym_nb_queues and max_asym_nb_queues with rule: > > max_nb_queue_pair = max_nb_sym_qp + max_nb_asym_qp. > > If device has no restrictions on qp to be used per service, such PMDs can > leave > max_nb_sym_qp = max_nb_asym_qp = 0. In such case, application can > setup any of > the service upto limit defined by max_nb_queue_pair. > > Here, max_nb_sym_qp and max_nb_asym_qp, if non-zero, just define limit > on qp which are > available for each ser
[dpdk-dev] [PATCH] Adding maintainers for Intel QAT PMD
On 05/02/16 16:36, Fiona Trahe wrote: > Signed-off-by: Fiona Trahe Acked-by: John Griffin Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] qat: fix for VFs not getting recognized
Due to addition of CLASS_ID in EAL, class_id is
amended into the code.
Fixes: 701c8d80c820 ("pci: support class id probing")
Signed-off-by: Deepak Kumar Jain
---
drivers/crypto/qat/rte_qat_cryptodev.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/qat/rte_qat_cryptodev.c
b/drivers/crypto/qat/rte_qat_cryptodev.c
index a7912f5..2bad201 100644
--- a/drivers/crypto/qat/rte_qat_cryptodev.c
+++ b/drivers/crypto/qat/rte_qat_cryptodev.c
@@ -72,7 +72,8 @@ static struct rte_pci_id pci_id_qat_map[] = {
.vendor_id = 0x8086,
.device_id = 0x0443,
.subsystem_vendor_id = PCI_ANY_ID,
- .subsystem_device_id = PCI_ANY_ID
+ .subsystem_device_id = PCI_ANY_ID,
+ .class_id = 0xB4000
},
{.device_id = 0},
};
--
2.5.5
[dpdk-dev] [PATCH] qat: fix for VFs not getting recognized
> -Original Message- > From: Thomas Monjalon [mailto:thomas.monjalon at 6wind.com] > Sent: Thursday, June 16, 2016 5:16 PM > To: Jain, Deepak K > Cc: dev at dpdk.org; Griffin, John ; De Lara > Guarch, > Pablo ; Doherty, Declan > > Subject: Re: [dpdk-dev] [PATCH] qat: fix for VFs not getting recognized > > 2016-06-16 16:29, Jain, Deepak K: > > Due to addition of CLASS_ID in EAL, class_id is amended into the code. > > Why the VF is not recognized? > The class id should not be mandatory. Without the change proposed, QuickAssist Devices were not visible and hence tests were not running. Seems like changes in EAL especially where class_id is added affected the QuickAssist tests. With this change, QuickAssist devices are visible during tests and tests working fine.
[dpdk-dev] [PATCH 0/4] Extending cryptodev Performance tests
Performance tests haven been extended in this patchset. Patchset consists of 4 patches: Patch 1 adds new function rte_crypto_op_bulk_free to be used in patch 2 and patch 3. Patch 2 add snow3g performance tests. Patch 3 updates the existing aes performanc test Patch 4 fixes the typo in names of perftest Declan Doherty (1): cryptodev: add rte_crypto_op_bulk_free function Fiona Trahe (2): app/test: adding Snow3g performance test app/test: updating AES SHA performance test Jain, Deepak K (1): app/test: typo fixing app/test/test_cryptodev.h |4 +- app/test/test_cryptodev_perf.c| 1153 - lib/librte_cryptodev/rte_crypto.h | 15 + 3 files changed, 1030 insertions(+), 142 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH 1/4] cryptodev: add rte_crypto_op_bulk_free function
From: Declan Doherty
Adding rte_crypto_op_bulk_free to free up the ops in bulk
so as to expect improvement in performance.
Signed-off-by: Declan Doherty
---
lib/librte_cryptodev/rte_crypto.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/lib/librte_cryptodev/rte_crypto.h
b/lib/librte_cryptodev/rte_crypto.h
index 5bc3eaa..31abbdc 100644
--- a/lib/librte_cryptodev/rte_crypto.h
+++ b/lib/librte_cryptodev/rte_crypto.h
@@ -328,6 +328,21 @@ rte_crypto_op_free(struct rte_crypto_op *op)
}
/**
+ * free crypto operation structure
+ * If operation has been allocate from a rte_mempool, then the operation will
+ * be returned to the mempool.
+ *
+ * @param op symmetric crypto operation
+ */
+static inline void
+rte_crypto_op_bulk_free(struct rte_mempool *mpool, struct rte_crypto_op **ops,
+ uint16_t nb_ops)
+{
+ if (ops != NULL)
+ rte_mempool_put_bulk(mpool, (void * const *)ops, nb_ops);
+}
+
+/**
* Allocate a symmetric crypto operation in the private data of an mbuf.
*
* @param m mbuf which is associated with the crypto operation, the
--
2.5.5
[dpdk-dev] [PATCH 2/4] app/test: adding Snow3g performance test
From: Fiona Trahe
Adding performance test for snow3g wireless algorithm.
Performance test can run over both software and hardware.
Signed-off-by: Fiona Trahe
Signed-off-by: Jain, Deepak K
Signed-off-by: Declan Doherty
---
app/test/test_cryptodev.h | 2 +-
app/test/test_cryptodev_perf.c | 688 -
2 files changed, 688 insertions(+), 2 deletions(-)
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index 6059a01..d549eca 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -46,7 +46,7 @@
#define DEFAULT_BURST_SIZE (64)
#define DEFAULT_NUM_XFORMS (2)
#define NUM_MBUFS (8191)
-#define MBUF_CACHE_SIZE (250)
+#define MBUF_CACHE_SIZE (256)
#define MBUF_DATAPAYLOAD_SIZE (2048 + DIGEST_BYTE_LENGTH_SHA512)
#define MBUF_SIZE (sizeof(struct rte_mbuf) + \
RTE_PKTMBUF_HEADROOM + MBUF_DATAPAYLOAD_SIZE)
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index b3f4fd9..06148d0 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -58,6 +58,25 @@ struct crypto_testsuite_params {
uint8_t dev_id;
};
+enum chain_mode {
+ CIPHER_HASH,
+ HASH_CIPHER,
+ CIPHER_ONLY,
+ HASH_ONLY
+};
+
+struct perf_test_params {
+
+ unsigned total_operations;
+ unsigned burst_size;
+ unsigned buf_size;
+
+ enum chain_mode chain;
+
+ enum rte_crypto_cipher_algorithm cipher_algo;
+ unsigned cipher_key_length;
+ enum rte_crypto_auth_algorithm auth_algo;
+};
#define MAX_NUM_OF_OPS_PER_UT (128)
@@ -75,6 +94,98 @@ struct crypto_unittest_params {
uint8_t *digest;
};
+static struct rte_cryptodev_sym_session *
+test_perf_create_snow3g_session(uint8_t dev_id, enum chain_mode chain,
+ enum rte_crypto_cipher_algorithm cipher_algo, unsigned
cipher_key_len,
+ enum rte_crypto_auth_algorithm auth_algo);
+static struct rte_mbuf *
+test_perf_create_pktmbuf(struct rte_mempool *mpool, unsigned buf_sz);
+static inline struct rte_crypto_op *
+test_perf_set_crypto_op_snow3g(struct rte_crypto_op *op, struct rte_mbuf *m,
+ struct rte_cryptodev_sym_session *sess, unsigned data_len,
+ unsigned digest_len);
+static uint32_t get_auth_digest_length(enum rte_crypto_auth_algorithm algo);
+
+
+static const char *chain_mode_name(enum chain_mode mode)
+{
+ switch (mode) {
+ case CIPHER_HASH: return "cipher_hash"; break;
+ case HASH_CIPHER: return "hash_cipher"; break;
+ case CIPHER_ONLY: return "cipher_only"; break;
+ case HASH_ONLY: return "hash_only"; break;
+ default: return ""; break;
+ }
+}
+
+static const char *pmd_name(enum rte_cryptodev_type pmd)
+{
+ switch (pmd) {
+ case RTE_CRYPTODEV_NULL_PMD: return CRYPTODEV_NAME_NULL_PMD; break;
+ case RTE_CRYPTODEV_AESNI_GCM_PMD:
+ return CRYPTODEV_NAME_AESNI_GCM_PMD;
+ case RTE_CRYPTODEV_AESNI_MB_PMD:
+ return CRYPTODEV_NAME_AESNI_MB_PMD;
+ case RTE_CRYPTODEV_QAT_SYM_PMD:
+ return CRYPTODEV_NAME_QAT_SYM_PMD;
+ case RTE_CRYPTODEV_SNOW3G_PMD:
+ return CRYPTODEV_NAME_SNOW3G_PMD;
+ default:
+ return "";
+ }
+}
+
+static const char *cipher_algo_name(enum rte_crypto_cipher_algorithm
cipher_algo)
+{
+ switch (cipher_algo) {
+ case RTE_CRYPTO_CIPHER_NULL: return "NULL";
+ case RTE_CRYPTO_CIPHER_3DES_CBC: return "3DES_CBC";
+ case RTE_CRYPTO_CIPHER_3DES_CTR: return "3DES_CTR";
+ case RTE_CRYPTO_CIPHER_3DES_ECB: return "3DES_ECB";
+ case RTE_CRYPTO_CIPHER_AES_CBC: return "AES_CBC";
+ case RTE_CRYPTO_CIPHER_AES_CCM: return "AES_CCM";
+ case RTE_CRYPTO_CIPHER_AES_CTR: return "AES_CTR";
+ case RTE_CRYPTO_CIPHER_AES_ECB: return "AES_ECB";
+ case RTE_CRYPTO_CIPHER_AES_F8: return "AES_F8";
+ case RTE_CRYPTO_CIPHER_AES_GCM: return "AES_GCM";
+ case RTE_CRYPTO_CIPHER_AES_XTS: return "AES_XTS";
+ case RTE_CRYPTO_CIPHER_ARC4: return "ARC4";
+ case RTE_CRYPTO_CIPHER_KASUMI_F8: return "KASUMI_F8";
+ case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: return "SNOW3G_UEA2";
+ case RTE_CRYPTO_CIPHER_ZUC_EEA3: return "ZUC_EEA3";
+ default: return "Another cipher algo";
+ }
+}
+
+static const char *auth_algo_name(enum rte_crypto_auth_algorithm auth_algo)
+{
+ switch (auth_algo) {
+ case RTE_CRYPTO_AUTH_NULL: return "NULL"; break;
+ case RTE_CRYPTO_AUTH_AES_CBC_MAC: return "AES_CBC_MAC"; break;
+ case RTE_CRYPTO_AUTH_
[dpdk-dev] [PATCH 3/4] app/test: updating AES SHA performance test
From: Fiona Trahe
Updating the AES performance test in line with snow3g peformance test.
Output format has been updated so as to get better understanding of numbers.
Signed-off-by: Fiona Trahe
Signed-off-by: Jain, Deepak K
---
app/test/test_cryptodev.h | 2 +
app/test/test_cryptodev_perf.c | 551 +++--
2 files changed, 370 insertions(+), 183 deletions(-)
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index d549eca..382802c 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -64,7 +64,9 @@
#define AES_XCBC_MAC_KEY_SZ(16)
#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA1 (12)
+#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA224(16)
#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA256(16)
+#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA384(24)
#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA512(32)
#endif /* TEST_CRYPTODEV_H_ */
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index 06148d0..6c43a93 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -492,12 +492,11 @@ const char plaintext_quote[] =
#define CIPHER_KEY_LENGTH_AES_CBC (16)
#define CIPHER_IV_LENGTH_AES_CBC (CIPHER_KEY_LENGTH_AES_CBC)
-
-static uint8_t aes_cbc_key[] = {
+static uint8_t aes_cbc_128_key[] = {
0xE4, 0x23, 0x33, 0x8A, 0x35, 0x64, 0x61, 0xE2,
0xF1, 0x35, 0x5C, 0x3B, 0xDD, 0x9A, 0x65, 0xBA };
-static uint8_t aes_cbc_iv[] = {
+static uint8_t aes_cbc_128_iv[] = {
0xf5, 0xd3, 0x89, 0x0f, 0x47, 0x00, 0xcb, 0x52,
0x42, 0x1a, 0x7d, 0x3d, 0xf5, 0x82, 0x80, 0xf1 };
@@ -1846,7 +1845,7 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_AES_CBC;
ut_params->cipher_xform.cipher.op = RTE_CRYPTO_CIPHER_OP_DECRYPT;
- ut_params->cipher_xform.cipher.key.data = aes_cbc_key;
+ ut_params->cipher_xform.cipher.key.data = aes_cbc_128_key;
ut_params->cipher_xform.cipher.key.length = CIPHER_IV_LENGTH_AES_CBC;
@@ -1902,7 +1901,7 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
op->sym->cipher.iv.phys_addr = rte_pktmbuf_mtophys(m);
op->sym->cipher.iv.length = CIPHER_IV_LENGTH_AES_CBC;
- rte_memcpy(op->sym->cipher.iv.data, aes_cbc_iv,
+ rte_memcpy(op->sym->cipher.iv.data, aes_cbc_128_iv,
CIPHER_IV_LENGTH_AES_CBC);
op->sym->cipher.data.offset = CIPHER_IV_LENGTH_AES_CBC;
@@ -1985,169 +1984,6 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
}
static int
-test_perf_AES_CBC_HMAC_SHA256_encrypt_digest_vary_req_size(uint16_t dev_num)
-{
- uint16_t index;
- uint32_t burst_sent, burst_received;
- uint32_t b, num_sent, num_received;
- uint64_t failed_polls, retries, start_cycles, end_cycles;
- const uint64_t mhz = rte_get_tsc_hz()/100;
- double throughput, mmps;
-
- struct rte_crypto_op *c_ops[DEFAULT_BURST_SIZE];
- struct rte_crypto_op *proc_ops[DEFAULT_BURST_SIZE];
-
- struct crypto_testsuite_params *ts_params = &testsuite_params;
- struct crypto_unittest_params *ut_params = &unittest_params;
- struct crypto_data_params *data_params = aes_cbc_hmac_sha256_output;
-
- if (rte_cryptodev_count() == 0) {
- printf("\nNo crypto devices available. Is kernel driver
loaded?\n");
- return TEST_FAILED;
- }
-
- /* Setup Cipher Parameters */
- ut_params->cipher_xform.type = RTE_CRYPTO_SYM_XFORM_CIPHER;
- ut_params->cipher_xform.next = &ut_params->auth_xform;
-
- ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_AES_CBC;
- ut_params->cipher_xform.cipher.op = RTE_CRYPTO_CIPHER_OP_ENCRYPT;
- ut_params->cipher_xform.cipher.key.data = aes_cbc_key;
- ut_params->cipher_xform.cipher.key.length = CIPHER_IV_LENGTH_AES_CBC;
-
- /* Setup HMAC Parameters */
- ut_params->auth_xform.type = RTE_CRYPTO_SYM_XFORM_AUTH;
- ut_params->auth_xform.next = NULL;
-
- ut_params->auth_xform.auth.op = RTE_CRYPTO_AUTH_OP_GENERATE;
- ut_params->auth_xform.auth.algo = RTE_CRYPTO_AUTH_SHA256_HMAC;
- ut_params->auth_xform.auth.key.data = hmac_sha256_key;
- ut_params->auth_xform.auth.key.length = HMAC_KEY_LENGTH_SHA256;
- ut_params->auth_xform.auth.digest_length = DIGEST_BYTE_LENGTH_SHA256;
-
- /* Create Crypto session*/
- ut_params->sess = rte_cryptodev_sym_session_create(ts_params->dev_id,
- &ut_params->cipher_xform);
-
- TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
-
- printf("\nThroughput test which will con
[dpdk-dev] [PATCH 4/4] app/test: typo fixing
Fixing typo in the performance tests for example preftest to perftest.
Signed-off-by: Jain, Deepak K
---
app/test/test_cryptodev_perf.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index 6c43a93..903529f 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -208,7 +208,7 @@ setup_test_string(struct rte_mempool *mpool,
static struct crypto_testsuite_params testsuite_params = { NULL };
static struct crypto_unittest_params unittest_params;
-static enum rte_cryptodev_type gbl_cryptodev_preftest_devtype;
+static enum rte_cryptodev_type gbl_cryptodev_perftest_devtype;
static int
testsuite_setup(void)
@@ -245,7 +245,7 @@ testsuite_setup(void)
}
/* Create 2 AESNI MB devices if required */
- if (gbl_cryptodev_preftest_devtype == RTE_CRYPTODEV_AESNI_MB_PMD) {
+ if (gbl_cryptodev_perftest_devtype == RTE_CRYPTODEV_AESNI_MB_PMD) {
nb_devs =
rte_cryptodev_count_devtype(RTE_CRYPTODEV_AESNI_MB_PMD);
if (nb_devs < 2) {
for (i = nb_devs; i < 2; i++) {
@@ -260,7 +260,7 @@ testsuite_setup(void)
}
/* Create 2 SNOW3G devices if required */
- if (gbl_cryptodev_preftest_devtype == RTE_CRYPTODEV_SNOW3G_PMD) {
+ if (gbl_cryptodev_perftest_devtype == RTE_CRYPTODEV_SNOW3G_PMD) {
nb_devs = rte_cryptodev_count_devtype(RTE_CRYPTODEV_SNOW3G_PMD);
if (nb_devs < 2) {
for (i = nb_devs; i < 2; i++) {
@@ -283,7 +283,7 @@ testsuite_setup(void)
/* Search for the first valid */
for (i = 0; i < nb_devs; i++) {
rte_cryptodev_info_get(i, &info);
- if (info.dev_type == gbl_cryptodev_preftest_devtype) {
+ if (info.dev_type == gbl_cryptodev_perftest_devtype) {
ts_params->dev_id = i;
valid_dev_id = 1;
break;
@@ -1956,7 +1956,7 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
}
while (num_received != num_to_submit) {
- if (gbl_cryptodev_preftest_devtype ==
+ if (gbl_cryptodev_perftest_devtype ==
RTE_CRYPTODEV_AESNI_MB_PMD)
rte_cryptodev_enqueue_burst(dev_num, 0,
NULL, 0);
@@ -2028,7 +2028,7 @@ test_perf_snow3G_optimise_cyclecount(struct
perf_test_params *pparams)
printf("\nOn %s dev%u qp%u, %s, cipher algo:%s, auth_algo:%s, "
"Packet Size %u bytes",
- pmd_name(gbl_cryptodev_preftest_devtype),
+ pmd_name(gbl_cryptodev_perftest_devtype),
ts_params->dev_id, 0,
chain_mode_name(pparams->chain),
cipher_algo_name(pparams->cipher_algo),
@@ -2072,7 +2072,7 @@ test_perf_snow3G_optimise_cyclecount(struct
perf_test_params *pparams)
}
while (num_ops_received != num_to_submit) {
- if (gbl_cryptodev_preftest_devtype ==
+ if (gbl_cryptodev_perftest_devtype ==
RTE_CRYPTODEV_AESNI_MB_PMD)
rte_cryptodev_enqueue_burst(ts_params->dev_id,
0,
NULL, 0);
@@ -2680,7 +2680,7 @@ test_perf_snow3g(uint8_t dev_id, uint16_t queue_id,
double cycles_B = cycles_buff / pparams->buf_size;
double throughput = (ops_s * pparams->buf_size * 8) / 100;
- if (gbl_cryptodev_preftest_devtype == RTE_CRYPTODEV_QAT_SYM_PMD) {
+ if (gbl_cryptodev_perftest_devtype == RTE_CRYPTODEV_QAT_SYM_PMD) {
/* Cycle count misleading on HW devices for this test, so don't
print */
printf("%4u\t%6.2f\t%10.2f\t n/a \t\t n/a "
"\t\t n/a \t\t%8"PRIu64"\t%8"PRIu64,
@@ -2824,7 +2824,7 @@ test_perf_snow3G_vary_pkt_size(void)
for (k = 0; k < RTE_DIM(burst_sizes); k++) {
printf("\nOn %s dev%u qp%u, %s, "
"cipher algo:%s, auth algo:%s, burst_size: %d
ops",
- pmd_name(gbl_cryptodev_preftest_devtype),
+ pmd_name(gbl_cryptodev_perftest_devtype),
testsuite_params.dev_id, 0,
chain_mode_name(params_set[i].chain),
cipher_algo_name(params_set[i].cipher_algo),
@@ -2893,7 +2893,7 @@ static struct unit_test_suite cryptodev_snow3g_testsuite
= {
static int
perftest_aesni_mb_cryptodev(voi
[dpdk-dev] [PATCH] qat: fix for VFs not getting recognized
> -Original Message- > From: Thomas Monjalon [mailto:thomas.monjalon at 6wind.com] > Sent: Friday, June 17, 2016 9:19 AM > To: Jain, Deepak K > Cc: dev at dpdk.org; Griffin, John ; De Lara > Guarch, > Pablo ; Doherty, Declan > > Subject: Re: [dpdk-dev] [PATCH] qat: fix for VFs not getting recognized > > 2016-06-16 16:25, Jain, Deepak K: > > From: Thomas Monjalon [mailto:thomas.monjalon at 6wind.com] > > > 2016-06-16 16:29, Jain, Deepak K: > > > > Due to addition of CLASS_ID in EAL, class_id is amended into the code. > > > > > > Why the VF is not recognized? > > > The class id should not be mandatory. > > > > Without the change proposed, QuickAssist Devices were not visible and > hence tests were not running. > > Seems like changes in EAL especially where class_id is added affected the > QuickAssist tests. > > With this change, QuickAssist devices are visible during tests and tests > working fine. > > Which tests? > Have you investigated why? Hi Thomas, On investigation, I found that when class_id is not set in the rte_qat_cryptodev.c, the value of id_table->class_id defaults to 0. Hence the following code snippet always executes and the probing of driver is never done. if (id_table->class_id != dev->id.class_id && id_table->class_id != RTE_CLASS_ANY_ID continue; If value of id_table->class_id is set, as shown in patch which was submitted, the id_table->class_ID is set to RTE_CLASS_ANY_ID and hence its probes the driver and fixes the issues. Other fix would be to set default value of class_id equal to RTE_CLASS_ANY_ID instead of 0.
[dpdk-dev] [PATCH v2 0/3] Add new KASUMI SW PMD
> -Original Message-
> From: De Lara Guarch, Pablo
> Sent: Friday, June 17, 2016 11:33 AM
> To: dev at dpdk.org
> Cc: Doherty, Declan ; De Lara Guarch, Pablo
>
> Subject: [PATCH v2 0/3] Add new KASUMI SW PMD
>
> Added new SW PMD which makes use of the libsso SW library, which
> provides wireless algorithms KASUMI F8 and F9 in software.
>
> This PMD supports cipher-only, hash-only and chained operations ("cipher
> then hash" and "hash then cipher") of the following
> algorithms:
> - RTE_CRYPTO_SYM_CIPHER_KASUMI_F8
> - RTE_CRYPTO_SYM_AUTH_KASUMI_F9
>
> The patchset also adds new macros to compare buffers at bit-level, since the
> PMD supports bit-level hash/cipher operations, and unit tests.
>
> The patchset should be merged after the following patches/patchsets, as
> they are making changes in some of the files of this patchset:
> - rework crypto AES unit test
> ("http://dpdk.org/ml/archives/dev/2016-June/041572.html";)
> - Refactor of debug information on cryptodev tests
> ("http://dpdk.org/ml/archives/dev/2016-June/041623.html";)
> - doc: fix wrong supported feature table
> ("http://dpdk.org/dev/patchwork/patch/13413/";)
>
> NOTE: The library necessary for this PMD is not available yet, but it will be
> released in the next few days.
>
> Changes in v2:
> - Fixed key length
> - Refactored enqueue burst function to avoid duplication
> - Added CPU flags in crypto feature flags
> - Added extra unit tets
> - Added documentation
> - Merged last patch in v1 into the first patch
> - Added new driver in MAINTAINERS
>
> Pablo de Lara (3):
> kasumi: add new KASUMI PMD
> test: add new buffer comparison macros
> test: add unit tests for KASUMI PMD
>
>
> --
> 2.5.0
Series Acked-by: Jain, Deepak K
[dpdk-dev] [PATCH v2 00/11] Snow3G bit-level support
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara > Sent: Friday, June 17, 2016 12:25 PM > To: dev at dpdk.org > Cc: Doherty, Declan ; De Lara Guarch, Pablo > > Subject: [dpdk-dev] [PATCH v2 00/11] Snow3G bit-level support > > The underlying library libsso for Snow3G PMD will be updated, to support bit- > level operations. > > This patchset updates the PMD to allow the user to perform crypto operation > at bit-level. It also add some unit tests and updates the documentation. > > This patchset depends on the following patchset: > "Add new KASUMI SW PMD" > (http://dpdk.org/ml/archives/dev/2016-June/041906.html) > > NOTE: The library necessary for this PMD is not available yet, but it will be > released in the next few days. > > Changes in v2: > - Include macros for IV/digest lengths > - Refactored enqueue burst function to avoid duplication > - Added cpu flags in crypto feature flags > - Removed/refactored functions in unit tests > > Pablo de Lara (11): > snow3g: rename libsso reference due to library update > doc: update build instructions for libsso_snow3g > snow3g: define IV/digest length macros > snow3g: support bit-level operations > snow3g: add missing feature flags > test: use new bit-level memcmp macro > test: fix buffer lengths for snow3G tests > test: add out-of-place crypto op tests for Snow3G PMD > test: add bit-level Snow3G UIA2 tests > test: add Snow3G UEA2 test with offset > test: refactor snow3g/kasumi tests > > app/test/test_cryptodev.c | 803 > ++--- > app/test/test_cryptodev_snow3g_hash_test_vectors.h | 107 +++ > config/common_base | 4 +- > doc/guides/cryptodevs/snow3g.rst | 40 +- > drivers/crypto/snow3g/Makefile | 10 +- > drivers/crypto/snow3g/rte_snow3g_pmd.c | 216 -- > mk/rte.app.mk | 2 +- > scripts/test-build.sh | 6 +- > 8 files changed, 677 insertions(+), 511 deletions(-) > > -- > 2.5.0 Series Acked-by: Jain, Deepak K
[dpdk-dev] [PATCH 1/4] cryptodev: add rte_crypto_op_bulk_free function
Hi Thomas, > -Original Message- > From: Thomas Monjalon [mailto:thomas.monjalon at 6wind.com] > Sent: Monday, June 20, 2016 10:46 AM > To: Jain, Deepak K ; Doherty, Declan > > Cc: dev at dpdk.org; Griffin, John ; Trahe, Fiona > ; De Lara Guarch, Pablo > > Subject: Re: [dpdk-dev] [PATCH 1/4] cryptodev: add > rte_crypto_op_bulk_free function > > 2016-06-16 20:49, Jain, Deepak K: > > From: Declan Doherty > > > > Adding rte_crypto_op_bulk_free to free up the ops in bulk so as to > > expect improvement in performance. > > > > Signed-off-by: Declan Doherty > > I wonder why these changes are dropped so late? I agree that these changes got late due to more than expected dubugging time spent on performance code. I will send v2 of the patches without addition of rte_crypto_op_bulk_free. > > > /** > > + * free crypto operation structure > > + * If operation has been allocate from a rte_mempool, then the > > + operation will > > + * be returned to the mempool. > > + * > > + * @param op symmetric crypto operation > > + */ > > Please check punctuation, grammar and document every parameters. Will not need any changes as in v2, this function will be removed. > > > +static inline void > > +rte_crypto_op_bulk_free(struct rte_mempool *mpool, struct > rte_crypto_op **ops, > > + uint16_t nb_ops)
[dpdk-dev] [PATCH v2 0/3] Extending cryptodev Performance tests
Performance tests haven been extended in this patchset. Patchset consists of 3 patches: Patch 1 add snow3g performance tests. Patch 2 updates the existing aes performanc test Patch 3 fixes the typo in names of perftest Changes in v2: Removed the addtion of rte_crypto_op_bulk_free Fiona Trahe (2): app/test: adding Snow3g performance test app/test: updating AES SHA performance test Jain, Deepak K (1): app/test: typo fixing app/test/test_cryptodev.h |4 +- app/test/test_cryptodev_perf.c | 1157 +++- 2 files changed, 1019 insertions(+), 142 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH v2 1/3] app/test: adding Snow3g performance test
From: Fiona Trahe
Adding performance test for snow3g wireless algorithm.
Performance test can run over both software and hardware.
Signed-off-by: Fiona Trahe
Signed-off-by: Jain, Deepak K
Signed-off-by: Declan Doherty
---
app/test/test_cryptodev.h | 2 +-
app/test/test_cryptodev_perf.c | 690 -
2 files changed, 690 insertions(+), 2 deletions(-)
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index 6059a01..d549eca 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -46,7 +46,7 @@
#define DEFAULT_BURST_SIZE (64)
#define DEFAULT_NUM_XFORMS (2)
#define NUM_MBUFS (8191)
-#define MBUF_CACHE_SIZE (250)
+#define MBUF_CACHE_SIZE (256)
#define MBUF_DATAPAYLOAD_SIZE (2048 + DIGEST_BYTE_LENGTH_SHA512)
#define MBUF_SIZE (sizeof(struct rte_mbuf) + \
RTE_PKTMBUF_HEADROOM + MBUF_DATAPAYLOAD_SIZE)
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index b3f4fd9..52fbbcf 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -58,6 +58,25 @@ struct crypto_testsuite_params {
uint8_t dev_id;
};
+enum chain_mode {
+ CIPHER_HASH,
+ HASH_CIPHER,
+ CIPHER_ONLY,
+ HASH_ONLY
+};
+
+struct perf_test_params {
+
+ unsigned total_operations;
+ unsigned burst_size;
+ unsigned buf_size;
+
+ enum chain_mode chain;
+
+ enum rte_crypto_cipher_algorithm cipher_algo;
+ unsigned cipher_key_length;
+ enum rte_crypto_auth_algorithm auth_algo;
+};
#define MAX_NUM_OF_OPS_PER_UT (128)
@@ -75,6 +94,98 @@ struct crypto_unittest_params {
uint8_t *digest;
};
+static struct rte_cryptodev_sym_session *
+test_perf_create_snow3g_session(uint8_t dev_id, enum chain_mode chain,
+ enum rte_crypto_cipher_algorithm cipher_algo, unsigned
cipher_key_len,
+ enum rte_crypto_auth_algorithm auth_algo);
+static struct rte_mbuf *
+test_perf_create_pktmbuf(struct rte_mempool *mpool, unsigned buf_sz);
+static inline struct rte_crypto_op *
+test_perf_set_crypto_op_snow3g(struct rte_crypto_op *op, struct rte_mbuf *m,
+ struct rte_cryptodev_sym_session *sess, unsigned data_len,
+ unsigned digest_len);
+static uint32_t get_auth_digest_length(enum rte_crypto_auth_algorithm algo);
+
+
+static const char *chain_mode_name(enum chain_mode mode)
+{
+ switch (mode) {
+ case CIPHER_HASH: return "cipher_hash"; break;
+ case HASH_CIPHER: return "hash_cipher"; break;
+ case CIPHER_ONLY: return "cipher_only"; break;
+ case HASH_ONLY: return "hash_only"; break;
+ default: return ""; break;
+ }
+}
+
+static const char *pmd_name(enum rte_cryptodev_type pmd)
+{
+ switch (pmd) {
+ case RTE_CRYPTODEV_NULL_PMD: return CRYPTODEV_NAME_NULL_PMD; break;
+ case RTE_CRYPTODEV_AESNI_GCM_PMD:
+ return CRYPTODEV_NAME_AESNI_GCM_PMD;
+ case RTE_CRYPTODEV_AESNI_MB_PMD:
+ return CRYPTODEV_NAME_AESNI_MB_PMD;
+ case RTE_CRYPTODEV_QAT_SYM_PMD:
+ return CRYPTODEV_NAME_QAT_SYM_PMD;
+ case RTE_CRYPTODEV_SNOW3G_PMD:
+ return CRYPTODEV_NAME_SNOW3G_PMD;
+ default:
+ return "";
+ }
+}
+
+static const char *cipher_algo_name(enum rte_crypto_cipher_algorithm
cipher_algo)
+{
+ switch (cipher_algo) {
+ case RTE_CRYPTO_CIPHER_NULL: return "NULL";
+ case RTE_CRYPTO_CIPHER_3DES_CBC: return "3DES_CBC";
+ case RTE_CRYPTO_CIPHER_3DES_CTR: return "3DES_CTR";
+ case RTE_CRYPTO_CIPHER_3DES_ECB: return "3DES_ECB";
+ case RTE_CRYPTO_CIPHER_AES_CBC: return "AES_CBC";
+ case RTE_CRYPTO_CIPHER_AES_CCM: return "AES_CCM";
+ case RTE_CRYPTO_CIPHER_AES_CTR: return "AES_CTR";
+ case RTE_CRYPTO_CIPHER_AES_ECB: return "AES_ECB";
+ case RTE_CRYPTO_CIPHER_AES_F8: return "AES_F8";
+ case RTE_CRYPTO_CIPHER_AES_GCM: return "AES_GCM";
+ case RTE_CRYPTO_CIPHER_AES_XTS: return "AES_XTS";
+ case RTE_CRYPTO_CIPHER_ARC4: return "ARC4";
+ case RTE_CRYPTO_CIPHER_KASUMI_F8: return "KASUMI_F8";
+ case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: return "SNOW3G_UEA2";
+ case RTE_CRYPTO_CIPHER_ZUC_EEA3: return "ZUC_EEA3";
+ default: return "Another cipher algo";
+ }
+}
+
+static const char *auth_algo_name(enum rte_crypto_auth_algorithm auth_algo)
+{
+ switch (auth_algo) {
+ case RTE_CRYPTO_AUTH_NULL: return "NULL"; break;
+ case RTE_CRYPTO_AUTH_AES_CBC_MAC: return "AES_CBC_MAC"; break;
+ case RTE_CRYPTO_AUTH_
[dpdk-dev] [PATCH v2 2/3] app/test: updating AES SHA performance test
From: Fiona Trahe
Updating the AES performance test in line with snow3g peformance test.
Output format has been updated so as to get better understanding of numbers.
Signed-off-by: Fiona Trahe
Signed-off-by: Jain, Deepak K
---
app/test/test_cryptodev.h | 2 +
app/test/test_cryptodev_perf.c | 553 +++--
2 files changed, 372 insertions(+), 183 deletions(-)
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index d549eca..382802c 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -64,7 +64,9 @@
#define AES_XCBC_MAC_KEY_SZ(16)
#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA1 (12)
+#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA224(16)
#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA256(16)
+#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA384(24)
#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA512(32)
#endif /* TEST_CRYPTODEV_H_ */
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index 52fbbcf..3ea12c9 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -492,12 +492,11 @@ const char plaintext_quote[] =
#define CIPHER_KEY_LENGTH_AES_CBC (16)
#define CIPHER_IV_LENGTH_AES_CBC (CIPHER_KEY_LENGTH_AES_CBC)
-
-static uint8_t aes_cbc_key[] = {
+static uint8_t aes_cbc_128_key[] = {
0xE4, 0x23, 0x33, 0x8A, 0x35, 0x64, 0x61, 0xE2,
0xF1, 0x35, 0x5C, 0x3B, 0xDD, 0x9A, 0x65, 0xBA };
-static uint8_t aes_cbc_iv[] = {
+static uint8_t aes_cbc_128_iv[] = {
0xf5, 0xd3, 0x89, 0x0f, 0x47, 0x00, 0xcb, 0x52,
0x42, 0x1a, 0x7d, 0x3d, 0xf5, 0x82, 0x80, 0xf1 };
@@ -1846,7 +1845,7 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_AES_CBC;
ut_params->cipher_xform.cipher.op = RTE_CRYPTO_CIPHER_OP_DECRYPT;
- ut_params->cipher_xform.cipher.key.data = aes_cbc_key;
+ ut_params->cipher_xform.cipher.key.data = aes_cbc_128_key;
ut_params->cipher_xform.cipher.key.length = CIPHER_IV_LENGTH_AES_CBC;
@@ -1902,7 +1901,7 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
op->sym->cipher.iv.phys_addr = rte_pktmbuf_mtophys(m);
op->sym->cipher.iv.length = CIPHER_IV_LENGTH_AES_CBC;
- rte_memcpy(op->sym->cipher.iv.data, aes_cbc_iv,
+ rte_memcpy(op->sym->cipher.iv.data, aes_cbc_128_iv,
CIPHER_IV_LENGTH_AES_CBC);
op->sym->cipher.data.offset = CIPHER_IV_LENGTH_AES_CBC;
@@ -1985,169 +1984,6 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
}
static int
-test_perf_AES_CBC_HMAC_SHA256_encrypt_digest_vary_req_size(uint16_t dev_num)
-{
- uint16_t index;
- uint32_t burst_sent, burst_received;
- uint32_t b, num_sent, num_received;
- uint64_t failed_polls, retries, start_cycles, end_cycles;
- const uint64_t mhz = rte_get_tsc_hz()/100;
- double throughput, mmps;
-
- struct rte_crypto_op *c_ops[DEFAULT_BURST_SIZE];
- struct rte_crypto_op *proc_ops[DEFAULT_BURST_SIZE];
-
- struct crypto_testsuite_params *ts_params = &testsuite_params;
- struct crypto_unittest_params *ut_params = &unittest_params;
- struct crypto_data_params *data_params = aes_cbc_hmac_sha256_output;
-
- if (rte_cryptodev_count() == 0) {
- printf("\nNo crypto devices available. Is kernel driver
loaded?\n");
- return TEST_FAILED;
- }
-
- /* Setup Cipher Parameters */
- ut_params->cipher_xform.type = RTE_CRYPTO_SYM_XFORM_CIPHER;
- ut_params->cipher_xform.next = &ut_params->auth_xform;
-
- ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_AES_CBC;
- ut_params->cipher_xform.cipher.op = RTE_CRYPTO_CIPHER_OP_ENCRYPT;
- ut_params->cipher_xform.cipher.key.data = aes_cbc_key;
- ut_params->cipher_xform.cipher.key.length = CIPHER_IV_LENGTH_AES_CBC;
-
- /* Setup HMAC Parameters */
- ut_params->auth_xform.type = RTE_CRYPTO_SYM_XFORM_AUTH;
- ut_params->auth_xform.next = NULL;
-
- ut_params->auth_xform.auth.op = RTE_CRYPTO_AUTH_OP_GENERATE;
- ut_params->auth_xform.auth.algo = RTE_CRYPTO_AUTH_SHA256_HMAC;
- ut_params->auth_xform.auth.key.data = hmac_sha256_key;
- ut_params->auth_xform.auth.key.length = HMAC_KEY_LENGTH_SHA256;
- ut_params->auth_xform.auth.digest_length = DIGEST_BYTE_LENGTH_SHA256;
-
- /* Create Crypto session*/
- ut_params->sess = rte_cryptodev_sym_session_create(ts_params->dev_id,
- &ut_params->cipher_xform);
-
- TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
-
- printf("\nThroughput test which will con
[dpdk-dev] [PATCH v2 3/3] app/test: typo fixing
Fixing typo in the performance tests for example preftest to perftest.
Signed-off-by: Jain, Deepak K
---
app/test/test_cryptodev_perf.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index 3ea12c9..a01817c 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -208,7 +208,7 @@ setup_test_string(struct rte_mempool *mpool,
static struct crypto_testsuite_params testsuite_params = { NULL };
static struct crypto_unittest_params unittest_params;
-static enum rte_cryptodev_type gbl_cryptodev_preftest_devtype;
+static enum rte_cryptodev_type gbl_cryptodev_perftest_devtype;
static int
testsuite_setup(void)
@@ -245,7 +245,7 @@ testsuite_setup(void)
}
/* Create 2 AESNI MB devices if required */
- if (gbl_cryptodev_preftest_devtype == RTE_CRYPTODEV_AESNI_MB_PMD) {
+ if (gbl_cryptodev_perftest_devtype == RTE_CRYPTODEV_AESNI_MB_PMD) {
nb_devs =
rte_cryptodev_count_devtype(RTE_CRYPTODEV_AESNI_MB_PMD);
if (nb_devs < 2) {
for (i = nb_devs; i < 2; i++) {
@@ -260,7 +260,7 @@ testsuite_setup(void)
}
/* Create 2 SNOW3G devices if required */
- if (gbl_cryptodev_preftest_devtype == RTE_CRYPTODEV_SNOW3G_PMD) {
+ if (gbl_cryptodev_perftest_devtype == RTE_CRYPTODEV_SNOW3G_PMD) {
nb_devs = rte_cryptodev_count_devtype(RTE_CRYPTODEV_SNOW3G_PMD);
if (nb_devs < 2) {
for (i = nb_devs; i < 2; i++) {
@@ -283,7 +283,7 @@ testsuite_setup(void)
/* Search for the first valid */
for (i = 0; i < nb_devs; i++) {
rte_cryptodev_info_get(i, &info);
- if (info.dev_type == gbl_cryptodev_preftest_devtype) {
+ if (info.dev_type == gbl_cryptodev_perftest_devtype) {
ts_params->dev_id = i;
valid_dev_id = 1;
break;
@@ -1956,7 +1956,7 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
}
while (num_received != num_to_submit) {
- if (gbl_cryptodev_preftest_devtype ==
+ if (gbl_cryptodev_perftest_devtype ==
RTE_CRYPTODEV_AESNI_MB_PMD)
rte_cryptodev_enqueue_burst(dev_num, 0,
NULL, 0);
@@ -2028,7 +2028,7 @@ test_perf_snow3G_optimise_cyclecount(struct
perf_test_params *pparams)
printf("\nOn %s dev%u qp%u, %s, cipher algo:%s, auth_algo:%s, "
"Packet Size %u bytes",
- pmd_name(gbl_cryptodev_preftest_devtype),
+ pmd_name(gbl_cryptodev_perftest_devtype),
ts_params->dev_id, 0,
chain_mode_name(pparams->chain),
cipher_algo_name(pparams->cipher_algo),
@@ -2072,7 +2072,7 @@ test_perf_snow3G_optimise_cyclecount(struct
perf_test_params *pparams)
}
while (num_ops_received != num_to_submit) {
- if (gbl_cryptodev_preftest_devtype ==
+ if (gbl_cryptodev_perftest_devtype ==
RTE_CRYPTODEV_AESNI_MB_PMD)
rte_cryptodev_enqueue_burst(ts_params->dev_id,
0,
NULL, 0);
@@ -2684,7 +2684,7 @@ test_perf_snow3g(uint8_t dev_id, uint16_t queue_id,
double cycles_B = cycles_buff / pparams->buf_size;
double throughput = (ops_s * pparams->buf_size * 8) / 100;
- if (gbl_cryptodev_preftest_devtype == RTE_CRYPTODEV_QAT_SYM_PMD) {
+ if (gbl_cryptodev_perftest_devtype == RTE_CRYPTODEV_QAT_SYM_PMD) {
/* Cycle count misleading on HW devices for this test, so don't
print */
printf("%4u\t%6.2f\t%10.2f\t n/a \t\t n/a "
"\t\t n/a \t\t%8"PRIu64"\t%8"PRIu64,
@@ -2828,7 +2828,7 @@ test_perf_snow3G_vary_pkt_size(void)
for (k = 0; k < RTE_DIM(burst_sizes); k++) {
printf("\nOn %s dev%u qp%u, %s, "
"cipher algo:%s, auth algo:%s, burst_size: %d
ops",
- pmd_name(gbl_cryptodev_preftest_devtype),
+ pmd_name(gbl_cryptodev_perftest_devtype),
testsuite_params.dev_id, 0,
chain_mode_name(params_set[i].chain),
cipher_algo_name(params_set[i].cipher_algo),
@@ -2897,7 +2897,7 @@ static struct unit_test_suite cryptodev_snow3g_testsuite
= {
static int
perftest_aesni_mb_cryptodev(voi
[dpdk-dev] [PATCH v3 0/3] Extending cryptodev Performance tests
Performance tests haven been extended in this patchset. Patchset consists of 3 patches: Patch 1 add snow3g performance tests. Patch 2 updates the existing aes performanc test Patch 3 fixes the typo in names of perftest Changes in v3: -Minor refactoring Changes in v2: -Removed the addtion of rte_crypto_op_bulk_free Fiona Trahe (2): app/test: adding Snow3g performance test app/test: updating AES SHA performance test Jain, Deepak K (1): app/test: typo fixing app/test/test_cryptodev.h |4 +- app/test/test_cryptodev_perf.c | 1153 +++- 2 files changed, 1015 insertions(+), 142 deletions(-) -- 2.5.5
[dpdk-dev] [PATCH v3 3/3] app/test: typo fixing
Fixing typo in the performance tests for example preftest to perftest.
Signed-off-by: Jain, Deepak K
---
app/test/test_cryptodev_perf.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index e3778a9..34daecb 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -208,7 +208,7 @@ setup_test_string(struct rte_mempool *mpool,
static struct crypto_testsuite_params testsuite_params = { NULL };
static struct crypto_unittest_params unittest_params;
-static enum rte_cryptodev_type gbl_cryptodev_preftest_devtype;
+static enum rte_cryptodev_type gbl_cryptodev_perftest_devtype;
static int
testsuite_setup(void)
@@ -245,7 +245,7 @@ testsuite_setup(void)
}
/* Create 2 AESNI MB devices if required */
- if (gbl_cryptodev_preftest_devtype == RTE_CRYPTODEV_AESNI_MB_PMD) {
+ if (gbl_cryptodev_perftest_devtype == RTE_CRYPTODEV_AESNI_MB_PMD) {
nb_devs =
rte_cryptodev_count_devtype(RTE_CRYPTODEV_AESNI_MB_PMD);
if (nb_devs < 2) {
for (i = nb_devs; i < 2; i++) {
@@ -260,7 +260,7 @@ testsuite_setup(void)
}
/* Create 2 SNOW3G devices if required */
- if (gbl_cryptodev_preftest_devtype == RTE_CRYPTODEV_SNOW3G_PMD) {
+ if (gbl_cryptodev_perftest_devtype == RTE_CRYPTODEV_SNOW3G_PMD) {
nb_devs = rte_cryptodev_count_devtype(RTE_CRYPTODEV_SNOW3G_PMD);
if (nb_devs < 2) {
for (i = nb_devs; i < 2; i++) {
@@ -283,7 +283,7 @@ testsuite_setup(void)
/* Search for the first valid */
for (i = 0; i < nb_devs; i++) {
rte_cryptodev_info_get(i, &info);
- if (info.dev_type == gbl_cryptodev_preftest_devtype) {
+ if (info.dev_type == gbl_cryptodev_perftest_devtype) {
ts_params->dev_id = i;
valid_dev_id = 1;
break;
@@ -1956,7 +1956,7 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
}
while (num_received != num_to_submit) {
- if (gbl_cryptodev_preftest_devtype ==
+ if (gbl_cryptodev_perftest_devtype ==
RTE_CRYPTODEV_AESNI_MB_PMD)
rte_cryptodev_enqueue_burst(dev_num, 0,
NULL, 0);
@@ -2028,7 +2028,7 @@ test_perf_snow3G_optimise_cyclecount(struct
perf_test_params *pparams)
printf("\nOn %s dev%u qp%u, %s, cipher algo:%s, auth_algo:%s, "
"Packet Size %u bytes",
- pmd_name(gbl_cryptodev_preftest_devtype),
+ pmd_name(gbl_cryptodev_perftest_devtype),
ts_params->dev_id, 0,
chain_mode_name(pparams->chain),
cipher_algo_name(pparams->cipher_algo),
@@ -2072,7 +2072,7 @@ test_perf_snow3G_optimise_cyclecount(struct
perf_test_params *pparams)
}
while (num_ops_received != num_to_submit) {
- if (gbl_cryptodev_preftest_devtype ==
+ if (gbl_cryptodev_perftest_devtype ==
RTE_CRYPTODEV_AESNI_MB_PMD)
rte_cryptodev_enqueue_burst(ts_params->dev_id,
0,
NULL, 0);
@@ -2680,7 +2680,7 @@ test_perf_snow3g(uint8_t dev_id, uint16_t queue_id,
double cycles_B = cycles_buff / pparams->buf_size;
double throughput = (ops_s * pparams->buf_size * 8) / 100;
- if (gbl_cryptodev_preftest_devtype == RTE_CRYPTODEV_QAT_SYM_PMD) {
+ if (gbl_cryptodev_perftest_devtype == RTE_CRYPTODEV_QAT_SYM_PMD) {
/* Cycle count misleading on HW devices for this test, so don't
print */
printf("%4u\t%6.2f\t%10.2f\t n/a \t\t n/a "
"\t\t n/a \t\t%8"PRIu64"\t%8"PRIu64,
@@ -2824,7 +2824,7 @@ test_perf_snow3G_vary_pkt_size(void)
for (k = 0; k < RTE_DIM(burst_sizes); k++) {
printf("\nOn %s dev%u qp%u, %s, "
"cipher algo:%s, auth algo:%s, burst_size: %d
ops",
- pmd_name(gbl_cryptodev_preftest_devtype),
+ pmd_name(gbl_cryptodev_perftest_devtype),
testsuite_params.dev_id, 0,
chain_mode_name(params_set[i].chain),
cipher_algo_name(params_set[i].cipher_algo),
@@ -2893,7 +2893,7 @@ static struct unit_test_suite cryptodev_snow3g_testsuite
= {
static int
perftest_aesni_mb_cryptodev(voi
[dpdk-dev] [PATCH v3 1/3] app/test: adding Snow3g performance test
From: Fiona Trahe
Adding performance test for snow3g wireless algorithm.
Performance test can run over both software and hardware.
Signed-off-by: Fiona Trahe
Signed-off-by: Jain, Deepak K
Signed-off-by: Declan Doherty
---
app/test/test_cryptodev.h | 2 +-
app/test/test_cryptodev_perf.c | 688 -
2 files changed, 688 insertions(+), 2 deletions(-)
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index 6059a01..d549eca 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -46,7 +46,7 @@
#define DEFAULT_BURST_SIZE (64)
#define DEFAULT_NUM_XFORMS (2)
#define NUM_MBUFS (8191)
-#define MBUF_CACHE_SIZE (250)
+#define MBUF_CACHE_SIZE (256)
#define MBUF_DATAPAYLOAD_SIZE (2048 + DIGEST_BYTE_LENGTH_SHA512)
#define MBUF_SIZE (sizeof(struct rte_mbuf) + \
RTE_PKTMBUF_HEADROOM + MBUF_DATAPAYLOAD_SIZE)
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index b3f4fd9..52a2a72 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -58,6 +58,25 @@ struct crypto_testsuite_params {
uint8_t dev_id;
};
+enum chain_mode {
+ CIPHER_HASH,
+ HASH_CIPHER,
+ CIPHER_ONLY,
+ HASH_ONLY
+};
+
+struct perf_test_params {
+
+ unsigned total_operations;
+ unsigned burst_size;
+ unsigned buf_size;
+
+ enum chain_mode chain;
+
+ enum rte_crypto_cipher_algorithm cipher_algo;
+ unsigned cipher_key_length;
+ enum rte_crypto_auth_algorithm auth_algo;
+};
#define MAX_NUM_OF_OPS_PER_UT (128)
@@ -75,6 +94,98 @@ struct crypto_unittest_params {
uint8_t *digest;
};
+static struct rte_cryptodev_sym_session *
+test_perf_create_snow3g_session(uint8_t dev_id, enum chain_mode chain,
+ enum rte_crypto_cipher_algorithm cipher_algo, unsigned
cipher_key_len,
+ enum rte_crypto_auth_algorithm auth_algo);
+static struct rte_mbuf *
+test_perf_create_pktmbuf(struct rte_mempool *mpool, unsigned buf_sz);
+static inline struct rte_crypto_op *
+test_perf_set_crypto_op_snow3g(struct rte_crypto_op *op, struct rte_mbuf *m,
+ struct rte_cryptodev_sym_session *sess, unsigned data_len,
+ unsigned digest_len);
+static uint32_t get_auth_digest_length(enum rte_crypto_auth_algorithm algo);
+
+
+static const char *chain_mode_name(enum chain_mode mode)
+{
+ switch (mode) {
+ case CIPHER_HASH: return "cipher_hash"; break;
+ case HASH_CIPHER: return "hash_cipher"; break;
+ case CIPHER_ONLY: return "cipher_only"; break;
+ case HASH_ONLY: return "hash_only"; break;
+ default: return ""; break;
+ }
+}
+
+static const char *pmd_name(enum rte_cryptodev_type pmd)
+{
+ switch (pmd) {
+ case RTE_CRYPTODEV_NULL_PMD: return CRYPTODEV_NAME_NULL_PMD; break;
+ case RTE_CRYPTODEV_AESNI_GCM_PMD:
+ return CRYPTODEV_NAME_AESNI_GCM_PMD;
+ case RTE_CRYPTODEV_AESNI_MB_PMD:
+ return CRYPTODEV_NAME_AESNI_MB_PMD;
+ case RTE_CRYPTODEV_QAT_SYM_PMD:
+ return CRYPTODEV_NAME_QAT_SYM_PMD;
+ case RTE_CRYPTODEV_SNOW3G_PMD:
+ return CRYPTODEV_NAME_SNOW3G_PMD;
+ default:
+ return "";
+ }
+}
+
+static const char *cipher_algo_name(enum rte_crypto_cipher_algorithm
cipher_algo)
+{
+ switch (cipher_algo) {
+ case RTE_CRYPTO_CIPHER_NULL: return "NULL";
+ case RTE_CRYPTO_CIPHER_3DES_CBC: return "3DES_CBC";
+ case RTE_CRYPTO_CIPHER_3DES_CTR: return "3DES_CTR";
+ case RTE_CRYPTO_CIPHER_3DES_ECB: return "3DES_ECB";
+ case RTE_CRYPTO_CIPHER_AES_CBC: return "AES_CBC";
+ case RTE_CRYPTO_CIPHER_AES_CCM: return "AES_CCM";
+ case RTE_CRYPTO_CIPHER_AES_CTR: return "AES_CTR";
+ case RTE_CRYPTO_CIPHER_AES_ECB: return "AES_ECB";
+ case RTE_CRYPTO_CIPHER_AES_F8: return "AES_F8";
+ case RTE_CRYPTO_CIPHER_AES_GCM: return "AES_GCM";
+ case RTE_CRYPTO_CIPHER_AES_XTS: return "AES_XTS";
+ case RTE_CRYPTO_CIPHER_ARC4: return "ARC4";
+ case RTE_CRYPTO_CIPHER_KASUMI_F8: return "KASUMI_F8";
+ case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: return "SNOW3G_UEA2";
+ case RTE_CRYPTO_CIPHER_ZUC_EEA3: return "ZUC_EEA3";
+ default: return "Another cipher algo";
+ }
+}
+
+static const char *auth_algo_name(enum rte_crypto_auth_algorithm auth_algo)
+{
+ switch (auth_algo) {
+ case RTE_CRYPTO_AUTH_NULL: return "NULL"; break;
+ case RTE_CRYPTO_AUTH_AES_CBC_MAC: return "AES_CBC_MAC"; break;
+ case RTE_CRYPTO_AUTH_
[dpdk-dev] [PATCH v3 2/3] app/test: updating AES SHA performance test
From: Fiona Trahe
Updating the AES performance test in line with snow3g peformance test.
Output format has been updated so as to get better understanding of numbers.
Signed-off-by: Fiona Trahe
Signed-off-by: Jain, Deepak K
---
app/test/test_cryptodev.h | 2 +
app/test/test_cryptodev_perf.c | 551 +++--
2 files changed, 370 insertions(+), 183 deletions(-)
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index d549eca..382802c 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -64,7 +64,9 @@
#define AES_XCBC_MAC_KEY_SZ(16)
#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA1 (12)
+#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA224(16)
#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA256(16)
+#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA384(24)
#define TRUNCATED_DIGEST_BYTE_LENGTH_SHA512(32)
#endif /* TEST_CRYPTODEV_H_ */
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index 52a2a72..e3778a9 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -492,12 +492,11 @@ const char plaintext_quote[] =
#define CIPHER_KEY_LENGTH_AES_CBC (16)
#define CIPHER_IV_LENGTH_AES_CBC (CIPHER_KEY_LENGTH_AES_CBC)
-
-static uint8_t aes_cbc_key[] = {
+static uint8_t aes_cbc_128_key[] = {
0xE4, 0x23, 0x33, 0x8A, 0x35, 0x64, 0x61, 0xE2,
0xF1, 0x35, 0x5C, 0x3B, 0xDD, 0x9A, 0x65, 0xBA };
-static uint8_t aes_cbc_iv[] = {
+static uint8_t aes_cbc_128_iv[] = {
0xf5, 0xd3, 0x89, 0x0f, 0x47, 0x00, 0xcb, 0x52,
0x42, 0x1a, 0x7d, 0x3d, 0xf5, 0x82, 0x80, 0xf1 };
@@ -1846,7 +1845,7 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_AES_CBC;
ut_params->cipher_xform.cipher.op = RTE_CRYPTO_CIPHER_OP_DECRYPT;
- ut_params->cipher_xform.cipher.key.data = aes_cbc_key;
+ ut_params->cipher_xform.cipher.key.data = aes_cbc_128_key;
ut_params->cipher_xform.cipher.key.length = CIPHER_IV_LENGTH_AES_CBC;
@@ -1902,7 +1901,7 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
op->sym->cipher.iv.phys_addr = rte_pktmbuf_mtophys(m);
op->sym->cipher.iv.length = CIPHER_IV_LENGTH_AES_CBC;
- rte_memcpy(op->sym->cipher.iv.data, aes_cbc_iv,
+ rte_memcpy(op->sym->cipher.iv.data, aes_cbc_128_iv,
CIPHER_IV_LENGTH_AES_CBC);
op->sym->cipher.data.offset = CIPHER_IV_LENGTH_AES_CBC;
@@ -1985,169 +1984,6 @@ test_perf_crypto_qp_vary_burst_size(uint16_t dev_num)
}
static int
-test_perf_AES_CBC_HMAC_SHA256_encrypt_digest_vary_req_size(uint16_t dev_num)
-{
- uint16_t index;
- uint32_t burst_sent, burst_received;
- uint32_t b, num_sent, num_received;
- uint64_t failed_polls, retries, start_cycles, end_cycles;
- const uint64_t mhz = rte_get_tsc_hz()/100;
- double throughput, mmps;
-
- struct rte_crypto_op *c_ops[DEFAULT_BURST_SIZE];
- struct rte_crypto_op *proc_ops[DEFAULT_BURST_SIZE];
-
- struct crypto_testsuite_params *ts_params = &testsuite_params;
- struct crypto_unittest_params *ut_params = &unittest_params;
- struct crypto_data_params *data_params = aes_cbc_hmac_sha256_output;
-
- if (rte_cryptodev_count() == 0) {
- printf("\nNo crypto devices available. Is kernel driver
loaded?\n");
- return TEST_FAILED;
- }
-
- /* Setup Cipher Parameters */
- ut_params->cipher_xform.type = RTE_CRYPTO_SYM_XFORM_CIPHER;
- ut_params->cipher_xform.next = &ut_params->auth_xform;
-
- ut_params->cipher_xform.cipher.algo = RTE_CRYPTO_CIPHER_AES_CBC;
- ut_params->cipher_xform.cipher.op = RTE_CRYPTO_CIPHER_OP_ENCRYPT;
- ut_params->cipher_xform.cipher.key.data = aes_cbc_key;
- ut_params->cipher_xform.cipher.key.length = CIPHER_IV_LENGTH_AES_CBC;
-
- /* Setup HMAC Parameters */
- ut_params->auth_xform.type = RTE_CRYPTO_SYM_XFORM_AUTH;
- ut_params->auth_xform.next = NULL;
-
- ut_params->auth_xform.auth.op = RTE_CRYPTO_AUTH_OP_GENERATE;
- ut_params->auth_xform.auth.algo = RTE_CRYPTO_AUTH_SHA256_HMAC;
- ut_params->auth_xform.auth.key.data = hmac_sha256_key;
- ut_params->auth_xform.auth.key.length = HMAC_KEY_LENGTH_SHA256;
- ut_params->auth_xform.auth.digest_length = DIGEST_BYTE_LENGTH_SHA256;
-
- /* Create Crypto session*/
- ut_params->sess = rte_cryptodev_sym_session_create(ts_params->dev_id,
- &ut_params->cipher_xform);
-
- TEST_ASSERT_NOT_NULL(ut_params->sess, "Session creation failed");
-
- printf("\nThroughput test which will con
[dpdk-dev] [PATCH v2] qat: fix for VFs not getting recognized
Updated the code to use RTE_PCI_DEVICE.
Fixes: 701c8d80c820 ("pci: support class id probing")
Signed-off-by: Jain, Deepak K
---
drivers/crypto/qat/rte_qat_cryptodev.c | 10 +++---
lib/librte_eal/common/include/rte_pci_dev_ids.h | 10 ++
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/qat/rte_qat_cryptodev.c
b/drivers/crypto/qat/rte_qat_cryptodev.c
index a7912f5..31d3c0c 100644
--- a/drivers/crypto/qat/rte_qat_cryptodev.c
+++ b/drivers/crypto/qat/rte_qat_cryptodev.c
@@ -68,13 +68,9 @@ static struct rte_cryptodev_ops crypto_qat_ops = {
*/
static struct rte_pci_id pci_id_qat_map[] = {
- {
- .vendor_id = 0x8086,
- .device_id = 0x0443,
- .subsystem_vendor_id = PCI_ANY_ID,
- .subsystem_device_id = PCI_ANY_ID
- },
- {.device_id = 0},
+#define RTE_PCI_DEV_ID_DECL_QATVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
+#include "rte_pci_dev_ids.h"
+{.device_id = 0},
};
static int
diff --git a/lib/librte_eal/common/include/rte_pci_dev_ids.h
b/lib/librte_eal/common/include/rte_pci_dev_ids.h
index cf7b548..a4fc430 100644
--- a/lib/librte_eal/common/include/rte_pci_dev_ids.h
+++ b/lib/librte_eal/common/include/rte_pci_dev_ids.h
@@ -152,6 +152,10 @@
#define RTE_PCI_DEV_ID_DECL_BNX2XVF(vend, dev)
#endif
+#ifndef RTE_PCI_DEV_ID_DECL_QATVF
+#define RTE_PCI_DEV_ID_DECL_QATVF(vend, dev)
+#endif
+
#ifndef PCI_VENDOR_ID_INTEL
/** Vendor ID used by Intel devices */
#define PCI_VENDOR_ID_INTEL 0x8086
@@ -615,6 +619,12 @@ RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL,
I40E_DEV_ID_X722_A0_VF)
RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_X722_VF)
RTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_X722_VF_HV)
+/** Intel QuickAssist(QAT) Device **/
+
+#define QAT_DEV_ID_895XCC_VF0x0443
+
+RTE_PCI_DEV_ID_DECL_QATVF(PCI_VENDOR_ID_INTEL, QAT_DEV_ID_895XCC_VF)
+
/** Virtio devices from virtio.h **/
#define QUMRANET_DEV_ID_VIRTIO 0x1000
--
2.5.5
[dpdk-dev] [PATCH] app/test: avoid freeing mbufs twice in qat test
> -Original Message-
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara
> Sent: Monday, June 27, 2016 1:41 PM
> To: dev at dpdk.org
> Cc: De Lara Guarch, Pablo
> Subject: [dpdk-dev] [PATCH] app/test: avoid freeing mbufs twice in qat test
>
> Test_multi_session was freeing mbufs used in the multiple sessions created
> and setting obuf to NULL after it, but ibuf was not being set to NULL, and
> therefore, it was being freed again (ibuf and obuf are pointing at the same
> address), in the ut_teardown() function.
>
> Fixes: 1b9cb73ecef1 ("app/test: fix qat autotest failure")
>
> Signed-off-by: Pablo de Lara
> ---
> app/test/test_cryptodev.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> --
> 2.5.0
Acked-by: Deepak K Jain
[dpdk-dev] [Crypto-API]
HI Amartya, Please see answers below. > -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of > amartya.das at wipro.com > Sent: Tuesday, June 28, 2016 6:26 AM > To: dev at dpdk.org > Subject: [dpdk-dev] [Crypto-API] > > Hi, > > Is it possible to use Crypto API with virtual device without VFIO and by using > UIO only. > YES it is possible to use crypto API with virtual device using UIO. Please send this kind of questions to users at dpdk.org next time. Regarding error which are getting: There is no driver for the PMD, have you enabled it in the config? it is disabled by default. You can read more info: http://dpdk.readthedocs.io/en/v16.04/cryptodevs/index.html In Future, please remove the disclaimer when sending public emails. > Thanks, > Amartya > The information contained in this electronic message and any attachments to > this message are intended for the exclusive use of the addressee(s) and may > contain proprietary, confidential or privileged information. If you are not > the > intended recipient, you should not disseminate, distribute or copy this e- > mail. Please notify the sender immediately and destroy all copies of this > message and any attachments. WARNING: Computer viruses can be > transmitted via email. The recipient should check this email and any > attachments for the presence of viruses. The company accepts no liability for > any damage caused by any virus transmitted by this email. www.wipro.com
[dpdk-dev] [PATCH v7 0/2] cryptodev API changes
-Original Message- From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Fiona Trahe Sent: Monday, March 7, 2016 11:50 AM To: dev at dpdk.org Subject: [dpdk-dev] [PATCH v7 0/2] cryptodev API changes This patch set separates the symmetric crypto operations from generic operations and then modifies the cryptodev burst API to accept bursts of rte_crypto_op rather than rte_mbufs. v7: - remove trailing spaces introduced in v6 - rebase against recent config file changes v6: - restore EXPERIMENTAL label to cryptodev. Will handle removal in separate thread. (email subject was incorrect in v5, so v5 hasn't arrived in patchwork, therefore v6 is in-reply-to v4 message id) V5: - updates .map file - removes EXPERIMENTAL label from rte_cryptodev.h V4: - Fixes for issues introduced in __rte_crypto_op_raw_bulk_alloc in V3 patcheset. - Typo fix in cached attribute on rte_crypto_op structure. V3: - Addresses V2 comments - Rebased for head Declan Doherty (1): cryptodev: change burst API to be crypto op oriented Fiona Trahe (2): cryptodev: API tidy and changes to support future extensions cryptodev: change burst API to be crypto op oriented MAINTAINERS| 4 - app/test/test_cryptodev.c | 894 +++-- app/test/test_cryptodev.h | 9 +- app/test/test_cryptodev_perf.c | 270 --- config/common_base | 7 - doc/api/doxy-api-index.md | 1 - drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 199 ++--- drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c | 18 +- drivers/crypto/aesni_mb/rte_aesni_mb_pmd_private.h | 6 +- drivers/crypto/qat/qat_crypto.c| 150 ++-- drivers/crypto/qat/qat_crypto.h| 14 +- drivers/crypto/qat/rte_qat_cryptodev.c | 8 +- examples/l2fwd-crypto/main.c | 300 --- lib/Makefile | 1 - lib/librte_cryptodev/Makefile | 1 + lib/librte_cryptodev/rte_crypto.h | 819 +++ lib/librte_cryptodev/rte_crypto_sym.h | 642 +++ lib/librte_cryptodev/rte_cryptodev.c | 115 ++- lib/librte_cryptodev/rte_cryptodev.h | 189 ++--- lib/librte_cryptodev/rte_cryptodev_pmd.h | 32 +- lib/librte_cryptodev/rte_cryptodev_version.map | 7 +- lib/librte_mbuf/rte_mbuf.h | 6 - lib/librte_mbuf_offload/Makefile | 52 -- lib/librte_mbuf_offload/rte_mbuf_offload.c | 100 --- lib/librte_mbuf_offload/rte_mbuf_offload.h | 310 --- .../rte_mbuf_offload_version.map | 7 - 26 files changed, 2145 insertions(+), 2016 deletions(-) create mode 100644 lib/librte_cryptodev/rte_crypto_sym.h delete mode 100644 lib/librte_mbuf_offload/Makefile delete mode 100644 lib/librte_mbuf_offload/rte_mbuf_offload.c delete mode 100644 lib/librte_mbuf_offload/rte_mbuf_offload.h delete mode 100644 lib/librte_mbuf_offload/rte_mbuf_offload_version.map -- 2.1.0 Series-acked-by: Deepak Kumar JAIN
[dpdk-dev] [PATCH v3] pmd/snow3g: add new SNOW 3G SW PMD
-Original Message-
From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Pablo de Lara
Sent: Monday, March 7, 2016 7:48 PM
To: dev at dpdk.org
Subject: [dpdk-dev] [PATCH v3] pmd/snow3g: add new SNOW 3G SW PMD
Added new SW PMD which makes use of the libsso SW library, which provides
wireless algorithms SNOW 3G UEA2 and UIA2 in software.
This PMD supports cipher-only, hash-only and chained operations ("cipher then
hash" and "hash then cipher") of the following
algorithms:
- RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2
- RTE_CRYPTO_SYM_HASH_SNOW3G_UIA2
The SNOW 3G hash and cipher algorithms, which are enabled by this crypto PMD
are implemented by Intel's libsso software library. For library download and
build instructions, see the documentation included
(doc/guides/cryptodevs/snow3g.rst)
The patch also contains the related unit tests function to test the PMD
supported operations.
Signed-off-by: Pablo de Lara
---
This patch depends on "Snow3G support for Intel Quick Assist Devices" patchset
(http://dpdk.org/ml/archives/dev/2016-March/034503.html).
Changes in v3:
- Corrected patch dependency
Changes in v2:
- Rebased against crypto API changes
- Removed static config options and allow user to provide them
as virtual device parameters.
- Added unit tests
- Changed DPDK version references from 2.3 to 16.04
- Fixed crypto operation status handling
- Fixed copyright dates
- Fixed enqueue error stats
MAINTAINERS | 4 +
app/test/test_cryptodev.c| 78
config/common_base | 6 +
doc/guides/cryptodevs/index.rst | 1 +
doc/guides/cryptodevs/snow3g.rst | 69 +++
doc/guides/rel_notes/release_16_04.rst | 4 +
drivers/crypto/Makefile | 3 +-
drivers/crypto/snow3g/Makefile | 64 +++
drivers/crypto/snow3g/rte_pmd_snow3g_version.map | 3 +
drivers/crypto/snow3g/rte_snow3g_pmd.c | 531 +++
drivers/crypto/snow3g/rte_snow3g_pmd_ops.c | 291 +
drivers/crypto/snow3g/rte_snow3g_pmd_private.h | 107 +
lib/librte_cryptodev/Makefile| 3 +-
lib/librte_cryptodev/rte_cryptodev.h | 120 -
mk/rte.app.mk| 6 +-
15 files changed, 1286 insertions(+), 4 deletions(-) create mode 100644
doc/guides/cryptodevs/snow3g.rst create mode 100644
drivers/crypto/snow3g/Makefile create mode 100644
drivers/crypto/snow3g/rte_pmd_snow3g_version.map
create mode 100644 drivers/crypto/snow3g/rte_snow3g_pmd.c
create mode 100644 drivers/crypto/snow3g/rte_snow3g_pmd_ops.c
create mode 100644 drivers/crypto/snow3g/rte_snow3g_pmd_private.h
--
2.5.0
Acked-by: Deepak Kumar JAIN
[dpdk-dev] [PATCH v2] qat: fix phys address of content descriptor
> -Original Message-
> From: Kusztal, ArkadiuszX
> Sent: Wednesday, June 1, 2016 11:52 AM
> To: dev at dpdk.org
> Cc: Trahe, Fiona ; Griffin, John
> ; Jain, Deepak K ;
> olivier.matz at 6wind.com; thomas.monjalon at 6wind.com; Kusztal, ArkadiuszX
>
> Subject: [PATCH v2] qat: fix phys address of content descriptor
>
> From: Arkadiusz Kusztal
>
> Fix an error with computation of physical address of content descriptor in the
> symmetric operations session
>
> Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")
>
> Signed-off-by: Arkadiusz Kusztal
> ---
> v2: Added fixes line to commit message
Acked-by: Deepak Kumar JAIN
[dpdk-dev] [PATCH v2] aesni_mb: fix control issues in aesni pmd
Fix wrong indentation for return value
Coverity ID: 126585
Fixes: 924e84f87306 ("aesni_mb: add driver for multi buffer based crypto")
Signed-off-by: Deepak Kumar Jain
---
v2: Corrected PMD in commit message
drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
index 3415ac1..9c42f88 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
@@ -560,7 +560,7 @@ aesni_mb_pmd_enqueue_burst(void *queue_pair, struct
rte_crypto_op **ops,
goto flush_jobs;
else
qp->stats.enqueued_count += processed_jobs;
- return i;
+ return i;
flush_jobs:
/*
--
2.5.5
[dpdk-dev] [PATCH v2] aesni_mb: fix null pointer dereferencing
Fix null pointer dereferencing by reporing if null and
exiting the function.
Coverity issue: 126584
Fixes: c0f87eb5252b ("cryptodev: change burst API to be crypto op oriented")
Signed-off-by: Deepak Kumar Jain
---
v2: Corrected PMD name in commit message
drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
index 9c42f88..31784e1 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
@@ -379,9 +379,11 @@ process_crypto_op(struct aesni_mb_qp *qp, struct
rte_crypto_op *op,
/* append space for output data to mbuf */
char *odata = rte_pktmbuf_append(m_dst,
rte_pktmbuf_data_len(op->sym->m_src));
- if (odata == NULL)
+ if (odata == NULL) {
MB_LOG_ERR("failed to allocate space in destination "
"mbuf for source data");
+ return NULL;
+ }
memcpy(odata, rte_pktmbuf_mtod(op->sym->m_src, void*),
rte_pktmbuf_data_len(op->sym->m_src));
--
2.5.5
[dpdk-dev] [PATCH 0/2] Change optimization flag for Intel QuickAssist Technology driver Makefile
> -Original Message- > From: Kusztal, ArkadiuszX > Sent: Tuesday, June 7, 2016 5:58 PM > To: dev at dpdk.org > Cc: Trahe, Fiona ; Griffin, John > ; Jain, Deepak K ; > Kusztal, ArkadiuszX > Subject: [PATCH 0/2] Change optimization flag for Intel QuickAssist > Technology driver Makefile > > This patch changes to -O3 optimization flag in Intel QuickAssist Technology > driver Makefile > > Arek Kusztal (2): > qat: add aad_len variable to avoid GCC break strict-aliasing rules > warning > qat: change optimization flag for Intel QuickAssist Technology > Makefile > > drivers/crypto/qat/Makefile | 1 + > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 8 +--- > 2 files changed, 6 insertions(+), 3 deletions(-) > > -- > 2.1.0 Series-Acked-by: Deepak Kumar JAIN
[dpdk-dev] [PATCH] doc: fix wrong supported feature table
> -Original Message-
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara
> Sent: Thursday, June 9, 2016 4:45 PM
> To: dev at dpdk.org
> Cc: Mcnamara, John ; Doherty, Declan
> ; De Lara Guarch, Pablo
>
> Subject: [dpdk-dev] [PATCH] doc: fix wrong supported feature table
>
> Some crypto PMDs that support symmetric crypto were not marked as
> supported in the supported feature flags table.
>
> Fixes: 2373c0661b2f0 ("doc: add cryptodevs guide overview")
>
> Signed-off-by: Pablo de Lara
> ---
> doc/guides/cryptodevs/overview.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> --
> 2.5.0
Acked-by: Deepak Kumar JAIN
[dpdk-dev] [PATCH v2] null_crypto_pmd: PMD to support null crypto operations
-Original Message- From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Pablo de Lara Sent: Thursday, March 10, 2016 4:47 PM To: dev at dpdk.org Subject: [dpdk-dev] [PATCH v2] null_crypto_pmd: PMD to support null crypto operations From: Declan Doherty This patch provides the implementation of a NULL crypto PMD, which supports NULL cipher and NULL authentication operations, which can be chained together as follows: - Authentication Only - Cipher Only - Authentication then Cipher - Cipher then Authentication As this is a NULL operation device the crypto operations which are submitted for processing are not actually modified and are stored in a queue pairs processed packets ring ready for collection when rte_cryptodev_burst_dequeue() is called. The patch also contains the related unit tests function to test the PMDs supported operations. Signed-off-by: Declan Doherty --- This patch depends on "AES GCM, AES CMAC fixes and addition of GCM tests for QAT" patchset (http://dpdk.org/ml/archives/dev/2016-March/034974.html) Changes in v2: - Rebased to include Cryptodev API changes -- 2.5.0 Acked-by: Deepak Kumar JAIN
[dpdk-dev] [PATCH v4] pmd/snow3g: add new SNOW 3G SW PMD
-Original Message-
From: De Lara Guarch, Pablo
Sent: Thursday, March 10, 2016 4:33 PM
To: dev at dpdk.org
Cc: Doherty, Declan ; Jain, Deepak K
; De Lara Guarch, Pablo
Subject: [PATCH v4] pmd/snow3g: add new SNOW 3G SW PMD
Added new SW PMD which makes use of the libsso SW library, which provides
wireless algorithms SNOW 3G UEA2 and UIA2 in software.
This PMD supports cipher-only, hash-only and chained operations ("cipher then
hash" and "hash then cipher") of the following
algorithms:
- RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2
- RTE_CRYPTO_SYM_AUTH_SNOW3G_UIA2
The SNOW 3G hash and cipher algorithms, which are enabled by this crypto PMD
are implemented by Intel's libsso software library. For library download and
build instructions, see the documentation included
(doc/guides/cryptodevs/snow3g.rst)
The patch also contains the related unit tests function to test the PMD
supported operations.
Signed-off-by: Pablo de Lara
---
This patch depends on "Snow3G support for Intel Quick Assist Devices" patchset
(http://dpdk.org/ml/archives/dev/2016-March/03548.html).
Changes in v4:
- Added missing fix casting that was breaking C++ compilation.
- Fixed documentation
- Rebased against latest DPDK code
Changes in v3:
- Corrected patch dependency
Changes in v2:
- Rebased against crypto API changes
- Removed static config options and allow user to provide them
as virtual device parameters.
- Added unit tests
- Changed DPDK version references from 2.3 to 16.04
- Fixed crypto operation status handling
- Fixed copyright dates
- Fixed enqueue error stats
--
2.5.0
Acked-by: Deepak Kumar JAIN
[dpdk-dev] [PATCH 1/2] driver/crypto: out-of-place symmetric operations
Hi, "Out-of-place" operation means the result of the operation will be written to the destination buffer instead of overwriting the source buffer as done in "in-place" operation. -Original Message- From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Thomas Monjalon Sent: Tuesday, March 29, 2016 1:02 PM To: Trahe, Fiona ; Kusztal, ArkadiuszX Cc: dev at dpdk.org; Doherty, Declan Subject: Re: [dpdk-dev] [PATCH 1/2] driver/crypto: out-of-place symmetric operations 2016-03-29 10:39, Fiona Trahe: > From: Arek Kusztal > > Driver now support out of place crypto operations, driver assumes both > buffers can be of different size. Please, could you explain what exactly means "out of place" operations?
[dpdk-dev] [PATCH v2] tools: add crypto device details
> -Original Message- > From: Breen, Eoin > Sent: Thursday, August 25, 2016 2:52 PM > To: Jain, Deepak K ; Trahe, Fiona > ; Griffin, John > Cc: dev at dpdk.org; Breen, Eoin > Subject: [PATCH v2] tools: add crypto device details > > Adding the support to bind/unbind crypto devices with dpdk-devbind.py > script, as now it is not restricted to network devices anymore. > > Signed-off-by: Eoin Breen > --- > Changes since v1: > * Resolved coding issues > > tools/dpdk-devbind.py | 107 > ++ > 1 file changed, 99 insertions(+), 8 deletions(-) > -- > 2.5.5 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH 0/3] Fix compability issues between crypto drivers for GCM test cases
> -Original Message- > From: Kusztal, ArkadiuszX > Sent: Thursday, August 25, 2016 1:03 PM > To: dev at dpdk.org > Cc: Trahe, Fiona ; Jain, Deepak K > ; De Lara Guarch, Pablo > ; Griffin, John intel.com>; > Kusztal, ArkadiuszX > Subject: [PATCH 0/3] Fix compability issues between crypto drivers for GCM > test cases > > This patchset fix pre-counter block issues between crypto divers for AES- > GCM tests. > Pre-counter block 96b computation from test file is moved into the AES-GCM > PMD. > This patch set fixes too problems with verification of digest for AES-GCM. > > Arek Kusztal (3): > crypto/aesni_gcm: move pre-counter block to GCM driver > app/test: move pre-counter block computation from test files > app/test: fix verification of digest in GCM crypto test > > app/test/test_cryptodev.c| 20 > drivers/crypto/aesni_gcm/aesni_gcm_pmd.c | 7 ++- > 2 files changed, 14 insertions(+), 13 deletions(-) > > -- > 2.1.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH 0/3] add GMAC capability Intel QAT driver
> -Original Message- > From: Kusztal, ArkadiuszX > Sent: Thursday, August 25, 2016 5:04 PM > To: dev at dpdk.org > Cc: Trahe, Fiona ; Jain, Deepak K > ; De Lara Guarch, Pablo > ; Griffin, John intel.com>; > Kusztal, ArkadiuszX > Subject: [PATCH 0/3] add GMAC capability Intel QAT driver > > This patches add AES GMAC capability to Intel(R) QuickAssist Technology > driver and corresponsing test cases. > > This patchset depends on the following patches/patchsets: > > "crypto/qat: enable Kasumi F9 support in QAT driver" > (http://dpdk.org/dev/patchwork/patch/15320/) > > Arek Kusztal (3): > crypto/qat: add GMAC capability to QAT crypto driver > app/test: add GMAC authentication tests to cryptodev tests > lib/librte_cryptodev: change GMAC API comments > > app/test/test_cryptodev.c | 265 > + > app/test/test_cryptodev_gcm_test_vectors.h | 150 > doc/guides/cryptodevs/qat.rst | 1 + > drivers/crypto/qat/qat_crypto.c| 42 - > lib/librte_cryptodev/rte_crypto_sym.h | 17 +- > 5 files changed, 465 insertions(+), 10 deletions(-) > > -- > 2.1.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH 0/2] Added AES counter mode capability
Series-Acked-by: Deepak Kumar JAIN -Original Message- From: Kusztal, ArkadiuszX Sent: Friday, May 6, 2016 11:22 AM To: dev at dpdk.org Cc: Trahe, Fiona ; Jain, Deepak K ; Griffin, John ; Kusztal, ArkadiuszX Subject: [PATCH 0/2] Added AES counter mode capability This patchset adds AES counter mode capability for Intel QuickAssist Technology crypto driver. It adds six test cases for 16B, 24B, 32B key size. NOTE: Need to repost this patchset because of the problem in email header. Arek Kusztal (2): qat: add AES counter mode capability app/test: add test cases for AES CTR app/test/test_cryptodev.c | 254 app/test/test_cryptodev_aes_ctr_test_vectors.h | 257 + doc/guides/cryptodevs/overview.rst | 6 +- doc/guides/cryptodevs/qat.rst | 3 + doc/guides/rel_notes/release_16_07.rst | 5 + drivers/crypto/qat/qat_crypto.c| 29 ++- 6 files changed, 550 insertions(+), 4 deletions(-) create mode 100644 app/test/test_cryptodev_aes_ctr_test_vectors.h -- 2.1.0
[dpdk-dev] [PATCH] qat: change optimization flag for Intel QuickAssist Technology
Acked-by: Deepak Kumar JAIN
-Original Message-
From: Kusztal, ArkadiuszX
Sent: Tuesday, May 10, 2016 10:24 AM
To: dev at dpdk.org
Cc: Trahe, Fiona ; Griffin, John ; Jain, Deepak K ; Kusztal, ArkadiuszX
Subject: [PATCH] qat: change optimization flag for Intel QuickAssist Technology
From: Arkadiusz Kusztal
Changed to -O3 optimization flag in Intel QuickAssist Technology Makefile
Signed-off-by: Arkadiusz Kusztal
---
drivers/crypto/qat/Makefile | 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 8 +---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/qat/Makefile b/drivers/crypto/qat/Makefile index
258c2d5..ee72a61 100644
--- a/drivers/crypto/qat/Makefile
+++ b/drivers/crypto/qat/Makefile
@@ -38,6 +38,7 @@ LIBABIVER := 1
# build flags
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -O3
# external library include paths
CFLAGS += -I$(SRCDIR)/qat_adf
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index bcccdf4..a5210d2 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -616,10 +616,12 @@ int qat_alg_aead_session_create_content_desc_auth(struct
qat_session *cdesc,
* Write (the length of AAD) into bytes 16-19 of state2
* in big-endian format. This field is 8 bytes
*/
- *(uint32_t *)&(hash->sha.state1[
+ uint32_t *aad_len = (uint32_t *)&hash->sha.state1[
ICP_QAT_HW_GALOIS_128_STATE1_SZ +
- ICP_QAT_HW_GALOIS_H_SZ]) =
- rte_bswap32(add_auth_data_length);
+ ICP_QAT_HW_GALOIS_H_SZ];
+
+ *aad_len = rte_bswap32(add_auth_data_length);
+
proto = ICP_QAT_FW_LA_GCM_PROTO;
} else if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
proto = ICP_QAT_FW_LA_SNOW_3G_PROTO;
--
2.1.0
[dpdk-dev] [PATCH] qat: change optimization flag for Intel QuickAssist Technology
Hi Thomas,
This change was made to fix the compilation issues arising when optimization
flag was changed. Hence its related to same optimization flag patch.
Do you want us to separate the Makefile and .c file change?
Regards,
Deepak
-Original Message-
From: Thomas Monjalon [mailto:thomas.monja...@6wind.com]
Sent: Friday, May 13, 2016 9:18 AM
To: Kusztal, ArkadiuszX
Cc: dev at dpdk.org; Trahe, Fiona ; Griffin, John
; Jain, Deepak K
Subject: Re: [dpdk-dev] [PATCH] qat: change optimization flag for Intel
QuickAssist Technology
2016-05-10 10:24, Arek Kusztal:
> From: Arkadiusz Kusztal
>
> Changed to -O3 optimization flag in Intel QuickAssist Technology Makefile
There is another change below. Should it be a separate patch?
> --- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
> +++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
> @@ -616,10 +616,12 @@ int
> qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
>* Write (the length of AAD) into bytes 16-19 of state2
>* in big-endian format. This field is 8 bytes
>*/
> - *(uint32_t *)&(hash->sha.state1[
> + uint32_t *aad_len = (uint32_t *)&hash->sha.state1[
> ICP_QAT_HW_GALOIS_128_STATE1_SZ +
> - ICP_QAT_HW_GALOIS_H_SZ]) =
> - rte_bswap32(add_auth_data_length);
> + ICP_QAT_HW_GALOIS_H_SZ];
> +
> + *aad_len = rte_bswap32(add_auth_data_length);
> +
> proto = ICP_QAT_FW_LA_GCM_PROTO;
> } else if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) {
> proto = ICP_QAT_FW_LA_SNOW_3G_PROTO;
>
[dpdk-dev] [PATCH v3 13/35] mempool: store physical address in objects
Hi,
While running the QAT PMD tests, a system hang is observed when this commit is
used.
rte_mempool_virt2phy is used in qat_crypto.c.
regards,
Deepak
-Original Message-
From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Olivier Matz
Sent: Wednesday, May 18, 2016 12:05 PM
To: dev at dpdk.org
Cc: Richardson, Bruce ; stephen at
networkplumber.org; Wiles, Keith
Subject: [dpdk-dev] [PATCH v3 13/35] mempool: store physical address in objects
Store the physical address of the object in its header. It simplifies
rte_mempool_virt2phy() and prepares the removing of the paddr[] table in the
mempool header.
Signed-off-by: Olivier Matz
---
lib/librte_mempool/rte_mempool.c | 17 +++--
lib/librte_mempool/rte_mempool.h | 11 ++-
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/lib/librte_mempool/rte_mempool.c b/lib/librte_mempool/rte_mempool.c
index 61e191e..ce12db5 100644
--- a/lib/librte_mempool/rte_mempool.c
+++ b/lib/librte_mempool/rte_mempool.c
@@ -133,19 +133,22 @@ static unsigned optimize_object_size(unsigned obj_size)
typedef void (*rte_mempool_obj_iter_t)(void * /*obj_iter_arg*/,
void * /*obj_start*/,
void * /*obj_end*/,
- uint32_t /*obj_index */);
+ uint32_t /*obj_index */,
+ phys_addr_t /*physaddr*/);
static void
-mempool_add_elem(struct rte_mempool *mp, void *obj)
+mempool_add_elem(struct rte_mempool *mp, void *obj, phys_addr_t
+physaddr)
{
struct rte_mempool_objhdr *hdr;
struct rte_mempool_objtlr *tlr __rte_unused;
obj = (char *)obj + mp->header_size;
+ physaddr += mp->header_size;
/* set mempool ptr in header */
hdr = RTE_PTR_SUB(obj, sizeof(*hdr));
hdr->mp = mp;
+ hdr->physaddr = physaddr;
STAILQ_INSERT_TAIL(&mp->elt_list, hdr, next);
#ifdef RTE_LIBRTE_MEMPOOL_DEBUG
@@ -175,6 +178,7 @@ rte_mempool_obj_mem_iter(void *vaddr, uint32_t elt_num,
size_t total_elt_sz,
uint32_t pgn, pgf;
uintptr_t end, start, va;
uintptr_t pg_sz;
+ phys_addr_t physaddr;
pg_sz = (uintptr_t)1 << pg_shift;
va = (uintptr_t)vaddr;
@@ -210,9 +214,10 @@ rte_mempool_obj_mem_iter(void *vaddr, uint32_t elt_num,
size_t total_elt_sz,
* otherwise, just skip that chunk unused.
*/
if (k == pgn) {
+ physaddr = paddr[k] + (start & (pg_sz - 1));
if (obj_iter != NULL)
obj_iter(obj_iter_arg, (void *)start,
- (void *)end, i);
+ (void *)end, i, physaddr);
va = end;
j += pgf;
i++;
@@ -249,11 +254,11 @@ rte_mempool_obj_iter(struct rte_mempool *mp,
static void
mempool_obj_populate(void *arg, void *start, void *end,
- __rte_unused uint32_t idx)
+ __rte_unused uint32_t idx, phys_addr_t physaddr)
{
struct rte_mempool *mp = arg;
- mempool_add_elem(mp, start);
+ mempool_add_elem(mp, start, physaddr);
mp->elt_va_end = (uintptr_t)end;
}
@@ -358,7 +363,7 @@ rte_mempool_xmem_size(uint32_t elt_num, size_t
total_elt_sz, uint32_t pg_shift)
*/
static void
mempool_lelem_iter(void *arg, __rte_unused void *start, void *end,
- __rte_unused uint32_t idx)
+ __rte_unused uint32_t idx, __rte_unused phys_addr_t physaddr)
{
*(uintptr_t *)arg = (uintptr_t)end;
}
diff --git a/lib/librte_mempool/rte_mempool.h b/lib/librte_mempool/rte_mempool.h
index 12215f6..4f95bdf 100644
--- a/lib/librte_mempool/rte_mempool.h
+++ b/lib/librte_mempool/rte_mempool.h
@@ -159,6 +159,7 @@ struct rte_mempool_objsz { struct rte_mempool_objhdr {
STAILQ_ENTRY(rte_mempool_objhdr) next; /**< Next in list. */
struct rte_mempool *mp; /**< The mempool owning the object. */
+ phys_addr_t physaddr;/**< Physical address of the object. */
#ifdef RTE_LIBRTE_MEMPOOL_DEBUG
uint64_t cookie; /**< Debug cookie. */
#endif
@@ -1131,13 +1132,13 @@ rte_mempool_empty(const struct rte_mempool *mp)
* The physical address of the elt element.
*/
static inline phys_addr_t
-rte_mempool_virt2phy(const struct rte_mempool *mp, const void *elt)
+rte_mempool_virt2phy(__rte_unused const struct rte_mempool *mp, const
+void *elt)
{
if (rte_eal_has_hugepages()) {
- uintptr_t off;
-
- off = (const char *)elt - (const char *)mp->elt_va_start;
- return mp->elt_pa[off >> mp->pg_shift] + (off & mp->pg_mask);
+ const struct rte_mempool_objhdr *hdr;
+ hdr = (const struct rte_mempool_objhdr *)RTE_PTR_SUB(elt,
+ sizeof(*hdr));
+ return hdr->physaddr;
} else {
/*
* If huge pages are disabled, we cannot assume the
--
2.8.0.rc3
[dpdk-dev] [PATCH] qat: fix phys address of content descriptor
-Original Message-
From: Kusztal, ArkadiuszX
Sent: Monday, May 30, 2016 1:39 PM
To: dev at dpdk.org
Cc: Trahe, Fiona ; Griffin, John ; Jain, Deepak K ; olivier.matz at
6wind.com; thomas.monjalon at 6wind.com; Kusztal, ArkadiuszX
Subject: [PATCH] qat: fix phys address of content descriptor
From: Arkadiusz Kusztal
this patch fixes an error with computation of physical address of content
descriptor in the symmetric operations session
Signed-off-by: Arkadiusz Kusztal
---
drivers/crypto/qat/qat_crypto.c | 9 ++---
lib/librte_cryptodev/rte_cryptodev.c | 2 +-
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 495ea1c..abe0511 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -807,12 +807,15 @@ static inline uint32_t adf_modulo(uint32_t data, uint32_t
shift)
return data - mult;
}
-void qat_crypto_sym_session_init(struct rte_mempool *mp, void *priv_sess)
+void qat_crypto_sym_session_init(struct rte_mempool *mp, void
+*sym_sess)
{
- struct qat_session *s = priv_sess;
+ struct rte_cryptodev_sym_session *sess = sym_sess;
+ struct qat_session *s = (void *)sess->_private;
PMD_INIT_FUNC_TRACE();
- s->cd_paddr = rte_mempool_virt2phy(mp, &s->cd);
+ s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
+ offsetof(struct qat_session, cd) +
+ offsetof(struct rte_cryptodev_sym_session, _private);
}
int qat_dev_config(__rte_unused struct rte_cryptodev *dev) diff --git
a/lib/librte_cryptodev/rte_cryptodev.c b/lib/librte_cryptodev/rte_cryptodev.c
index aa4ea42..960e2d5 100644
--- a/lib/librte_cryptodev/rte_cryptodev.c
+++ b/lib/librte_cryptodev/rte_cryptodev.c
@@ -956,7 +956,7 @@ rte_cryptodev_sym_session_init(struct rte_mempool *mp,
sess->mp = mp;
if (dev->dev_ops->session_initialize)
- (*dev->dev_ops->session_initialize)(mp, sess->_private);
+ (*dev->dev_ops->session_initialize)(mp, sess);
}
static int
--
2.1.0
Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] doc: fix typo in SNOW3G documentation
> -Original Message-
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara
> Sent: Thursday, October 6, 2016 9:55 PM
> To: dev at dpdk.org
> Cc: De Lara Guarch, Pablo
> Subject: [dpdk-dev] [PATCH] doc: fix typo in SNOW3G documentation
>
> Fixes: 1d0c90e6cf0b ("doc: update build instructions for libsso_snow3g")
>
> Signed-off-by: Pablo de Lara
> ---
> doc/guides/cryptodevs/snow3g.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/doc/guides/cryptodevs/snow3g.rst
> b/doc/guides/cryptodevs/snow3g.rst
> index f6eb538..75a08aa 100644
> --- a/doc/guides/cryptodevs/snow3g.rst
> +++ b/doc/guides/cryptodevs/snow3g.rst
> @@ -58,7 +58,7 @@ Limitations
> Installation
>
>
> -To build DPDK with the KASUMI_PMD the user is required to download
> +To build DPDK with the SNOW3G_PMD the user is required to download
> the export controlled ``libsso_snow3g`` library, by requesting it from
> ``_.
> Once approval has been granted, the user needs to log in
> --
> 2.7.4
Acked-by: Deepak kumar Jain
[dpdk-dev] [PATCH] doc: fix libcrypto title
> -Original Message-
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara
> Sent: Thursday, October 13, 2016 8:34 PM
> To: dev at dpdk.org
> Cc: De Lara Guarch, Pablo
> Subject: [dpdk-dev] [PATCH] doc: fix libcrypto title
>
> Libcrypto documentation was missing the equal signs ("="), in its title, so it
> was not present in the documentation generated.
>
> Fixes: d61f70b4c918 ("crypto/libcrypto: add driver for OpenSSL library")
>
> Signed-off-by: Pablo de Lara
> ---
> doc/guides/cryptodevs/libcrypto.rst | 1 +
> 1 file changed, 1 insertion(+)
> --
> 2.7.4
Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] doc: ZUC PMD cannot be built as a shared library
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara > Sent: Thursday, October 13, 2016 8:35 PM > To: dev at dpdk.org > Cc: De Lara Guarch, Pablo > Subject: [dpdk-dev] [PATCH] doc: ZUC PMD cannot be built as a shared > library > > ZUC PMD cannot be built as a shared library, due to the fact that some > assembly code in the underlying libsso library is not relocatable. > This will be fixed in the future, but for the moment, it is added as a > limitation > of the PMD. > > Signed-off-by: Pablo de Lara > --- > doc/guides/cryptodevs/zuc.rst | 3 +++ > 1 file changed, 3 insertions(+) > > > Installation > > -- > 2.7.4 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] doc: how to build KASUMI as shared library
> -Original Message- > From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Pablo de Lara > Sent: Thursday, October 13, 2016 8:34 PM > To: dev at dpdk.org > Cc: De Lara Guarch, Pablo > Subject: [dpdk-dev] [PATCH] doc: how to build KASUMI as shared library > > Libsso KASUMI library has to be built with specific parameters to make the > KASUMI PMD be built as a shared library, so a note has been added in its > documentation. > > Signed-off-by: Pablo de Lara > --- > doc/guides/cryptodevs/kasumi.rst | 8 +++- > 1 file changed, 7 insertions(+), 1 deletion(-) > + make KASUMI_CFLAGS=-DKASUMI_C > + > > Initialization > -- > -- > 2.7.4 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] app/test: add tests with corrupted data for QAT test suite
> -Original Message- > From: Kusztal, ArkadiuszX > Sent: Thursday, October 13, 2016 11:04 AM > To: dev at dpdk.org > Cc: Trahe, Fiona ; Jain, Deepak K > ; De Lara Guarch, Pablo > ; Griffin, John intel.com>; > Kusztal, ArkadiuszX > Subject: [PATCH] app/test: add tests with corrupted data for QAT test suite > > This commit adds tests with corrupted data to the Intel QuickAssist > Technology tests suite in test_cryptodev.c > > Signed-off-by: Arek Kusztal > --- > app/test/test_cryptodev.c | 14 ++ > 1 file changed, 14 insertions(+) > > }; > -- > 2.1.0 Acked-by: Deepak Kumar Jain
[dpdk-dev] [PATCH] app/test: add crypto continual tests
> -Original Message- > From: Kusztal, ArkadiuszX > Sent: Thursday, October 13, 2016 1:18 PM > To: dev at dpdk.org > Cc: Trahe, Fiona ; De Lara Guarch, Pablo > ; Griffin, John intel.com>; > Jain, Deepak K ; Kusztal, ArkadiuszX > > Subject: [PATCH] app/test: add crypto continual tests > > This commit adds continual performace tests to Intel(R) QuickAssist > Technology tests suite. Performance tests are run continually with some > number of repeating loops. > > Signed-off-by: Arek Kusztal > --- > app/test/test_cryptodev_perf.c | 133 > - > 1 file changed, 119 insertions(+), 14 deletions(-) > > diff --git a/app/test/test_cryptodev_perf.c > b/app/test/test_cryptodev_perf.c index 43a7166..dd741fa 100644 > --- a/app/test/test_cryptodev_perf.c > -- > 2.1.0 Acked-by: Deepak Kumar Jain
