[dpdk-dev] Intel 82599 tx_conf setting

[Gyumin]

Hi

I've read the Intel 82599 official manual and I found that optimal 
PTHRESH is the tx descriptor buffer size - N (N is CPU cache line 
divided by 16).
1. I guess the size of the tx descriptor buffer is 128. Isn't it right?
Where is the size of the tx descriptor buffer in the official manual?

2. What it means that the TX_PTHRESH=36 in the testpmd.c?
If the size of tx descriptor buffer is 128 then optimal thresholds 
to minimize latency are pthresh=4(cache line / 16), hthresh=0 and 
wthresh=0. Is there something I missed?


Thanks.

[dpdk-dev] Relationship between H/W ring and S/W ring

[Gyumin]

Hi

I`m reading the ixgbe code especially about H/W ring and S/W ring. Is 
the relationship between H/W ring and S/W ring one-to-one mapping?
As far as I know, H/W ring size is determined in the code(hard coded) 
while S/W ring size is determined in port configuration time.
In the ixgbe_rx_alloc_bufs function, H/W ring header address and packet 
address indicate the DMA address of S/W ring's mbuf. I understand it 
means that the relationship between the H/W ring and S/W ring is 
one-to-one mapping. For example, if the size of H/W ring is greater than 
the size of  S/W ring then some portion of H/W ring is unused. Is it 
correct?

Thanks

[dpdk-dev] Relationship between H/W ring and S/W ring

[Gyumin]

Thanks Bruce.

I also agree with that the size of the S/W ring depends on the 
configuration parameters because the size of the S/W ring is 
/sizeof(struct igb_rx_entry) * len/ in the ixgbe_dev_rx_queue_setup 
function. H/W ring is also allocated in the same function by using the 
ring_dma_zone_reserve function, and its size is RX_RING_SZ. I don't 
think the RX_RING_SZ is configurable but it is fixed value. Is there any 
other code configuring the size of H/W ring?

2014-10-30 ?? 6:55? Bruce Richardson ?(?) ? ?:
> On Thu, Oct 30, 2014 at 04:32:16PM +0900, Gyumin wrote:
>> Hi
>>
>> I`m reading the ixgbe code especially about H/W ring and S/W ring. Is the
>> relationship between H/W ring and S/W ring one-to-one mapping?
>> As far as I know, H/W ring size is determined in the code(hard coded) while
>> S/W ring size is determined in port configuration time.
>> In the ixgbe_rx_alloc_bufs function, H/W ring header address and packet
>> address indicate the DMA address of S/W ring's mbuf. I understand it means
>> that the relationship between the H/W ring and S/W ring is one-to-one
>> mapping. For example, if the size of H/W ring is greater than the size of
>> S/W ring then some portion of H/W ring is unused. Is it correct?
>>
>> Thanks
> Hi,
>
> Yes, there is a 1:1 mapping between the hardware and software ring entries, 
> and both are sized depending on the configuration parameters passed to the 
> ring setup APIs. As you state, the HW ring contains the DMA addresses of the 
> packet buffers, while the sw_ring contains the pointers to the original 
> mbufs. The two rings are always kept in sync in the code.
>
> /Bruce
>

[dpdk-dev] Why doesn`t test-acl work when IP filed is RTE_ACL_FIELD_TYPE_RANGE?

[Gyumin]

hi,

I ran test-acl without any modification and it worked well, and I 
modified test-acl like below:
 {
 //.type = RTE_ACL_FIELD_TYPE_MASK,
 .type = RTE_ACL_FIELD_TYPE_RANGE,
 .size = sizeof(uint32_t),
 .field_index = SRC_FIELD_IPV4,
 .input_index = RTE_ACL_IPV4VLAN_SRC,
 .offset = offsetof(struct ipv4_5tuple, ip_src),
 },
 {
 //.type = RTE_ACL_FIELD_TYPE_MASK,
 .type = RTE_ACL_FIELD_TYPE_RANGE,
 .size = sizeof(uint32_t),
 .field_index = DST_FIELD_IPV4,
 .input_index = RTE_ACL_IPV4VLAN_DST,
 .offset = offsetof(struct ipv4_5tuple, ip_dst),
 },


static int
parse_ipv4_net(const char *in, uint32_t *addr, uint32_t *mask_len)
   {
 uint8_t a, b, c, d, m;

 GET_CB_FIELD(in, a, 0, UINT8_MAX, '.');
 GET_CB_FIELD(in, b, 0, UINT8_MAX, '.');
 GET_CB_FIELD(in, c, 0, UINT8_MAX, '.');
 GET_CB_FIELD(in, d, 0, UINT8_MAX, '/');
 //GET_CB_FIELD(in, m, 0, sizeof(uint32_t) * CHAR_BIT, 0);
 GET_CB_FIELD(in, m, 0, 4294967295, 0);

 addr[0] = IPv4(a, b, c, d);
 mask_len[0] = m;

 printf("m[%d]\n", m);

 return 0;
   }

test-acl didn`t match any rules when I ran modified test-acl. Here are 
my rule and trace file:
cat rule1.range
  @192.168.0.1/100 192.168.0.0/24 400 : 500 0 : 52 6/0xff
cat trace1
  0xc0a80005 0xc0a80009 450 53 0x06

Is there anything that I`m missing?

[dpdk-dev] Why doesn`t test-acl work when IP filed is RTE_ACL_FIELD_TYPE_RANGE?

[Gyumin]

ok, I notice now that my rule file was wrong.
I modified the range of SIP/DIP like the value of SIP/DIP (like
192.168.10.100), and it works!