Hi I`m reading the ixgbe code especially about H/W ring and S/W ring. Is the relationship between H/W ring and S/W ring one-to-one mapping? As far as I know, H/W ring size is determined in the code(hard coded) while S/W ring size is determined in port configuration time. In the ixgbe_rx_alloc_bufs function, H/W ring header address and packet address indicate the DMA address of S/W ring's mbuf. I understand it means that the relationship between the H/W ring and S/W ring is one-to-one mapping. For example, if the size of H/W ring is greater than the size of S/W ring then some portion of H/W ring is unused. Is it correct?
Thanks
