RE: [PATCH] net/ice: fix ACL filter uninit
> -Original Message-
> From: Mingjin Ye
> Sent: Friday, February 21, 2025 4:25 PM
> To: dev@dpdk.org
> Cc: Ye, MingjinX ; Richardson, Bruce
> ; Burakov, Anatoly
>
> Subject: [PATCH] net/ice: fix ACL filter uninit
>
> The pf has enabled the ACL filter, so uninit is no longer limited to the DCF.
>
> Fixes: a9d612291c2d ("net/ice: support IPv4 fragments in ACL filters")
>
> Signed-off-by: Mingjin Ye
> ---
Tested-by: Li, Hongbo
Re: [PATCH v13 00/28] [v13]drivers/net Add Support mucse N10 Pmd Driver
On Thu, 20 Feb 2025 13:06:30 +0800 "11" wrote: > Hi Stephen, > > For the release thing, that be ok. > > But for Debian 12 with MUSDK it be failed, do I need to fixed it , > The ability when I used it that I had been memset it. But the compile-tool > is warning it, > hw->phy_port_ids[idx] = ability.port_ids[idx]; > > Branch: master > CommitID:968f7b6d7b6a7e60e6e551db430c4eecaccbbfd2 > > 151613-151639 --> testing issues > > Upstream job id: Generic-DPDK-Compile-Meson#362983 > > Test environment and result as below: > > +++ > | Environment | dpdk_meson_compile | > +++ > | RHEL9 (ARM)| PASS | > +++ > | Ubuntu 20.04 ARM GCC Cross Compile | PASS | > +++ > | Ubuntu 20.04 ARM SVE | PASS | > +++ > | Debian 12 with MUSDK | FAIL | > +++ > | Fedora 40 (ARM Clang) | PASS | > +++ > | Fedora 41 (ARM Clang) | PASS | > +++ > | Fedora 41 (ARM)| PASS | > +++ > | Fedora 40 (ARM)| PASS | > +++ > | Ubuntu 20.04 (ARM) | PASS | > +++ > | Ubuntu 22.04 (ARM) | PASS | > +++ > | Ubuntu 24.04 (ARM) | PASS | > +++ > | CentOS Stream 9 (ARM) | PASS | > +++ > | CentOS Stream 10 (ARM) | PASS | > +++ > | Debian 11 (Buster) (ARM) | PASS | > +++ > | Ubuntu 20.04 ARM Clang Cross Compile | PASS | > +++ > | Ubuntu 20.04 aarch32 GCC Cross Compile | PASS | > +++ > | Debian 12 (arm)| PASS | > +++ > > 20 line log output for Debian 12 with MUSDK (dpdk_meson_compile): > [888/1284] Linking static target drivers/libtmp_rte_net_r8169.a [889/1284] > Generating rte_net_r8169.pmd.c with a custom command [890/1284] Compiling C > object drivers/librte_net_r8169.a.p/meson-generated_.._rte_net_r8169.pmd.c.o > [891/1284] Linking static target drivers/librte_net_r8169.a [892/1284] > Compiling C object > drivers/librte_net_r8169.so.25.1.p/meson-generated_.._rte_net_r8169.pmd.c.o > [893/1284] Linking target drivers/librte_net_r8169.so.25.1 [894/1284] > Compiling C object drivers/net/rnp/base/librnp_base.a.p/rnp_mbx.c.o > [895/1284] Compiling C object > drivers/net/rnp/base/librnp_base.a.p/rnp_fw_cmd.c.o > [896/1284] Compiling C object > drivers/net/rnp/base/librnp_base.a.p/rnp_mbx_fw.c.o > FAILED: drivers/net/rnp/base/librnp_base.a.p/rnp_mbx_fw.c.o > ccache aarch64-linux-gnu-gcc -Idrivers/net/rnp/base/librnp_base.a.p > -Idrivers/net/rnp/base -I../drivers/net/rnp/base -I. -I.. -Iconfig > -I../config -Ilib/eal/include -I../lib/eal/include -Ilib/eal/linux/include > -I../lib/eal/linux/include -Ilib/eal/arm/include -I../lib/eal/arm/include > -I../kernel/linux -Ilib/eal/common -I../lib/eal/common -Ilib/eal > -I../lib/eal -Ilib/kvargs -I../lib/kvargs -Ilib/log -I../lib/log > -Ilib/metrics -I../lib/metrics -Ilib/telemetry -I../lib/telemetry -Ilib/net > -I../lib/net -Ilib/mbuf -I../lib/mbuf -Ilib/mempool -I../lib/mempool > -Ilib/ring -I../lib/ring -Ilib/ethdev -I../lib/ethdev -Ilib/meter > -I../lib/meter -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -Wall > -Winvalid-pch -Wextra -Werror -std=c11 -O3 -include rte_config.h -Wvla > -Wcast-qual -Wdeprecated -Wformat -Wformat-nonliteral -Wformat-security > -Wmissing-declarations -Wmissing-prototypes -Wnested-externs > -Wold-style-definition -Wpointer-arith -Wsign-compare -Wstrict-prototypes > -Wundef -Wwrite-st rings -Wno-packed-not-aligned > -Wno-missing-field-initializers -D_GNU_SOURCE -fPIC -mcpu=cortex-a72 > -DALLOW_EXPERIMENTAL_API -DALL
Re: [PATCH v6 2/2] net/af_xdp: Refactor af_xdp_tx_zc
On Sat, 1 Feb 2025 00:10:21 +0100
Ariel Otilibili wrote:
> @ -559,21 +582,12 @@ af_xdp_tx_zc(void *queue, struct rte_mbuf **bufs,
> uint16_t nb_pkts)
> mbuf = bufs[i];
>
> if (mbuf->pool == umem->mb_pool) {
> - if (!xsk_ring_prod__reserve(&txq->tx, 1, &idx_tx)) {
> + if (!(desc = reserve_and_fill(txq, mbuf, umem))) {
> kick_tx(txq, cq);
> - if (!xsk_ring_prod__reserve(&txq->tx, 1,
> - &idx_tx))
> + if (!(desc = reserve_and_fill(txq, mbuf, umem)))
> goto out;
> }
Please avoid doing assignment in a conditional statement, can be error prone.
Surprised checkpatch doesn't complain about it.
Better as:
desc = reserve_and_fill(txq, mbuf, umem);
if (!desc) {
kick_tx(txq, cq);
desc = reserve_and_fill(txq, mbuf, umem);
if (!desc)
goto out;
[PATCH 3/6] config: allow faster instruction sets to be used with MSVC
Up to now MSVC has being used with the default mode, which uses SSE2
instructions for scalar floating-point and vector calculations.
https://learn.microsoft.com/en-us/cpp/build/reference/arch-x64?view=msvc-170
This patch allows users to specify the CPU for which the generated
code should be optimized for in the same way it's done for GCC: by
passing the CPU name.
When no explicit CPU name is passed, 'native' is assumed (like it
happens with GCC) and the code will be optimized for the same CPU
type used to compile the code.
MSVC does not provide this functionality natively, so logic was
added to meson.build to handle these differences, detecting which
instruction sets are supported by the CPU(s), passing the best
options to MSVC and setting the correct macros (like __AVX512F__)
so that the DPDK code can rely on them like it is done with GCC.
Signed-off-by: Andre Muezerie
---
config/x86/meson.build | 364 -
1 file changed, 325 insertions(+), 39 deletions(-)
diff --git a/config/x86/meson.build b/config/x86/meson.build
index 47a5b0c04a..9260969c54 100644
--- a/config/x86/meson.build
+++ b/config/x86/meson.build
@@ -14,7 +14,194 @@ if is_linux or cc.get_id() == 'gcc'
endif
endif
-cc_avx512_flags = ['-mavx512f', '-mavx512vl', '-mavx512dq', '-mavx512bw']
+cpuid_code = '''
+#include
+#include
+#include
+
+uint32_t f1_ECX = 0;
+uint32_t f1_EDX = 0;
+uint32_t f7_EBX = 0;
+uint32_t f7_ECX = 0;
+
+void get_support_flags()
+{
+int ids_max;
+int data[4];
+
+/*
+ * Calling __cpuid with 0x0 as the function_id argument
+ * gets the number of the highest valid function ID.
+ */
+__cpuid(data, 0);
+ids_max = data[0];
+
+if (1 <= ids_max) {
+__cpuidex(data, 1, 0);
+f1_ECX = data[2];
+f1_EDX = data[3];
+
+if (7 <= ids_max) {
+__cpuidex(data, 7, 0);
+f7_EBX = data[1];
+f7_ECX = data[2];
+}
+}
+}
+
+int get_instruction_support()
+{
+get_support_flags();
+
+#ifdef SSE3
+return (f1_ECX & (1UL << 0)) ? 1 : 0;
+#endif
+#ifdef PCLMUL
+return (f1_ECX & (1UL << 1)) ? 1 : 0;
+#endif
+#ifdef SSSE3
+return (f1_ECX & (1UL << 9)) ? 1 : 0;
+#endif
+#ifdef SSE4_1
+return (f1_ECX & (1UL << 19)) ? 1 : 0;
+#endif
+#ifdef SSE4_2
+return (f1_ECX & (1UL << 20)) ? 1 : 0;
+#endif
+#ifdef AES
+return (f1_ECX & (1UL << 25)) ? 1 : 0;
+#endif
+#ifdef AVX
+return (f1_ECX & (1UL << 28)) ? 1 : 0;
+#endif
+#ifdef RDRND
+return (f1_ECX & (1UL << 30)) ? 1 : 0;
+#endif
+#ifdef SSE
+return (f1_EDX & (1UL << 25)) ? 1 : 0;
+#endif
+#ifdef SSE2
+return (f1_EDX & (1UL << 26)) ? 1 : 0;
+#endif
+#ifdef AVX2
+return (f7_EBX & (1UL << 5)) ? 1 : 0;
+#endif
+#ifdef AVX512F
+return (f7_EBX & (1UL << 16)) ? 1 : 0;
+#endif
+#ifdef AVX512DQ
+return (f7_EBX & (1UL << 17)) ? 1 : 0;
+#endif
+#ifdef RDSEED
+return (f7_EBX & (1UL << 18)) ? 1 : 0;
+#endif
+#ifdef AVX512IFMA
+return (f7_EBX & (1UL << 21)) ? 1 : 0;
+#endif
+#ifdef AVX512CD
+return (f7_EBX & (1UL << 28)) ? 1 : 0;
+#endif
+#ifdef AVX512BW
+return (f7_EBX & (1UL << 30)) ? 1 : 0;
+#endif
+#ifdef AVX512VL
+return (f7_EBX & (1UL << 31)) ? 1 : 0;
+#endif
+#ifdef GFNI
+return (f7_ECX & (1UL << 8)) ? 1 : 0;
+#endif
+#ifdef VPCLMULQDQ
+return (f7_ECX & (1UL << 10)) ? 1 : 0;
+#endif
+
+return -1;
+}
+
+int main(int argc, char *argv[])
+{
+int res = get_instruction_support();
+if (res == -1) {
+printf("Unknown instruction set");
+return -1;
+}
+printf("%d", res);
+
+return 0;
+}
+'''
+
+# The data in table below can be found here:
+# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
+# This table only contains CPUs that have SSE4.2, as this instruction set is
required by DPDK.
+# That means that in addition to the instruction sets mentioned in the table,
all these CPUs
+# also have ['SSE', 'SSE2', 'SSE3', 'SSEE3', 'SSE4_1', 'SSE4_2']
+cpu_type_to_flags = {
+ 'x86-64-v2': [],
+ 'x86-64-v3': ['AVX', 'AVX2'],
+ 'x86-64-v4': ['AVX', 'AVX2', 'AVX512F', 'AVX512VL', 'AVX512BW',
'AVX512DQ', 'AVX512CD'],
+ 'nehalem': [],
+ 'corei7': [],
+'westmere': ['PCLMUL'],
+ 'sandybridge': ['AVX', 'PCLMUL'],
+ 'corei7-avx': ['AVX', 'PCLMUL'],
+ 'ivybridge': ['AVX', 'PCLMUL', 'RDRND'],
+ 'core-avx-i': ['AVX', 'PCLMUL', 'RDRND'],
+ 'haswell': ['AVX', 'PCLMUL', 'RDRND', 'AVX2'],
+ 'core-avx2': ['AVX', 'PCLMUL', 'RDRND', 'AVX2'],
+ 'broadwell': ['AVX', 'PCLMUL', 'RDRND',
[PATCH 0/6] allow faster instruction sets to be used with MSVC
Up to now MSVC has being used with the default mode, which uses SSE2 instructions for scalar floating-point and vector calculations. https://learn.microsoft.com/en-us/cpp/build/reference/arch-x64?view=msvc-170 This series allows users to specify the CPU for which the generated code should be optimized for in the same way it's done for GCC: by passing the CPU name. When no explicit CPU name is passed, 'native' is assumed (like it happens with GCC) and the code will be optimized for the same CPU type used to compile the code. MSVC does not provide this functionality natively, so logic was added to handle these differences, detecting which instruction sets are supported by the CPU(s), passing the best options to MSVC and setting the correct macros (like __AVX512F__) so that the DPDK code can rely on them like it is done with GCC. Andre Muezerie (6): eal: make compatible with instruction set updates for MSVC eal: only use numbers as align parameters for MSVC config: allow faster instruction sets to be used with MSVC drivers/net: make compatible with instruction set updates for MSVC acl: make compatible with instruction set updates for MSVC member: make compatible with instruction set updates for MSVC config/x86/meson.build | 364 + drivers/net/bnxt/meson.build | 2 +- drivers/net/enic/meson.build | 2 +- drivers/net/intel/i40e/meson.build | 2 +- drivers/net/intel/iavf/meson.build | 2 +- drivers/net/intel/ice/meson.build | 2 +- drivers/net/intel/idpf/meson.build | 2 +- drivers/net/nfp/meson.build| 2 +- drivers/net/octeon_ep/meson.build | 4 +- lib/acl/meson.build| 16 +- lib/eal/common/rte_random.c| 2 + lib/eal/x86/include/rte_vect.h | 11 +- lib/member/meson.build | 11 +- 13 files changed, 363 insertions(+), 59 deletions(-) -- 2.48.1.vfs.0.0
[PATCH 2/6] eal: only use numbers as align parameters for MSVC
After the instruction set updates for MSVC the error below poped up:
..\lib\eal\x86\include\rte_vect.h(82): error C2059: syntax error: '('
The issue is that MSVC does not allow __rte_aligned(RTE_X86_ZMM_SIZE).
It only accepts numbers that are power of 2. So, even though
RTE_X86_ZMM_SIZE represents a number that is a power of two it cannot
be used directly.
https://learn.microsoft.com/en-us/cpp/cpp/align-cpp?view=msvc-170
Signed-off-by: Andre Muezerie
---
lib/eal/x86/include/rte_vect.h | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/lib/eal/x86/include/rte_vect.h b/lib/eal/x86/include/rte_vect.h
index 70c78e9b77..0a51c539a4 100644
--- a/lib/eal/x86/include/rte_vect.h
+++ b/lib/eal/x86/include/rte_vect.h
@@ -79,7 +79,16 @@ __extension__ ({\
#define RTE_X86_ZMM_SIZE (sizeof(__m512i))
#define RTE_X86_ZMM_MASK (RTE_X86_ZMM_SIZE - 1)
-typedef union __rte_aligned(RTE_X86_ZMM_SIZE) __rte_x86_zmm {
+/*
+ * MSVC does not allow __rte_aligned(RTE_X86_ZMM_SIZE). It only accepts
+ * numbers that are power of 2. So, even though RTE_X86_ZMM_SIZE represents a
+ * number that is a power of two it cannot be used directly.
+ * Ref: https://learn.microsoft.com/en-us/cpp/cpp/align-cpp?view=msvc-170
+ * The static assert below ensures that RTE_X86_ZMM_SIZE is equal to what is
+ * used in the __rte_aligned() expression.
+ */
+static_assert(RTE_X86_ZMM_SIZE == 64, "Unexpected size of __m512i");
+typedef union __rte_aligned(64) __rte_x86_zmm {
__m512i z;
ymm_ty[RTE_X86_ZMM_SIZE / sizeof(ymm_t)];
xmm_tx[RTE_X86_ZMM_SIZE / sizeof(xmm_t)];
--
2.48.1.vfs.0.0
[PATCH 4/6] drivers/net: make compatible with instruction set updates for MSVC
Top level 'cc_avx2_flags' was created and holds the correct flags
depending on the compiler used.
Signed-off-by: Andre Muezerie
---
drivers/net/bnxt/meson.build | 2 +-
drivers/net/enic/meson.build | 2 +-
drivers/net/intel/i40e/meson.build | 2 +-
drivers/net/intel/iavf/meson.build | 2 +-
drivers/net/intel/ice/meson.build | 2 +-
drivers/net/intel/idpf/meson.build | 2 +-
drivers/net/nfp/meson.build| 2 +-
drivers/net/octeon_ep/meson.build | 4 ++--
8 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index e26cf13a65..fd82d0c409 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -65,7 +65,7 @@ if arch_subdir == 'x86'
static_rte_bus_pci,
static_rte_kvargs, static_rte_hash],
include_directories: includes,
-c_args: [cflags, '-mavx2'])
+c_args: [cflags, cc_avx2_flags])
objs += bnxt_avx2_lib.extract_objects('bnxt_rxtx_vec_avx2.c')
elif arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64')
sources += files('bnxt_rxtx_vec_neon.c')
diff --git a/drivers/net/enic/meson.build b/drivers/net/enic/meson.build
index 1e26338350..cfe5ec170a 100644
--- a/drivers/net/enic/meson.build
+++ b/drivers/net/enic/meson.build
@@ -38,7 +38,7 @@ if dpdk_conf.has('RTE_ARCH_X86_64')
'enic_rxtx_vec_avx2.c',
dependencies: [static_rte_ethdev, static_rte_bus_pci],
include_directories: includes,
-c_args: [cflags, '-mavx2'])
+c_args: [cflags, cc_avx2_flags])
objs += enic_avx2_lib.extract_objects('enic_rxtx_vec_avx2.c')
endif
diff --git a/drivers/net/intel/i40e/meson.build
b/drivers/net/intel/i40e/meson.build
index ffa40c5d64..2973ed1a01 100644
--- a/drivers/net/intel/i40e/meson.build
+++ b/drivers/net/intel/i40e/meson.build
@@ -49,7 +49,7 @@ if arch_subdir == 'x86'
'i40e_rxtx_vec_avx2.c',
dependencies: [static_rte_ethdev, static_rte_kvargs,
static_rte_hash],
include_directories: includes,
-c_args: [cflags, '-mavx2'])
+c_args: [cflags, cc_avx2_flags])
objs += i40e_avx2_lib.extract_objects('i40e_rxtx_vec_avx2.c')
if cc_has_avx512
diff --git a/drivers/net/intel/iavf/meson.build
b/drivers/net/intel/iavf/meson.build
index 19cd1cfbc8..f7eac7c57a 100644
--- a/drivers/net/intel/iavf/meson.build
+++ b/drivers/net/intel/iavf/meson.build
@@ -37,7 +37,7 @@ if arch_subdir == 'x86'
'iavf_rxtx_vec_avx2.c',
dependencies: [static_rte_ethdev],
include_directories: includes,
-c_args: [cflags, '-mavx2'])
+c_args: [cflags, cc_avx2_flags])
objs += iavf_avx2_lib.extract_objects('iavf_rxtx_vec_avx2.c')
if cc_has_avx512
diff --git a/drivers/net/intel/ice/meson.build
b/drivers/net/intel/ice/meson.build
index a34b7c966a..cbdf38c1c4 100644
--- a/drivers/net/intel/ice/meson.build
+++ b/drivers/net/intel/ice/meson.build
@@ -43,7 +43,7 @@ if arch_subdir == 'x86'
'ice_rxtx_vec_avx2.c',
dependencies: [static_rte_ethdev, static_rte_hash],
include_directories: includes,
-c_args: [cflags, '-mavx2'])
+c_args: [cflags, cc_avx2_flags])
objs += ice_avx2_lib.extract_objects('ice_rxtx_vec_avx2.c')
if cc_has_avx512
diff --git a/drivers/net/intel/idpf/meson.build
b/drivers/net/intel/idpf/meson.build
index 802b13035b..4b272d02b1 100644
--- a/drivers/net/intel/idpf/meson.build
+++ b/drivers/net/intel/idpf/meson.build
@@ -23,7 +23,7 @@ if arch_subdir == 'x86' and dpdk_conf.get('RTE_IOVA_IN_MBUF')
== 1
'idpf_common_rxtx_avx2.c',
dependencies: [static_rte_ethdev, static_rte_hash],
include_directories: includes,
-c_args: [cflags, '-mavx2'])
+c_args: [cflags, cc_avx2_flags])
objs += idpf_avx2_lib.extract_objects('idpf_common_rxtx_avx2.c')
if cc_has_avx512
diff --git a/drivers/net/nfp/meson.build b/drivers/net/nfp/meson.build
index 39762bd45a..0a12b7dce7 100644
--- a/drivers/net/nfp/meson.build
+++ b/drivers/net/nfp/meson.build
@@ -61,7 +61,7 @@ if arch_subdir == 'x86'
avx2_sources,
dependencies: [static_rte_ethdev, static_rte_bus_pci],
include_directories: includes,
-c_args: [cflags, '-mavx2']
+c_args: [cflags, cc_avx2_flags]
)
objs += nfp_avx2_lib.extract_all_objects(recursive: true)
diff --git a/drivers/net/octeon_ep/meson.build
b/drivers/net/octeon_ep/meson.build
index d5d40b23a1..1b34db3edc 100644
--- a/drivers/net/octeon_ep/meson.build
+++ b/drivers/net/octeon_ep/meson.build
@@ -18,13 +18,13 @@ if arch_subdir == 'x86'
if cc.get_define('__AVX2__', args: machine_args) != ''
cflags += ['-DCC_AVX2_SUPPORT']
sources += files('cnxk_ep_rx_avx.c')
-elif cc.has_argument('-mavx2')
+elif cc.has_multi_arguments
[PATCH 5/6] acl: make compatible with instruction set updates for MSVC
Top level 'cc_avx2_flags' was created and holds the correct flags
depending on the compiler used.
File meson.build was updated to handle the correct AVX512 flags
depending on compiler used.
Signed-off-by: Andre Muezerie
---
lib/acl/meson.build | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/lib/acl/meson.build b/lib/acl/meson.build
index fefe131a48..24e47b6cc1 100644
--- a/lib/acl/meson.build
+++ b/lib/acl/meson.build
@@ -19,7 +19,7 @@ if dpdk_conf.has('RTE_ARCH_X86')
avx2_tmplib = static_library('avx2_tmp',
'acl_run_avx2.c',
dependencies: static_rte_eal,
-c_args: cflags + ['-mavx2'])
+c_args: [cflags, cc_avx2_flags])
objs += avx2_tmplib.extract_objects('acl_run_avx2.c')
# compile AVX512 version if:
@@ -38,6 +38,12 @@ if dpdk_conf.has('RTE_ARCH_X86')
# compiler flags, and then have the .o file from static lib
# linked into main lib.
+if is_ms_compiler
+acl_avx512_args = cc_avx512_flags
+else
+acl_avx512_args = ['-mavx512f', '-mavx512vl', '-mavx512cd',
'-mavx512bw']
+endif
+
# check if all required flags already enabled (variant a).
acl_avx512_flags = ['__AVX512F__', '__AVX512VL__',
'__AVX512CD__', '__AVX512BW__']
@@ -55,15 +61,11 @@ if dpdk_conf.has('RTE_ARCH_X86')
sources += files('acl_run_avx512.c')
cflags += '-DCC_AVX512_SUPPORT'
-elif cc.has_multi_arguments('-mavx512f', '-mavx512vl',
-'-mavx512cd', '-mavx512bw')
-
+elif cc.has_multi_arguments(acl_avx512_args)
avx512_tmplib = static_library('avx512_tmp',
'acl_run_avx512.c',
dependencies: static_rte_eal,
-c_args: cflags +
-['-mavx512f', '-mavx512vl',
- '-mavx512cd', '-mavx512bw'])
+c_args: cflags + acl_avx512_args)
objs += avx512_tmplib.extract_objects(
'acl_run_avx512.c')
cflags += '-DCC_AVX512_SUPPORT'
--
2.48.1.vfs.0.0
[PATCH 1/6] eal: make compatible with instruction set updates for MSVC
After the instruction set updates for MSVC the error below poped up: ../lib/eal/common/rte_random.c(6): fatal error C1083: Cannot open include file: 'x86intrin.h': No such file or directory The fix is to not include header x86intrin.h with MSVC. Signed-off-by: Andre Muezerie --- lib/eal/common/rte_random.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/eal/common/rte_random.c b/lib/eal/common/rte_random.c index 8e62578176..9354358818 100644 --- a/lib/eal/common/rte_random.c +++ b/lib/eal/common/rte_random.c @@ -3,8 +3,10 @@ */ #ifdef __RDSEED__ +#ifndef RTE_TOOLCHAIN_MSVC #include #endif +#endif #include #include -- 2.48.1.vfs.0.0
Re: [PATCH v7 1/4] bus/pci: fix registration of PCI device
On Wed, 12 Feb 2025 18:38:32 +0200
Shani Peretz wrote:
> When registering a new PCI device, the device->name field stored
> the user-provided string from devargs (e.g., "08:00.0" or ":08:00.0").
> This approach led to inconsistencies when registering new devices.
>
> This patch fix this issue by saving the parsed PCI in device->name,
> so when a new PCI device is registering the name displayed in the device
> list will be the parsed version.
>
> Fixes: 23eaa9059ec2 ("bus/pci: use given name as generic name")
>
> Cc: sta...@dpdk.org
> Signed-off-by: Shani Peretz
Is there a bugzilla entry for this?
Would like to be able to see what exactly was broken.
The PCI name thing goes back to 17.01 release where this was added.
Did something regress? If so why is there no test for this?
commit 23eaa9059ec24e95e32361f333ed0686f82bea74
Author: Gaetan Rivet
Date: Sat Jul 15 19:56:39 2017 +0200
bus/pci: use given name as generic name
When an application requests the use of a PCI device, it can currently
interchangeably use either the longform DomBDF format (:00:00.0) or
the shorter BDF format (00:00.0).
When a device is inserted via the hotplug API, it must first be scanned
and then will be identified by its name using `find_device`. The name of
the device must match the name given by the user to be found and then
probed.
A new function sets the expected name for a scanned PCI device. It was
previously generated from parsing the PCI address. This canonical name
is superseded when an rte_devargs exists describing the device. In such
case, the device takes the given name found within the rte_devargs.
As the rte_devargs is linked to the rte_pci_device during scanning, it
can be avoided during the probe. Additionally, this fixes the issue of
the rte_devargs lookup not being done within rte_pci_probe_one.
Fixes: beec692c5157 ("eal: add name field to generic device")
Cc: sta...@dpdk.org
Signed-off-by: Gaetan Rivet
[PATCH 6/6] member: make compatible with instruction set updates for MSVC
File meson.build was updated to handle the correct AVX512 flags
depending on compiler used.
Signed-off-by: Andre Muezerie
---
lib/member/meson.build | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/lib/member/meson.build b/lib/member/meson.build
index f92cbb7f25..8416dc6f8a 100644
--- a/lib/member/meson.build
+++ b/lib/member/meson.build
@@ -33,6 +33,12 @@ if dpdk_conf.has('RTE_ARCH_X86_64') and binutils_ok
# compiler flags, and then have the .o file from static lib
# linked into main lib.
+if is_ms_compiler
+member_avx512_args = cc_avx512_flags
+else
+member_avx512_args = ['-mavx512f', '-mavx512dq', '-mavx512ifma']
+endif
+
# check if all required flags already enabled
sketch_avx512_flags = ['__AVX512F__', '__AVX512DQ__', '__AVX512IFMA__']
@@ -46,13 +52,12 @@ if dpdk_conf.has('RTE_ARCH_X86_64') and binutils_ok
if sketch_avx512_on == true
cflags += ['-DCC_AVX512_SUPPORT']
sources += files('rte_member_sketch_avx512.c')
-elif cc.has_multi_arguments('-mavx512f', '-mavx512dq', '-mavx512ifma')
+elif cc.has_multi_arguments(member_avx512_args)
sketch_avx512_tmp = static_library('sketch_avx512_tmp',
'rte_member_sketch_avx512.c',
include_directories: includes,
dependencies: [static_rte_eal, static_rte_hash],
-c_args: cflags +
-['-mavx512f', '-mavx512dq', '-mavx512ifma'])
+c_args: cflags + member_avx512_args)
objs += sketch_avx512_tmp.extract_objects('rte_member_sketch_avx512.c')
cflags += ['-DCC_AVX512_SUPPORT']
endif
--
2.48.1.vfs.0.0
[PATCH 2/3] net/mlx5: add jump FDB Rx flag
When jump FDB Rx is supported, flow will be able to jump
from FDB Tx to FDB Rx, in that case the dest action in FDB
Rx table should support FDB Tx as well.
Signed-off-by: Suanming Mou
---
drivers/common/mlx5/mlx5_devx_cmds.c | 8
drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
drivers/net/mlx5/linux/mlx5_os.c | 1 +
drivers/net/mlx5/mlx5.h | 1 +
drivers/net/mlx5/mlx5_flow_hw.c | 8 +++-
5 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
b/drivers/common/mlx5/mlx5_devx_cmds.c
index f504b29f31..eb8553e8ad 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -924,6 +924,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
bool hca_cap_2_sup;
uint64_t general_obj_types_supported = 0;
+ uint64_t stc_action_type_127_64;
void *hcattr;
int rc, i;
@@ -1352,6 +1353,13 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
attr->fdb_unified_en = MLX5_GET(wqe_based_flow_table_cap,
hcattr,
fdb_unified_en);
+ stc_action_type_127_64 = MLX5_GET64(wqe_based_flow_table_cap,
+ hcattr,
+ stc_action_type_127_64);
+ if (stc_action_type_127_64 &
+ (1 <<
(MLX5_IFC_STC_ACTION_TYPE_JUMP_FLOW_TABLE_FDB_RX_BIT_INDEX -
+ MLX5_IFC_STC_ACTION_TYPE_BIT_64_INDEX)))
+ attr->jump_fdb_rx_en = true;
}
/* Query HCA attribute for ROCE. */
if (attr->roce) {
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h
b/drivers/common/mlx5/mlx5_devx_cmds.h
index 8de4210fb2..6c726a0d46 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -326,6 +326,7 @@ struct mlx5_hca_attr {
uint32_t lag_rx_port_affinity:1;
uint32_t wqe_based_flow_table_sup:1;
uint32_t fdb_unified_en:1;
+ uint32_t jump_fdb_rx_en:1;
uint8_t max_header_modify_pattern_length;
uint64_t system_image_guid;
uint32_t log_max_conn_track_offload:5;
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 9410211e3b..4e64026137 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1718,6 +1718,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
priv->unified_fdb_en = !!priv->master;
DRV_LOG(DEBUG, "port %u: unified FDB %s enabled.",
eth_dev->data->port_id, priv->unified_fdb_en ? "is" :
"isn't");
+ priv->jump_fdb_rx_en = sh->cdev->config.hca_attr.jump_fdb_rx_en;
if (priv->sh->config.dv_esw_en) {
uint32_t usable_bits;
uint32_t required_bits;
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index f73f6e63ff..545ba48b3c 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1987,6 +1987,7 @@ struct mlx5_priv {
uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
uint32_t tunnel_enabled:1; /* If tunnel offloading is enabled on rxqs.
*/
uint32_t unified_fdb_en:1; /* Unified FDB flag per port. */
+ uint32_t jump_fdb_rx_en:1; /* Jump from FDB Tx to FDB Rx flag per port.
*/
uint16_t domain_id; /* Switch domain identifier. */
uint16_t vport_id; /* Associated VF vport index (if any). */
uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index f0888dbf0e..83f55ed3e8 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -9322,6 +9322,7 @@ flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx)
struct mlx5_flow_group *grp_data;
struct mlx5dr_table *tbl = NULL;
struct mlx5dr_action *jump;
+ uint32_t hws_flags;
uint32_t idx = 0;
MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
attr->transfer ? "FDB" : "NIC", attr->egress ? "egress" :
"ingress",
@@ -9342,10 +9343,15 @@ flow_hw_grp_create_cb(void *tool_ctx, void *cb_ctx)
goto error;
grp_data->tbl = tbl;
if (attr->group) {
+ hws_flags = mlx5_hw_act_dest_table_flag[dr_tbl_attr.type];
+ /* For case of jump from FDB Tx to FDB Rx as it is supported
now. */
+ if (priv->jump_fdb_rx_en &&
+ dr_tbl_attr.type == MLX5DR_TABLE_TYPE_FDB_RX)
+ hws_flags |= MLX5DR_ACTION_FLAG_HWS_FDB_TX;
/* Jump action be used by non-root table. */
jump = mlx5dr_action_create_dest_table
(priv->dr_ctx, tbl,
-mlx5_hw
[PATCH 0/2] net/xsc: Resolve warnings from PVS
This patch series resolves two warnings reported by PVS studio. --- Renyong Wan (2): net/xsc: check possible null pointer dereference net/xsc: suppress assign the same value warning drivers/net/xsc/xsc_rx.c| 6 +- drivers/net/xsc/xsc_vfio_mbox.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.25.1
[PATCH 1/2] net/xsc: check possible null pointer dereference
This issue was reported by PVS studio, described as:
https://pvs-studio.com/en/docs/warnings/v522/
Signed-off-by: Rong Qian
Signed-off-by: Renyong Wan
---
drivers/net/xsc/xsc_rx.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/xsc/xsc_rx.c b/drivers/net/xsc/xsc_rx.c
index a702b9592b..0100ccdcfd 100644
--- a/drivers/net/xsc/xsc_rx.c
+++ b/drivers/net/xsc/xsc_rx.c
@@ -308,7 +308,9 @@ xsc_rss_qp_create(struct xsc_ethdev_priv *priv, int port_id)
in->req_len = rte_cpu_to_be_32(cmd_len);
for (i = 0; i < priv->num_rq; i++) {
- rxq_data = (*priv->rxqs)[i];
+ rxq_data = xsc_rxq_get(priv, i);
+ if (rxq_data == NULL)
+ return -EINVAL;
req = (struct xsc_cmd_create_qp_request *)(&in->data[0] +
entry_len * i);
req->input_qpn = rte_cpu_to_be_16(0); /* useless for eth */
req->pa_num = rte_cpu_to_be_16(pa_num);
@@ -348,6 +350,8 @@ xsc_rss_qp_create(struct xsc_ethdev_priv *priv, int port_id)
for (i = 0; i < priv->num_rq; i++) {
rxq_data = xsc_rxq_get(priv, i);
+ if (rxq_data == NULL)
+ return -EINVAL;
rxq_data->wqes = rxq_data->rq_pas->addr;
if (!xsc_dev_is_vf(xdev))
rxq_data->rq_db = (uint32_t *)((uint8_t
*)xdev->bar_addr +
--
2.25.1
[PATCH 2/2] net/xsc: suppress assign the same value warning
This issue was reported by PVS studio, described as: https://pvs-studio.com/en/docs/warnings/v1048/ This warning is harmless since both structs have the same size. The tool is just being annoying, so we should suppress it. Signed-off-by: Rong Qian Signed-off-by: Renyong Wan --- drivers/net/xsc/xsc_vfio_mbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/xsc/xsc_vfio_mbox.c b/drivers/net/xsc/xsc_vfio_mbox.c index c465679527..3c8bb54601 100644 --- a/drivers/net/xsc/xsc_vfio_mbox.c +++ b/drivers/net/xsc/xsc_vfio_mbox.c @@ -572,7 +572,7 @@ xsc_vfio_mbox_init(struct xsc_dev *xdev) cmdq->req_lay = cmdq->req_mz->addr; snprintf(name, RTE_MEMZONE_NAMESIZE, "%s_cmd_cq", xdev->pci_dev->device.name); - size = (1 << XSC_CMDQ_DEPTH_LOG) * sizeof(struct xsc_cmdq_rsp_layout); + size = (1 << XSC_CMDQ_DEPTH_LOG) * sizeof(struct xsc_cmdq_rsp_layout); /* -V1048 */ cmdq->rsp_mz = rte_memzone_reserve_aligned(name, size, SOCKET_ID_ANY, RTE_MEMZONE_IOVA_CONTIG, -- 2.25.1
[PATCH 1/3] net/mlx5/hws: support jump FDB Rx
Before FW introduced the JUMP_FDB_RX action feature, jump from
FDB Tx to Rx is not allowed. JUMP_FDB_RX feature introduces
the internal loopback for Tx case and allow the REG C0 C1 B be
preserved as well.
This commit adds the JUMP_FDB_RX cap bit check and use
JUMP_FDB_RX instead of FT for dest table FDB Rx case.
Signed-off-by: Suanming Mou
Signed-off-by: Alex Vesker
---
drivers/common/mlx5/mlx5_prm.h| 9 -
drivers/net/mlx5/hws/mlx5dr_action.c | 26 +-
drivers/net/mlx5/hws/mlx5dr_action.h | 4
drivers/net/mlx5/hws/mlx5dr_cmd.c | 9 +
drivers/net/mlx5/hws/mlx5dr_cmd.h | 2 ++
drivers/net/mlx5/hws/mlx5dr_context.c | 17 +
drivers/net/mlx5/hws/mlx5dr_context.h | 2 ++
7 files changed, 63 insertions(+), 6 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 3fc3b0cd2a..84e3347794 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -2466,7 +2466,8 @@ struct mlx5_ifc_wqe_based_flow_table_cap_bits {
u8 reserved_at_60[0x8];
u8 max_header_modify_pattern_length[0x8];
u8 ste_format[0x10];
- u8 stc_action_type[0x80];
+ u8 stc_action_type_63_0[0x40];
+ u8 stc_action_type_127_64[0x40];
u8 header_insert_type[0x10];
u8 header_remove_type[0x10];
u8 trivial_match_definer[0x20];
@@ -3543,6 +3544,11 @@ enum mlx5_ifc_rtc_reparse_mode {
MLX5_IFC_RTC_REPARSE_BY_STC = 0x2,
};
+enum mlx5_ifc_stc_action_type_bit_index {
+ MLX5_IFC_STC_ACTION_TYPE_BIT_64_INDEX = 64,
+ MLX5_IFC_STC_ACTION_TYPE_JUMP_FLOW_TABLE_FDB_RX_BIT_INDEX = 71,
+};
+
#define MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX 16
struct mlx5_ifc_rtc_bits {
@@ -3621,6 +3627,7 @@ enum mlx5_ifc_stc_action_type {
MLX5_IFC_STC_ACTION_TYPE_ALLOW = 0x84,
MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT = 0x85,
MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_UPLINK = 0x86,
+ MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FLOW_TABLE_FDB_RX = 0x87,
};
enum mlx5_ifc_stc_reparse_mode {
diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c
b/drivers/net/mlx5/hws/mlx5dr_action.c
index b9452a3ebc..e21db5b327 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -803,6 +803,9 @@ int mlx5dr_action_root_build_attr(struct mlx5dr_rule_action
rule_actions[],
switch (action->type) {
case MLX5DR_ACTION_TYP_TBL:
+ attr[i].type = MLX5DV_FLOW_ACTION_DEST_DEVX;
+ attr[i].obj = action->dest_tbl.devx_obj->obj;
+ break;
case MLX5DR_ACTION_TYP_TIR:
attr[i].type = MLX5DV_FLOW_ACTION_DEST_DEVX;
attr[i].obj = action->devx_obj;
@@ -1097,6 +1100,17 @@ static void mlx5dr_action_fill_stc_attr(struct
mlx5dr_action *action,
}
break;
case MLX5DR_ACTION_TYP_TBL:
+ attr->action_offset = MLX5DR_ACTION_OFFSET_HIT;
+ attr->dest_table_id = obj->id;
+ /* Only for unified FDB Rx case */
+ if (mlx5dr_context_cap_stc(action->ctx,
+ MLX5_IFC_STC_ACTION_TYPE_JUMP_FLOW_TABLE_FDB_RX_BIT_INDEX)
&&
+ action->dest_tbl.type == MLX5DR_TABLE_TYPE_FDB_RX)
+ attr->action_type =
MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FLOW_TABLE_FDB_RX;
+ else
+ attr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT;
+
+ break;
case MLX5DR_ACTION_TYP_DEST_ARRAY:
attr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT;
attr->action_offset = MLX5DR_ACTION_OFFSET_HIT;
@@ -1419,17 +1433,19 @@ mlx5dr_action_create_dest_table(struct mlx5dr_context
*ctx,
if (!action)
return NULL;
+ action->dest_tbl.type = tbl->type;
+
if (mlx5dr_action_is_root_flags(flags)) {
if (mlx5dr_context_shared_gvmi_used(ctx))
- action->devx_obj = tbl->local_ft->obj;
+ action->dest_tbl.devx_obj = tbl->local_ft;
else
- action->devx_obj = tbl->ft->obj;
+ action->dest_tbl.devx_obj = tbl->ft;
} else {
+ action->dest_tbl.devx_obj = tbl->ft;
+
ret = mlx5dr_action_create_stcs(action, tbl->ft);
if (ret)
goto free_action;
-
- action->devx_dest.devx_obj = tbl->ft;
}
return action;
@@ -2526,7 +2542,7 @@ mlx5dr_action_create_dest_array(struct mlx5dr_context
*ctx,
case MLX5DR_ACTION_TYP_TBL:
dest_list[i].destination_type =
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
- dest_list[i].destination_id =
dests[i].dest->devx_dest.devx_obj->
[PATCH 0/3] net/mlx5: support jump FDB Rx
Before FW introduced the JUMP_FDB_RX action feature, jump from FDB Tx to Rx is not allowed. JUMP_FDB_RX feature introduces the internal loopback for Tx case and allow the REG C0 C1 B be preserved as well. This series adds the jump from FDB Tx to FDB Rx support and allows RSS action in FDB domain rule when jump FDB Rx is supported. Suanming Mou (3): net/mlx5/hws: support jump FDB Rx net/mlx5: add jump FDB Rx flag net/mlx5: allow FDB RSS drivers/common/mlx5/mlx5_devx_cmds.c | 8 +++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h| 9 +++- drivers/net/mlx5/hws/mlx5dr_action.c | 26 +- drivers/net/mlx5/hws/mlx5dr_action.h | 4 drivers/net/mlx5/hws/mlx5dr_cmd.c | 9 drivers/net/mlx5/hws/mlx5dr_cmd.h | 2 ++ drivers/net/mlx5/hws/mlx5dr_context.c | 17 ++ drivers/net/mlx5/hws/mlx5dr_context.h | 2 ++ drivers/net/mlx5/linux/mlx5_os.c | 1 + drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_flow.c | 4 ++-- drivers/net/mlx5/mlx5_flow_dv.c | 32 ++- drivers/net/mlx5/mlx5_flow_hw.c | 27 +- 14 files changed, 114 insertions(+), 29 deletions(-) -- 2.34.1
[PATCH] net/nfp: fix get represetor wrong port stats
From: Long Wu
The 'ipackets'/'opackets' are used to record the number
of packets on represetor port received/sent. But the
code does not consider concurrent calculation of
'ipackets'/'opackets'. If multiple queues are calculated
'ipackets'/'opackets' simultaneously, it will result in
incorrect results.
The previous logic has recorded the number of packets on
each queue, therefore driver only needs to add the data of
all queues to obtain the data of the representor port.
Based on this, modify code to fix the issue.
Fixes: 636e133ec891 ("net/nfp: update Tx and Rx for multiple PF")
Fixes: 82a2c286f35a ("net/nfp: support xstats for flower firmware")
Cc: peng.zh...@corigine.com
Cc: chaoyong...@corigine.com
Cc: sta...@dpdk.org
Signed-off-by: Long Wu
---
drivers/net/nfp/flower/nfp_flower.c| 2 --
.../net/nfp/flower/nfp_flower_representor.c| 18 --
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/net/nfp/flower/nfp_flower.c
b/drivers/net/nfp/flower/nfp_flower.c
index f087d0dfdc..804ad494d5 100644
--- a/drivers/net/nfp/flower/nfp_flower.c
+++ b/drivers/net/nfp/flower/nfp_flower.c
@@ -238,7 +238,6 @@ nfp_flower_multiple_pf_recv_pkts(void *rx_queue,
for (i = 0; i < recv; i++)
data_len += rx_pkts[i]->data_len;
- repr->repr_stats.ipackets += recv;
repr->repr_stats.q_ipackets[rxq->qidx] += recv;
repr->repr_stats.q_ibytes[rxq->qidx] += data_len;
}
@@ -277,7 +276,6 @@ nfp_flower_multiple_pf_xmit_pkts(void *tx_queue,
for (i = 0; i < sent; i++)
data_len += tx_pkts[i]->data_len;
- repr->repr_stats.opackets += sent;
repr->repr_stats.q_opackets[txq->qidx] += sent;
repr->repr_stats.q_obytes[txq->qidx] += data_len;
}
diff --git a/drivers/net/nfp/flower/nfp_flower_representor.c
b/drivers/net/nfp/flower/nfp_flower_representor.c
index 9601aa5f96..e377d45e53 100644
--- a/drivers/net/nfp/flower/nfp_flower_representor.c
+++ b/drivers/net/nfp/flower/nfp_flower_representor.c
@@ -315,9 +315,25 @@ static int
nfp_flower_repr_stats_get(struct rte_eth_dev *ethdev,
struct rte_eth_stats *stats)
{
+ uint16_t i;
struct nfp_flower_representor *repr;
repr = ethdev->data->dev_private;
+
+ repr->repr_stats.ipackets = 0;
+ repr->repr_stats.ibytes = 0;
+ for (i = 0; i < ethdev->data->nb_rx_queues; i++) {
+ repr->repr_stats.ipackets += repr->repr_stats.q_ipackets[i];
+ repr->repr_stats.ibytes += repr->repr_stats.q_ibytes[i];
+ }
+
+ repr->repr_stats.opackets = 0;
+ repr->repr_stats.obytes = 0;
+ for (i = 0; i < ethdev->data->nb_tx_queues; i++) {
+ repr->repr_stats.opackets += repr->repr_stats.q_opackets[i];
+ repr->repr_stats.obytes += repr->repr_stats.q_obytes[i];
+ }
+
rte_memcpy(stats, &repr->repr_stats, sizeof(struct rte_eth_stats));
return 0;
@@ -385,7 +401,6 @@ nfp_flower_repr_rx_burst(void *rx_queue,
for (i = 0; i < total_dequeue; i++)
data_len += rx_pkts[i]->data_len;
- repr->repr_stats.ipackets += total_dequeue;
repr->repr_stats.q_ipackets[rxq->qidx] += total_dequeue;
repr->repr_stats.q_ibytes[rxq->qidx] += data_len;
}
@@ -434,7 +449,6 @@ nfp_flower_repr_tx_burst(void *tx_queue,
for (i = 0; i < sent; i++)
data_len += tx_pkts[i]->data_len;
- repr->repr_stats.opackets += sent;
repr->repr_stats.q_opackets[txq->qidx] += sent;
repr->repr_stats.q_obytes[txq->qidx] += data_len;
}
--
2.43.5
[PATCH 3/3] net/mlx5: allow FDB RSS
RSS can be used in FDB Rx rules when JUMP_FDB_RX action to allow
jump from FDB Tx to FDB Rx table.
Different with NIC RSS, FDB RSS will not do the internal implicit
metadata copy.
This commit enables the FDB RSS if JUMP_FDB_RX is supported.
Signed-off-by: Suanming Mou
---
drivers/net/mlx5/mlx5_flow.c| 4 ++--
drivers/net/mlx5/mlx5_flow_dv.c | 32 +---
drivers/net/mlx5/mlx5_flow_hw.c | 19 ++-
3 files changed, 33 insertions(+), 22 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 3fbe89a9d4..9c6a4f39fb 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1977,9 +1977,9 @@ mlx5_flow_validate_action_mark(struct rte_eth_dev *dev,
RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,
"mark action not supported for "
"egress");
- if (attr->transfer && mlx5_hws_active(dev))
+ if (attr->transfer && !mlx5_hws_active(dev))
return rte_flow_error_set(error, ENOTSUP,
- RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,
+ RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
NULL,
"non-template mark action not
supported for transfer");
return 0;
}
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 633c41e358..61d3101ce8 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -8939,21 +8939,23 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct
rte_flow_attr *attr,
RTE_FLOW_ERROR_TYPE_ACTION,
NULL,
"unsupported action MARK");
- if (action_flags & MLX5_FLOW_ACTION_QUEUE)
- return rte_flow_error_set(error, ENOTSUP,
- RTE_FLOW_ERROR_TYPE_ACTION,
- NULL,
- "unsupported action QUEUE");
- if (action_flags & MLX5_FLOW_ACTION_RSS)
- return rte_flow_error_set(error, ENOTSUP,
- RTE_FLOW_ERROR_TYPE_ACTION,
- NULL,
- "unsupported action RSS");
- if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
- return rte_flow_error_set(error, EINVAL,
- RTE_FLOW_ERROR_TYPE_ACTION,
- actions,
- "no fate action is found");
+ if (!priv->jump_fdb_rx_en) {
+ if (action_flags & MLX5_FLOW_ACTION_QUEUE)
+ return rte_flow_error_set(error, ENOTSUP,
+
RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "unsupported action
QUEUE");
+ if (action_flags & MLX5_FLOW_ACTION_RSS)
+ return rte_flow_error_set(error, ENOTSUP,
+
RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "unsupported action
RSS");
+ if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
+ return rte_flow_error_set(error, EINVAL,
+
RTE_FLOW_ERROR_TYPE_ACTION,
+ actions,
+ "no fate action is
found");
+ }
} else {
if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
return rte_flow_error_set(error, EINVAL,
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 83f55ed3e8..a063e5ac9c 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -7026,6 +7026,7 @@ mlx5_hw_validate_action_queue(struct rte_eth_dev *dev,
uint64_t action_flags,
struct rte_flow_error *error)
{
+ struct mlx5_priv *priv = dev->data->dev_private;
const struct rte_flow_action_queue *queue_mask = template_mask->conf;
const struct rte_flow_attr attr = {
.ingress = template_attr->ingress,
@@ -7034,7 +7035,7 @@ mlx5_hw_validate_action_queue(struct rte_eth_dev
[PATCH v3 0/3] Rx adapter API to add Rx queues in burst
This patch series introduces the rte_event_eth_rx_adapter_queues_add() API, allowing multiple Rx queues to be added to an Rx adapter in a single burst. This enhancement benefits applications that require bulk addition of Rx queues. To support this API, a new internal eventdev PMD operation for adding Rx queues has been implemented. The second patch in the series enables this operation for the CNXK PMD. Additionally, a unit test has been added to validate the API's functionality. RFC: - https://patches.dpdk.org/project/dpdk/patch/20241219073405.1724200-1-sthot...@marvell.com/ v2: - Updated documentation to explain the new API. v3: - Improved MULTI_EVENTQ check. Shijith Thotton (3): eventdev/eth_rx: add API to burst add queues to Rx adapter event/cnxk: enable PMD op to burst add queues to Rx adapter test/event: unit test to burst add Rx queues to adapter app/test/test_event_eth_rx_adapter.c | 86 .../eventdev/event_ethernet_rx_adapter.rst| 60 +- drivers/event/cnxk/cn10k_eventdev.c | 82 ++-- drivers/event/cnxk/cn20k_eventdev.c | 195 +- drivers/event/cnxk/cn9k_eventdev.c| 38 +++- drivers/event/cnxk/cnxk_eventdev.h| 8 +- drivers/event/cnxk/cnxk_eventdev_adptr.c | 102 + lib/eventdev/eventdev_pmd.h | 34 +++ lib/eventdev/eventdev_trace.h | 14 ++ lib/eventdev/eventdev_trace_points.c | 3 + lib/eventdev/rte_event_eth_rx_adapter.c | 160 ++ lib/eventdev/rte_event_eth_rx_adapter.h | 33 +++ lib/eventdev/version.map | 3 + 13 files changed, 691 insertions(+), 127 deletions(-) -- 2.25.1
[PATCH v3 1/3] eventdev/eth_rx: add API to burst add queues to Rx adapter
This patch introduces a new API, rte_event_eth_rx_adapter_queues_add(),
to allow bulk addition of multiple Rx queues in the eventdev Rx adapter.
The existing rte_event_eth_rx_adapter_queue_add() API supports adding
multiple queues by specifying rx_queue_id = -1, but it lacks the ability
to apply specific configurations to each of the added queues.
A new internal PMD operation, eventdev_eth_rx_adapter_queues_add_t, has
been introduced to enable this functionality. It takes an array of
receive queue IDs along with their corresponding queue configurations.
Signed-off-by: Shijith Thotton
---
.../eventdev/event_ethernet_rx_adapter.rst| 60 +--
lib/eventdev/eventdev_pmd.h | 34
lib/eventdev/eventdev_trace.h | 14 ++
lib/eventdev/eventdev_trace_points.c | 3 +
lib/eventdev/rte_event_eth_rx_adapter.c | 160 ++
lib/eventdev/rte_event_eth_rx_adapter.h | 33
lib/eventdev/version.map | 3 +
7 files changed, 297 insertions(+), 10 deletions(-)
diff --git a/doc/guides/prog_guide/eventdev/event_ethernet_rx_adapter.rst
b/doc/guides/prog_guide/eventdev/event_ethernet_rx_adapter.rst
index 2e68cca798..bae46cc7d7 100644
--- a/doc/guides/prog_guide/eventdev/event_ethernet_rx_adapter.rst
+++ b/doc/guides/prog_guide/eventdev/event_ethernet_rx_adapter.rst
@@ -96,16 +96,23 @@ when the adapter is created using the above-mentioned APIs.
Adding Rx Queues to the Adapter Instance
-Ethdev Rx queues are added to the instance using the
-``rte_event_eth_rx_adapter_queue_add()`` function. Configuration for the Rx
-queue is passed in using a ``struct rte_event_eth_rx_adapter_queue_conf``
-parameter. Event information for packets from this Rx queue is encoded in the
-``ev`` field of ``struct rte_event_eth_rx_adapter_queue_conf``. The
-servicing_weight member of the struct rte_event_eth_rx_adapter_queue_conf
-is the relative polling frequency of the Rx queue and is applicable when the
-adapter uses a service core function. The applications can configure queue
-event buffer size in ``struct
rte_event_eth_rx_adapter_queue_conf::event_buf_size``
-parameter.
+Ethdev Rx queues can be added to the instance using either the
+``rte_event_eth_rx_adapter_queue_add()`` function or
+``rte_event_eth_rx_adapter_queues_add()``. The former is used to add a single
Rx
+queue at a time, while the latter allows adding multiple Rx queues in a single
+call.
+
+Single Queue Addition
+^
+
+The ``rte_event_eth_rx_adapter_queue_add()`` API allows adding a single Rx
queue
+to the adapter instance. Configuration for the Rx queue is passed using a
+``struct rte_event_eth_rx_adapter_queue_conf`` parameter. Event information for
+packets from this Rx queue is encoded in the ``ev`` field of this struct. The
+``servicing_weight`` member of the struct determines the relative polling
+frequency of the Rx queue and is applicable when the adapter uses a service
core
+function. Applications can also configure the queue event buffer size using the
+``event_buf_size`` parameter in ``struct rte_event_eth_rx_adapter_queue_conf``.
.. code-block:: c
@@ -122,6 +129,39 @@ parameter.
eth_dev_id,
0, &queue_config);
+Bulk Queue Addition
+^^^
+
+The ``rte_event_eth_rx_adapter_queues_add()`` API allows the addition of
+multiple Rx queues in a single call. While
+``rte_event_eth_rx_adapter_queue_add()`` supports adding multiple queues by
+specifying ``rx_queue_id = -1``, it does not allow applying specific
+configurations to each queue individually. The
+``rte_event_eth_rx_adapter_queues_add()`` API accepts an array of receive queue
+IDs along with their corresponding configurations, enabling control over each
Rx
+queue's settings.
+
+.. code-block:: c
+
+struct rte_event_eth_rx_adapter_queue_conf queue_config[nb_rx_queues];
+int rx_queue_id[nb_rx_queues];
+
+for (int i = 0; i < nb_rx_queues; i++) {
+rx_queue_id[i] = i;
+queue_config[i].rx_queue_flags = 0;
+queue_config[i].ev.queue_id = i;
+queue_config[i].ev.sched_type = RTE_SCHED_TYPE_ATOMIC;
+queue_config[i].ev.priority = 0;
+queue_config[i].servicing_weight = 1;
+queue_config[i].event_buf_size = 1024;
+}
+
+err = rte_event_eth_rx_adapter_queues_add(id,
+ eth_dev_id,
+ rx_queue_id,
+ queue_config,
+ nb_rx_queues);
+
Querying Adapter Capabilities
~
diff --git a/lib/eventdev/eventdev_pmd.h b/lib/eventdev/eventdev_pmd.h
index 36148f8d86..ad13ba5b03 100644
--- a/lib/eventdev/eventdev_pmd.h
+
[PATCH v3 2/3] event/cnxk: enable PMD op to burst add queues to Rx adapter
Implemented PMD support for the eventdev PMD operation to burst add
queues to the Rx adapter.
Signed-off-by: Shijith Thotton
---
drivers/event/cnxk/cn10k_eventdev.c | 82 --
drivers/event/cnxk/cn20k_eventdev.c | 195 ---
drivers/event/cnxk/cn9k_eventdev.c | 38 -
drivers/event/cnxk/cnxk_eventdev.h | 8 +-
drivers/event/cnxk/cnxk_eventdev_adptr.c | 102 +++-
5 files changed, 308 insertions(+), 117 deletions(-)
diff --git a/drivers/event/cnxk/cn10k_eventdev.c
b/drivers/event/cnxk/cn10k_eventdev.c
index f2e591f547..3832eb7e00 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -685,6 +685,22 @@ cn10k_sso_rx_offload_cb(uint16_t port_id, uint64_t flags)
eventdev_fops_update(event_dev);
}
+static int
+cn10k_sso_configure_queue_stash_default(struct cnxk_sso_evdev *dev, uint16_t
hwgrp)
+{
+ struct roc_sso_hwgrp_stash stash;
+ int rc;
+
+ stash.hwgrp = hwgrp;
+ stash.stash_offset = CN10K_SSO_DEFAULT_STASH_OFFSET;
+ stash.stash_count = CN10K_SSO_DEFAULT_STASH_LENGTH;
+ rc = roc_sso_hwgrp_stash_config(&dev->sso, &stash, 1);
+ if (rc)
+ plt_warn("failed to configure HWGRP WQE stashing rc = %d", rc);
+
+ return rc;
+}
+
static int
cn10k_sso_rx_adapter_queue_add(
const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
@@ -693,8 +709,8 @@ cn10k_sso_rx_adapter_queue_add(
{
struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
- struct roc_sso_hwgrp_stash stash;
struct cn10k_eth_rxq *rxq;
+ uint16_t nb_rx_queues;
void *lookup_mem;
int rc;
@@ -702,8 +718,42 @@ cn10k_sso_rx_adapter_queue_add(
if (rc)
return -EINVAL;
- rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
- queue_conf);
+ nb_rx_queues = rx_queue_id == -1 ? 0 : 1;
+ rc = cnxk_sso_rx_adapter_queues_add(event_dev, eth_dev, &rx_queue_id,
queue_conf,
+ nb_rx_queues);
+ if (rc)
+ return -EINVAL;
+
+ cnxk_eth_dev->cnxk_sso_ptp_tstamp_cb = cn10k_sso_tstamp_hdl_update;
+ cnxk_eth_dev->evdev_priv = (struct rte_eventdev *)(uintptr_t)event_dev;
+
+ rxq = eth_dev->data->rx_queues[0];
+ lookup_mem = rxq->lookup_mem;
+ cn10k_sso_set_priv_mem(event_dev, lookup_mem);
+ cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
+ if (roc_feature_sso_has_stash() && dev->nb_event_ports > 1)
+ rc = cn10k_sso_configure_queue_stash_default(dev,
queue_conf->ev.queue_id);
+
+ return rc;
+}
+static int
+cn10k_sso_rx_adapter_queues_add(const struct rte_eventdev *event_dev,
+ const struct rte_eth_dev *eth_dev, int32_t
rx_queue_id[],
+ const struct
rte_event_eth_rx_adapter_queue_conf queue_conf[],
+ uint16_t nb_rx_queues)
+{
+ struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
+ struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+ struct cn10k_eth_rxq *rxq;
+ void *lookup_mem;
+ int rc, i;
+
+ rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
+ if (rc)
+ return -EINVAL;
+
+ rc = cnxk_sso_rx_adapter_queues_add(event_dev, eth_dev, rx_queue_id,
queue_conf,
+ nb_rx_queues);
if (rc)
return -EINVAL;
@@ -715,15 +765,24 @@ cn10k_sso_rx_adapter_queue_add(
cn10k_sso_set_priv_mem(event_dev, lookup_mem);
cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
if (roc_feature_sso_has_stash() && dev->nb_event_ports > 1) {
- stash.hwgrp = queue_conf->ev.queue_id;
- stash.stash_offset = CN10K_SSO_DEFAULT_STASH_OFFSET;
- stash.stash_count = CN10K_SSO_DEFAULT_STASH_LENGTH;
- rc = roc_sso_hwgrp_stash_config(&dev->sso, &stash, 1);
- if (rc < 0)
- plt_warn("failed to configure HWGRP WQE stashing rc =
%d", rc);
+ uint16_t hwgrp = dev->sso.max_hwgrp;
+
+ if (nb_rx_queues == 0)
+ rc = cn10k_sso_configure_queue_stash_default(dev,
+
queue_conf[0].ev.queue_id);
+
+ for (i = 0; i < nb_rx_queues; i++) {
+ if (hwgrp == queue_conf[i].ev.queue_id)
+ continue;
+
+ hwgrp = queue_conf[i].ev.queue_id;
+ rc = cn10k_sso_configure_queue_stash_default(dev,
hwgrp);
+ if (rc < 0)
+ break;
+ }
}
[PATCH v3 3/3] test/event: unit test to burst add Rx queues to adapter
Added unit test for adding queues to Rx adapter in bursts using
rte_event_eth_rx_adapter_queues_add().
Signed-off-by: Shijith Thotton
---
app/test/test_event_eth_rx_adapter.c | 86
1 file changed, 86 insertions(+)
diff --git a/app/test/test_event_eth_rx_adapter.c
b/app/test/test_event_eth_rx_adapter.c
index 0233c87779..92b7ff6d99 100644
--- a/app/test/test_event_eth_rx_adapter.c
+++ b/app/test/test_event_eth_rx_adapter.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#ifdef RTE_EXEC_ENV_WINDOWS
static int
@@ -819,6 +820,89 @@ adapter_queue_add_del(void)
return TEST_SUCCESS;
}
+static int
+adapter_queues_add_del(void)
+{
+ struct rte_event_eth_rx_adapter_queue_conf *queue_conf;
+ struct rte_event_dev_info event_dev_info;
+ struct rte_eth_dev_info dev_info;
+ uint16_t i, max_rx_queues;
+ int32_t *rx_queue_ids;
+ struct rte_event ev;
+ uint32_t cap;
+ int err;
+
+ err = rte_event_eth_rx_adapter_caps_get(TEST_DEV_ID, TEST_ETHDEV_ID,
&cap);
+ TEST_ASSERT(err == 0, "Expected 0 got %d", err);
+
+ err = rte_eth_dev_info_get(TEST_ETHDEV_ID, &dev_info);
+ TEST_ASSERT(err == 0, "Expected 0 got %d", err);
+
+ max_rx_queues = RTE_MIN(dev_info.max_rx_queues, MAX_NUM_RX_QUEUE);
+
+ err = rte_event_dev_info_get(TEST_DEV_ID, &event_dev_info);
+ TEST_ASSERT(err == 0, "Expected 0 got %d", err);
+
+ queue_conf = rte_zmalloc(NULL, sizeof(*queue_conf) * max_rx_queues, 0);
+ TEST_ASSERT(queue_conf != NULL, "Failed to allocate memory");
+
+ rx_queue_ids = rte_zmalloc(NULL, sizeof(*rx_queue_ids) * max_rx_queues,
0);
+ TEST_ASSERT(rx_queue_ids != NULL, "Failed to allocate memory");
+
+ ev.sched_type = RTE_SCHED_TYPE_ATOMIC;
+ for (i = 0; i < max_rx_queues; i++) {
+ rx_queue_ids[i] = i;
+ ev.queue_id = i % event_dev_info.max_event_queues;
+ if (cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID) {
+ ev.flow_id = 1;
+ queue_conf[i].rx_queue_flags =
+ RTE_EVENT_ETH_RX_ADAPTER_QUEUE_FLOW_ID_VALID;
+ }
+ queue_conf[i].ev = ev;
+ queue_conf[i].servicing_weight = 1;
+ }
+
+ err = rte_event_eth_rx_adapter_queues_add(TEST_INST_ID,
+ rte_eth_dev_count_total(),
+ rx_queue_ids, queue_conf, 0);
+ TEST_ASSERT(err == -EINVAL, "Expected -EINVAL got %d", err);
+
+ err = rte_event_eth_rx_adapter_queues_add(TEST_INST_ID + 1,
TEST_ETHDEV_ID,
+ NULL, queue_conf, 0);
+ TEST_ASSERT(err == -EINVAL, "Expected -EINVAL got %d", err);
+
+ err = rte_event_eth_rx_adapter_queues_add(TEST_INST_ID, TEST_ETHDEV_ID,
+ rx_queue_ids, queue_conf, 1);
+ TEST_ASSERT(err == 0, "Expected 0 got %d", err);
+
+ err = rte_event_eth_rx_adapter_queue_del(TEST_INST_ID, TEST_ETHDEV_ID,
0);
+ TEST_ASSERT(err == 0, "Expected 0 got %d", err);
+
+ if (cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ) {
+ err = rte_event_eth_rx_adapter_queues_add(
+ TEST_INST_ID, TEST_ETHDEV_ID, rx_queue_ids, queue_conf,
+ max_rx_queues);
+ TEST_ASSERT(err == 0, "Expected 0 got %d", err);
+
+ err = rte_event_eth_rx_adapter_queue_del(TEST_INST_ID,
+TEST_ETHDEV_ID, -1);
+ TEST_ASSERT(err == 0, "Expected 0 got %d", err);
+ } else {
+ err = rte_event_eth_rx_adapter_queues_add(
+ TEST_INST_ID, TEST_ETHDEV_ID, NULL, queue_conf, 0);
+ TEST_ASSERT(err == 0, "Expected 0 got %d", err);
+
+ err = rte_event_eth_rx_adapter_queue_del(TEST_INST_ID,
+TEST_ETHDEV_ID, -1);
+ TEST_ASSERT(err == 0, "Expected 0 got %d", err);
+ }
+
+ rte_free(rx_queue_ids);
+ rte_free(queue_conf);
+
+ return TEST_SUCCESS;
+}
+
static int
adapter_multi_eth_add_del(void)
{
@@ -1423,6 +1507,8 @@ static struct unit_test_suite event_eth_rx_tests = {
TEST_CASE_ST(NULL, NULL, adapter_create_free_with_params),
TEST_CASE_ST(adapter_create, adapter_free,
adapter_queue_add_del),
+ TEST_CASE_ST(adapter_create, adapter_free,
+ adapter_queues_add_del),
TEST_CASE_ST(adapter_create, adapter_free,
adapter_multi_eth_add_del),
TEST_CASE_ST(adapter_create, adapter_free, adapter_start_stop),
--
2.25.1
Re: [PATCH 1/8] net/mlx5/hws: introduce capability for unified mode
Hi, From: Hamdan Igbaria Sent: Sunday, February 16, 2025 1:04 PM To: Hamdan Agbariya; Slava Ovsiienko; NBU-Contact-Thomas Monjalon (EXTERNAL); Suanming Mou; Dariusz Sosnowski; Bing Zhao; Ori Kam; Matan Azrad Cc: dev@dpdk.org; Erez Shitrit Subject: [PATCH 1/8] net/mlx5/hws: introduce capability for unified mode From: Erez Shitrit Till now the FDB processing domain is split into two mutually exclusive sub domains FDB_RX and FDB_TX. Packets originating from the Uplink(s) are processed in the FDB_RX sub domain, while packets originating from all other Vports are processed in the FDB_TX sub domain. Now adding new sub domain: FDB_UNIFIED which can process packets originated by any VPORT / WIRE. This new domain will process actions only that allowed on both RX and TX domains. That way the user can define specifically the domain he wants the packet to be processed, whenever it is RX/TX only he will use FDB_RX/TX, or whenever it can by FDB_UNIFIED. Signed-off-by: Erez Shitrit Signed-off-by: Hamdan Igbaria Acked-by: Matan Azrad Series applied to next-net-mlx, Kindest regards, Raslan Darawsheh
Re: [PATCH] power: use hugepage memory for queue list entry structure
在 2025/2/20 17:41, Konstantin Ananyev 写道:
Hi
Hi all,
Kindly ping for review.
在 2024/12/19 15:53, Huisong Li 写道:
The queue_list_entry structure data is used in rx_callback of io path
when enable PMD Power Management. However its memory is currently from
normal heap memory. For better performance, use hugepage memory to
replace it.
Make sense to me.
Acked-by: Konstantin Ananyev
I suppose it would also help if you can provide some numbers:
i.e.: how much exactly it is 'better'?
Did you see any changes in throughput/latency numbers, etc.
This patch is just from my knowledge of DPDK.
I don't what is the good way to evaluate the performance of l3fwd-power.
But I did a test for this after you said.
I found that the throughput of using malloc is better than rte_malloc in
continuous packet flow case.😮
Can you test this patch on your platform?
Signed-off-by: Huisong Li
---
lib/power/rte_power_pmd_mgmt.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/lib/power/rte_power_pmd_mgmt.c b/lib/power/rte_power_pmd_mgmt.c
index a2fff3b765..c7bf57a910 100644
--- a/lib/power/rte_power_pmd_mgmt.c
+++ b/lib/power/rte_power_pmd_mgmt.c
@@ -97,7 +97,7 @@ queue_list_find(const struct pmd_core_cfg *cfg, const union
queue *q)
}
static int
-queue_list_add(struct pmd_core_cfg *cfg, const union queue *q)
+queue_list_add(struct pmd_core_cfg *cfg, const union queue *q, unsigned int
lcore_id)
{
struct queue_list_entry *qle;
@@ -105,10 +105,10 @@ queue_list_add(struct pmd_core_cfg *cfg, const union
queue *q)
if (queue_list_find(cfg, q) != NULL)
return -EEXIST;
- qle = malloc(sizeof(*qle));
+ qle = rte_zmalloc_socket(NULL, sizeof(*qle), RTE_CACHE_LINE_SIZE,
+rte_lcore_to_socket_id(lcore_id));
if (qle == NULL)
return -ENOMEM;
- memset(qle, 0, sizeof(*qle));
queue_copy(&qle->queue, q);
TAILQ_INSERT_TAIL(&cfg->head, qle, next);
@@ -570,7 +570,7 @@ rte_power_ethdev_pmgmt_queue_enable(unsigned int lcore_id,
uint16_t port_id,
goto end;
}
/* add this queue to the list */
- ret = queue_list_add(lcore_cfg, &qdata);
+ ret = queue_list_add(lcore_cfg, &qdata, lcore_id);
if (ret < 0) {
POWER_LOG(DEBUG, "Failed to add queue to list: %s",
strerror(-ret));
@@ -664,7 +664,7 @@ rte_power_ethdev_pmgmt_queue_disable(unsigned int lcore_id,
* callbacks can be freed. we're intentionally casting away const-ness.
*/
rte_free((void *)(uintptr_t)queue_cfg->cb);
- free(queue_cfg);
+ rte_free(queue_cfg);
return 0;
}
[PATCH v2 01/33] net/cnxk: allow duplicate SPI in outbound IPsec
Since outbound IPsec is not really dependent on SPI,
allow duplicate SPI in outbound inline IPsec sessions.
Signed-off-by: Nithin Dabilpuram
---
v2:
- Rebased on top of latest code
- Fixed build issue with 26/33
- Updated release notes
drivers/net/cnxk/cn10k_ethdev_sec.c | 14 +++---
drivers/net/cnxk/cn9k_ethdev_sec.c | 14 +++---
drivers/net/cnxk/cnxk_ethdev.h | 4 ++--
drivers/net/cnxk/cnxk_ethdev_sec.c | 8 ++--
4 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 6acab8afa0..41dfba36d3 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -793,13 +793,6 @@ cn10k_eth_sec_session_create(void *device,
inbound = !!(ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS);
inl_dev = !!dev->inb.inl_dev;
- /* Search if a session already exits */
- if (cnxk_eth_sec_sess_get_by_spi(dev, ipsec->spi, inbound)) {
- plt_err("%s SA with SPI %u already in use",
- inbound ? "Inbound" : "Outbound", ipsec->spi);
- return -EEXIST;
- }
-
memset(eth_sec, 0, sizeof(struct cnxk_eth_sec_sess));
sess_priv.u64 = 0;
@@ -821,6 +814,13 @@ cn10k_eth_sec_session_create(void *device,
spi_mask = roc_nix_inl_inb_spi_range(nix, inl_dev, NULL, NULL);
+ /* Search if a session already exits */
+ if (cnxk_eth_sec_sess_get_by_sa_idx(dev, ipsec->spi & spi_mask,
true)) {
+ plt_err("Inbound SA with SPI/SA index %u already in
use", ipsec->spi);
+ rc = -EEXIST;
+ goto err;
+ }
+
/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE */
sa = roc_nix_inl_inb_sa_get(nix, inl_dev, ipsec->spi);
if (!sa && dev->inb.inl_dev) {
diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c
b/drivers/net/cnxk/cn9k_ethdev_sec.c
index 390853c728..5e13dc862e 100644
--- a/drivers/net/cnxk/cn9k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn9k_ethdev_sec.c
@@ -604,13 +604,6 @@ cn9k_eth_sec_session_create(void *device,
crypto = conf->crypto_xform;
inbound = !!(ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS);
- /* Search if a session already exists */
- if (cnxk_eth_sec_sess_get_by_spi(dev, ipsec->spi, inbound)) {
- plt_err("%s SA with SPI %u already in use",
- inbound ? "Inbound" : "Outbound", ipsec->spi);
- return -EEXIST;
- }
-
lock = inbound ? &dev->inb.lock : &dev->outb.lock;
rte_spinlock_lock(lock);
@@ -633,6 +626,13 @@ cn9k_eth_sec_session_create(void *device,
spi_mask = roc_nix_inl_inb_spi_range(nix, false, NULL, NULL);
+ /* Search if a session already exits */
+ if (cnxk_eth_sec_sess_get_by_sa_idx(dev, ipsec->spi & spi_mask,
true)) {
+ plt_err("Inbound SA with SPI/SA index %u already in
use", ipsec->spi);
+ rc = -EEXIST;
+ goto err;
+ }
+
/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE. Assume no inline
* device always for CN9K.
*/
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 350adc1161..eae5336a9b 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -729,8 +729,8 @@ typedef void (*cnxk_ethdev_rx_offload_cb_t)(uint16_t
port_id, uint64_t flags);
__rte_internal
void cnxk_ethdev_rx_offload_cb_register(cnxk_ethdev_rx_offload_cb_t cb);
-struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev
*dev,
- uint32_t spi, bool inb);
+struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_sa_idx(struct cnxk_eth_dev
*dev,
+ uint32_t sa_idx, bool
inb);
struct cnxk_eth_sec_sess *
cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,
struct rte_security_session *sess);
diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c
b/drivers/net/cnxk/cnxk_ethdev_sec.c
index ef75e5f0f1..2c649c985a 100644
--- a/drivers/net/cnxk/cnxk_ethdev_sec.c
+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c
@@ -231,6 +231,10 @@ cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev,
uint32_t *idx_p,
if (spi > dev->outb.max_sa)
return -ENOTSUP;
idx = spi;
+ if (!plt_bitmap_get(dev->outb.sa_bmap, idx)) {
+ plt_err("Outbound SA index %u already in use", idx);
+ return -EEXIST;
+ }
} else {
/* Scan bitmap to get the free sa index */
rc = plt_bitmap_scan(dev->outb.sa_bmap, &pos, &slab);
@@ -265,14 +269,14 @@ cnxk_eth_outb_sa_idx_put(stru
[PATCH v2 02/33] common/cnxk: remove unused param in SA init
From: Anoob Joseph
Remove unused param in SA init.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/cnxk_security.c | 5 ++---
drivers/common/cnxk/cnxk_security.h | 3 +--
drivers/common/cnxk/roc_ie_ot.c | 4 +---
drivers/common/cnxk/roc_ie_ot.h | 3 +--
drivers/common/cnxk/roc_nix_inl.c | 2 +-
drivers/common/cnxk/roc_nix_inl_dev.c | 2 +-
drivers/crypto/cnxk/cn10k_ipsec.c | 5 ++---
drivers/net/cnxk/cn10k_ethdev_sec.c | 8 +++-
8 files changed, 12 insertions(+), 20 deletions(-)
diff --git a/drivers/common/cnxk/cnxk_security.c
b/drivers/common/cnxk/cnxk_security.c
index 9446c14ac8..8953e901a1 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -304,8 +304,7 @@ ot_ipsec_inb_tunnel_hdr_fill(struct roc_ot_ipsec_inb_sa *sa,
int
cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
struct rte_security_ipsec_xform *ipsec_xfrm,
- struct rte_crypto_sym_xform *crypto_xfrm,
- bool is_inline)
+ struct rte_crypto_sym_xform *crypto_xfrm)
{
uint16_t sport = 4500, dport = 4500;
union roc_ot_ipsec_sa_word2 w2;
@@ -314,7 +313,7 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
int rc;
/* Initialize the SA */
- roc_ot_ipsec_inb_sa_init(sa, is_inline);
+ roc_ot_ipsec_inb_sa_init(sa);
w2.u64 = 0;
rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->w8.s.salt,
diff --git a/drivers/common/cnxk/cnxk_security.h
b/drivers/common/cnxk/cnxk_security.h
index 19eb9bb03d..cd78b283f0 100644
--- a/drivers/common/cnxk/cnxk_security.h
+++ b/drivers/common/cnxk/cnxk_security.h
@@ -39,8 +39,7 @@ cnxk_ipsec_outb_roundup_byte(enum rte_crypto_cipher_algorithm
c_algo,
int __roc_api
cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
struct rte_security_ipsec_xform *ipsec_xfrm,
- struct rte_crypto_sym_xform *crypto_xfrm,
- bool is_inline);
+ struct rte_crypto_sym_xform *crypto_xfrm);
int __roc_api
cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
struct rte_security_ipsec_xform *ipsec_xfrm,
diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c
index 1b436dba72..b906834672 100644
--- a/drivers/common/cnxk/roc_ie_ot.c
+++ b/drivers/common/cnxk/roc_ie_ot.c
@@ -6,7 +6,7 @@
#include "roc_priv.h"
void
-roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline)
+roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa)
{
size_t offset;
@@ -18,8 +18,6 @@ roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool
is_inline)
sa->w0.s.et_ovrwr = 1;
sa->w2.s.l3hdr_on_err = 1;
- PLT_SET_USED(is_inline);
-
offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index 1420e3d586..26616be901 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -554,7 +554,6 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa,
ctx) ==
#define ROC_OT_IPSEC_SA_SZ_MAX \
(PLT_MAX(sizeof(struct roc_ot_ipsec_inb_sa), sizeof(struct
roc_ot_ipsec_outb_sa)))
-void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa,
- bool is_inline);
+void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa);
void __roc_api roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa);
#endif /* __ROC_IE_OT_H__ */
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 5b79bc2266..88d5a678b1 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -423,7 +423,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
if (roc_model_is_cn10k()) {
for (i = 0; i < max_sa; i++) {
sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
- roc_ot_ipsec_inb_sa_init(sa, true);
+ roc_ot_ipsec_inb_sa_init(sa);
}
}
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index ffe6eef81f..d26cbee0cc 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -440,7 +440,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
for (i = 0; i < max_sa; i++) {
sa = ((uint8_t *)inl_dev->inb_sa_base) +
(i * inb_sa_sz);
- roc_ot_ipsec_inb_sa_init(sa, true);
+ roc_ot_ipsec_inb_sa_init(sa);
}
}
/* Setup device specific inb SA table */
diff --git
[PATCH v2 04/33] common/cnxk: move CTX defines to common
From: Anoob Joseph
CTX defines are common for all cases using CPT CTX.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/cnxk_security.h | 1 +
drivers/common/cnxk/roc_cpt.h | 16
drivers/common/cnxk/roc_ie_ot.h | 16
drivers/net/cnxk/cn10k_rxtx.h | 4 ++--
drivers/net/cnxk/cn20k_rxtx.h | 4 ++--
5 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/common/cnxk/cnxk_security.h
b/drivers/common/cnxk/cnxk_security.h
index cd78b283f0..8ede6c88a3 100644
--- a/drivers/common/cnxk/cnxk_security.h
+++ b/drivers/common/cnxk/cnxk_security.h
@@ -7,6 +7,7 @@
#include
#include
+#include "roc_cpt.h"
#include "roc_ie_on.h"
#include "roc_ie_ot.h"
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 0b9c933925..70129531eb 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -104,6 +104,22 @@
#define ROC_CPT_RES_ALIGN 16
+/* Context units in bytes */
+#define ROC_CTX_UNIT_8B 8
+#define ROC_CTX_UNIT_128B128
+#define ROC_CTX_MAX_CKEY_LEN 32
+#define ROC_CTX_MAX_OPAD_IPAD_LEN 128
+
+/* Anti reply window size supported */
+#define ROC_AR_WIN_SIZE_MIN 64
+#define ROC_AR_WIN_SIZE_MAX 4096
+#define ROC_LOG_MIN_AR_WIN_SIZE_M1 5
+
+/* u64 array size to fit anti replay window bits */
+#define ROC_AR_WINBITS_SZ
\
+ (PLT_ALIGN_CEIL(ROC_AR_WIN_SIZE_MAX, BITS_PER_LONG_LONG) / \
+BITS_PER_LONG_LONG)
+
enum {
ROC_CPT_REVISION_ID_83XX = 0,
ROC_CPT_REVISION_ID_96XX_B0 = 1,
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index 26616be901..932d3b6131 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -155,22 +155,6 @@ roc_ie_ot_ucc_is_success(uint8_t ucc)
return (ucc >= uc_base);
}
-/* Context units in bytes */
-#define ROC_CTX_UNIT_8B 8
-#define ROC_CTX_UNIT_128B128
-#define ROC_CTX_MAX_CKEY_LEN 32
-#define ROC_CTX_MAX_OPAD_IPAD_LEN 128
-
-/* Anti reply window size supported */
-#define ROC_AR_WIN_SIZE_MIN 64
-#define ROC_AR_WIN_SIZE_MAX 4096
-#define ROC_LOG_MIN_AR_WIN_SIZE_M1 5
-
-/* u64 array size to fit anti replay window bits */
-#define ROC_AR_WINBITS_SZ
\
- (PLT_ALIGN_CEIL(ROC_AR_WIN_SIZE_MAX, BITS_PER_LONG_LONG) / \
-BITS_PER_LONG_LONG)
-
#define ROC_IPSEC_ERR_RING_MAX_ENTRY 65536
union roc_ot_ipsec_err_ring_head {
diff --git a/drivers/net/cnxk/cn10k_rxtx.h b/drivers/net/cnxk/cn10k_rxtx.h
index 9861aa6571..98f9e2efa3 100644
--- a/drivers/net/cnxk/cn10k_rxtx.h
+++ b/drivers/net/cnxk/cn10k_rxtx.h
@@ -27,8 +27,6 @@
#include "hw/npc.h"
#include "hw/ssow.h"
-#include "roc_ie_ot.h"
-
/* NPA */
#include "roc_npa_dp.h"
@@ -38,6 +36,8 @@
/* CPT */
#include "roc_cpt.h"
+#include "roc_ie_ot.h"
+
/* NIX Inline dev */
#include "roc_nix_inl_dp.h"
diff --git a/drivers/net/cnxk/cn20k_rxtx.h b/drivers/net/cnxk/cn20k_rxtx.h
index 4a8f194eb8..7aa06444e2 100644
--- a/drivers/net/cnxk/cn20k_rxtx.h
+++ b/drivers/net/cnxk/cn20k_rxtx.h
@@ -27,8 +27,6 @@
#include "hw/npc.h"
#include "hw/ssow.h"
-#include "roc_ie_ot.h"
-
/* NPA */
#include "roc_npa_dp.h"
@@ -38,6 +36,8 @@
/* CPT */
#include "roc_cpt.h"
+#include "roc_ie_ot.h"
+
/* NIX Inline dev */
#include "roc_nix_inl_dp.h"
--
2.34.1
[PATCH v2 03/33] net/cnxk: remove unnecessary delay on stats read
Remove unnecessary delay on security stats read as application is expected to poll if stats are not updated as expected. It is expected that there would be a delay in stats to show up like any other ethdev stats get API. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_ethdev_sec.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 3f81913d41..68691d2bfe 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -1243,7 +1243,6 @@ cn10k_eth_sec_session_stats_get(void *device, struct rte_security_session *sess, ROC_NIX_INL_SA_OP_FLUSH); if (rc) return -EINVAL; - rte_delay_ms(1); stats->protocol = RTE_SECURITY_PROTOCOL_IPSEC; -- 2.34.1
[PATCH v2 05/33] common/cnxk: add cn20k CPT result struct
From: Anoob Joseph
CPT result structure is same as in cn10k. Add entry for cn20k.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/hw/cpt.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index 47df3fbf9f..b308a18f0d 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -289,6 +289,16 @@ struct cpt_inst_s {
};
union cpt_res_s {
+ struct cpt_cn20k_res_s {
+ uint64_t compcode : 7;
+ uint64_t doneint : 1;
+ uint64_t uc_compcode : 8;
+ uint64_t rlen : 16;
+ uint64_t spi : 32;
+
+ uint64_t esn;
+ } cn20k;
+
struct cpt_cn10k_res_s {
uint64_t compcode : 7;
uint64_t doneint : 1;
--
2.34.1
[PATCH v2 06/33] common/cnxk: enable IE with cn9k and cn10k only
From: Anoob Joseph
IE engines are present only with cn9k and cn10k.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/roc_cpt.c | 43 +++
drivers/common/cnxk/roc_cpt.h | 3 +++
2 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 90433e2390..88f6044e60 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -624,9 +624,13 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf,
bool rxc_ena, uint16_t
for (i = 0; i < nb_lf; i++)
cpt->lf_blkaddr[i] = blkaddr[blknum];
- eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
-(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |
-(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);
+ if (roc_cpt_has_ie_engines())
+ eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
+(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |
+(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);
+ else
+ eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
+(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]);
if (roc_errata_cpt_has_ctx_fetch_issue()) {
ctx_ilen_valid = true;
@@ -1180,12 +1184,13 @@ int
roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr,
uint16_t sa_len)
{
- uintptr_t lmt_base = lf->lmt_base;
union cpt_res_s res, *hw_res;
uint64_t lmt_arg, io_addr;
struct cpt_inst_s *inst;
+ uintptr_t lmt_base;
uint16_t lmt_id;
uint64_t *dptr;
+ uint8_t egrp;
int i;
if (!plt_is_aligned(sa_cptr, 128)) {
@@ -1193,6 +1198,25 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr,
void *sa_cptr,
return -EINVAL;
}
+ if (lf == NULL) {
+ plt_err("Invalid CPT LF");
+ return -EINVAL;
+ }
+
+ if (lf->roc_cpt == NULL) {
+ if (roc_cpt_has_ie_engines())
+ egrp = ROC_CPT_DFLT_ENG_GRP_SE_IE;
+ else
+ egrp = ROC_CPT_DFLT_ENG_GRP_SE;
+ } else {
+ if (roc_cpt_has_ie_engines())
+ egrp = lf->roc_cpt->eng_grp[CPT_ENG_TYPE_IE];
+ else
+ egrp = lf->roc_cpt->eng_grp[CPT_ENG_TYPE_SE];
+ }
+
+ lmt_base = lf->lmt_base;
+
/* Use this lcore's LMT line as no one else is using it */
ROC_LMT_BASE_ID_GET(lmt_base, lmt_id);
inst = (struct cpt_inst_s *)lmt_base;
@@ -1225,7 +1249,7 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr,
void *sa_cptr,
inst->w4.s.opcode_minor = ROC_IE_OT_MINOR_OP_WRITE_SA;
inst->w7.s.cptr = (uint64_t)sa_cptr;
inst->w7.s.ctx_val = 1;
- inst->w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE_IE;
+ inst->w7.s.egrp = egrp;
lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;
io_addr = lf->io_addr | ROC_CN10K_CPT_INST_DW_M1 << 4;
@@ -1276,3 +1300,12 @@ roc_cpt_int_misc_cb_unregister(roc_cpt_int_misc_cb_t cb,
void *args)
int_cb.cb_args = NULL;
return 0;
}
+
+bool
+roc_cpt_has_ie_engines(void)
+{
+ if (roc_model_is_cn9k() || roc_model_is_cn10k())
+ return true;
+
+ return false;
+}
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 70129531eb..c8cf9354da 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -226,4 +226,7 @@ int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void
*sa_dptr, void *sa_c
void __roc_api roc_cpt_int_misc_cb_register(roc_cpt_int_misc_cb_t cb, void
*args);
int __roc_api roc_cpt_int_misc_cb_unregister(roc_cpt_int_misc_cb_t cb, void
*args);
+
+bool roc_cpt_has_ie_engines(void);
+
#endif /* _ROC_CPT_H_ */
--
2.34.1
[PATCH v2 08/33] common/cnxk: add CPT cn20k device enumeration
From: Anoob Joseph Add CPT cn20k device enumeration. Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_constants.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h index 67cd74b28a..ac492651de 100644 --- a/drivers/common/cnxk/roc_constants.h +++ b/drivers/common/cnxk/roc_constants.h @@ -55,6 +55,8 @@ #define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE #define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2 #define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3 +#define PCI_DEVID_CN20K_RVU_CPT_PF 0xA0F2 +#define PCI_DEVID_CN20K_RVU_CPT_VF 0xA0F3 #define PCI_DEVID_CN10K_ML_PF 0xA092 -- 2.34.1
[PATCH v2 07/33] common/cnxk: make special handling only for 9k
From: Anoob Joseph 9k would need special handling compared to 10k & 20k. Update the check to reflect the same. Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_cpt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 88f6044e60..a6d2d83f76 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -930,10 +930,10 @@ roc_cpt_iq_reset(struct roc_cpt_lf *lf) lf_ctl.s.ena = 1; plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL); - if (roc_model_is_cn10k()) - cpt_10k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE); - else + if (roc_model_is_cn9k()) cpt_9k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE); + else + cpt_10k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE); plt_read64(lf->rbase + CPT_LF_INPROG); plt_delay_us(2); -- 2.34.1
[PATCH v2 10/33] common/cnxk: add 20k defines for IPsec
From: Anoob Joseph
Add 20K defines for IPsec.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/meson.build | 1 +
drivers/common/cnxk/roc_api.h | 1 +
drivers/common/cnxk/roc_ie_ow.c | 41 +++
drivers/common/cnxk/roc_ie_ow.h | 537
drivers/common/cnxk/version.map | 2 +
5 files changed, 582 insertions(+)
create mode 100644 drivers/common/cnxk/roc_ie_ow.c
create mode 100644 drivers/common/cnxk/roc_ie_ow.h
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 00a352dc55..59f4eacf84 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -25,6 +25,7 @@ sources = files(
'roc_idev.c',
'roc_irq.c',
'roc_ie_ot.c',
+'roc_ie_ow.c',
'roc_mbox.c',
'roc_mcs.c',
'roc_mcs_sec_cfg.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 93e7bf11bb..3cee5aa87c 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -93,6 +93,7 @@
#include "roc_ie.h"
#include "roc_ie_on.h"
#include "roc_ie_ot.h"
+#include "roc_ie_ow.h"
#include "roc_se.h"
/* DPI */
diff --git a/drivers/common/cnxk/roc_ie_ow.c b/drivers/common/cnxk/roc_ie_ow.c
new file mode 100644
index 00..dd83578b62
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_ow.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2024 Marvell.
+ */
+
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+void
+roc_ow_ipsec_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa)
+{
+ size_t offset;
+
+ memset(sa, 0, sizeof(struct roc_ow_ipsec_inb_sa));
+
+ sa->w0.s.pkt_output = ROC_IE_OW_SA_PKT_OUTPUT_NO_FRAG;
+ sa->w0.s.pkt_format = ROC_IE_OW_SA_PKT_FMT_META;
+ sa->w0.s.pkind = ROC_IE_OW_CPT_PKIND;
+ sa->w0.s.et_ovrwr = 1;
+ sa->w2.s.l3hdr_on_err = 1;
+
+ offset = offsetof(struct roc_ow_ipsec_inb_sa, ctx);
+ sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
+ sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
+ sa->w0.s.ctx_size = ROC_IE_OW_CTX_ILEN;
+ sa->w0.s.ctx_hdr_size = ROC_IE_OW_SA_CTX_HDR_SIZE;
+ sa->w0.s.aop_valid = 1;
+}
+
+void
+roc_ow_ipsec_outb_sa_init(struct roc_ow_ipsec_outb_sa *sa)
+{
+ size_t offset;
+
+ memset(sa, 0, sizeof(struct roc_ow_ipsec_outb_sa));
+
+ offset = offsetof(struct roc_ow_ipsec_outb_sa, ctx);
+ sa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B) + 1;
+ sa->w0.s.ctx_size = ROC_IE_OW_CTX_ILEN;
+ sa->w0.s.aop_valid = 1;
+}
diff --git a/drivers/common/cnxk/roc_ie_ow.h b/drivers/common/cnxk/roc_ie_ow.h
new file mode 100644
index 00..56ca1e7f75
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_ow.h
@@ -0,0 +1,537 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2024 Marvell.
+ */
+
+#ifndef __ROC_IE_OW_H__
+#define __ROC_IE_OW_H__
+
+#include "roc_platform.h"
+
+#include "roc_cpt.h"
+
+/* CN20K IPsec opcodes */
+#define ROC_IE_OW_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL
+#define ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x29UL
+
+#define ROC_IE_OW_MAJOR_OP_WRITE_SA 0x01UL
+#define ROC_IE_OW_MINOR_OP_WRITE_SA 0x09UL
+
+#define ROC_IE_OW_CTX_ILEN 2
+
+/* PKIND to be used for CPT Meta parsing */
+#define ROC_IE_OW_CPT_PKIND 58
+#define ROC_IE_OW_CPT_TS_PKIND 54
+#define ROC_IE_OW_SA_CTX_HDR_SIZE 1
+
+#define ROC_IE_OW_INPLACE_BIT BIT(6)
+
+enum roc_ie_ow_ucc_ipsec {
+ ROC_IE_OW_UCC_SUCCESS = 0x00,
+ ROC_IE_OW_UCC_ERR_SA_INVAL = 0xb0,
+ ROC_IE_OW_UCC_ERR_SA_EXPIRED = 0xb1,
+ ROC_IE_OW_UCC_ERR_SA_OVERFLOW = 0xb2,
+ ROC_IE_OW_UCC_ERR_SA_ESP_BAD_ALGO = 0xb3,
+ ROC_IE_OW_UCC_ERR_SA_AH_BAD_ALGO = 0xb4,
+ ROC_IE_OW_UCC_ERR_SA_BAD_CTX = 0xb5,
+ ROC_IE_OW_UCC_SA_CTX_FLAG_MISMATCH = 0xb6,
+ ROC_IE_OW_UCC_ERR_AOP_IPSEC = 0xb7,
+ ROC_IE_OW_UCC_ERR_PKT_IP = 0xb8,
+ ROC_IE_OW_UCC_ERR_PKT_IP6_BAD_EXT = 0xb9,
+ ROC_IE_OW_UCC_ERR_PKT_IP6_HBH = 0xba,
+ ROC_IE_OW_UCC_ERR_PKT_IP6_BIGEXT = 0xbb,
+ ROC_IE_OW_UCC_ERR_PKT_IP_ULP = 0xbc,
+ ROC_IE_OW_UCC_ERR_PKT_SA_MISMATCH = 0xbd,
+ ROC_IE_OW_UCC_ERR_PKT_SPI_MISMATCH = 0xbe,
+ ROC_IE_OW_UCC_ERR_PKT_ESP_BADPAD = 0xbf,
+ ROC_IE_OW_UCC_ERR_PKT_BADICV = 0xc0,
+ ROC_IE_OW_UCC_ERR_PKT_REPLAY_SEQ = 0xc1,
+ ROC_IE_OW_UCC_ERR_PKT_BADNH = 0xc2,
+ ROC_IE_OW_UCC_ERR_PKT_SA_PORT_MISMATCH = 0xc3,
+ ROC_IE_OW_UCC_ERR_PKT_BAD_DLEN = 0xc4,
+ ROC_IE_OW_UCC_ERR_SA_ESP_BAD_KEYS = 0xc5,
+ ROC_IE_OW_UCC_ERR_SA_AH_BAD_KEYS = 0xc6,
+ ROC_IE_OW_UCC_ERR_SA_BAD_IP = 0xc7,
+ ROC_IE_OW_UCC_ERR_PKT_IP_FRAG = 0xc8,
+ ROC_IE_OW_UCC_ERR_PKT_REPLAY_WINDOW = 0xc9,
+ ROC_IE_OW_UCC_SUCCESS_PKT_IP_BADCSUM = 0xed,
+ ROC_IE_OW_UCC_SUCCESS_PKT_L4_GOODCSUM = 0xee,
+ ROC_IE_OW_UCC_SUCCESS_PKT_L4_BADCSUM = 0xef,
+ ROC_IE_OW_UCC_SUCCESS_SA_SOFTEXP_FIRST = 0xf0,
+ ROC_IE_OW_UCC_SUCCESS_PKT_UDPESP_NZCSUM = 0xf1
[PATCH v2 11/33] common/cnxk: update default eng group for cn20k
CN20K does not have IE engines, hence change the default eng group
for cn20k and use legacy for cn10k or older version.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/roc_cpt.c | 6 +++---
drivers/common/cnxk/roc_cpt.h | 10 +++---
drivers/common/cnxk/roc_nix_inl.c | 15 +++
drivers/common/cnxk/roc_nix_inl_dev.c | 12
drivers/event/cnxk/cn9k_worker.h | 2 +-
drivers/net/cnxk/cn10k_rx.h | 2 +-
drivers/net/cnxk/cn10k_tx.h | 4 ++--
drivers/net/cnxk/cn20k_tx.h | 4 ++--
8 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index a6d2d83f76..b4bf0ccd64 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -931,9 +931,9 @@ roc_cpt_iq_reset(struct roc_cpt_lf *lf)
plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
if (roc_model_is_cn9k())
- cpt_9k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE);
+ cpt_9k_lf_rst_lmtst(lf, ROC_LEGACY_CPT_DFLT_ENG_GRP_SE);
else
- cpt_10k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE);
+ cpt_10k_lf_rst_lmtst(lf,
ROC_LEGACY_CPT_DFLT_ENG_GRP_SE);
plt_read64(lf->rbase + CPT_LF_INPROG);
plt_delay_us(2);
@@ -1205,7 +1205,7 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr,
void *sa_cptr,
if (lf->roc_cpt == NULL) {
if (roc_cpt_has_ie_engines())
- egrp = ROC_CPT_DFLT_ENG_GRP_SE_IE;
+ egrp = ROC_LEGACY_CPT_DFLT_ENG_GRP_SE_IE;
else
egrp = ROC_CPT_DFLT_ENG_GRP_SE;
} else {
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index ac27479371..30bd2a094d 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -15,10 +15,14 @@
#define ROC_LOADFVC_MAJOR_OP 0x01UL
#define ROC_LOADFVC_MINOR_OP 0x08UL
+/* Default engine groups for CN9K, CN10K */
+#define ROC_LEGACY_CPT_DFLT_ENG_GRP_SE 0UL
+#define ROC_LEGACY_CPT_DFLT_ENG_GRP_SE_IE 1UL
+#define ROC_LEGACY_CPT_DFLT_ENG_GRP_AE 2UL
+
/* Default engine groups */
-#define ROC_CPT_DFLT_ENG_GRP_SE 0UL
-#define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL
-#define ROC_CPT_DFLT_ENG_GRP_AE 2UL
+#define ROC_CPT_DFLT_ENG_GRP_SE 0UL
+#define ROC_CPT_DFLT_ENG_GRP_AE 1UL
#define ROC_CPT_MAX_LFS 64
#define ROC_CPT_MAX_BLKS 2
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 88d5a678b1..6b7532b1f0 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -811,7 +811,10 @@ nix_inl_eng_caps_get(struct nix *nix)
inst.rptr = (uint64_t)rptr;
inst.w4.s.opcode_major = ROC_LOADFVC_MAJOR_OP;
inst.w4.s.opcode_minor = ROC_LOADFVC_MINOR_OP;
- inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;
+ if (roc_model_is_cn9k() || roc_model_is_cn10k())
+ inst.w7.s.egrp = ROC_LEGACY_CPT_DFLT_ENG_GRP_SE;
+ else
+ inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;
/* Use 1 min timeout for the poll */
const uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz();
@@ -1053,10 +1056,14 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
ctx_ilen_valid = true;
}
+ if (roc_model_is_cn9k() || roc_model_is_cn10k())
+ eng_grpmask = (1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_SE |
+ 1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_SE_IE |
+ 1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_AE);
+ else
+ eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE | 1ULL <<
ROC_CPT_DFLT_ENG_GRP_AE);
+
/* Alloc CPT LF */
- eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
- 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
- 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr,
!roc_nix->ipsec_out_sso_pffunc, ctx_ilen_valid,
ctx_ilen,
rx_inj, nb_lf - 1);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index d26cbee0cc..da28b22bcc 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -179,15 +179,19 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool
inl_dev_sso)
if (!inl_dev->attach_cptlf)
return 0;
- /* Alloc CPT LF */
- eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
- 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
- 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
+ if (roc_model_is_cn9k() || roc_model_is_cn10k())
+ eng_grpmask = (1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_SE |
+ 1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_SE_IE |
+
[PATCH v2 09/33] common/cnxk: add CPT LMT defines
From: Anoob Joseph add CPT LMT defines Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_cpt.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index c8cf9354da..ac27479371 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -60,6 +60,9 @@ ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 13) | \ ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 14)) +#define ROC_CN20K_CPT_LMT_ARG ROC_CN10K_CPT_LMT_ARG +#define ROC_CN20K_DUAL_CPT_LMT_ARG ROC_CN10K_DUAL_CPT_LMT_ARG + /* CPT helper macros */ #define ROC_CPT_AH_HDR_LEN 12 #define ROC_CPT_AES_GCM_IV_LEN 8 -- 2.34.1
[PATCH v2 12/33] common/cnxk: support for cn20k IPsec session
Add support for cn20k IPsec session create/destroy.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/cnxk_security.c | 546 +++-
drivers/common/cnxk/cnxk_security.h | 12 +-
drivers/common/cnxk/version.map | 2 +
3 files changed, 557 insertions(+), 3 deletions(-)
diff --git a/drivers/common/cnxk/cnxk_security.c
b/drivers/common/cnxk/cnxk_security.c
index 8953e901a1..3a747ed441 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -4,10 +4,10 @@
#include
-#include "cnxk_security.h"
-
#include "roc_api.h"
+#include "cnxk_security.h"
+
static int
ot_ipsec_sa_common_param_fill(union roc_ot_ipsec_sa_word2 *w2, uint8_t
*cipher_key,
uint8_t *salt_key, uint8_t *hmac_opad_ipad,
@@ -1183,3 +1183,545 @@ cnxk_on_ipsec_inb_sa_create(struct
rte_security_ipsec_xform *ipsec,
return ctx_len;
}
+
+static int
+ow_ipsec_sa_common_param_fill(union roc_ow_ipsec_sa_word2 *w2, uint8_t
*cipher_key,
+ uint8_t *salt_key, uint8_t *hmac_opad_ipad,
+ struct rte_security_ipsec_xform *ipsec_xfrm,
+ struct rte_crypto_sym_xform *crypto_xfrm)
+{
+ struct rte_crypto_sym_xform *auth_xfrm, *cipher_xfrm;
+ const uint8_t *key = NULL;
+ uint8_t ccm_flag = 0;
+ uint32_t *tmp_salt;
+ uint64_t *tmp_key;
+ int i, length = 0;
+
+ /* Set direction */
+ if (ipsec_xfrm->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS)
+ w2->s.dir = ROC_IE_SA_DIR_OUTBOUND;
+ else
+ w2->s.dir = ROC_IE_SA_DIR_INBOUND;
+
+ if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
+ auth_xfrm = crypto_xfrm;
+ cipher_xfrm = crypto_xfrm->next;
+ } else {
+ cipher_xfrm = crypto_xfrm;
+ auth_xfrm = crypto_xfrm->next;
+ }
+
+ /* Set protocol - ESP vs AH */
+ switch (ipsec_xfrm->proto) {
+ case RTE_SECURITY_IPSEC_SA_PROTO_ESP:
+ w2->s.protocol = ROC_IE_SA_PROTOCOL_ESP;
+ break;
+ case RTE_SECURITY_IPSEC_SA_PROTO_AH:
+ w2->s.protocol = ROC_IE_SA_PROTOCOL_AH;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Set mode - transport vs tunnel */
+ switch (ipsec_xfrm->mode) {
+ case RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT:
+ w2->s.mode = ROC_IE_SA_MODE_TRANSPORT;
+ break;
+ case RTE_SECURITY_IPSEC_SA_MODE_TUNNEL:
+ w2->s.mode = ROC_IE_SA_MODE_TUNNEL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Set encryption algorithm */
+ if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
+ key = crypto_xfrm->aead.key.data;
+ length = crypto_xfrm->aead.key.length;
+
+ switch (crypto_xfrm->aead.algo) {
+ case RTE_CRYPTO_AEAD_AES_GCM:
+ w2->s.enc_type = ROC_IE_SA_ENC_AES_GCM;
+ w2->s.auth_type = ROC_IE_SA_AUTH_NULL;
+ memcpy(salt_key, &ipsec_xfrm->salt, 4);
+ tmp_salt = (uint32_t *)salt_key;
+ *tmp_salt = rte_be_to_cpu_32(*tmp_salt);
+ break;
+ case RTE_CRYPTO_AEAD_AES_CCM:
+ w2->s.enc_type = ROC_IE_SA_ENC_AES_CCM;
+ w2->s.auth_type = ROC_IE_SA_AUTH_NULL;
+ ccm_flag = 0x07 & ~ROC_CPT_AES_CCM_CTR_LEN;
+ *salt_key = ccm_flag;
+ memcpy(PLT_PTR_ADD(salt_key, 1), &ipsec_xfrm->salt, 3);
+ tmp_salt = (uint32_t *)salt_key;
+ *tmp_salt = rte_be_to_cpu_32(*tmp_salt);
+ break;
+ default:
+ return -ENOTSUP;
+ }
+ } else {
+ if (cipher_xfrm != NULL) {
+ switch (cipher_xfrm->cipher.algo) {
+ case RTE_CRYPTO_CIPHER_NULL:
+ w2->s.enc_type = ROC_IE_SA_ENC_NULL;
+ break;
+ case RTE_CRYPTO_CIPHER_AES_CBC:
+ w2->s.enc_type = ROC_IE_SA_ENC_AES_CBC;
+ break;
+ case RTE_CRYPTO_CIPHER_AES_CTR:
+ w2->s.enc_type = ROC_IE_SA_ENC_AES_CTR;
+ break;
+ case RTE_CRYPTO_CIPHER_3DES_CBC:
+ w2->s.enc_type = ROC_IE_SA_ENC_3DES_CBC;
+ break;
+ default:
+ return -ENOTSUP;
+ }
+
+ key = cipher_xfrm->cipher.key.data;
+ length = cipher_xfrm->cipher.key.length
[PATCH v2 13/33] common/cnxk: add cn20k meta pkt structs
From: Rahul Bhansali
Adds below structures for cn20k,
- cpt_parse_hdr_s
- cpt_rxc_sg_s
- cpt_rxc_ptr_info_s
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/hw/cpt.h| 211 +---
drivers/common/cnxk/roc_cpt.h | 2 +-
drivers/common/cnxk/roc_cpt_debug.c | 143 +--
drivers/net/cnxk/cn10k_ethdev.c | 5 +-
drivers/net/cnxk/cn10k_rx.h | 21 +--
drivers/net/cnxk/cn20k_ethdev.c | 4 +-
6 files changed, 304 insertions(+), 82 deletions(-)
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index b308a18f0d..f2c222a920 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -322,60 +322,124 @@ union cpt_res_s {
};
/* [CN10K, .) */
-struct cpt_parse_hdr_s {
- /* WORD 0 */
- union {
- uint64_t u64;
- struct {
- uint8_t pad_len : 3;
- uint8_t num_frags : 3;
- uint8_t pkt_out : 2;
-
- uint8_t err_sum : 1;
- uint8_t reas_sts : 4;
- uint8_t reserved_53 : 1;
- uint8_t et_owr : 1;
- uint8_t pkt_fmt : 1;
-
- uint16_t match_id : 16;
-
- uint32_t cookie : 32;
- };
- } w0;
-
- /* WORD 1 */
- uint64_t wqe_ptr;
-
- /* WORD 2 */
- union {
- uint64_t u64;
- struct {
- uint8_t fi_pad : 3;
- uint8_t fi_offset : 5;
- uint8_t il3_off;
- uint16_t orig_pf_func;
- uint16_t reserved_145_160;
- uint16_t frag_age;
- };
- } w2;
-
- /* WORD 3 */
- union {
- uint64_t u64;
- struct {
- uint32_t spi;
- uint16_t reserved_209_224;
- uint8_t uc_ccode;
- uint8_t hw_ccode;
+union cpt_parse_hdr_u {
+ struct cpt_parse_hdr_s {
+ /* WORD 0 */
+ union {
+ uint64_t u64;
+ struct {
+ uint64_t cookie : 32;
+ uint64_t match_id : 16;
+ uint64_t err_sum : 1;
+ uint64_t reas_sts : 4;
+ uint64_t pad_len : 3;
+ uint64_t et_owr : 1;
+ uint64_t pkt_fmt : 1;
+ uint64_t num_frags : 4;
+ uint64_t pkt_out : 2;
+ };
+ } w0;
+
+ /* WORD 1 */
+ uint64_t wqe_ptr;
+
+ /* WORD 2 */
+ union {
+ uint64_t u64;
+ struct {
+ uint64_t rsvd_134_128 : 7;
+ uint64_t pkt_inline : 1;
+ uint64_t new_pkt_aura : 20;
+ uint64_t orig_pkt_aura : 20;
+ uint64_t il3_off : 8;
+ uint64_t ptr_pad : 3;
+ uint64_t ptr_offset : 5;
+ };
+ } w2;
+
+ /* WORD 3 */
+ union {
+ uint64_t u64;
+ struct {
+ uint8_t hw_ccode;
+ uint8_t uc_ccode;
+ uint16_t frag_age;
+ uint16_t pf_func;
+ uint16_t rlen;
+ };
+ } w3;
+
+ /* WORD 4 */
+ union {
+ uint64_t u64;
+ struct {
+ uint32_t l4_chksum;
+ uint32_t l4_chksum_type : 1;
+ uint32_t rsvd_298_289 : 10;
+ uint32_t channel : 12;
+ uint32_t sctr_size : 4;
+ uint32_t gthr_size : 5;
+ };
+ } w4;
+ } s;
+
+ struct cpt_cn10k_parse_hdr_s {
+ /* WORD 0 */
+ union {
+ uint64_t u64;
+ struct {
+ uint8_t pad_len : 3;
+ uint8_t num_frags : 3;
+ uint8_t pkt_out : 2;
+
+ uint8_t err_sum : 1;
+ uint8_t reas_sts : 4;
+ uint8_t reserved_53 : 1;
+ uint8_t et_owr : 1;
+ uint8_t pkt_
[PATCH v2 15/33] common/cnxk: support inline SA context invalidate
From: Rahul Bhansali
Add SA context invalidate support for cn20k.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/hw/cpt.h | 11 -
drivers/common/cnxk/roc_nix.h | 1 +
drivers/common/cnxk/roc_nix_inl.c | 37 ++-
3 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index f2c222a920..40987abbb9 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -44,7 +44,8 @@
#define CPT_LF_CTX_ENC_PKT_CNT (0x540ull)
#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull)
#define CPT_LF_CTX_DEC_PKT_CNT (0x560ull)
-#define CPT_LF_CTX_RELOAD (0x570ull)
+#define CPT_LF_CTX_RELOAD (0x570ull) /* [CN10k] */
+#define CPT_LF_CTX_INVAL (0x570ull) /* [CN20k] */
#define CPT_AF_LFX_CTL(a) (0x27000ull | (uint64_t)(a) << 3)
#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
@@ -126,6 +127,14 @@ union cpt_lf_ctx_reload {
} s;
};
+union cpt_lf_ctx_inval {
+ uint64_t u;
+ struct {
+ uint64_t cptr : 46;
+ uint64_t reserved_46_63 : 18;
+ } s;
+};
+
union cpt_lf_inprog {
uint64_t u;
struct cpt_lf_inprog_s {
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 15823ab16c..2597b8d56b 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -474,6 +474,7 @@ struct roc_nix {
bool custom_meta_aura_ena;
bool rx_inj_ena;
bool custom_inb_sa;
+ bool use_write_sa;
uint32_t root_sched_weight;
uint16_t inb_cfg_param1;
uint16_t inb_cfg_param2;
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index db1969038a..991a81b50d 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -1744,6 +1744,7 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa,
bool inb,
union cpt_lf_ctx_reload reload;
union cpt_lf_ctx_flush flush;
union cpt_lf_ctx_err err;
+ union cpt_lf_ctx_inval inval;
bool get_inl_lf = true;
uintptr_t rbase;
struct nix *nix;
@@ -1778,8 +1779,15 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa,
bool inb,
flush.u = 0;
reload.u = 0;
+ inval.u = 0;
switch (op) {
case ROC_NIX_INL_SA_OP_FLUSH_INVAL:
+ if (!roc_model_is_cn10k()) {
+ inval.s.cptr = ((uintptr_t)sa) >> 7;
+ plt_write64(inval.u, rbase + CPT_LF_CTX_INVAL);
+ break;
+ }
+
flush.s.inval = 1;
/* fall through */
case ROC_NIX_INL_SA_OP_FLUSH:
@@ -1815,10 +1823,12 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void
*sa_dptr, void *sa_cptr,
struct nix_inl_dev *inl_dev = NULL;
struct roc_cpt_lf *outb_lf = NULL;
union cpt_lf_ctx_flush flush;
+ union cpt_lf_ctx_inval inval;
union cpt_lf_ctx_err err;
bool get_inl_lf = true;
uintptr_t rbase;
struct nix *nix;
+ uint64_t *sa;
int rc;
/* Nothing much to do on cn9k */
@@ -1850,7 +1860,10 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void
*sa_dptr, void *sa_cptr,
outb_lf = &inl_dev->cpt_lf[0];
}
- if (outb_lf) {
+ if (outb_lf == NULL)
+ goto exit;
+
+ if (roc_model_is_cn10k() || roc_nix->use_write_sa) {
rbase = outb_lf->rbase;
flush.u = 0;
@@ -1869,7 +1882,29 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void
*sa_dptr, void *sa_cptr,
if (err.s.flush_st_flt)
plt_warn("CTX flush could not complete");
return 0;
+ } else {
+ sa = sa_dptr;
+
+ /* Clear bit 58 aop_valid */
+ sa[0] &= ~(1ULL << 58);
+ memcpy(sa_cptr, sa_dptr, sa_len);
+ plt_io_wmb();
+
+ /* Trigger CTX invalidate */
+ rbase = outb_lf->rbase;
+ inval.u = 0;
+ inval.s.cptr = ((uintptr_t)sa_cptr) >> 7;
+ plt_write64(inval.u, rbase + CPT_LF_CTX_INVAL);
+
+ /* Set bit 58 aop_valid */
+ sa = sa_cptr;
+ sa[0] |= (1ULL << 58);
+ plt_io_wmb();
+
+ return 0;
}
+
+exit:
plt_nix_dbg("Could not get CPT LF for CTX write");
return -ENOTSUP;
}
--
2.34.1
[PATCH v2 16/33] common/cnxk: update feature flags for cn20k
From: Rahul Bhansali
Features updated for cn20k platform.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_features.h | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/common/cnxk/roc_features.h
b/drivers/common/cnxk/roc_features.h
index 0002a7b5c3..59c09fbc85 100644
--- a/drivers/common/cnxk/roc_features.h
+++ b/drivers/common/cnxk/roc_features.h
@@ -13,49 +13,49 @@ roc_feature_sso_has_stash(void)
static inline bool
roc_feature_nix_has_inl_ipsec_mseg(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_drop_re_mask(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_inl_rq_mask(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_own_meta_aura(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_late_bp(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_reass(void)
{
- return roc_model_is_cn10ka();
+ return (roc_model_is_cn20k() || roc_model_is_cn10ka());
}
static inline bool
roc_feature_nix_has_cqe_stash(void)
{
- return roc_model_is_cn10ka_b0();
+ return (roc_model_is_cn20k() || roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_rxchan_multi_bpid(void)
{
- if (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0())
+ if (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0())
return true;
return false;
}
@@ -63,7 +63,7 @@ roc_feature_nix_has_rxchan_multi_bpid(void)
static inline bool
roc_feature_nix_has_age_drop_stats(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
@@ -87,13 +87,13 @@ roc_feature_nix_has_inl_ipsec(void)
static inline bool
roc_feature_nix_has_rx_inject(void)
{
- return (roc_model_is_cn10ka_b0() || roc_model_is_cn10kb());
+ return (roc_model_is_cn20k() || roc_model_is_cn10ka_b0() ||
roc_model_is_cn10kb());
}
static inline bool
roc_feature_nix_has_second_pass_drop(void)
{
- return 0;
+ return roc_model_is_cn20k();
}
static inline bool
--
2.34.1
[PATCH v2 17/33] common/cnxk: add mbox define for inline profile support
Add mbox support for global inline profile allocation.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/roc_mbox.h| 45 ++
drivers/common/cnxk/roc_nix_inl.c | 53 +++
2 files changed, 85 insertions(+), 13 deletions(-)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index f3024057b5..beb7fb6e62 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -336,6 +336,13 @@ struct mbox_msghdr {
nix_mcast_grp_update_rsp)
\
M(NIX_GET_LF_STATS,0x802e, nix_get_lf_stats, nix_get_lf_stats_req,
nix_lf_stats_rsp) \
M(NIX_CN20K_AQ_ENQ, 0x802f, nix_cn20k_aq_enq, nix_cn20k_aq_enq_req,
nix_cn20k_aq_enq_rsp) \
+ M(NIX_LSO_ALT_FLAGS_CFG, 0x8030, nix_lso_alt_flags_cfg,
nix_lso_alt_flags_cfg_req, \
+ nix_lso_alt_flags_cfg_rsp)
\
+ M(NIX_RX_INLINE_PROFILE_CFG, 0x8031, nix_rx_inl_profile_cfg,
\
+ nix_rx_inl_profile_cfg_req,
\
+ nix_rx_inl_profile_cfg_rsp)
\
+ M(NIX_RX_INLINE_LF_CFG, 0x8032, nix_rx_inl_lf_cfg,
nix_rx_inl_lf_cfg_req, \
+ msg_rsp)
\
/* MCS mbox IDs (range 0xa000 - 0xbFFF) */
\
M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,
\
mcs_alloc_rsrc_rsp)
\
@@ -2008,6 +2015,32 @@ struct nix_inline_ipsec_cfg {
uint32_t __io credit_th;
};
+#define NIX_RX_INL_PROFILE_PROTO_CNT 9
+struct nix_rx_inl_profile_cfg_req {
+ struct mbox_msghdr hdr;
+ uint64_t __io def_cfg;
+ uint64_t __io extract_cfg;
+ uint64_t __io gen_cfg;
+ uint64_t __io prot_field_cfg[NIX_RX_INL_PROFILE_PROTO_CNT];
+ uint64_t __io rsvd[32]; /* reserved fields for future expansion
*/
+};
+
+struct nix_rx_inl_profile_cfg_rsp {
+ struct mbox_msghdr hdr;
+ uint8_t __io profile_id;
+ uint8_t __io rsvd[32]; /* reserved fields for future expansion
*/
+};
+
+struct nix_rx_inl_lf_cfg_req {
+ struct mbox_msghdr hdr;
+ uint64_t __io rx_inline_cfg0;
+ uint64_t __io rx_inline_cfg1;
+ uint64_t __io rx_inline_sa_base;
+ uint8_t __io enable;
+ uint8_t __io profile_id;
+ uint8_t __io rsvd[32]; /* reserved fields for future expansion
*/
+};
+
/* Per NIX LF inline IPSec configuration */
struct nix_inline_ipsec_lf_cfg {
struct mbox_msghdr hdr;
@@ -2064,6 +2097,17 @@ struct nix_bandprof_get_hwinfo_rsp {
uint32_t __io policer_timeunit;
};
+struct nix_lso_alt_flags_cfg_req {
+ struct mbox_msghdr hdr;
+ uint64_t __io cfg;
+ uint64_t __io cfg1;
+};
+
+struct nix_lso_alt_flags_cfg_rsp {
+ struct mbox_msghdr hdr;
+ uint8_t __io lso_alt_flags_idx;
+};
+
/* SSO mailbox error codes
* Range 501 - 600.
*/
@@ -3090,6 +3134,7 @@ struct nix_spi_to_sa_add_req {
uint32_t __io spi_index;
uint16_t __io match_id;
bool __io valid;
+ uint8_t __io inline_profile_id;
};
struct nix_spi_to_sa_add_rsp {
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 991a81b50d..37e1bfc0ed 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -395,7 +395,8 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
uint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;
uint32_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
- struct roc_nix_ipsec_cfg cfg;
+ struct mbox *mbox = mbox_get((&nix->dev)->mbox);
+ struct nix_inline_ipsec_lf_cfg *lf_cfg;
uint64_t max_sa, i;
size_t inb_sa_sz;
void *sa;
@@ -419,8 +420,9 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
nix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
ROC_NIX_INL_SA_BASE_ALIGN);
if (!nix->inb_sa_base) {
+ rc = -ENOMEM;
plt_err("Failed to allocate memory for Inbound SA");
- return -ENOMEM;
+ goto exit;
}
if (!roc_model_is_cn9k()) {
@@ -433,23 +435,36 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
}
}
- memset(&cfg, 0, sizeof(cfg));
- cfg.sa_size = inb_sa_sz;
- cfg.iova = (uintptr_t)nix->inb_sa_base;
- cfg.max_sa = max_sa;
- cfg.tt = SSO_TT_ORDERED;
-
/* Setup device specific inb SA table */
- rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
+ lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_
[PATCH v2 14/33] common/cnxk: support for inline IPsec for cn20k
From: Rahul Bhansali
Support in NIX inline device for inbound and outbound SA init.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_cpt.h | 1 +
drivers/common/cnxk/roc_nix_inl.c | 62 ++-
drivers/common/cnxk/roc_nix_inl_dev.c | 22 ++
drivers/common/cnxk/roc_nix_inl_dp.h | 46
drivers/net/cnxk/cn10k_rxtx.h | 2 +
drivers/net/cnxk/cn20k_rxtx.h | 2 +
6 files changed, 116 insertions(+), 19 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 238f55eff4..37634793d4 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -66,6 +66,7 @@
#define ROC_CN20K_CPT_LMT_ARG ROC_CN10K_CPT_LMT_ARG
#define ROC_CN20K_DUAL_CPT_LMT_ARG ROC_CN10K_DUAL_CPT_LMT_ARG
+#define ROC_CN20K_CPT_INST_DW_M1 ROC_CN10K_CPT_INST_DW_M1
/* CPT helper macros */
#define ROC_CPT_AH_HDR_LEN 12
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 6b7532b1f0..db1969038a 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -404,12 +404,14 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);
/* CN9K SA size is different */
- if (roc_model_is_cn9k())
- inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
- else if (roc_nix->custom_inb_sa)
+ if (roc_nix->custom_inb_sa)
inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ;
- else
+ else if (roc_model_is_cn9k())
+ inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
+ else if (roc_model_is_cn10k())
inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
+ else
+ inb_sa_sz = ROC_NIX_INL_OW_IPSEC_INB_SA_SZ;
/* Alloc contiguous memory for Inbound SA's */
nix->inb_sa_sz = inb_sa_sz;
@@ -420,10 +422,14 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
plt_err("Failed to allocate memory for Inbound SA");
return -ENOMEM;
}
- if (roc_model_is_cn10k()) {
+
+ if (!roc_model_is_cn9k()) {
for (i = 0; i < max_sa; i++) {
sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
- roc_ot_ipsec_inb_sa_init(sa);
+ if (roc_model_is_cn10k())
+ roc_ot_ipsec_inb_sa_init(sa);
+ else
+ roc_ow_ipsec_inb_sa_init(sa);
}
}
@@ -841,7 +847,7 @@ nix_inl_eng_caps_get(struct nix *nix)
plt_err("LOAD FVC operation timed out");
return;
}
- } else {
+ } else if (roc_model_is_cn10k()) {
uint64_t lmt_arg, io_addr;
uint16_t lmt_id;
@@ -870,6 +876,35 @@ nix_inl_eng_caps_get(struct nix *nix)
plt_err("LOAD FVC operation timed out");
goto exit;
}
+ } else {
+ uint64_t lmt_arg, io_addr;
+ uint16_t lmt_id;
+
+ hw_res->cn20k.compcode = CPT_COMP_NOT_DONE;
+
+ /* Use this reserved LMT line as no one else is using it */
+ lmt_id = roc_plt_control_lmt_id_get();
+ lmt_base += ((uint64_t)lmt_id << ROC_LMT_LINE_SIZE_LOG2);
+
+ memcpy((void *)lmt_base, &inst, sizeof(inst));
+
+ lmt_arg = ROC_CN20K_CPT_LMT_ARG | (uint64_t)lmt_id;
+ io_addr = lf->io_addr | ROC_CN20K_CPT_INST_DW_M1 << 4;
+
+ roc_lmt_submit_steorl(lmt_arg, io_addr);
+ plt_io_wmb();
+
+ /* Wait until CPT instruction completes */
+ do {
+ res.u64[0] = __atomic_load_n(&hw_res->u64[0],
__ATOMIC_RELAXED);
+ if (unlikely(plt_tsc_cycles() > timeout))
+ break;
+ } while (res.cn20k.compcode == CPT_COMP_NOT_DONE);
+
+ if (res.cn20k.compcode != CPT_COMP_GOOD ||
res.cn20k.uc_compcode) {
+ plt_err("LOAD FVC operation timed out");
+ goto exit;
+ }
}
nix->cpt_eng_caps = plt_be_to_cpu_64(*rptr);
@@ -1127,8 +1162,11 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
/* CN9K SA size is different */
if (roc_model_is_cn9k())
sa_sz = ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ;
- else
+ else if (roc_model_is_cn10k())
sa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ;
+ else
+ sa_sz = ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ;
+
/* Alloc contiguous memory of outbound SA */
sa_base = plt_zmalloc(sa_sz * roc_nix->ipsec_out_max_sa,
ROC_NIX_INL_SA_BASE_ALIGN);
@@ -1136,10 +1174,14 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix
[PATCH v2 20/33] common/cnxk: add API to fetch inline profile ID
From: Rahul Bhansali
For Inline device, add new roc API to get IPsec and
reassembly profile id.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_nix_inl.c | 60 +++
drivers/common/cnxk/roc_nix_inl.h | 2 ++
2 files changed, 62 insertions(+)
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 652698d13b..6927de6505 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -743,6 +743,66 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool
inb_inl_dev)
return (uintptr_t)nix->inb_sa_base[nix->ipsec_prof_id];
}
+uint16_t
+roc_nix_inl_inb_ipsec_profile_id_get(struct roc_nix *roc_nix, bool inb_inl_dev)
+{
+ struct idev_cfg *idev = idev_get_cfg();
+ struct nix_inl_dev *inl_dev;
+ struct nix *nix = NULL;
+
+ if (idev == NULL)
+ return 0;
+
+ if (!inb_inl_dev && roc_nix == NULL)
+ return -EINVAL;
+
+ if (roc_nix) {
+ nix = roc_nix_to_nix_priv(roc_nix);
+ if (!nix->inl_inb_ena)
+ return 0;
+ }
+
+ if (inb_inl_dev) {
+ inl_dev = idev->nix_inl_dev;
+ /* Return inline Ipsec profile ID */
+ if (inl_dev)
+ return inl_dev->ipsec_prof_id;
+ return 0;
+ }
+
+ return nix->ipsec_prof_id;
+}
+
+uint16_t
+roc_nix_inl_inb_reass_profile_id_get(struct roc_nix *roc_nix, bool inb_inl_dev)
+{
+ struct idev_cfg *idev = idev_get_cfg();
+ struct nix_inl_dev *inl_dev;
+ struct nix *nix = NULL;
+
+ if (idev == NULL)
+ return 0;
+
+ if (!inb_inl_dev && roc_nix == NULL)
+ return -EINVAL;
+
+ if (roc_nix) {
+ nix = roc_nix_to_nix_priv(roc_nix);
+ if (!nix->inl_inb_ena)
+ return 0;
+ }
+
+ if (inb_inl_dev) {
+ inl_dev = idev->nix_inl_dev;
+ /* Return inline reassembly profile ID */
+ if (inl_dev)
+ return inl_dev->reass_prof_id;
+ return 0;
+ }
+
+ return nix->reass_prof_id;
+}
+
bool
roc_nix_inl_inb_rx_inject_enable(struct roc_nix *roc_nix, bool inb_inl_dev)
{
diff --git a/drivers/common/cnxk/roc_nix_inl.h
b/drivers/common/cnxk/roc_nix_inl.h
index 12f36187cf..10bf7d5c25 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -140,6 +140,8 @@ int __roc_api roc_nix_inl_inb_fini(struct roc_nix *roc_nix);
bool __roc_api roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix);
uintptr_t __roc_api roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix,
bool inl_dev_sa);
+uint16_t roc_nix_inl_inb_ipsec_profile_id_get(struct roc_nix *roc_nix, bool
inb_inl_dev);
+uint16_t roc_nix_inl_inb_reass_profile_id_get(struct roc_nix *roc_nix, bool
inb_inl_dev);
bool __roc_api roc_nix_inl_inb_rx_inject_enable(struct roc_nix *roc_nix, bool
inl_dev_sa);
uint32_t __roc_api roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix,
bool inl_dev_sa, uint32_t *min,
--
2.34.1
[PATCH v2 21/33] common/cnxk: add NPC action2 support
From: Rahul Bhansali
Add action2 config for IPsec rule.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/hw/nix.h | 13 +++--
drivers/common/cnxk/roc_mbox.h | 1 +
drivers/common/cnxk/roc_npc.h | 1 +
drivers/common/cnxk/roc_npc_mcam.c | 1 +
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
index dd629a2080..e4d8d285d5 100644
--- a/drivers/common/cnxk/hw/nix.h
+++ b/drivers/common/cnxk/hw/nix.h
@@ -1678,6 +1678,15 @@ struct nix_rx_action_s {
uint64_t rsvd_63_61 : 3;
};
+/* NIX receive action structure */
+struct nix_rx_action2_s {
+ uint64_t ipsec_qsel : 3;
+ uint64_t ipsec_qidx : 4;
+ uint64_t reserved_7_7: 1;
+ uint64_t inline_profile_id : 4;
+ uint64_t reserved_12_63 : 52;
+
+};
/* NIX receive immediate sub descriptor structure */
struct nix_rx_imm_s {
uint64_t size : 16;
@@ -2666,9 +2675,9 @@ struct nix_lso_format {
#define NIX_SENDSTAT_IOFFSET_MASK 0xFFF
#define NIX_SENDSTAT_OOFFSET_MASK 0xFFF
-/* The mask is to extract lower 10-bits of channel number
+/* The mask is to extract lower 11-bits of channel number
* which CPT will pass to X2P.
*/
-#define NIX_CHAN_CPT_X2P_MASK (0x3ffull)
+#define NIX_CHAN_CPT_X2P_MASK (0x7ffull)
#endif /* __NIX_HW_H__ */
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index fbea15690b..22a7258074 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -2694,6 +2694,7 @@ struct cn20k_mcam_entry {
uint64_t __io kw_mask[NPC_CN20K_MAX_KWS_IN_KEY];
uint64_t __io action;
uint64_t __io vtag_action;
+ uint64_t __io action2;
};
struct npc_cn20k_mcam_write_entry_req {
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index 4da21a8eb3..2a409cce99 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -328,6 +328,7 @@ struct roc_npc_flow {
uint64_t mcam_data[ROC_NPC_MAX_MCAM_WIDTH_DWORDS];
uint64_t mcam_mask[ROC_NPC_MAX_MCAM_WIDTH_DWORDS];
uint64_t npc_action;
+ uint64_t npc_action2;
uint64_t vtag_action;
bool vtag_insert_enabled;
int8_t vtag_insert_count;
diff --git a/drivers/common/cnxk/roc_npc_mcam.c
b/drivers/common/cnxk/roc_npc_mcam.c
index 412b2611b7..5db72c22ae 100644
--- a/drivers/common/cnxk/roc_npc_mcam.c
+++ b/drivers/common/cnxk/roc_npc_mcam.c
@@ -511,6 +511,7 @@ npc_mcam_write_entry(struct mbox *mbox, struct roc_npc_flow
*mcam)
cn20k_req->intf = mcam->nix_intf;
cn20k_req->enable_entry = mcam->enable;
cn20k_req->entry_data.action = mcam->npc_action;
+ cn20k_req->entry_data.action2 = mcam->npc_action2;
cn20k_req->entry_data.vtag_action = mcam->vtag_action;
cn20k_req->hw_prio = mcam->priority;
if (mcam->use_ctr)
--
2.34.1
[PATCH v2 19/33] common/cnxk: add NIX inline reassembly profile config
From: Rahul Bhansali
Reassembly profile configuration for nix inline path.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_features.h | 6 +
drivers/common/cnxk/roc_ie_ow.c| 22 +++
drivers/common/cnxk/roc_ie_ow.h| 2 +
drivers/common/cnxk/roc_nix.h | 3 +-
drivers/common/cnxk/roc_nix_debug.c| 8 +-
drivers/common/cnxk/roc_nix_inl.c | 202
drivers/common/cnxk/roc_nix_inl.h | 10 +-
drivers/common/cnxk/roc_nix_inl_dev.c | 205 +++--
drivers/common/cnxk/roc_nix_inl_priv.h | 19 ++-
drivers/common/cnxk/roc_nix_priv.h | 9 +-
drivers/common/cnxk/version.map| 1 +
11 files changed, 425 insertions(+), 62 deletions(-)
diff --git a/drivers/common/cnxk/roc_features.h
b/drivers/common/cnxk/roc_features.h
index 49a563ef95..48ba2fade7 100644
--- a/drivers/common/cnxk/roc_features.h
+++ b/drivers/common/cnxk/roc_features.h
@@ -114,4 +114,10 @@ roc_feature_nix_has_inl_profile(void)
return roc_model_is_cn20k();
}
+static inline bool
+roc_feature_nix_has_plain_pkt_reassembly(void)
+{
+ return roc_model_is_cn20k();
+}
+
#endif
diff --git a/drivers/common/cnxk/roc_ie_ow.c b/drivers/common/cnxk/roc_ie_ow.c
index dd83578b62..9537e48389 100644
--- a/drivers/common/cnxk/roc_ie_ow.c
+++ b/drivers/common/cnxk/roc_ie_ow.c
@@ -27,6 +27,28 @@ roc_ow_ipsec_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa)
sa->w0.s.aop_valid = 1;
}
+void
+roc_ow_reass_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa)
+{
+ size_t offset;
+
+ memset(sa, 0, sizeof(struct roc_ow_ipsec_inb_sa));
+
+ sa->w0.s.pkt_output = ROC_IE_OW_SA_PKT_OUTPUT_HW_BASED_DEFRAG;
+ sa->w0.s.pkt_format = ROC_IE_OW_SA_PKT_FMT_META;
+ sa->w0.s.pkind = ROC_IE_OW_CPT_PKIND;
+ sa->w2.s.l3hdr_on_err = 1;
+ sa->w2.s.valid = 1;
+ sa->w2.s.dir = ROC_IE_SA_DIR_INBOUND;
+
+ offset = offsetof(struct roc_ow_ipsec_inb_sa, ctx);
+ sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
+ sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
+ sa->w0.s.ctx_size = ROC_IE_OW_CTX_ILEN;
+ sa->w0.s.ctx_hdr_size = ROC_IE_OW_SA_CTX_HDR_SIZE;
+ sa->w0.s.aop_valid = 1;
+}
+
void
roc_ow_ipsec_outb_sa_init(struct roc_ow_ipsec_outb_sa *sa)
{
diff --git a/drivers/common/cnxk/roc_ie_ow.h b/drivers/common/cnxk/roc_ie_ow.h
index 56ca1e7f75..4a3291d458 100644
--- a/drivers/common/cnxk/roc_ie_ow.h
+++ b/drivers/common/cnxk/roc_ie_ow.h
@@ -12,6 +12,7 @@
/* CN20K IPsec opcodes */
#define ROC_IE_OW_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL
#define ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x29UL
+#define ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_REASS 0x2BUL
#define ROC_IE_OW_MAJOR_OP_WRITE_SA 0x01UL
#define ROC_IE_OW_MINOR_OP_WRITE_SA 0x09UL
@@ -532,6 +533,7 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ow_ipsec_outb_sa,
ctx) == 31 * sizeof(uint
(PLT_MAX(sizeof(struct roc_ow_ipsec_inb_sa), sizeof(struct
roc_ow_ipsec_outb_sa)))
void __roc_api roc_ow_ipsec_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa);
+void __roc_api roc_ow_reass_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa);
void __roc_api roc_ow_ipsec_outb_sa_init(struct roc_ow_ipsec_outb_sa *sa);
#endif /* __ROC_IE_OW_H__ */
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index a66391449f..a1bd14ffc4 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -490,9 +490,10 @@ struct roc_nix {
uintptr_t meta_mempool;
uint16_t rep_cnt;
uint16_t rep_pfvf_map[MAX_PFVF_REP];
+ bool reass_ena;
TAILQ_ENTRY(roc_nix) next;
-#define ROC_NIX_MEM_SZ (6 * 1070)
+#define ROC_NIX_MEM_SZ (6 * 1112)
uint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned;
} __plt_cache_aligned;
diff --git a/drivers/common/cnxk/roc_nix_debug.c
b/drivers/common/cnxk/roc_nix_debug.c
index 0cc8d7cc1e..f9294e693b 100644
--- a/drivers/common/cnxk/roc_nix_debug.c
+++ b/drivers/common/cnxk/roc_nix_debug.c
@@ -1510,8 +1510,8 @@ roc_nix_dump(struct roc_nix *roc_nix, FILE *file)
nix_dump(file, " \ttx_pause = %d", nix->tx_pause);
nix_dump(file, " \tinl_inb_ena = %d", nix->inl_inb_ena);
nix_dump(file, " \tinl_outb_ena = %d", nix->inl_outb_ena);
- nix_dump(file, " \tinb_sa_base = 0x%p", nix->inb_sa_base);
- nix_dump(file, " \tinb_sa_sz = %" PRIu64, nix->inb_sa_sz);
+ nix_dump(file, " \tinb_sa_base = 0x%p",
nix->inb_sa_base[nix->ipsec_prof_id]);
+ nix_dump(file, " \tinb_sa_sz = %" PRIu64,
nix->inb_sa_sz[nix->ipsec_prof_id]);
nix_dump(file, " \toutb_sa_base = 0x%p", nix->outb_sa_base);
nix_dump(file, " \toutb_sa_sz = %" PRIu64, nix->outb_sa_sz);
nix_dump(file, " \toutb_err_sso_pffunc = 0x%x",
nix->outb_err_sso_pffunc);
@@ -1554,8 +1554,8 @@ roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev,
FILE *file)
nix_dump(file, " \tssow_msixoff = %d", inl_dev->ssow_msixoff);
nix_dump(fil
[PATCH v2 23/33] net/cnxk: support for cn20k inline IPsec session
Add support for cn20k inline IPsec session create/destroy.
Signed-off-by: Nithin Dabilpuram
---
drivers/net/cnxk/cn10k_ethdev_sec.c |7 -
drivers/net/cnxk/cn20k_ethdev.c | 11 +
drivers/net/cnxk/cn20k_ethdev.h | 17 +
drivers/net/cnxk/cn20k_ethdev_sec.c | 1182 +++
drivers/net/cnxk/cnxk_ethdev.c | 13 +-
drivers/net/cnxk/cnxk_ethdev.h |5 +-
drivers/net/cnxk/meson.build|1 +
7 files changed, 1227 insertions(+), 9 deletions(-)
create mode 100644 drivers/net/cnxk/cn20k_ethdev_sec.c
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 68691d2bfe..0dc5c22444 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -28,13 +28,6 @@ PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WIN_SIZE_MAX ==
ROC_AR_WIN_SIZE_MAX);
PLT_STATIC_ASSERT(RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 ==
ROC_LOG_MIN_AR_WIN_SIZE_M1);
PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WINBITS_SZ == ROC_AR_WINBITS_SZ);
-cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb;
-void
-cnxk_ethdev_rx_offload_cb_register(cnxk_ethdev_rx_offload_cb_t cb)
-{
- cnxk_ethdev_rx_offload_cb = cb;
-}
-
static struct rte_cryptodev_capabilities cn10k_eth_sec_crypto_caps[] = {
{ /* AES GCM */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c
index 1b608442cf..ea22112f69 100644
--- a/drivers/net/cnxk/cn20k_ethdev.c
+++ b/drivers/net/cnxk/cn20k_ethdev.c
@@ -403,6 +403,12 @@ cn20k_nix_configure(struct rte_eth_dev *eth_dev)
if (rc)
return rc;
+ if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
+ dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
+ /* Register callback to handle security error work */
+ roc_nix_inl_cb_register(cn20k_eth_sec_sso_work_cb, NULL);
+ }
+
/* Update offload flags */
dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
@@ -896,6 +902,8 @@ cn20k_nix_probe(struct rte_pci_driver *pci_drv, struct
rte_pci_device *pci_dev)
nix_tm_ops_override();
npc_flow_ops_override();
+ cn20k_eth_sec_ops_override();
+
/* Common probe */
rc = cnxk_nix_probe(pci_drv, pci_dev);
if (rc)
@@ -922,6 +930,9 @@ cn20k_nix_probe(struct rte_pci_driver *pci_drv, struct
rte_pci_device *pci_dev)
/* Register up msg callbacks for PTP information */
roc_nix_ptp_info_cb_register(&dev->nix, cn20k_nix_ptp_info_update_cb);
+ /* Use WRITE SA for inline IPsec */
+ dev->nix.use_write_sa = true;
+
return 0;
}
diff --git a/drivers/net/cnxk/cn20k_ethdev.h b/drivers/net/cnxk/cn20k_ethdev.h
index cb46044d60..74b03b23d2 100644
--- a/drivers/net/cnxk/cn20k_ethdev.h
+++ b/drivers/net/cnxk/cn20k_ethdev.h
@@ -8,8 +8,25 @@
#include
#include
+/* Private data in sw rsvd area of struct roc_ow_ipsec_outb_sa */
+struct cn20k_outb_priv_data {
+ void *userdata;
+ /* Rlen computation data */
+ struct cnxk_ipsec_outb_rlens rlens;
+ /* Back pointer to eth sec session */
+ struct cnxk_eth_sec_sess *eth_sec;
+ /* SA index */
+ uint32_t sa_idx;
+};
+
/* Rx and Tx routines */
void cn20k_eth_set_rx_function(struct rte_eth_dev *eth_dev);
void cn20k_eth_set_tx_function(struct rte_eth_dev *eth_dev);
+/* Security context setup */
+void cn20k_eth_sec_ops_override(void);
+
+/* SSO Work callback */
+void cn20k_eth_sec_sso_work_cb(uint64_t *gw, void *args, uint32_t
soft_exp_event);
+
#endif /* __CN20K_ETHDEV_H__ */
diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c
b/drivers/net/cnxk/cn20k_ethdev_sec.c
new file mode 100644
index 00..4284b726ee
--- /dev/null
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -0,0 +1,1182 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2024 Marvell.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+PLT_STATIC_ASSERT(offsetof(struct rte_pmd_cnxk_ipsec_inb_sa, ctx.ar_winbits) ==
+ offsetof(struct roc_ow_ipsec_inb_sa, ctx.ar_winbits));
+
+PLT_STATIC_ASSERT(offsetof(struct rte_pmd_cnxk_ipsec_outb_sa, ctx.mib_pkts) ==
+ offsetof(struct roc_ow_ipsec_outb_sa, ctx.mib_pkts));
+
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_CTX_MAX_CKEY_LEN == ROC_CTX_MAX_CKEY_LEN);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN ==
RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN);
+
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WIN_SIZE_MIN == ROC_AR_WIN_SIZE_MIN);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WIN_SIZE_MAX == ROC_AR_WIN_SIZE_MAX);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 ==
ROC_LOG_MIN_AR_WIN_SIZE_M1);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WINBITS_SZ == ROC_AR_WINBITS_SZ);
+
+static struct rte_cryptodev_capabilities cn20k_eth_sec_crypto_caps[] = {
+ { /* AES GCM */
+ .op = RTE_CRYPTO_
[PATCH v2 25/33] net/cnxk: store pool buffer size in lookup memory
From: Rahul Bhansali
Store the pool buffer size in lookup memory to calculate
mbuf start address for reassembly case in fastpath.
Also, restructured lookup memory data per port.
Signed-off-by: Rahul Bhansali
---
drivers/net/cnxk/cn20k_ethdev.c | 17 +
drivers/net/cnxk/cn20k_rxtx.h | 1 +
drivers/net/cnxk/cnxk_ethdev.h| 2 +
drivers/net/cnxk/cnxk_ethdev_dp.h | 29 ---
drivers/net/cnxk/cnxk_lookup.c| 61 +++
5 files changed, 98 insertions(+), 12 deletions(-)
diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c
index db8d08cb2a..740fdb7f76 100644
--- a/drivers/net/cnxk/cn20k_ethdev.c
+++ b/drivers/net/cnxk/cn20k_ethdev.c
@@ -319,6 +319,8 @@ cn20k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev,
uint16_t qid, uint16_t nb_
/* Data offset from data to start of mbuf is first_skip */
rxq->data_off = rq->first_skip;
rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
+ rxq->mp_buf_sz = (mp->elt_size + mp->header_size + mp->trailer_size) &
0x;
+ rxq->mp_buf_sz |= (uint64_t)mp->header_size << 32;
/* Setup security related info */
if (dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F) {
@@ -358,6 +360,18 @@ cn20k_nix_rx_queue_meta_aura_update(struct rte_eth_dev
*eth_dev)
cnxk_nix_lookup_mem_metapool_set(dev);
}
+static void
+cn20k_nix_rx_queue_bufsize_update(struct rte_eth_dev *eth_dev)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct cn20k_eth_rxq *rxq;
+
+ rxq = eth_dev->data->rx_queues[0];
+
+ /* Store bufsize in lookup mem */
+ cnxk_nix_lookup_mem_bufsize_set(dev, rxq->mp_buf_sz);
+}
+
static int
cn20k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
{
@@ -590,6 +604,9 @@ cn20k_nix_dev_start(struct rte_eth_dev *eth_dev)
if (roc_idev_nix_rx_inject_get(nix->port_id))
dev->rx_offload_flags |= NIX_RX_SEC_REASSEMBLY_F;
+ if (dev->rx_offload_flags & NIX_RX_REAS_F)
+ cn20k_nix_rx_queue_bufsize_update(eth_dev);
+
cn20k_eth_set_tx_function(eth_dev);
cn20k_eth_set_rx_function(eth_dev);
return 0;
diff --git a/drivers/net/cnxk/cn20k_rxtx.h b/drivers/net/cnxk/cn20k_rxtx.h
index e40edba69d..f23c16ec07 100644
--- a/drivers/net/cnxk/cn20k_rxtx.h
+++ b/drivers/net/cnxk/cn20k_rxtx.h
@@ -82,6 +82,7 @@ struct cn20k_eth_rxq {
uint64_t meta_aura;
uintptr_t meta_pool;
uint16_t rq;
+ uint64_t mp_buf_sz;
struct cnxk_timesync_info *tstamp;
} __plt_cache_aligned;
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 9b85927f48..daf80be51b 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -727,6 +727,8 @@ int cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev
*dev);
int cnxk_nix_lookup_mem_sa_base_clear(struct cnxk_eth_dev *dev);
int cnxk_nix_lookup_mem_metapool_set(struct cnxk_eth_dev *dev);
int cnxk_nix_lookup_mem_metapool_clear(struct cnxk_eth_dev *dev);
+int cnxk_nix_lookup_mem_bufsize_set(struct cnxk_eth_dev *dev, uint64_t size);
+int cnxk_nix_lookup_mem_bufsize_clear(struct cnxk_eth_dev *dev);
__rte_internal
int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev);
__rte_internal
diff --git a/drivers/net/cnxk/cnxk_ethdev_dp.h
b/drivers/net/cnxk/cnxk_ethdev_dp.h
index 100d22e759..b5836b491e 100644
--- a/drivers/net/cnxk/cnxk_ethdev_dp.h
+++ b/drivers/net/cnxk/cnxk_ethdev_dp.h
@@ -35,8 +35,11 @@
#define ERRCODE_ERRLEN_WIDTH 12
#define ERR_ARRAY_SZ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))
-#define SA_BASE_TBL_SZ (RTE_MAX_ETHPORTS * sizeof(uintptr_t))
-#define MEMPOOL_TBL_SZ (RTE_MAX_ETHPORTS * sizeof(uintptr_t))
+#define SA_BASE_OFFSET 8 /* offset in bytes */
+#define MEMPOOL_OFFSET 8 /* offset in bytes */
+#define BUFLEN_OFFSET 8 /* offset in bytes */
+#define LOOKUP_MEM_PORTDATA_SZ (SA_BASE_OFFSET + MEMPOOL_OFFSET +
BUFLEN_OFFSET)
+#define LOOKUP_MEM_PORTDATA_TOTAL_SZ (RTE_MAX_ETHPORTS *
LOOKUP_MEM_PORTDATA_SZ)
#define CNXK_NIX_UDP_TUN_BITMASK
\
((1ull << (RTE_MBUF_F_TX_TUNNEL_VXLAN >> 45)) |
\
@@ -174,20 +177,36 @@ static __rte_always_inline uintptr_t
cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem)
{
uintptr_t sa_base_tbl;
+ uint32_t offset;
sa_base_tbl = (uintptr_t)lookup_mem;
sa_base_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ;
- return *((const uintptr_t *)sa_base_tbl + port);
+ offset = port * LOOKUP_MEM_PORTDATA_SZ;
+ return *((const uintptr_t *)sa_base_tbl + offset / 8);
}
static __rte_always_inline uintptr_t
cnxk_nix_inl_metapool_get(uint16_t port, const void *lookup_mem)
{
uintptr_t metapool_tbl;
+ uint32_t offset;
metapool_tbl = (uintptr_t)lookup_mem;
- metapool_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ +
[PATCH v2 24/33] common/cnxk: update CPT RXC time config mbox for cn20k
From: Rahul Bhansali
Sync in CPT_RXC_TIME_CFG mbox as per new fields added for
cn20k and restructure to support it.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_mbox.h| 2 ++
drivers/common/cnxk/roc_nix_inl.c | 55 +--
drivers/common/cnxk/roc_nix_inl.h | 3 +-
drivers/net/cnxk/cn10k_ethdev.c | 5 +--
drivers/net/cnxk/cn20k_ethdev.c | 3 +-
5 files changed, 54 insertions(+), 14 deletions(-)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 22a7258074..6d927c7972 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -2468,6 +2468,8 @@ struct cpt_rxc_time_cfg_req {
uint16_t __io zombie_limit;
uint16_t __io active_thres;
uint16_t __io active_limit;
+ uint16_t __io queue_id;
+ uint64_t __io cpt_af_rxc_que_cfg;
};
/* Mailbox message format to request for CPT faulted engines */
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 6927de6505..8ade58e1a2 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -930,30 +930,65 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool
inb_inl_dev, uint32_t spi)
}
int
-roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags)
+roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t
max_wait_time)
{
struct idev_cfg *idev = idev_get_cfg();
- struct roc_cpt *roc_cpt;
+ struct nix_inl_dev *inl_dev = NULL;
+ struct cpt_rxc_time_cfg_req *req;
struct roc_cpt_rxc_time_cfg cfg;
+ struct roc_cpt *roc_cpt;
+ struct mbox *mbox;
+ int rc;
if (!idev)
return -EFAULT;
- PLT_SET_USED(max_frags);
-
roc_cpt = idev->cpt;
if (!roc_cpt) {
plt_err("Cannot support inline inbound, cryptodev not probed");
return -ENOTSUP;
}
- cfg.step = (max_wait_time * 1000 / ROC_NIX_INL_REAS_ACTIVE_LIMIT);
- cfg.zombie_limit = ROC_NIX_INL_REAS_ZOMBIE_LIMIT;
- cfg.zombie_thres = ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD;
- cfg.active_limit = ROC_NIX_INL_REAS_ACTIVE_LIMIT;
- cfg.active_thres = ROC_NIX_INL_REAS_ACTIVE_THRESHOLD;
+ cfg.step = req_cfg->step ? req_cfg->step :
+ (max_wait_time * 1000 /
ROC_NIX_INL_REAS_ACTIVE_LIMIT);
+ cfg.zombie_limit =
+ req_cfg->zombie_limit ? req_cfg->zombie_limit :
ROC_NIX_INL_REAS_ZOMBIE_LIMIT;
+ cfg.zombie_thres =
+ req_cfg->zombie_thres ? req_cfg->zombie_thres :
ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD;
+ cfg.active_limit =
+ req_cfg->active_limit ? req_cfg->active_limit :
ROC_NIX_INL_REAS_ACTIVE_LIMIT;
+ cfg.active_thres =
+ req_cfg->active_thres ? req_cfg->active_thres :
ROC_NIX_INL_REAS_ACTIVE_THRESHOLD;
- return roc_cpt_rxc_time_cfg(roc_cpt, &cfg);
+ if (roc_model_is_cn10k())
+ return roc_cpt_rxc_time_cfg(roc_cpt, &cfg);
+
+ inl_dev = idev->nix_inl_dev;
+ if (!inl_dev) {
+ plt_err("Cannot support RXC config, inlinedev is not probed");
+ return -ENOTSUP;
+ }
+
+ mbox = mbox_get((&inl_dev->dev)->mbox);
+
+ req = mbox_alloc_msg_cpt_rxc_time_cfg(mbox);
+ if (req == NULL) {
+ rc = -ENOSPC;
+ goto exit;
+ }
+
+ req->blkaddr = 0;
+ req->queue_id = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
+ req->step = cfg.step;
+ req->zombie_limit = cfg.zombie_limit;
+ req->zombie_thres = cfg.zombie_thres;
+ req->active_limit = cfg.active_limit;
+ req->active_thres = cfg.active_thres;
+
+ rc = mbox_process(mbox);
+exit:
+ mbox_put(mbox);
+ return rc;
}
static void
diff --git a/drivers/common/cnxk/roc_nix_inl.h
b/drivers/common/cnxk/roc_nix_inl.h
index 10bf7d5c25..2db3a0d0f2 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -157,7 +157,8 @@ int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq);
bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix);
struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(struct roc_nix *roc_nix);
int __roc_api roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t
tag_const, uint8_t tt);
-int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t
max_frags);
+int __roc_api roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg
*req_cfg,
+ uint32_t max_wait_time);
int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena,
bool inb_inl_dev,
uint8_t profile_id);
int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena);
diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index 3f8c66615d..e491854cb2 100644
[PATCH v2 28/33] common/cnxk: enable allmulti mode on rpm/cgx VF
From: Monendra Singh Kushwaha
This patch enables allmulti mode on rpm/cgx vf devices.
Signed-off-by: Monendra Singh Kushwaha
---
.mailmap | 1 +
drivers/common/cnxk/roc_mbox.h| 1 +
drivers/common/cnxk/roc_nix_npc.c | 10 +++---
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/.mailmap b/.mailmap
index a03d3cfb59..d5eb506ad5 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1059,6 +1059,7 @@ Mohammed Gamal
Mohsin Kazmi
Mohsin Mazhar Shaikh
Mohsin Shaikh
+Monendra Singh Kushwaha
Morten Brørup
Moti Haimovsky
Muhammad Ahmad
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 6d927c7972..a82d120d1d 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1848,6 +1848,7 @@ struct nix_rx_mode {
#define NIX_RX_MODE_UCASTBIT(0)
#define NIX_RX_MODE_PROMISC BIT(1)
#define NIX_RX_MODE_ALLMULTI BIT(2)
+#define NIX_RX_MODE_USE_MCE BIT(3)
uint16_t __io mode;
};
diff --git a/drivers/common/cnxk/roc_nix_npc.c
b/drivers/common/cnxk/roc_nix_npc.c
index 8c4a5753ee..1d445c0d92 100644
--- a/drivers/common/cnxk/roc_nix_npc.c
+++ b/drivers/common/cnxk/roc_nix_npc.c
@@ -101,7 +101,7 @@ roc_nix_npc_mcast_config(struct roc_nix *roc_nix, bool
mcast_enable,
struct nix_rx_mode *req;
int rc = -ENOSPC;
- if (roc_nix_is_vf_or_sdp(roc_nix)) {
+ if (roc_nix_is_sdp(roc_nix) || roc_nix_is_lbk(roc_nix)) {
rc = 0;
goto exit;
}
@@ -110,9 +110,13 @@ roc_nix_npc_mcast_config(struct roc_nix *roc_nix, bool
mcast_enable,
if (req == NULL)
goto exit;
- if (mcast_enable)
+ if (mcast_enable) {
req->mode = NIX_RX_MODE_ALLMULTI;
- if (prom_enable)
+ if (dev_is_vf(&nix->dev))
+ req->mode |= NIX_RX_MODE_USE_MCE;
+ }
+
+ if (prom_enable && !dev_is_vf(&nix->dev))
req->mode = NIX_RX_MODE_PROMISC;
rc = mbox_process(mbox);
--
2.34.1
[PATCH v2 29/33] common/cnxk: fix inbound IPsec sa setup
Make sure the w2 in inbound SA is set for inline IPsec have
L3 header on errors.
Fixes: 350b7a536a51 ("common/cnxk: enable L3 header write back in SA")
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/cnxk_security.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/cnxk_security.c
b/drivers/common/cnxk/cnxk_security.c
index 3a747ed441..a3c06c1e88 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -315,7 +315,7 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
/* Initialize the SA */
roc_ot_ipsec_inb_sa_init(sa);
- w2.u64 = 0;
+ w2.u64 = sa->w2.u64;
rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->w8.s.salt,
sa->hmac_opad_ipad, ipsec_xfrm,
crypto_xfrm);
--
2.34.1
[PATCH v2 26/33] net/cnxk: inline IPsec Rx support for cn20k
From: Rahul Bhansali
Inline IPsec Rx support for cn20k
Signed-off-by: Rahul Bhansali
---
drivers/event/cnxk/cn20k_worker.h | 4 +-
drivers/net/cnxk/cn20k_rx.h | 736 --
2 files changed, 688 insertions(+), 52 deletions(-)
diff --git a/drivers/event/cnxk/cn20k_worker.h
b/drivers/event/cnxk/cn20k_worker.h
index b014e549b9..2366196d9d 100644
--- a/drivers/event/cnxk/cn20k_worker.h
+++ b/drivers/event/cnxk/cn20k_worker.h
@@ -24,7 +24,7 @@ cn20k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf,
uint8_t port_id, const ui
struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
cn20k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag, (struct
rte_mbuf *)mbuf, lookup_mem,
- mbuf_init | ((uint64_t)port_id) << 48, cpth,
sa_base, flags);
+ mbuf_init | ((uint64_t)port_id) << 48, cpth,
sa_base, 0, flags);
}
static void
@@ -83,7 +83,7 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const
uint32_t flags, struc
/* Mark mempool obj as "get" as it is alloc'ed by NIX */
RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
- cn20k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
mbuf_init, cpth, sa_base,
+ cn20k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
mbuf_init, cpth, sa_base, 0,
flags);
if (flags & NIX_RX_OFFLOAD_TSTAMP_F)
diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index 01bf483787..b54d9df662 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -82,6 +82,42 @@ union mbuf_initializer {
uint64_t value;
};
+static __rte_always_inline void
+nix_sec_flush_meta_burst(uint16_t lmt_id, uint64_t data, uint16_t lnum,
uintptr_t aura_handle)
+{
+ uint64_t pa;
+
+ /* Prepare PA and Data */
+ pa = roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_FREE0;
+ pa |= ((data & 0x7) << 4);
+
+ data >>= 3;
+ data <<= 19;
+ data |= (uint64_t)lmt_id;
+ data |= (uint64_t)(lnum - 1) << 12;
+
+ roc_lmt_submit_steorl(data, pa);
+}
+
+static __rte_always_inline void
+nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff, uintptr_t
aura_handle)
+{
+ uint64_t pa;
+
+ /* laddr is pointing to first pointer */
+ laddr -= 8;
+
+ /* Trigger free either on lmtline full or different aura handle */
+ pa = roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_FREE0;
+
+ /* Update aura handle */
+ *(uint64_t *)laddr =
+ (((uint64_t)(loff & 0x1) << 32) |
roc_npa_aura_handle_to_aura(aura_handle));
+
+ pa |= ((uint64_t)(loff >> 1) << 4);
+ roc_lmt_submit_steorl(lmt_id, pa);
+}
+
static __rte_always_inline uint64_t
nix_clear_data_off(uint64_t oldval)
{
@@ -101,6 +137,56 @@ nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)
return (struct rte_mbuf *)(buff - data_off);
}
+static __rte_always_inline uint64_t
+nix_sec_meta_to_mbuf_sc(uint64_t cq_w5, uint64_t cpth, const uint64_t sa_base,
+ struct rte_mbuf *mbuf, uint16_t *len, uint64_t
*mbuf_init,
+ const uint16_t flags)
+{
+ const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s
*)cpth;
+ struct cn20k_inb_priv_data *inb_priv;
+ uint64_t ol_flags, w3 = hdr->w3.u64;
+ uint32_t sa_idx;
+ uint16_t ucc;
+ void *inb_sa;
+
+ /* Get SPI from CPT_PARSE_S's cookie(already swapped) */
+ sa_idx = hdr->w0.cookie;
+ inb_sa = roc_nix_inl_ow_ipsec_inb_sa(sa_base, sa_idx);
+ inb_priv = roc_nix_inl_ow_ipsec_inb_sa_sw_rsvd(inb_sa);
+
+ /* Cryptodev injected packet can be identified from SA IDX 0x,
and
+* Ethdev injected packet can be identified with match ID 0x.
+*/
+ if (flags & NIX_RX_REAS_F && !hdr->w2.pkt_inline) {
+ *mbuf_init = (*mbuf_init & ~(BIT_ULL(16) - 1)) | mbuf->data_off;
+ if (hdr->w0.match_id == 0xU)
+ *rte_security_dynfield(mbuf) =
(uint64_t)inb_priv->userdata;
+ } else {
+ /* Update dynamic field with userdata */
+ *rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata;
+ }
+
+ *len = ((w3 >> 48) & 0x) + ((cq_w5 >> 16) & 0xFF) - (cq_w5 & 0xFF);
+
+ /* Get ucc from cpt parse header */
+ ucc = w3 & 0xFF;
+ ol_flags = ((CPT_COMP_HWGOOD_MASK & (1U << ucc)) ?
+ RTE_MBUF_F_RX_SEC_OFFLOAD :
+ RTE_MBUF_F_RX_SEC_OFFLOAD |
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED);
+
+ ucc = (w3 >> 8) & 0xFF;
+ if (ucc && ucc < ROC_IE_OW_UCC_SUCCESS_PKT_IP_BADCSUM) {
+ ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
+ } else {
+ ucc += 3; /* To make codes in 0xFx series except 0 */
+
[PATCH v2 27/33] event/cnxk: inline IPsec Rx support for cn20k
From: Rahul Bhansali
Inline IPsec Rx support for cn20k
Signed-off-by: Rahul Bhansali
---
doc/guides/rel_notes/release_25_03.rst | 1 +
drivers/event/cnxk/cn20k_worker.h | 111 -
2 files changed, 108 insertions(+), 4 deletions(-)
diff --git a/doc/guides/rel_notes/release_25_03.rst
b/doc/guides/rel_notes/release_25_03.rst
index ca67c17c5c..6a7b3b5803 100644
--- a/doc/guides/rel_notes/release_25_03.rst
+++ b/doc/guides/rel_notes/release_25_03.rst
@@ -116,6 +116,7 @@ New Features
* **Updated Marvell cnxk net driver.**
* Added flow rules support for CN20K SoC.
+ * Added Inline IPsec support for CN20K SoC.
* **Updated NVIDIA mlx5 driver.**
diff --git a/drivers/event/cnxk/cn20k_worker.h
b/drivers/event/cnxk/cn20k_worker.h
index 2366196d9d..6ed1f78a86 100644
--- a/drivers/event/cnxk/cn20k_worker.h
+++ b/drivers/event/cnxk/cn20k_worker.h
@@ -22,9 +22,13 @@ cn20k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf,
uint8_t port_id, const ui
const uint64_t mbuf_init =
0x10001ULL | RTE_PKTMBUF_HEADROOM | (flags &
NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
+ uint64_t buf_sz = 0;
+
+ if (flags & NIX_RX_REAS_F)
+ buf_sz = cnxk_nix_inl_bufsize_get(port_id, lookup_mem);
cn20k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag, (struct
rte_mbuf *)mbuf, lookup_mem,
- mbuf_init | ((uint64_t)port_id) << 48, cpth,
sa_base, 0, flags);
+ mbuf_init | ((uint64_t)port_id) << 48, cpth,
sa_base, buf_sz, flags);
}
static void
@@ -47,14 +51,20 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const
uint32_t flags, struc
{
uint64_t mbuf_init = 0x10001ULL | RTE_PKTMBUF_HEADROOM;
struct cnxk_timesync_info *tstamp = ws->tstamp[port_id];
+ uint8_t m_sz = sizeof(struct rte_mbuf);
void *lookup_mem = ws->lookup_mem;
uintptr_t lbase = ws->lmt_base;
+ uint64_t meta_aura = 0, laddr;
struct rte_event_vector *vec;
uint16_t nb_mbufs, non_vec;
+ struct rte_mempool *mp;
+ uint16_t lmt_id, d_off;
struct rte_mbuf **wqe;
struct rte_mbuf *mbuf;
uint64_t sa_base = 0;
+ uint64_t buf_sz = 0;
uintptr_t cpth = 0;
+ uint8_t loff = 0;
int i;
mbuf_init |= ((uint64_t)port_id) << 48;
@@ -69,12 +79,39 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const
uint32_t flags, struc
if (flags & NIX_RX_OFFLOAD_TSTAMP_F && tstamp)
mbuf_init |= 8;
+ if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
+ mp = (struct rte_mempool *)cnxk_nix_inl_metapool_get(port_id,
lookup_mem);
+ if (mp)
+ meta_aura = mp->pool_id;
+ }
+
nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);
nb_mbufs = cn20k_nix_recv_pkts_vector(&mbuf_init, wqe, nb_mbufs, flags
| NIX_RX_VWQE_F,
- lookup_mem, tstamp, lbase, 0);
+ lookup_mem, tstamp, lbase,
meta_aura);
wqe += nb_mbufs;
non_vec = vec->nb_elem - nb_mbufs;
+ if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {
+ uint64_t sg_w1;
+
+ mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] - sizeof(struct
rte_mbuf));
+ /* Pick first mbuf's aura handle assuming all
+* mbufs are from a vec and are from same RQ.
+*/
+ if (!meta_aura)
+ meta_aura = mbuf->pool->pool_id;
+ ROC_LMT_BASE_ID_GET(lbase, lmt_id);
+ laddr = lbase;
+ laddr += 8;
+ sg_w1 = *(uint64_t *)(((uintptr_t)wqe[0]) + 72);
+ d_off = sg_w1 - (uintptr_t)mbuf;
+ sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);
+ sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
+
+ if (flags & NIX_RX_REAS_F)
+ buf_sz = cnxk_nix_inl_bufsize_get(port_id, lookup_mem);
+ }
+
while (non_vec) {
struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];
@@ -83,8 +120,29 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const
uint32_t flags, struc
/* Mark mempool obj as "get" as it is alloc'ed by NIX */
RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
- cn20k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
mbuf_init, cpth, sa_base, 0,
- flags);
+ /* Translate meta to mbuf */
+ if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
+ const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
+
+ cpth = ((uintptr_t)mbuf + (uint16_t)d_off);
+
+ if (cq_w1 & BIT(11)) {
+
[PATCH v2 30/33] common/cnxk: add stats reset for inline device
From: Monendra Singh Kushwaha
This patch adds support to reset inline device stats.
Signed-off-by: Monendra Singh Kushwaha
---
drivers/common/cnxk/roc_nix_inl.h | 1 +
drivers/common/cnxk/roc_nix_inl_dev.c | 27 +++
drivers/common/cnxk/version.map | 1 +
3 files changed, 29 insertions(+)
diff --git a/drivers/common/cnxk/roc_nix_inl.h
b/drivers/common/cnxk/roc_nix_inl.h
index 2db3a0d0f2..dab4918535 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -130,6 +130,7 @@ void __roc_api roc_nix_inl_dev_lock(void);
void __roc_api roc_nix_inl_dev_unlock(void);
int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);
int __roc_api roc_nix_inl_dev_stats_get(struct roc_nix_stats *stats);
+int __roc_api roc_nix_inl_dev_stats_reset(void);
int __roc_api roc_nix_inl_dev_cpt_setup(bool use_inl_dev_sso);
int __roc_api roc_nix_inl_dev_cpt_release(void);
bool __roc_api roc_nix_inl_dev_is_multi_channel(void);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index 041ccd9c13..2e753440b7 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -1295,6 +1295,33 @@ roc_nix_inl_dev_stats_get(struct roc_nix_stats *stats)
return 0;
}
+int
+roc_nix_inl_dev_stats_reset(void)
+{
+ struct idev_cfg *idev = idev_get_cfg();
+ struct nix_inl_dev *inl_dev = NULL;
+ struct mbox *mbox;
+ int rc;
+
+ if (idev && idev->nix_inl_dev)
+ inl_dev = idev->nix_inl_dev;
+
+ if (!inl_dev)
+ return -EINVAL;
+
+ mbox = mbox_get((&inl_dev->dev)->mbox);
+
+ if (mbox_alloc_msg_nix_stats_rst(mbox) == NULL) {
+ rc = -ENOMEM;
+ goto exit;
+ }
+
+ rc = mbox_process(mbox);
+exit:
+ mbox_put(mbox);
+ return rc;
+}
+
int
roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
{
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 36eb46e3a1..cdbfc1d39a 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -252,6 +252,7 @@ INTERNAL {
roc_nix_inl_dev_is_multi_channel;
roc_nix_inl_dev_is_probed;
roc_nix_inl_dev_stats_get;
+ roc_nix_inl_dev_stats_reset;
roc_nix_inl_dev_lock;
roc_nix_inl_dev_rq;
roc_nix_inl_dev_rq_get;
--
2.34.1
[PATCH v2 32/33] net/cnxk: update MC address list configure API
From: Satha Rao
Return -ENOSPC when there is no space to update the complete MC address
list, without flushing the existing list of addresses.
Signed-off-by: Satha Rao
---
drivers/net/cnxk/cnxk_ethdev_ops.c | 32 ++
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c
b/drivers/net/cnxk/cnxk_ethdev_ops.c
index 5b0948e07a..9970c5ff5c 100644
--- a/drivers/net/cnxk/cnxk_ethdev_ops.c
+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c
@@ -1117,17 +1117,14 @@ cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
return 0;
}
-int
-cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
- struct rte_ether_addr *mc_addr_set,
- uint32_t nb_mc_addr)
+static inline int
+nix_mc_addr_list_flush(struct rte_eth_dev *eth_dev)
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
struct rte_eth_dev_data *data = eth_dev->data;
struct rte_ether_addr null_mac_addr;
struct roc_nix *nix = &dev->nix;
- int rc, index;
- uint32_t i;
+ int i, rc = 0;
memset(&null_mac_addr, 0, sizeof(null_mac_addr));
@@ -1148,15 +1145,34 @@ cnxk_nix_mc_addr_list_configure(struct rte_eth_dev
*eth_dev,
}
}
+ return rc;
+}
+
+int
+cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev, struct
rte_ether_addr *mc_addr_set,
+ uint32_t nb_mc_addr)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct rte_eth_dev_data *data = eth_dev->data;
+ struct roc_nix *nix = &dev->nix;
+ int index, mc_addr_cnt = 0;
+ uint32_t i;
+
if (!mc_addr_set || !nb_mc_addr)
- return 0;
+ return nix_mc_addr_list_flush(eth_dev);
+
+ /* Count multicast MAC addresses in list */
+ for (i = 0; i < dev->max_mac_entries; i++)
+ if (rte_is_multicast_ether_addr(&data->mac_addrs[i]))
+ mc_addr_cnt++;
/* Check for available space */
if (nb_mc_addr >
- ((uint32_t)(dev->max_mac_entries - dev->dmac_filter_count))) {
+ ((uint32_t)(dev->max_mac_entries - (dev->dmac_filter_count -
mc_addr_cnt {
plt_err("No space is available to add multicast filters");
return -ENOSPC;
}
+ nix_mc_addr_list_flush(eth_dev);
/* Multicast addresses are to be installed */
for (i = 0; i < nb_mc_addr; i++) {
--
2.34.1
[PATCH v2 31/33] common/cnxk: change the error log to a debug log
From: Srujana Challa
This patch updates the error log to a debug log since
it is not needed.
Signed-off-by: Srujana Challa
---
drivers/common/cnxk/roc_nix_inl_dev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index 2e753440b7..376582f5db 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -1250,7 +1250,7 @@ roc_nix_inl_dev_qptr_get(uint8_t qid)
inl_dev = idev->nix_inl_dev;
if (!inl_dev) {
- plt_err("Inline Device could not be detected");
+ plt_nix_dbg("Inline Device could not be detected");
return NULL;
}
if (!inl_dev->attach_cptlf) {
--
2.34.1
[PATCH v2 18/33] common/cnxk: support for inline inbound queue
In CN20k, since we have 16 Inline inbound queues possible, add
support to attach inline inbound queue directly to the application
instead of getting it attached to CPT PF.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/roc_features.h | 12 +
drivers/common/cnxk/roc_mbox.h | 82 ++
drivers/common/cnxk/roc_nix.h | 1 +
drivers/common/cnxk/roc_nix_fc.c | 24 +-
drivers/common/cnxk/roc_nix_inl.c | 281
drivers/common/cnxk/roc_nix_inl.h | 6 +-
drivers/common/cnxk/roc_nix_inl_dev.c | 347 +
drivers/common/cnxk/roc_nix_inl_priv.h | 28 +-
drivers/common/cnxk/roc_nix_priv.h | 6 +
drivers/common/cnxk/roc_platform.h | 1 +
drivers/net/cnxk/cnxk_ethdev.h | 2 +-
drivers/net/cnxk/cnxk_ethdev_sec.c | 9 +-
12 files changed, 686 insertions(+), 113 deletions(-)
diff --git a/drivers/common/cnxk/roc_features.h
b/drivers/common/cnxk/roc_features.h
index 59c09fbc85..49a563ef95 100644
--- a/drivers/common/cnxk/roc_features.h
+++ b/drivers/common/cnxk/roc_features.h
@@ -102,4 +102,16 @@ roc_feature_dpi_has_priority(void)
return roc_model_is_cn10k();
}
+static inline bool
+roc_feature_nix_has_inl_multi_queue(void)
+{
+ return roc_model_is_cn20k();
+}
+
+static inline bool
+roc_feature_nix_has_inl_profile(void)
+{
+ return roc_model_is_cn20k();
+}
+
#endif
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index beb7fb6e62..fbea15690b 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -183,11 +183,19 @@ struct mbox_msghdr {
msg_rsp) \
M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
+ M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req,
\
+ cpt_flt_eng_info_rsp)
\
+ M(CPT_RX_INLINE_QALLOC, 0xA0A, cpt_rx_inline_qalloc, msg_req,
\
+ cpt_rx_inline_qalloc_rsp)
\
+ M(CPT_RX_INL_QUEUE_CFG, 0xA0B, cpt_rx_inl_queue_cfg,
\
+ cpt_rx_inline_qcfg_req, msg_rsp)\
M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
cpt_rx_inline_lf_cfg_msg, msg_rsp) \
M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)\
M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,\
cpt_eng_grp_rsp) \
+ M(CPT_SET_QUEUE_PRI, 0xBFB, cpt_set_que_pri, cpt_queue_pri_req_msg,
\
+ msg_rsp) \
/* REE mbox IDs (range 0xE00 - 0xFFF) */ \
M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)\
M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,\
@@ -343,6 +351,8 @@ struct mbox_msghdr {
nix_rx_inl_profile_cfg_rsp)
\
M(NIX_RX_INLINE_LF_CFG, 0x8032, nix_rx_inl_lf_cfg,
nix_rx_inl_lf_cfg_req, \
msg_rsp)
\
+ M(NIX_RX_INL_QUEUE_CFG, 0x8033, nix_rx_inl_queue_cfg,
\
+ nix_rx_inline_qcfg_req, msg_rsp) \
/* MCS mbox IDs (range 0xa000 - 0xbFFF) */
\
M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,
\
mcs_alloc_rsrc_rsp)
\
@@ -1966,6 +1976,34 @@ struct nix_mcast_grp_update_rsp {
uint32_t __io mce_start_index;
};
+#define IPSEC_GEN_CFG_EGRP GENMASK_ULL(50, 48)
+#define IPSEC_GEN_CFG_OPCODE GENMASK_ULL(47, 32)
+#define IPSEC_GEN_CFG_PARAM1 GENMASK_ULL(31, 16)
+#define IPSEC_GEN_CFG_PARAM2 GENMASK_ULL(15, 0)
+
+#define CPT_INST_QSEL_BLOCK GENMASK_ULL(28, 24)
+#define CPT_INST_QSEL_PF_FUNC GENMASK_ULL(23, 8)
+#define CPT_INST_QSEL_SLOTGENMASK_ULL(7, 0)
+
+#define CPT_INST_CREDIT_HYST GENMASK_ULL(61, 56)
+#define CPT_INST_CREDIT_TH GENMASK_ULL(53, 32)
+#define CPT_INST_CREDIT_BPID GENMASK_ULL(30, 22)
+#define CPT_INST_CREDIT_CNT GENMASK_ULL(21, 0)
+
+/* Per queue NIX inline IPSec configuration */
+struct nix_rx_inline_qcfg_req {
+ struct mbox_msghdr hdr;
+ uint32_t __io cpt_credit;
+ uint32_t __io credit_th;
+ uint16_t __io cpt_pf_func;
+ uint16_t __io bpid;
+ uint8_t __io cpt_slot;
+ uint8_t __io rx_queue_id;
+ uint8_t __io enable;
+ uint8_t __io hysteresis;
+ uint
[PATCH v2 33/33] common/cnxk: move interrupt handling to platform-specific
From: Satha Rao
This change refactors the interrupt handling to be platform-specific.
Some platforms directly call ioctls, while others provide a library API
for the same functionality. Moving the interrupt handling to
platform-specific implementations enhances clarity and maintainability.
Signed-off-by: Satha Rao
---
drivers/common/cnxk/roc_irq.c | 239 +++--
drivers/common/cnxk/roc_platform.c | 231
drivers/common/cnxk/roc_platform.h | 7 +
3 files changed, 259 insertions(+), 218 deletions(-)
diff --git a/drivers/common/cnxk/roc_irq.c b/drivers/common/cnxk/roc_irq.c
index 0b21b9e2d9..b1d41346c0 100644
--- a/drivers/common/cnxk/roc_irq.c
+++ b/drivers/common/cnxk/roc_irq.c
@@ -7,243 +7,37 @@
#if defined(__linux__)
-#include
-#include
-#include
-#include
-#include
-
-#define MSIX_IRQ_SET_BUF_LEN
\
- (sizeof(struct vfio_irq_set) + sizeof(int) * \
- ((uint32_t)plt_intr_max_intr_get(intr_handle)))
-
-static int
-irq_get_info(struct plt_intr_handle *intr_handle)
-{
- struct vfio_irq_info irq = {.argsz = sizeof(irq)};
- int rc, vfio_dev_fd;
-
- irq.index = VFIO_PCI_MSIX_IRQ_INDEX;
-
- vfio_dev_fd = plt_intr_dev_fd_get(intr_handle);
- rc = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
- if (rc < 0) {
- plt_err("Failed to get IRQ info rc=%d errno=%d", rc, errno);
- return rc;
- }
-
- plt_base_dbg("Flags=0x%x index=0x%x count=0x%x max_intr_vec_id=0x%x",
-irq.flags, irq.index, irq.count, PLT_MAX_RXTX_INTR_VEC_ID);
-
- if (irq.count == 0) {
- plt_err("HW max=%d > PLT_MAX_RXTX_INTR_VEC_ID: %d", irq.count,
- PLT_MAX_RXTX_INTR_VEC_ID);
- plt_intr_max_intr_set(intr_handle, PLT_MAX_RXTX_INTR_VEC_ID);
- } else {
- if (plt_intr_max_intr_set(intr_handle, irq.count))
- return -1;
- }
-
- return 0;
-}
-
-static int
-irq_config(struct plt_intr_handle *intr_handle, unsigned int vec)
-{
- char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
- struct vfio_irq_set *irq_set;
- int len, rc, vfio_dev_fd;
- int32_t *fd_ptr;
-
- if (vec > (uint32_t)plt_intr_max_intr_get(intr_handle)) {
- plt_err("vector=%d greater than max_intr=%d", vec,
- plt_intr_max_intr_get(intr_handle));
- return -EINVAL;
- }
-
- len = sizeof(struct vfio_irq_set) + sizeof(int32_t);
-
- irq_set = (struct vfio_irq_set *)irq_set_buf;
- irq_set->argsz = len;
-
- irq_set->start = vec;
- irq_set->count = 1;
- irq_set->flags =
- VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
- irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
-
- /* Use vec fd to set interrupt vectors */
- fd_ptr = (int32_t *)&irq_set->data[0];
- fd_ptr[0] = plt_intr_efds_index_get(intr_handle, vec);
-
- vfio_dev_fd = plt_intr_dev_fd_get(intr_handle);
- rc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
- if (rc)
- plt_err("Failed to set_irqs vector=0x%x rc=%d", vec, rc);
-
- return rc;
-}
-
-static int
-irq_init(struct plt_intr_handle *intr_handle)
-{
- char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
- struct vfio_irq_set *irq_set;
- int len, rc, vfio_dev_fd;
- int32_t *fd_ptr;
- uint32_t i;
-
- len = sizeof(struct vfio_irq_set) +
- sizeof(int32_t) * plt_intr_max_intr_get(intr_handle);
-
- irq_set = (struct vfio_irq_set *)irq_set_buf;
- irq_set->argsz = len;
- irq_set->start = 0;
- irq_set->count = plt_intr_max_intr_get(intr_handle);
- irq_set->flags =
- VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
- irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
-
- fd_ptr = (int32_t *)&irq_set->data[0];
- for (i = 0; i < irq_set->count; i++)
- fd_ptr[i] = -1;
-
- vfio_dev_fd = plt_intr_dev_fd_get(intr_handle);
- rc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
- if (rc)
- plt_err("Failed to set irqs vector rc=%d", rc);
-
- return rc;
-}
-
int
dev_irqs_disable(struct plt_intr_handle *intr_handle)
{
- /* Clear max_intr to indicate re-init next time */
- plt_intr_max_intr_set(intr_handle, 0);
- return plt_intr_disable(intr_handle);
+ return plt_irq_disable(intr_handle);
}
int
dev_irq_reconfigure(struct plt_intr_handle *intr_handle, uint16_t max_intr)
{
- /* Disable interrupts if enabled. */
- if (plt_intr_max_intr_get(intr_handle))
- dev_irqs_disable(intr_handle);
-
- plt_intr_max_intr_set(intr_handle, max_intr);
- return irq_init(intr_handle);
+ return plt_irq_reconfigure(intr_handle, max_intr);
}
int
[PATCH v2 22/33] common/cnxk: support for NPC inline rule for cn20k
Use UCAST_CPT in cn20k as opposed to UCAST_IPSEC in cn10k
for inline IPsec rule.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/hw/nix.h| 1 +
drivers/common/cnxk/roc_npc.c | 15 +++
drivers/common/cnxk/roc_npc_mcam.c | 7 ---
drivers/common/cnxk/roc_npc_mcam_dump.c | 5 +
drivers/common/cnxk/roc_npc_priv.h | 8
5 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
index e4d8d285d5..d16fa3b3ec 100644
--- a/drivers/common/cnxk/hw/nix.h
+++ b/drivers/common/cnxk/hw/nix.h
@@ -645,6 +645,7 @@
#define NIX_RX_ACTIONOP_RSS (0x4ull)
#define NIX_RX_ACTIONOP_PF_FUNC_DROP (0x5ull)
#define NIX_RX_ACTIONOP_MIRROR (0x6ull)
+#define NIX_RX_ACTIONOP_UCAST_CPT(0x7ull)
#define NIX_RX_ACTIONOP_DEFAULT (0xfull)
#define NIX_RX_VTAGACTION_VTAG0_RELPTR (0x0ull)
diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index 138f12f6d8..94d5cc84f8 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -568,6 +568,7 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct
roc_npc_attr *attr,
struct npc *npc = roc_npc_to_npc_priv(roc_npc);
const struct roc_npc_action *sec_action = NULL;
const struct roc_npc_action_sample *act_sample;
+ struct roc_nix *roc_nix = roc_npc->roc_nix;
const struct roc_npc_action_mark *act_mark;
const struct roc_npc_action_meter *act_mtr;
const struct roc_npc_action_queue *act_q;
@@ -576,7 +577,6 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct
roc_npc_attr *attr,
uint8_t has_spi_to_sa_act = 0;
int sel_act, req_act = 0;
uint16_t pf_func, vf_id;
- struct roc_nix *roc_nix;
int errcode = 0;
int mark = 0;
int rq = 0;
@@ -885,8 +885,15 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct
roc_npc_attr *attr,
} else if (req_act & ROC_NPC_ACTION_TYPE_RSS) {
flow->npc_action = NIX_RX_ACTIONOP_UCAST;
} else if (req_act & ROC_NPC_ACTION_TYPE_SEC) {
- flow->npc_action = NIX_RX_ACTIONOP_UCAST_IPSEC;
- flow->npc_action |= (uint64_t)rq << 20;
+ if (roc_model_is_cn20k()) {
+ flow->npc_action = NIX_RX_ACTIONOP_UCAST_CPT;
+ flow->npc_action |= (uint64_t)rq << 20;
+ flow->npc_action2 =
+ roc_nix_inl_inb_ipsec_profile_id_get(roc_nix,
true) << 8;
+ } else {
+ flow->npc_action = NIX_RX_ACTIONOP_UCAST_IPSEC;
+ flow->npc_action |= (uint64_t)rq << 20;
+ }
} else if (req_act & (ROC_NPC_ACTION_TYPE_FLAG |
ROC_NPC_ACTION_TYPE_MARK)) {
flow->npc_action = NIX_RX_ACTIONOP_UCAST;
} else if (req_act & ROC_NPC_ACTION_TYPE_COUNT) {
@@ -1550,7 +1557,7 @@ npc_inline_dev_ipsec_action_free(struct npc *npc, struct
roc_npc_flow *flow)
inl_dev = idev->nix_inl_dev;
if (flow->nix_intf == NIX_INTF_RX && inl_dev && inl_dev->ipsec_index &&
- ((flow->npc_action & 0xF) == NIX_RX_ACTIONOP_UCAST_IPSEC)) {
+ roc_npc_action_is_rx_inline(flow->npc_action)) {
inl_dev->curr_ipsec_idx--;
inl_dev->ipsec_index[inl_dev->curr_ipsec_idx] = flow->mcam_id;
flow->enable = 0;
diff --git a/drivers/common/cnxk/roc_npc_mcam.c
b/drivers/common/cnxk/roc_npc_mcam.c
index 5db72c22ae..3aa7ff56a9 100644
--- a/drivers/common/cnxk/roc_npc_mcam.c
+++ b/drivers/common/cnxk/roc_npc_mcam.c
@@ -747,7 +747,7 @@ npc_mcam_set_channel(struct roc_npc_flow *flow, struct
npc_cn20k_mcam_write_entr
chan = (channel | NIX_CHAN_CPT_CH_START);
mask = (chan_mask | NIX_CHAN_CPT_CH_START);
} else {
- if (!(flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) {
+ if (!roc_npc_action_is_rx_inline(flow->npc_action)) {
/*
* Clear bits 10 & 11 corresponding to CPT
* channel. By default, rules should match
@@ -951,6 +951,7 @@ npc_mcam_alloc_and_write(struct npc *npc, struct
roc_npc_flow *flow, struct npc_
if (flow->nix_intf == NIX_INTF_RX)
flow->npc_action |= (uint64_t)flow->recv_queue << 20;
req.entry_data.action = flow->npc_action;
+ req.entry_data.action2 = flow->npc_action2;
/*
* Driver sets vtag action on per interface basis, not
@@ -973,7 +974,7 @@ npc_mcam_alloc_and_write(struct npc *npc, struct
roc_npc_flow *flow, struct npc_
if (flow->nix_intf == NIX_INTF_RX) {
if (inl_dev && inl_dev->is_multi_channel &&
- (flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) {
+ roc_npc_action
[PATCH v3 06/33] common/cnxk: enable IE with cn9k and cn10k only
From: Anoob Joseph
IE engines are present only with cn9k and cn10k.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/roc_cpt.c | 43 +++
drivers/common/cnxk/roc_cpt.h | 3 +++
2 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 90433e2390..88f6044e60 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -624,9 +624,13 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf,
bool rxc_ena, uint16_t
for (i = 0; i < nb_lf; i++)
cpt->lf_blkaddr[i] = blkaddr[blknum];
- eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
-(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |
-(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);
+ if (roc_cpt_has_ie_engines())
+ eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
+(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |
+(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);
+ else
+ eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
+(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]);
if (roc_errata_cpt_has_ctx_fetch_issue()) {
ctx_ilen_valid = true;
@@ -1180,12 +1184,13 @@ int
roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr,
uint16_t sa_len)
{
- uintptr_t lmt_base = lf->lmt_base;
union cpt_res_s res, *hw_res;
uint64_t lmt_arg, io_addr;
struct cpt_inst_s *inst;
+ uintptr_t lmt_base;
uint16_t lmt_id;
uint64_t *dptr;
+ uint8_t egrp;
int i;
if (!plt_is_aligned(sa_cptr, 128)) {
@@ -1193,6 +1198,25 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr,
void *sa_cptr,
return -EINVAL;
}
+ if (lf == NULL) {
+ plt_err("Invalid CPT LF");
+ return -EINVAL;
+ }
+
+ if (lf->roc_cpt == NULL) {
+ if (roc_cpt_has_ie_engines())
+ egrp = ROC_CPT_DFLT_ENG_GRP_SE_IE;
+ else
+ egrp = ROC_CPT_DFLT_ENG_GRP_SE;
+ } else {
+ if (roc_cpt_has_ie_engines())
+ egrp = lf->roc_cpt->eng_grp[CPT_ENG_TYPE_IE];
+ else
+ egrp = lf->roc_cpt->eng_grp[CPT_ENG_TYPE_SE];
+ }
+
+ lmt_base = lf->lmt_base;
+
/* Use this lcore's LMT line as no one else is using it */
ROC_LMT_BASE_ID_GET(lmt_base, lmt_id);
inst = (struct cpt_inst_s *)lmt_base;
@@ -1225,7 +1249,7 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr,
void *sa_cptr,
inst->w4.s.opcode_minor = ROC_IE_OT_MINOR_OP_WRITE_SA;
inst->w7.s.cptr = (uint64_t)sa_cptr;
inst->w7.s.ctx_val = 1;
- inst->w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE_IE;
+ inst->w7.s.egrp = egrp;
lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;
io_addr = lf->io_addr | ROC_CN10K_CPT_INST_DW_M1 << 4;
@@ -1276,3 +1300,12 @@ roc_cpt_int_misc_cb_unregister(roc_cpt_int_misc_cb_t cb,
void *args)
int_cb.cb_args = NULL;
return 0;
}
+
+bool
+roc_cpt_has_ie_engines(void)
+{
+ if (roc_model_is_cn9k() || roc_model_is_cn10k())
+ return true;
+
+ return false;
+}
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 70129531eb..c8cf9354da 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -226,4 +226,7 @@ int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void
*sa_dptr, void *sa_c
void __roc_api roc_cpt_int_misc_cb_register(roc_cpt_int_misc_cb_t cb, void
*args);
int __roc_api roc_cpt_int_misc_cb_unregister(roc_cpt_int_misc_cb_t cb, void
*args);
+
+bool roc_cpt_has_ie_engines(void);
+
#endif /* _ROC_CPT_H_ */
--
2.34.1
[PATCH v3 08/33] common/cnxk: add CPT cn20k device enumeration
From: Anoob Joseph Add CPT cn20k device enumeration. Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_constants.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h index 67cd74b28a..ac492651de 100644 --- a/drivers/common/cnxk/roc_constants.h +++ b/drivers/common/cnxk/roc_constants.h @@ -55,6 +55,8 @@ #define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE #define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2 #define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3 +#define PCI_DEVID_CN20K_RVU_CPT_PF 0xA0F2 +#define PCI_DEVID_CN20K_RVU_CPT_VF 0xA0F3 #define PCI_DEVID_CN10K_ML_PF 0xA092 -- 2.34.1
[PATCH v3 14/33] common/cnxk: support for inline IPsec for cn20k
From: Rahul Bhansali
Support in NIX inline device for inbound and outbound SA init.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_cpt.h | 1 +
drivers/common/cnxk/roc_nix_inl.c | 62 ++-
drivers/common/cnxk/roc_nix_inl_dev.c | 22 ++
drivers/common/cnxk/roc_nix_inl_dp.h | 46
drivers/net/cnxk/cn10k_rxtx.h | 2 +
drivers/net/cnxk/cn20k_rxtx.h | 2 +
6 files changed, 116 insertions(+), 19 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 238f55eff4..37634793d4 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -66,6 +66,7 @@
#define ROC_CN20K_CPT_LMT_ARG ROC_CN10K_CPT_LMT_ARG
#define ROC_CN20K_DUAL_CPT_LMT_ARG ROC_CN10K_DUAL_CPT_LMT_ARG
+#define ROC_CN20K_CPT_INST_DW_M1 ROC_CN10K_CPT_INST_DW_M1
/* CPT helper macros */
#define ROC_CPT_AH_HDR_LEN 12
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 6b7532b1f0..db1969038a 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -404,12 +404,14 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);
/* CN9K SA size is different */
- if (roc_model_is_cn9k())
- inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
- else if (roc_nix->custom_inb_sa)
+ if (roc_nix->custom_inb_sa)
inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ;
- else
+ else if (roc_model_is_cn9k())
+ inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
+ else if (roc_model_is_cn10k())
inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
+ else
+ inb_sa_sz = ROC_NIX_INL_OW_IPSEC_INB_SA_SZ;
/* Alloc contiguous memory for Inbound SA's */
nix->inb_sa_sz = inb_sa_sz;
@@ -420,10 +422,14 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
plt_err("Failed to allocate memory for Inbound SA");
return -ENOMEM;
}
- if (roc_model_is_cn10k()) {
+
+ if (!roc_model_is_cn9k()) {
for (i = 0; i < max_sa; i++) {
sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
- roc_ot_ipsec_inb_sa_init(sa);
+ if (roc_model_is_cn10k())
+ roc_ot_ipsec_inb_sa_init(sa);
+ else
+ roc_ow_ipsec_inb_sa_init(sa);
}
}
@@ -841,7 +847,7 @@ nix_inl_eng_caps_get(struct nix *nix)
plt_err("LOAD FVC operation timed out");
return;
}
- } else {
+ } else if (roc_model_is_cn10k()) {
uint64_t lmt_arg, io_addr;
uint16_t lmt_id;
@@ -870,6 +876,35 @@ nix_inl_eng_caps_get(struct nix *nix)
plt_err("LOAD FVC operation timed out");
goto exit;
}
+ } else {
+ uint64_t lmt_arg, io_addr;
+ uint16_t lmt_id;
+
+ hw_res->cn20k.compcode = CPT_COMP_NOT_DONE;
+
+ /* Use this reserved LMT line as no one else is using it */
+ lmt_id = roc_plt_control_lmt_id_get();
+ lmt_base += ((uint64_t)lmt_id << ROC_LMT_LINE_SIZE_LOG2);
+
+ memcpy((void *)lmt_base, &inst, sizeof(inst));
+
+ lmt_arg = ROC_CN20K_CPT_LMT_ARG | (uint64_t)lmt_id;
+ io_addr = lf->io_addr | ROC_CN20K_CPT_INST_DW_M1 << 4;
+
+ roc_lmt_submit_steorl(lmt_arg, io_addr);
+ plt_io_wmb();
+
+ /* Wait until CPT instruction completes */
+ do {
+ res.u64[0] = __atomic_load_n(&hw_res->u64[0],
__ATOMIC_RELAXED);
+ if (unlikely(plt_tsc_cycles() > timeout))
+ break;
+ } while (res.cn20k.compcode == CPT_COMP_NOT_DONE);
+
+ if (res.cn20k.compcode != CPT_COMP_GOOD ||
res.cn20k.uc_compcode) {
+ plt_err("LOAD FVC operation timed out");
+ goto exit;
+ }
}
nix->cpt_eng_caps = plt_be_to_cpu_64(*rptr);
@@ -1127,8 +1162,11 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
/* CN9K SA size is different */
if (roc_model_is_cn9k())
sa_sz = ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ;
- else
+ else if (roc_model_is_cn10k())
sa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ;
+ else
+ sa_sz = ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ;
+
/* Alloc contiguous memory of outbound SA */
sa_base = plt_zmalloc(sa_sz * roc_nix->ipsec_out_max_sa,
ROC_NIX_INL_SA_BASE_ALIGN);
@@ -1136,10 +1174,14 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix
[PATCH v3 15/33] common/cnxk: support inline SA context invalidate
From: Rahul Bhansali
Add SA context invalidate support for cn20k.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/hw/cpt.h | 11 -
drivers/common/cnxk/roc_nix.h | 1 +
drivers/common/cnxk/roc_nix_inl.c | 37 ++-
3 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index f2c222a920..40987abbb9 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -44,7 +44,8 @@
#define CPT_LF_CTX_ENC_PKT_CNT (0x540ull)
#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull)
#define CPT_LF_CTX_DEC_PKT_CNT (0x560ull)
-#define CPT_LF_CTX_RELOAD (0x570ull)
+#define CPT_LF_CTX_RELOAD (0x570ull) /* [CN10k] */
+#define CPT_LF_CTX_INVAL (0x570ull) /* [CN20k] */
#define CPT_AF_LFX_CTL(a) (0x27000ull | (uint64_t)(a) << 3)
#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
@@ -126,6 +127,14 @@ union cpt_lf_ctx_reload {
} s;
};
+union cpt_lf_ctx_inval {
+ uint64_t u;
+ struct {
+ uint64_t cptr : 46;
+ uint64_t reserved_46_63 : 18;
+ } s;
+};
+
union cpt_lf_inprog {
uint64_t u;
struct cpt_lf_inprog_s {
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 15823ab16c..2597b8d56b 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -474,6 +474,7 @@ struct roc_nix {
bool custom_meta_aura_ena;
bool rx_inj_ena;
bool custom_inb_sa;
+ bool use_write_sa;
uint32_t root_sched_weight;
uint16_t inb_cfg_param1;
uint16_t inb_cfg_param2;
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index db1969038a..991a81b50d 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -1744,6 +1744,7 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa,
bool inb,
union cpt_lf_ctx_reload reload;
union cpt_lf_ctx_flush flush;
union cpt_lf_ctx_err err;
+ union cpt_lf_ctx_inval inval;
bool get_inl_lf = true;
uintptr_t rbase;
struct nix *nix;
@@ -1778,8 +1779,15 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa,
bool inb,
flush.u = 0;
reload.u = 0;
+ inval.u = 0;
switch (op) {
case ROC_NIX_INL_SA_OP_FLUSH_INVAL:
+ if (!roc_model_is_cn10k()) {
+ inval.s.cptr = ((uintptr_t)sa) >> 7;
+ plt_write64(inval.u, rbase + CPT_LF_CTX_INVAL);
+ break;
+ }
+
flush.s.inval = 1;
/* fall through */
case ROC_NIX_INL_SA_OP_FLUSH:
@@ -1815,10 +1823,12 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void
*sa_dptr, void *sa_cptr,
struct nix_inl_dev *inl_dev = NULL;
struct roc_cpt_lf *outb_lf = NULL;
union cpt_lf_ctx_flush flush;
+ union cpt_lf_ctx_inval inval;
union cpt_lf_ctx_err err;
bool get_inl_lf = true;
uintptr_t rbase;
struct nix *nix;
+ uint64_t *sa;
int rc;
/* Nothing much to do on cn9k */
@@ -1850,7 +1860,10 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void
*sa_dptr, void *sa_cptr,
outb_lf = &inl_dev->cpt_lf[0];
}
- if (outb_lf) {
+ if (outb_lf == NULL)
+ goto exit;
+
+ if (roc_model_is_cn10k() || roc_nix->use_write_sa) {
rbase = outb_lf->rbase;
flush.u = 0;
@@ -1869,7 +1882,29 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void
*sa_dptr, void *sa_cptr,
if (err.s.flush_st_flt)
plt_warn("CTX flush could not complete");
return 0;
+ } else {
+ sa = sa_dptr;
+
+ /* Clear bit 58 aop_valid */
+ sa[0] &= ~(1ULL << 58);
+ memcpy(sa_cptr, sa_dptr, sa_len);
+ plt_io_wmb();
+
+ /* Trigger CTX invalidate */
+ rbase = outb_lf->rbase;
+ inval.u = 0;
+ inval.s.cptr = ((uintptr_t)sa_cptr) >> 7;
+ plt_write64(inval.u, rbase + CPT_LF_CTX_INVAL);
+
+ /* Set bit 58 aop_valid */
+ sa = sa_cptr;
+ sa[0] |= (1ULL << 58);
+ plt_io_wmb();
+
+ return 0;
}
+
+exit:
plt_nix_dbg("Could not get CPT LF for CTX write");
return -ENOTSUP;
}
--
2.34.1
[PATCH v3 16/33] common/cnxk: update feature flags for cn20k
From: Rahul Bhansali
Features updated for cn20k platform.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_features.h | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/common/cnxk/roc_features.h
b/drivers/common/cnxk/roc_features.h
index 0002a7b5c3..59c09fbc85 100644
--- a/drivers/common/cnxk/roc_features.h
+++ b/drivers/common/cnxk/roc_features.h
@@ -13,49 +13,49 @@ roc_feature_sso_has_stash(void)
static inline bool
roc_feature_nix_has_inl_ipsec_mseg(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_drop_re_mask(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_inl_rq_mask(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_own_meta_aura(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_late_bp(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_reass(void)
{
- return roc_model_is_cn10ka();
+ return (roc_model_is_cn20k() || roc_model_is_cn10ka());
}
static inline bool
roc_feature_nix_has_cqe_stash(void)
{
- return roc_model_is_cn10ka_b0();
+ return (roc_model_is_cn20k() || roc_model_is_cn10ka_b0());
}
static inline bool
roc_feature_nix_has_rxchan_multi_bpid(void)
{
- if (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0())
+ if (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0())
return true;
return false;
}
@@ -63,7 +63,7 @@ roc_feature_nix_has_rxchan_multi_bpid(void)
static inline bool
roc_feature_nix_has_age_drop_stats(void)
{
- return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0());
+ return (roc_model_is_cn20k() || roc_model_is_cn10kb() ||
roc_model_is_cn10ka_b0());
}
static inline bool
@@ -87,13 +87,13 @@ roc_feature_nix_has_inl_ipsec(void)
static inline bool
roc_feature_nix_has_rx_inject(void)
{
- return (roc_model_is_cn10ka_b0() || roc_model_is_cn10kb());
+ return (roc_model_is_cn20k() || roc_model_is_cn10ka_b0() ||
roc_model_is_cn10kb());
}
static inline bool
roc_feature_nix_has_second_pass_drop(void)
{
- return 0;
+ return roc_model_is_cn20k();
}
static inline bool
--
2.34.1
[PATCH v3 17/33] common/cnxk: add mbox define for inline profile support
Add mbox support for global inline profile allocation.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/roc_mbox.h| 45 ++
drivers/common/cnxk/roc_nix_inl.c | 53 +++
2 files changed, 85 insertions(+), 13 deletions(-)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index f3024057b5..beb7fb6e62 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -336,6 +336,13 @@ struct mbox_msghdr {
nix_mcast_grp_update_rsp)
\
M(NIX_GET_LF_STATS,0x802e, nix_get_lf_stats, nix_get_lf_stats_req,
nix_lf_stats_rsp) \
M(NIX_CN20K_AQ_ENQ, 0x802f, nix_cn20k_aq_enq, nix_cn20k_aq_enq_req,
nix_cn20k_aq_enq_rsp) \
+ M(NIX_LSO_ALT_FLAGS_CFG, 0x8030, nix_lso_alt_flags_cfg,
nix_lso_alt_flags_cfg_req, \
+ nix_lso_alt_flags_cfg_rsp)
\
+ M(NIX_RX_INLINE_PROFILE_CFG, 0x8031, nix_rx_inl_profile_cfg,
\
+ nix_rx_inl_profile_cfg_req,
\
+ nix_rx_inl_profile_cfg_rsp)
\
+ M(NIX_RX_INLINE_LF_CFG, 0x8032, nix_rx_inl_lf_cfg,
nix_rx_inl_lf_cfg_req, \
+ msg_rsp)
\
/* MCS mbox IDs (range 0xa000 - 0xbFFF) */
\
M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,
\
mcs_alloc_rsrc_rsp)
\
@@ -2008,6 +2015,32 @@ struct nix_inline_ipsec_cfg {
uint32_t __io credit_th;
};
+#define NIX_RX_INL_PROFILE_PROTO_CNT 9
+struct nix_rx_inl_profile_cfg_req {
+ struct mbox_msghdr hdr;
+ uint64_t __io def_cfg;
+ uint64_t __io extract_cfg;
+ uint64_t __io gen_cfg;
+ uint64_t __io prot_field_cfg[NIX_RX_INL_PROFILE_PROTO_CNT];
+ uint64_t __io rsvd[32]; /* reserved fields for future expansion
*/
+};
+
+struct nix_rx_inl_profile_cfg_rsp {
+ struct mbox_msghdr hdr;
+ uint8_t __io profile_id;
+ uint8_t __io rsvd[32]; /* reserved fields for future expansion
*/
+};
+
+struct nix_rx_inl_lf_cfg_req {
+ struct mbox_msghdr hdr;
+ uint64_t __io rx_inline_cfg0;
+ uint64_t __io rx_inline_cfg1;
+ uint64_t __io rx_inline_sa_base;
+ uint8_t __io enable;
+ uint8_t __io profile_id;
+ uint8_t __io rsvd[32]; /* reserved fields for future expansion
*/
+};
+
/* Per NIX LF inline IPSec configuration */
struct nix_inline_ipsec_lf_cfg {
struct mbox_msghdr hdr;
@@ -2064,6 +2097,17 @@ struct nix_bandprof_get_hwinfo_rsp {
uint32_t __io policer_timeunit;
};
+struct nix_lso_alt_flags_cfg_req {
+ struct mbox_msghdr hdr;
+ uint64_t __io cfg;
+ uint64_t __io cfg1;
+};
+
+struct nix_lso_alt_flags_cfg_rsp {
+ struct mbox_msghdr hdr;
+ uint8_t __io lso_alt_flags_idx;
+};
+
/* SSO mailbox error codes
* Range 501 - 600.
*/
@@ -3090,6 +3134,7 @@ struct nix_spi_to_sa_add_req {
uint32_t __io spi_index;
uint16_t __io match_id;
bool __io valid;
+ uint8_t __io inline_profile_id;
};
struct nix_spi_to_sa_add_rsp {
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 991a81b50d..37e1bfc0ed 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -395,7 +395,8 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
uint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;
uint32_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
- struct roc_nix_ipsec_cfg cfg;
+ struct mbox *mbox = mbox_get((&nix->dev)->mbox);
+ struct nix_inline_ipsec_lf_cfg *lf_cfg;
uint64_t max_sa, i;
size_t inb_sa_sz;
void *sa;
@@ -419,8 +420,9 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
nix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
ROC_NIX_INL_SA_BASE_ALIGN);
if (!nix->inb_sa_base) {
+ rc = -ENOMEM;
plt_err("Failed to allocate memory for Inbound SA");
- return -ENOMEM;
+ goto exit;
}
if (!roc_model_is_cn9k()) {
@@ -433,23 +435,36 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
}
}
- memset(&cfg, 0, sizeof(cfg));
- cfg.sa_size = inb_sa_sz;
- cfg.iova = (uintptr_t)nix->inb_sa_base;
- cfg.max_sa = max_sa;
- cfg.tt = SSO_TT_ORDERED;
-
/* Setup device specific inb SA table */
- rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
+ lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_
[PATCH v3 19/33] common/cnxk: add NIX inline reassembly profile config
From: Rahul Bhansali
Reassembly profile configuration for nix inline path.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_features.h | 6 +
drivers/common/cnxk/roc_ie_ow.c| 22 +++
drivers/common/cnxk/roc_ie_ow.h| 2 +
drivers/common/cnxk/roc_nix.h | 3 +-
drivers/common/cnxk/roc_nix_debug.c| 8 +-
drivers/common/cnxk/roc_nix_inl.c | 202
drivers/common/cnxk/roc_nix_inl.h | 10 +-
drivers/common/cnxk/roc_nix_inl_dev.c | 205 +++--
drivers/common/cnxk/roc_nix_inl_priv.h | 19 ++-
drivers/common/cnxk/roc_nix_priv.h | 9 +-
drivers/common/cnxk/version.map| 1 +
11 files changed, 425 insertions(+), 62 deletions(-)
diff --git a/drivers/common/cnxk/roc_features.h
b/drivers/common/cnxk/roc_features.h
index 49a563ef95..48ba2fade7 100644
--- a/drivers/common/cnxk/roc_features.h
+++ b/drivers/common/cnxk/roc_features.h
@@ -114,4 +114,10 @@ roc_feature_nix_has_inl_profile(void)
return roc_model_is_cn20k();
}
+static inline bool
+roc_feature_nix_has_plain_pkt_reassembly(void)
+{
+ return roc_model_is_cn20k();
+}
+
#endif
diff --git a/drivers/common/cnxk/roc_ie_ow.c b/drivers/common/cnxk/roc_ie_ow.c
index dd83578b62..9537e48389 100644
--- a/drivers/common/cnxk/roc_ie_ow.c
+++ b/drivers/common/cnxk/roc_ie_ow.c
@@ -27,6 +27,28 @@ roc_ow_ipsec_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa)
sa->w0.s.aop_valid = 1;
}
+void
+roc_ow_reass_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa)
+{
+ size_t offset;
+
+ memset(sa, 0, sizeof(struct roc_ow_ipsec_inb_sa));
+
+ sa->w0.s.pkt_output = ROC_IE_OW_SA_PKT_OUTPUT_HW_BASED_DEFRAG;
+ sa->w0.s.pkt_format = ROC_IE_OW_SA_PKT_FMT_META;
+ sa->w0.s.pkind = ROC_IE_OW_CPT_PKIND;
+ sa->w2.s.l3hdr_on_err = 1;
+ sa->w2.s.valid = 1;
+ sa->w2.s.dir = ROC_IE_SA_DIR_INBOUND;
+
+ offset = offsetof(struct roc_ow_ipsec_inb_sa, ctx);
+ sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
+ sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
+ sa->w0.s.ctx_size = ROC_IE_OW_CTX_ILEN;
+ sa->w0.s.ctx_hdr_size = ROC_IE_OW_SA_CTX_HDR_SIZE;
+ sa->w0.s.aop_valid = 1;
+}
+
void
roc_ow_ipsec_outb_sa_init(struct roc_ow_ipsec_outb_sa *sa)
{
diff --git a/drivers/common/cnxk/roc_ie_ow.h b/drivers/common/cnxk/roc_ie_ow.h
index 56ca1e7f75..4a3291d458 100644
--- a/drivers/common/cnxk/roc_ie_ow.h
+++ b/drivers/common/cnxk/roc_ie_ow.h
@@ -12,6 +12,7 @@
/* CN20K IPsec opcodes */
#define ROC_IE_OW_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL
#define ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x29UL
+#define ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_REASS 0x2BUL
#define ROC_IE_OW_MAJOR_OP_WRITE_SA 0x01UL
#define ROC_IE_OW_MINOR_OP_WRITE_SA 0x09UL
@@ -532,6 +533,7 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ow_ipsec_outb_sa,
ctx) == 31 * sizeof(uint
(PLT_MAX(sizeof(struct roc_ow_ipsec_inb_sa), sizeof(struct
roc_ow_ipsec_outb_sa)))
void __roc_api roc_ow_ipsec_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa);
+void __roc_api roc_ow_reass_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa);
void __roc_api roc_ow_ipsec_outb_sa_init(struct roc_ow_ipsec_outb_sa *sa);
#endif /* __ROC_IE_OW_H__ */
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index a66391449f..a1bd14ffc4 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -490,9 +490,10 @@ struct roc_nix {
uintptr_t meta_mempool;
uint16_t rep_cnt;
uint16_t rep_pfvf_map[MAX_PFVF_REP];
+ bool reass_ena;
TAILQ_ENTRY(roc_nix) next;
-#define ROC_NIX_MEM_SZ (6 * 1070)
+#define ROC_NIX_MEM_SZ (6 * 1112)
uint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned;
} __plt_cache_aligned;
diff --git a/drivers/common/cnxk/roc_nix_debug.c
b/drivers/common/cnxk/roc_nix_debug.c
index 0cc8d7cc1e..f9294e693b 100644
--- a/drivers/common/cnxk/roc_nix_debug.c
+++ b/drivers/common/cnxk/roc_nix_debug.c
@@ -1510,8 +1510,8 @@ roc_nix_dump(struct roc_nix *roc_nix, FILE *file)
nix_dump(file, " \ttx_pause = %d", nix->tx_pause);
nix_dump(file, " \tinl_inb_ena = %d", nix->inl_inb_ena);
nix_dump(file, " \tinl_outb_ena = %d", nix->inl_outb_ena);
- nix_dump(file, " \tinb_sa_base = 0x%p", nix->inb_sa_base);
- nix_dump(file, " \tinb_sa_sz = %" PRIu64, nix->inb_sa_sz);
+ nix_dump(file, " \tinb_sa_base = 0x%p",
nix->inb_sa_base[nix->ipsec_prof_id]);
+ nix_dump(file, " \tinb_sa_sz = %" PRIu64,
nix->inb_sa_sz[nix->ipsec_prof_id]);
nix_dump(file, " \toutb_sa_base = 0x%p", nix->outb_sa_base);
nix_dump(file, " \toutb_sa_sz = %" PRIu64, nix->outb_sa_sz);
nix_dump(file, " \toutb_err_sso_pffunc = 0x%x",
nix->outb_err_sso_pffunc);
@@ -1554,8 +1554,8 @@ roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev,
FILE *file)
nix_dump(file, " \tssow_msixoff = %d", inl_dev->ssow_msixoff);
nix_dump(fil
[PATCH v3 20/33] common/cnxk: add API to fetch inline profile ID
From: Rahul Bhansali
For Inline device, add new roc API to get IPsec and
reassembly profile id.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_nix_inl.c | 60 +++
drivers/common/cnxk/roc_nix_inl.h | 2 ++
2 files changed, 62 insertions(+)
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 652698d13b..6927de6505 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -743,6 +743,66 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool
inb_inl_dev)
return (uintptr_t)nix->inb_sa_base[nix->ipsec_prof_id];
}
+uint16_t
+roc_nix_inl_inb_ipsec_profile_id_get(struct roc_nix *roc_nix, bool inb_inl_dev)
+{
+ struct idev_cfg *idev = idev_get_cfg();
+ struct nix_inl_dev *inl_dev;
+ struct nix *nix = NULL;
+
+ if (idev == NULL)
+ return 0;
+
+ if (!inb_inl_dev && roc_nix == NULL)
+ return -EINVAL;
+
+ if (roc_nix) {
+ nix = roc_nix_to_nix_priv(roc_nix);
+ if (!nix->inl_inb_ena)
+ return 0;
+ }
+
+ if (inb_inl_dev) {
+ inl_dev = idev->nix_inl_dev;
+ /* Return inline Ipsec profile ID */
+ if (inl_dev)
+ return inl_dev->ipsec_prof_id;
+ return 0;
+ }
+
+ return nix->ipsec_prof_id;
+}
+
+uint16_t
+roc_nix_inl_inb_reass_profile_id_get(struct roc_nix *roc_nix, bool inb_inl_dev)
+{
+ struct idev_cfg *idev = idev_get_cfg();
+ struct nix_inl_dev *inl_dev;
+ struct nix *nix = NULL;
+
+ if (idev == NULL)
+ return 0;
+
+ if (!inb_inl_dev && roc_nix == NULL)
+ return -EINVAL;
+
+ if (roc_nix) {
+ nix = roc_nix_to_nix_priv(roc_nix);
+ if (!nix->inl_inb_ena)
+ return 0;
+ }
+
+ if (inb_inl_dev) {
+ inl_dev = idev->nix_inl_dev;
+ /* Return inline reassembly profile ID */
+ if (inl_dev)
+ return inl_dev->reass_prof_id;
+ return 0;
+ }
+
+ return nix->reass_prof_id;
+}
+
bool
roc_nix_inl_inb_rx_inject_enable(struct roc_nix *roc_nix, bool inb_inl_dev)
{
diff --git a/drivers/common/cnxk/roc_nix_inl.h
b/drivers/common/cnxk/roc_nix_inl.h
index 12f36187cf..10bf7d5c25 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -140,6 +140,8 @@ int __roc_api roc_nix_inl_inb_fini(struct roc_nix *roc_nix);
bool __roc_api roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix);
uintptr_t __roc_api roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix,
bool inl_dev_sa);
+uint16_t roc_nix_inl_inb_ipsec_profile_id_get(struct roc_nix *roc_nix, bool
inb_inl_dev);
+uint16_t roc_nix_inl_inb_reass_profile_id_get(struct roc_nix *roc_nix, bool
inb_inl_dev);
bool __roc_api roc_nix_inl_inb_rx_inject_enable(struct roc_nix *roc_nix, bool
inl_dev_sa);
uint32_t __roc_api roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix,
bool inl_dev_sa, uint32_t *min,
--
2.34.1
[PATCH v3 21/33] common/cnxk: add NPC action2 support
From: Rahul Bhansali
Add action2 config for IPsec rule.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/hw/nix.h | 13 +++--
drivers/common/cnxk/roc_mbox.h | 1 +
drivers/common/cnxk/roc_npc.h | 1 +
drivers/common/cnxk/roc_npc_mcam.c | 1 +
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
index dd629a2080..e4d8d285d5 100644
--- a/drivers/common/cnxk/hw/nix.h
+++ b/drivers/common/cnxk/hw/nix.h
@@ -1678,6 +1678,15 @@ struct nix_rx_action_s {
uint64_t rsvd_63_61 : 3;
};
+/* NIX receive action structure */
+struct nix_rx_action2_s {
+ uint64_t ipsec_qsel : 3;
+ uint64_t ipsec_qidx : 4;
+ uint64_t reserved_7_7: 1;
+ uint64_t inline_profile_id : 4;
+ uint64_t reserved_12_63 : 52;
+
+};
/* NIX receive immediate sub descriptor structure */
struct nix_rx_imm_s {
uint64_t size : 16;
@@ -2666,9 +2675,9 @@ struct nix_lso_format {
#define NIX_SENDSTAT_IOFFSET_MASK 0xFFF
#define NIX_SENDSTAT_OOFFSET_MASK 0xFFF
-/* The mask is to extract lower 10-bits of channel number
+/* The mask is to extract lower 11-bits of channel number
* which CPT will pass to X2P.
*/
-#define NIX_CHAN_CPT_X2P_MASK (0x3ffull)
+#define NIX_CHAN_CPT_X2P_MASK (0x7ffull)
#endif /* __NIX_HW_H__ */
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index fbea15690b..22a7258074 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -2694,6 +2694,7 @@ struct cn20k_mcam_entry {
uint64_t __io kw_mask[NPC_CN20K_MAX_KWS_IN_KEY];
uint64_t __io action;
uint64_t __io vtag_action;
+ uint64_t __io action2;
};
struct npc_cn20k_mcam_write_entry_req {
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index 4da21a8eb3..2a409cce99 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -328,6 +328,7 @@ struct roc_npc_flow {
uint64_t mcam_data[ROC_NPC_MAX_MCAM_WIDTH_DWORDS];
uint64_t mcam_mask[ROC_NPC_MAX_MCAM_WIDTH_DWORDS];
uint64_t npc_action;
+ uint64_t npc_action2;
uint64_t vtag_action;
bool vtag_insert_enabled;
int8_t vtag_insert_count;
diff --git a/drivers/common/cnxk/roc_npc_mcam.c
b/drivers/common/cnxk/roc_npc_mcam.c
index 412b2611b7..5db72c22ae 100644
--- a/drivers/common/cnxk/roc_npc_mcam.c
+++ b/drivers/common/cnxk/roc_npc_mcam.c
@@ -511,6 +511,7 @@ npc_mcam_write_entry(struct mbox *mbox, struct roc_npc_flow
*mcam)
cn20k_req->intf = mcam->nix_intf;
cn20k_req->enable_entry = mcam->enable;
cn20k_req->entry_data.action = mcam->npc_action;
+ cn20k_req->entry_data.action2 = mcam->npc_action2;
cn20k_req->entry_data.vtag_action = mcam->vtag_action;
cn20k_req->hw_prio = mcam->priority;
if (mcam->use_ctr)
--
2.34.1
[PATCH v3 23/33] net/cnxk: support for cn20k inline IPsec session
Add support for cn20k inline IPsec session create/destroy.
Signed-off-by: Nithin Dabilpuram
---
drivers/net/cnxk/cn10k_ethdev_sec.c |7 -
drivers/net/cnxk/cn20k_ethdev.c | 11 +
drivers/net/cnxk/cn20k_ethdev.h | 17 +
drivers/net/cnxk/cn20k_ethdev_sec.c | 1182 +++
drivers/net/cnxk/cnxk_ethdev.c | 13 +-
drivers/net/cnxk/cnxk_ethdev.h |5 +-
drivers/net/cnxk/meson.build|1 +
7 files changed, 1227 insertions(+), 9 deletions(-)
create mode 100644 drivers/net/cnxk/cn20k_ethdev_sec.c
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 68691d2bfe..0dc5c22444 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -28,13 +28,6 @@ PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WIN_SIZE_MAX ==
ROC_AR_WIN_SIZE_MAX);
PLT_STATIC_ASSERT(RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 ==
ROC_LOG_MIN_AR_WIN_SIZE_M1);
PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WINBITS_SZ == ROC_AR_WINBITS_SZ);
-cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb;
-void
-cnxk_ethdev_rx_offload_cb_register(cnxk_ethdev_rx_offload_cb_t cb)
-{
- cnxk_ethdev_rx_offload_cb = cb;
-}
-
static struct rte_cryptodev_capabilities cn10k_eth_sec_crypto_caps[] = {
{ /* AES GCM */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c
index 1b608442cf..ea22112f69 100644
--- a/drivers/net/cnxk/cn20k_ethdev.c
+++ b/drivers/net/cnxk/cn20k_ethdev.c
@@ -403,6 +403,12 @@ cn20k_nix_configure(struct rte_eth_dev *eth_dev)
if (rc)
return rc;
+ if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
+ dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
+ /* Register callback to handle security error work */
+ roc_nix_inl_cb_register(cn20k_eth_sec_sso_work_cb, NULL);
+ }
+
/* Update offload flags */
dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
@@ -896,6 +902,8 @@ cn20k_nix_probe(struct rte_pci_driver *pci_drv, struct
rte_pci_device *pci_dev)
nix_tm_ops_override();
npc_flow_ops_override();
+ cn20k_eth_sec_ops_override();
+
/* Common probe */
rc = cnxk_nix_probe(pci_drv, pci_dev);
if (rc)
@@ -922,6 +930,9 @@ cn20k_nix_probe(struct rte_pci_driver *pci_drv, struct
rte_pci_device *pci_dev)
/* Register up msg callbacks for PTP information */
roc_nix_ptp_info_cb_register(&dev->nix, cn20k_nix_ptp_info_update_cb);
+ /* Use WRITE SA for inline IPsec */
+ dev->nix.use_write_sa = true;
+
return 0;
}
diff --git a/drivers/net/cnxk/cn20k_ethdev.h b/drivers/net/cnxk/cn20k_ethdev.h
index cb46044d60..74b03b23d2 100644
--- a/drivers/net/cnxk/cn20k_ethdev.h
+++ b/drivers/net/cnxk/cn20k_ethdev.h
@@ -8,8 +8,25 @@
#include
#include
+/* Private data in sw rsvd area of struct roc_ow_ipsec_outb_sa */
+struct cn20k_outb_priv_data {
+ void *userdata;
+ /* Rlen computation data */
+ struct cnxk_ipsec_outb_rlens rlens;
+ /* Back pointer to eth sec session */
+ struct cnxk_eth_sec_sess *eth_sec;
+ /* SA index */
+ uint32_t sa_idx;
+};
+
/* Rx and Tx routines */
void cn20k_eth_set_rx_function(struct rte_eth_dev *eth_dev);
void cn20k_eth_set_tx_function(struct rte_eth_dev *eth_dev);
+/* Security context setup */
+void cn20k_eth_sec_ops_override(void);
+
+/* SSO Work callback */
+void cn20k_eth_sec_sso_work_cb(uint64_t *gw, void *args, uint32_t
soft_exp_event);
+
#endif /* __CN20K_ETHDEV_H__ */
diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c
b/drivers/net/cnxk/cn20k_ethdev_sec.c
new file mode 100644
index 00..4284b726ee
--- /dev/null
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -0,0 +1,1182 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2024 Marvell.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+PLT_STATIC_ASSERT(offsetof(struct rte_pmd_cnxk_ipsec_inb_sa, ctx.ar_winbits) ==
+ offsetof(struct roc_ow_ipsec_inb_sa, ctx.ar_winbits));
+
+PLT_STATIC_ASSERT(offsetof(struct rte_pmd_cnxk_ipsec_outb_sa, ctx.mib_pkts) ==
+ offsetof(struct roc_ow_ipsec_outb_sa, ctx.mib_pkts));
+
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_CTX_MAX_CKEY_LEN == ROC_CTX_MAX_CKEY_LEN);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN ==
RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN);
+
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WIN_SIZE_MIN == ROC_AR_WIN_SIZE_MIN);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WIN_SIZE_MAX == ROC_AR_WIN_SIZE_MAX);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 ==
ROC_LOG_MIN_AR_WIN_SIZE_M1);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WINBITS_SZ == ROC_AR_WINBITS_SZ);
+
+static struct rte_cryptodev_capabilities cn20k_eth_sec_crypto_caps[] = {
+ { /* AES GCM */
+ .op = RTE_CRYPTO_
[PATCH v3 05/33] common/cnxk: add cn20k CPT result struct
From: Anoob Joseph
CPT result structure is same as in cn10k. Add entry for cn20k.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/hw/cpt.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index 47df3fbf9f..b308a18f0d 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -289,6 +289,16 @@ struct cpt_inst_s {
};
union cpt_res_s {
+ struct cpt_cn20k_res_s {
+ uint64_t compcode : 7;
+ uint64_t doneint : 1;
+ uint64_t uc_compcode : 8;
+ uint64_t rlen : 16;
+ uint64_t spi : 32;
+
+ uint64_t esn;
+ } cn20k;
+
struct cpt_cn10k_res_s {
uint64_t compcode : 7;
uint64_t doneint : 1;
--
2.34.1
[PATCH v3 24/33] common/cnxk: update CPT RXC time config mbox for cn20k
From: Rahul Bhansali
Sync in CPT_RXC_TIME_CFG mbox as per new fields added for
cn20k and restructure to support it.
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/roc_mbox.h| 2 ++
drivers/common/cnxk/roc_nix_inl.c | 55 +--
drivers/common/cnxk/roc_nix_inl.h | 3 +-
drivers/net/cnxk/cn10k_ethdev.c | 5 +--
drivers/net/cnxk/cn20k_ethdev.c | 3 +-
5 files changed, 54 insertions(+), 14 deletions(-)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 22a7258074..6d927c7972 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -2468,6 +2468,8 @@ struct cpt_rxc_time_cfg_req {
uint16_t __io zombie_limit;
uint16_t __io active_thres;
uint16_t __io active_limit;
+ uint16_t __io queue_id;
+ uint64_t __io cpt_af_rxc_que_cfg;
};
/* Mailbox message format to request for CPT faulted engines */
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 6927de6505..8ade58e1a2 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -930,30 +930,65 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool
inb_inl_dev, uint32_t spi)
}
int
-roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags)
+roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t
max_wait_time)
{
struct idev_cfg *idev = idev_get_cfg();
- struct roc_cpt *roc_cpt;
+ struct nix_inl_dev *inl_dev = NULL;
+ struct cpt_rxc_time_cfg_req *req;
struct roc_cpt_rxc_time_cfg cfg;
+ struct roc_cpt *roc_cpt;
+ struct mbox *mbox;
+ int rc;
if (!idev)
return -EFAULT;
- PLT_SET_USED(max_frags);
-
roc_cpt = idev->cpt;
if (!roc_cpt) {
plt_err("Cannot support inline inbound, cryptodev not probed");
return -ENOTSUP;
}
- cfg.step = (max_wait_time * 1000 / ROC_NIX_INL_REAS_ACTIVE_LIMIT);
- cfg.zombie_limit = ROC_NIX_INL_REAS_ZOMBIE_LIMIT;
- cfg.zombie_thres = ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD;
- cfg.active_limit = ROC_NIX_INL_REAS_ACTIVE_LIMIT;
- cfg.active_thres = ROC_NIX_INL_REAS_ACTIVE_THRESHOLD;
+ cfg.step = req_cfg->step ? req_cfg->step :
+ (max_wait_time * 1000 /
ROC_NIX_INL_REAS_ACTIVE_LIMIT);
+ cfg.zombie_limit =
+ req_cfg->zombie_limit ? req_cfg->zombie_limit :
ROC_NIX_INL_REAS_ZOMBIE_LIMIT;
+ cfg.zombie_thres =
+ req_cfg->zombie_thres ? req_cfg->zombie_thres :
ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD;
+ cfg.active_limit =
+ req_cfg->active_limit ? req_cfg->active_limit :
ROC_NIX_INL_REAS_ACTIVE_LIMIT;
+ cfg.active_thres =
+ req_cfg->active_thres ? req_cfg->active_thres :
ROC_NIX_INL_REAS_ACTIVE_THRESHOLD;
- return roc_cpt_rxc_time_cfg(roc_cpt, &cfg);
+ if (roc_model_is_cn10k())
+ return roc_cpt_rxc_time_cfg(roc_cpt, &cfg);
+
+ inl_dev = idev->nix_inl_dev;
+ if (!inl_dev) {
+ plt_err("Cannot support RXC config, inlinedev is not probed");
+ return -ENOTSUP;
+ }
+
+ mbox = mbox_get((&inl_dev->dev)->mbox);
+
+ req = mbox_alloc_msg_cpt_rxc_time_cfg(mbox);
+ if (req == NULL) {
+ rc = -ENOSPC;
+ goto exit;
+ }
+
+ req->blkaddr = 0;
+ req->queue_id = inl_dev->nix_inb_qids[inl_dev->inb_cpt_lf_id];
+ req->step = cfg.step;
+ req->zombie_limit = cfg.zombie_limit;
+ req->zombie_thres = cfg.zombie_thres;
+ req->active_limit = cfg.active_limit;
+ req->active_thres = cfg.active_thres;
+
+ rc = mbox_process(mbox);
+exit:
+ mbox_put(mbox);
+ return rc;
}
static void
diff --git a/drivers/common/cnxk/roc_nix_inl.h
b/drivers/common/cnxk/roc_nix_inl.h
index 10bf7d5c25..2db3a0d0f2 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -157,7 +157,8 @@ int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq);
bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix);
struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(struct roc_nix *roc_nix);
int __roc_api roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t
tag_const, uint8_t tt);
-int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t
max_frags);
+int __roc_api roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg
*req_cfg,
+ uint32_t max_wait_time);
int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena,
bool inb_inl_dev,
uint8_t profile_id);
int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena);
diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index 3f8c66615d..e491854cb2 100644
[PATCH v3 04/33] common/cnxk: move CTX defines to common
From: Anoob Joseph
CTX defines are common for all cases using CPT CTX.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/cnxk_security.h | 1 +
drivers/common/cnxk/roc_cpt.h | 16
drivers/common/cnxk/roc_ie_ot.h | 16
drivers/net/cnxk/cn10k_rxtx.h | 4 ++--
drivers/net/cnxk/cn20k_rxtx.h | 4 ++--
5 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/common/cnxk/cnxk_security.h
b/drivers/common/cnxk/cnxk_security.h
index cd78b283f0..8ede6c88a3 100644
--- a/drivers/common/cnxk/cnxk_security.h
+++ b/drivers/common/cnxk/cnxk_security.h
@@ -7,6 +7,7 @@
#include
#include
+#include "roc_cpt.h"
#include "roc_ie_on.h"
#include "roc_ie_ot.h"
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 0b9c933925..70129531eb 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -104,6 +104,22 @@
#define ROC_CPT_RES_ALIGN 16
+/* Context units in bytes */
+#define ROC_CTX_UNIT_8B 8
+#define ROC_CTX_UNIT_128B128
+#define ROC_CTX_MAX_CKEY_LEN 32
+#define ROC_CTX_MAX_OPAD_IPAD_LEN 128
+
+/* Anti reply window size supported */
+#define ROC_AR_WIN_SIZE_MIN 64
+#define ROC_AR_WIN_SIZE_MAX 4096
+#define ROC_LOG_MIN_AR_WIN_SIZE_M1 5
+
+/* u64 array size to fit anti replay window bits */
+#define ROC_AR_WINBITS_SZ
\
+ (PLT_ALIGN_CEIL(ROC_AR_WIN_SIZE_MAX, BITS_PER_LONG_LONG) / \
+BITS_PER_LONG_LONG)
+
enum {
ROC_CPT_REVISION_ID_83XX = 0,
ROC_CPT_REVISION_ID_96XX_B0 = 1,
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index 26616be901..932d3b6131 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -155,22 +155,6 @@ roc_ie_ot_ucc_is_success(uint8_t ucc)
return (ucc >= uc_base);
}
-/* Context units in bytes */
-#define ROC_CTX_UNIT_8B 8
-#define ROC_CTX_UNIT_128B128
-#define ROC_CTX_MAX_CKEY_LEN 32
-#define ROC_CTX_MAX_OPAD_IPAD_LEN 128
-
-/* Anti reply window size supported */
-#define ROC_AR_WIN_SIZE_MIN 64
-#define ROC_AR_WIN_SIZE_MAX 4096
-#define ROC_LOG_MIN_AR_WIN_SIZE_M1 5
-
-/* u64 array size to fit anti replay window bits */
-#define ROC_AR_WINBITS_SZ
\
- (PLT_ALIGN_CEIL(ROC_AR_WIN_SIZE_MAX, BITS_PER_LONG_LONG) / \
-BITS_PER_LONG_LONG)
-
#define ROC_IPSEC_ERR_RING_MAX_ENTRY 65536
union roc_ot_ipsec_err_ring_head {
diff --git a/drivers/net/cnxk/cn10k_rxtx.h b/drivers/net/cnxk/cn10k_rxtx.h
index 9861aa6571..98f9e2efa3 100644
--- a/drivers/net/cnxk/cn10k_rxtx.h
+++ b/drivers/net/cnxk/cn10k_rxtx.h
@@ -27,8 +27,6 @@
#include "hw/npc.h"
#include "hw/ssow.h"
-#include "roc_ie_ot.h"
-
/* NPA */
#include "roc_npa_dp.h"
@@ -38,6 +36,8 @@
/* CPT */
#include "roc_cpt.h"
+#include "roc_ie_ot.h"
+
/* NIX Inline dev */
#include "roc_nix_inl_dp.h"
diff --git a/drivers/net/cnxk/cn20k_rxtx.h b/drivers/net/cnxk/cn20k_rxtx.h
index 4a8f194eb8..7aa06444e2 100644
--- a/drivers/net/cnxk/cn20k_rxtx.h
+++ b/drivers/net/cnxk/cn20k_rxtx.h
@@ -27,8 +27,6 @@
#include "hw/npc.h"
#include "hw/ssow.h"
-#include "roc_ie_ot.h"
-
/* NPA */
#include "roc_npa_dp.h"
@@ -38,6 +36,8 @@
/* CPT */
#include "roc_cpt.h"
+#include "roc_ie_ot.h"
+
/* NIX Inline dev */
#include "roc_nix_inl_dp.h"
--
2.34.1
[PATCH v3 07/33] common/cnxk: make special handling only for 9k
From: Anoob Joseph 9k would need special handling compared to 10k & 20k. Update the check to reflect the same. Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_cpt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 88f6044e60..a6d2d83f76 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -930,10 +930,10 @@ roc_cpt_iq_reset(struct roc_cpt_lf *lf) lf_ctl.s.ena = 1; plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL); - if (roc_model_is_cn10k()) - cpt_10k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE); - else + if (roc_model_is_cn9k()) cpt_9k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE); + else + cpt_10k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE); plt_read64(lf->rbase + CPT_LF_INPROG); plt_delay_us(2); -- 2.34.1
[PATCH v3 26/33] net/cnxk: inline IPsec Rx support for cn20k
From: Rahul Bhansali
Inline IPsec Rx support for cn20k
Signed-off-by: Rahul Bhansali
---
drivers/event/cnxk/cn20k_worker.h | 4 +-
drivers/net/cnxk/cn20k_rx.h | 736 --
2 files changed, 688 insertions(+), 52 deletions(-)
diff --git a/drivers/event/cnxk/cn20k_worker.h
b/drivers/event/cnxk/cn20k_worker.h
index b014e549b9..2366196d9d 100644
--- a/drivers/event/cnxk/cn20k_worker.h
+++ b/drivers/event/cnxk/cn20k_worker.h
@@ -24,7 +24,7 @@ cn20k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf,
uint8_t port_id, const ui
struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
cn20k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag, (struct
rte_mbuf *)mbuf, lookup_mem,
- mbuf_init | ((uint64_t)port_id) << 48, cpth,
sa_base, flags);
+ mbuf_init | ((uint64_t)port_id) << 48, cpth,
sa_base, 0, flags);
}
static void
@@ -83,7 +83,7 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const
uint32_t flags, struc
/* Mark mempool obj as "get" as it is alloc'ed by NIX */
RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
- cn20k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
mbuf_init, cpth, sa_base,
+ cn20k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
mbuf_init, cpth, sa_base, 0,
flags);
if (flags & NIX_RX_OFFLOAD_TSTAMP_F)
diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index 01bf483787..b54d9df662 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -82,6 +82,42 @@ union mbuf_initializer {
uint64_t value;
};
+static __rte_always_inline void
+nix_sec_flush_meta_burst(uint16_t lmt_id, uint64_t data, uint16_t lnum,
uintptr_t aura_handle)
+{
+ uint64_t pa;
+
+ /* Prepare PA and Data */
+ pa = roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_FREE0;
+ pa |= ((data & 0x7) << 4);
+
+ data >>= 3;
+ data <<= 19;
+ data |= (uint64_t)lmt_id;
+ data |= (uint64_t)(lnum - 1) << 12;
+
+ roc_lmt_submit_steorl(data, pa);
+}
+
+static __rte_always_inline void
+nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff, uintptr_t
aura_handle)
+{
+ uint64_t pa;
+
+ /* laddr is pointing to first pointer */
+ laddr -= 8;
+
+ /* Trigger free either on lmtline full or different aura handle */
+ pa = roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_FREE0;
+
+ /* Update aura handle */
+ *(uint64_t *)laddr =
+ (((uint64_t)(loff & 0x1) << 32) |
roc_npa_aura_handle_to_aura(aura_handle));
+
+ pa |= ((uint64_t)(loff >> 1) << 4);
+ roc_lmt_submit_steorl(lmt_id, pa);
+}
+
static __rte_always_inline uint64_t
nix_clear_data_off(uint64_t oldval)
{
@@ -101,6 +137,56 @@ nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)
return (struct rte_mbuf *)(buff - data_off);
}
+static __rte_always_inline uint64_t
+nix_sec_meta_to_mbuf_sc(uint64_t cq_w5, uint64_t cpth, const uint64_t sa_base,
+ struct rte_mbuf *mbuf, uint16_t *len, uint64_t
*mbuf_init,
+ const uint16_t flags)
+{
+ const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s
*)cpth;
+ struct cn20k_inb_priv_data *inb_priv;
+ uint64_t ol_flags, w3 = hdr->w3.u64;
+ uint32_t sa_idx;
+ uint16_t ucc;
+ void *inb_sa;
+
+ /* Get SPI from CPT_PARSE_S's cookie(already swapped) */
+ sa_idx = hdr->w0.cookie;
+ inb_sa = roc_nix_inl_ow_ipsec_inb_sa(sa_base, sa_idx);
+ inb_priv = roc_nix_inl_ow_ipsec_inb_sa_sw_rsvd(inb_sa);
+
+ /* Cryptodev injected packet can be identified from SA IDX 0x,
and
+* Ethdev injected packet can be identified with match ID 0x.
+*/
+ if (flags & NIX_RX_REAS_F && !hdr->w2.pkt_inline) {
+ *mbuf_init = (*mbuf_init & ~(BIT_ULL(16) - 1)) | mbuf->data_off;
+ if (hdr->w0.match_id == 0xU)
+ *rte_security_dynfield(mbuf) =
(uint64_t)inb_priv->userdata;
+ } else {
+ /* Update dynamic field with userdata */
+ *rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata;
+ }
+
+ *len = ((w3 >> 48) & 0x) + ((cq_w5 >> 16) & 0xFF) - (cq_w5 & 0xFF);
+
+ /* Get ucc from cpt parse header */
+ ucc = w3 & 0xFF;
+ ol_flags = ((CPT_COMP_HWGOOD_MASK & (1U << ucc)) ?
+ RTE_MBUF_F_RX_SEC_OFFLOAD :
+ RTE_MBUF_F_RX_SEC_OFFLOAD |
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED);
+
+ ucc = (w3 >> 8) & 0xFF;
+ if (ucc && ucc < ROC_IE_OW_UCC_SUCCESS_PKT_IP_BADCSUM) {
+ ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
+ } else {
+ ucc += 3; /* To make codes in 0xFx series except 0 */
+
[PATCH v3 27/33] event/cnxk: inline IPsec Rx support for cn20k
From: Rahul Bhansali
Inline IPsec Rx support for cn20k
Signed-off-by: Rahul Bhansali
---
doc/guides/rel_notes/release_25_03.rst | 1 +
drivers/event/cnxk/cn20k_worker.h | 111 -
2 files changed, 108 insertions(+), 4 deletions(-)
diff --git a/doc/guides/rel_notes/release_25_03.rst
b/doc/guides/rel_notes/release_25_03.rst
index ca67c17c5c..6a7b3b5803 100644
--- a/doc/guides/rel_notes/release_25_03.rst
+++ b/doc/guides/rel_notes/release_25_03.rst
@@ -116,6 +116,7 @@ New Features
* **Updated Marvell cnxk net driver.**
* Added flow rules support for CN20K SoC.
+ * Added Inline IPsec support for CN20K SoC.
* **Updated NVIDIA mlx5 driver.**
diff --git a/drivers/event/cnxk/cn20k_worker.h
b/drivers/event/cnxk/cn20k_worker.h
index 2366196d9d..6ed1f78a86 100644
--- a/drivers/event/cnxk/cn20k_worker.h
+++ b/drivers/event/cnxk/cn20k_worker.h
@@ -22,9 +22,13 @@ cn20k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf,
uint8_t port_id, const ui
const uint64_t mbuf_init =
0x10001ULL | RTE_PKTMBUF_HEADROOM | (flags &
NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
+ uint64_t buf_sz = 0;
+
+ if (flags & NIX_RX_REAS_F)
+ buf_sz = cnxk_nix_inl_bufsize_get(port_id, lookup_mem);
cn20k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag, (struct
rte_mbuf *)mbuf, lookup_mem,
- mbuf_init | ((uint64_t)port_id) << 48, cpth,
sa_base, 0, flags);
+ mbuf_init | ((uint64_t)port_id) << 48, cpth,
sa_base, buf_sz, flags);
}
static void
@@ -47,14 +51,20 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const
uint32_t flags, struc
{
uint64_t mbuf_init = 0x10001ULL | RTE_PKTMBUF_HEADROOM;
struct cnxk_timesync_info *tstamp = ws->tstamp[port_id];
+ uint8_t m_sz = sizeof(struct rte_mbuf);
void *lookup_mem = ws->lookup_mem;
uintptr_t lbase = ws->lmt_base;
+ uint64_t meta_aura = 0, laddr;
struct rte_event_vector *vec;
uint16_t nb_mbufs, non_vec;
+ struct rte_mempool *mp;
+ uint16_t lmt_id, d_off;
struct rte_mbuf **wqe;
struct rte_mbuf *mbuf;
uint64_t sa_base = 0;
+ uint64_t buf_sz = 0;
uintptr_t cpth = 0;
+ uint8_t loff = 0;
int i;
mbuf_init |= ((uint64_t)port_id) << 48;
@@ -69,12 +79,39 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const
uint32_t flags, struc
if (flags & NIX_RX_OFFLOAD_TSTAMP_F && tstamp)
mbuf_init |= 8;
+ if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
+ mp = (struct rte_mempool *)cnxk_nix_inl_metapool_get(port_id,
lookup_mem);
+ if (mp)
+ meta_aura = mp->pool_id;
+ }
+
nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP);
nb_mbufs = cn20k_nix_recv_pkts_vector(&mbuf_init, wqe, nb_mbufs, flags
| NIX_RX_VWQE_F,
- lookup_mem, tstamp, lbase, 0);
+ lookup_mem, tstamp, lbase,
meta_aura);
wqe += nb_mbufs;
non_vec = vec->nb_elem - nb_mbufs;
+ if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) {
+ uint64_t sg_w1;
+
+ mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] - sizeof(struct
rte_mbuf));
+ /* Pick first mbuf's aura handle assuming all
+* mbufs are from a vec and are from same RQ.
+*/
+ if (!meta_aura)
+ meta_aura = mbuf->pool->pool_id;
+ ROC_LMT_BASE_ID_GET(lbase, lmt_id);
+ laddr = lbase;
+ laddr += 8;
+ sg_w1 = *(uint64_t *)(((uintptr_t)wqe[0]) + 72);
+ d_off = sg_w1 - (uintptr_t)mbuf;
+ sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem);
+ sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
+
+ if (flags & NIX_RX_REAS_F)
+ buf_sz = cnxk_nix_inl_bufsize_get(port_id, lookup_mem);
+ }
+
while (non_vec) {
struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0];
@@ -83,8 +120,29 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const
uint32_t flags, struc
/* Mark mempool obj as "get" as it is alloc'ed by NIX */
RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
- cn20k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem,
mbuf_init, cpth, sa_base, 0,
- flags);
+ /* Translate meta to mbuf */
+ if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
+ const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
+
+ cpth = ((uintptr_t)mbuf + (uint16_t)d_off);
+
+ if (cq_w1 & BIT(11)) {
+
[PATCH v3 10/33] common/cnxk: add 20k defines for IPsec
From: Anoob Joseph
Add 20K defines for IPsec.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/meson.build | 1 +
drivers/common/cnxk/roc_api.h | 1 +
drivers/common/cnxk/roc_ie_ow.c | 41 +++
drivers/common/cnxk/roc_ie_ow.h | 537
drivers/common/cnxk/version.map | 2 +
5 files changed, 582 insertions(+)
create mode 100644 drivers/common/cnxk/roc_ie_ow.c
create mode 100644 drivers/common/cnxk/roc_ie_ow.h
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 00a352dc55..59f4eacf84 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -25,6 +25,7 @@ sources = files(
'roc_idev.c',
'roc_irq.c',
'roc_ie_ot.c',
+'roc_ie_ow.c',
'roc_mbox.c',
'roc_mcs.c',
'roc_mcs_sec_cfg.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 93e7bf11bb..3cee5aa87c 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -93,6 +93,7 @@
#include "roc_ie.h"
#include "roc_ie_on.h"
#include "roc_ie_ot.h"
+#include "roc_ie_ow.h"
#include "roc_se.h"
/* DPI */
diff --git a/drivers/common/cnxk/roc_ie_ow.c b/drivers/common/cnxk/roc_ie_ow.c
new file mode 100644
index 00..dd83578b62
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_ow.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2024 Marvell.
+ */
+
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+void
+roc_ow_ipsec_inb_sa_init(struct roc_ow_ipsec_inb_sa *sa)
+{
+ size_t offset;
+
+ memset(sa, 0, sizeof(struct roc_ow_ipsec_inb_sa));
+
+ sa->w0.s.pkt_output = ROC_IE_OW_SA_PKT_OUTPUT_NO_FRAG;
+ sa->w0.s.pkt_format = ROC_IE_OW_SA_PKT_FMT_META;
+ sa->w0.s.pkind = ROC_IE_OW_CPT_PKIND;
+ sa->w0.s.et_ovrwr = 1;
+ sa->w2.s.l3hdr_on_err = 1;
+
+ offset = offsetof(struct roc_ow_ipsec_inb_sa, ctx);
+ sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
+ sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
+ sa->w0.s.ctx_size = ROC_IE_OW_CTX_ILEN;
+ sa->w0.s.ctx_hdr_size = ROC_IE_OW_SA_CTX_HDR_SIZE;
+ sa->w0.s.aop_valid = 1;
+}
+
+void
+roc_ow_ipsec_outb_sa_init(struct roc_ow_ipsec_outb_sa *sa)
+{
+ size_t offset;
+
+ memset(sa, 0, sizeof(struct roc_ow_ipsec_outb_sa));
+
+ offset = offsetof(struct roc_ow_ipsec_outb_sa, ctx);
+ sa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B) + 1;
+ sa->w0.s.ctx_size = ROC_IE_OW_CTX_ILEN;
+ sa->w0.s.aop_valid = 1;
+}
diff --git a/drivers/common/cnxk/roc_ie_ow.h b/drivers/common/cnxk/roc_ie_ow.h
new file mode 100644
index 00..56ca1e7f75
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_ow.h
@@ -0,0 +1,537 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2024 Marvell.
+ */
+
+#ifndef __ROC_IE_OW_H__
+#define __ROC_IE_OW_H__
+
+#include "roc_platform.h"
+
+#include "roc_cpt.h"
+
+/* CN20K IPsec opcodes */
+#define ROC_IE_OW_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL
+#define ROC_IE_OW_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x29UL
+
+#define ROC_IE_OW_MAJOR_OP_WRITE_SA 0x01UL
+#define ROC_IE_OW_MINOR_OP_WRITE_SA 0x09UL
+
+#define ROC_IE_OW_CTX_ILEN 2
+
+/* PKIND to be used for CPT Meta parsing */
+#define ROC_IE_OW_CPT_PKIND 58
+#define ROC_IE_OW_CPT_TS_PKIND 54
+#define ROC_IE_OW_SA_CTX_HDR_SIZE 1
+
+#define ROC_IE_OW_INPLACE_BIT BIT(6)
+
+enum roc_ie_ow_ucc_ipsec {
+ ROC_IE_OW_UCC_SUCCESS = 0x00,
+ ROC_IE_OW_UCC_ERR_SA_INVAL = 0xb0,
+ ROC_IE_OW_UCC_ERR_SA_EXPIRED = 0xb1,
+ ROC_IE_OW_UCC_ERR_SA_OVERFLOW = 0xb2,
+ ROC_IE_OW_UCC_ERR_SA_ESP_BAD_ALGO = 0xb3,
+ ROC_IE_OW_UCC_ERR_SA_AH_BAD_ALGO = 0xb4,
+ ROC_IE_OW_UCC_ERR_SA_BAD_CTX = 0xb5,
+ ROC_IE_OW_UCC_SA_CTX_FLAG_MISMATCH = 0xb6,
+ ROC_IE_OW_UCC_ERR_AOP_IPSEC = 0xb7,
+ ROC_IE_OW_UCC_ERR_PKT_IP = 0xb8,
+ ROC_IE_OW_UCC_ERR_PKT_IP6_BAD_EXT = 0xb9,
+ ROC_IE_OW_UCC_ERR_PKT_IP6_HBH = 0xba,
+ ROC_IE_OW_UCC_ERR_PKT_IP6_BIGEXT = 0xbb,
+ ROC_IE_OW_UCC_ERR_PKT_IP_ULP = 0xbc,
+ ROC_IE_OW_UCC_ERR_PKT_SA_MISMATCH = 0xbd,
+ ROC_IE_OW_UCC_ERR_PKT_SPI_MISMATCH = 0xbe,
+ ROC_IE_OW_UCC_ERR_PKT_ESP_BADPAD = 0xbf,
+ ROC_IE_OW_UCC_ERR_PKT_BADICV = 0xc0,
+ ROC_IE_OW_UCC_ERR_PKT_REPLAY_SEQ = 0xc1,
+ ROC_IE_OW_UCC_ERR_PKT_BADNH = 0xc2,
+ ROC_IE_OW_UCC_ERR_PKT_SA_PORT_MISMATCH = 0xc3,
+ ROC_IE_OW_UCC_ERR_PKT_BAD_DLEN = 0xc4,
+ ROC_IE_OW_UCC_ERR_SA_ESP_BAD_KEYS = 0xc5,
+ ROC_IE_OW_UCC_ERR_SA_AH_BAD_KEYS = 0xc6,
+ ROC_IE_OW_UCC_ERR_SA_BAD_IP = 0xc7,
+ ROC_IE_OW_UCC_ERR_PKT_IP_FRAG = 0xc8,
+ ROC_IE_OW_UCC_ERR_PKT_REPLAY_WINDOW = 0xc9,
+ ROC_IE_OW_UCC_SUCCESS_PKT_IP_BADCSUM = 0xed,
+ ROC_IE_OW_UCC_SUCCESS_PKT_L4_GOODCSUM = 0xee,
+ ROC_IE_OW_UCC_SUCCESS_PKT_L4_BADCSUM = 0xef,
+ ROC_IE_OW_UCC_SUCCESS_SA_SOFTEXP_FIRST = 0xf0,
+ ROC_IE_OW_UCC_SUCCESS_PKT_UDPESP_NZCSUM = 0xf1
[PATCH v3 29/33] common/cnxk: fix inbound IPsec sa setup
Make sure the w2 in inbound SA is set for inline IPsec have
L3 header on errors.
Fixes: 350b7a536a51 ("common/cnxk: enable L3 header write back in SA")
Cc: sta...@dpdk.org
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/cnxk_security.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/cnxk_security.c
b/drivers/common/cnxk/cnxk_security.c
index 3a747ed441..a3c06c1e88 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -315,7 +315,7 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
/* Initialize the SA */
roc_ot_ipsec_inb_sa_init(sa);
- w2.u64 = 0;
+ w2.u64 = sa->w2.u64;
rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->w8.s.salt,
sa->hmac_opad_ipad, ipsec_xfrm,
crypto_xfrm);
--
2.34.1
[PATCH v3 11/33] common/cnxk: update default eng group for cn20k
CN20K does not have IE engines, hence change the default eng group
for cn20k and use legacy for cn10k or older version.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/roc_cpt.c | 6 +++---
drivers/common/cnxk/roc_cpt.h | 10 +++---
drivers/common/cnxk/roc_nix_inl.c | 15 +++
drivers/common/cnxk/roc_nix_inl_dev.c | 12
drivers/event/cnxk/cn9k_worker.h | 2 +-
drivers/net/cnxk/cn10k_rx.h | 2 +-
drivers/net/cnxk/cn10k_tx.h | 4 ++--
drivers/net/cnxk/cn20k_tx.h | 4 ++--
8 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index a6d2d83f76..b4bf0ccd64 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -931,9 +931,9 @@ roc_cpt_iq_reset(struct roc_cpt_lf *lf)
plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
if (roc_model_is_cn9k())
- cpt_9k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE);
+ cpt_9k_lf_rst_lmtst(lf, ROC_LEGACY_CPT_DFLT_ENG_GRP_SE);
else
- cpt_10k_lf_rst_lmtst(lf, ROC_CPT_DFLT_ENG_GRP_SE);
+ cpt_10k_lf_rst_lmtst(lf,
ROC_LEGACY_CPT_DFLT_ENG_GRP_SE);
plt_read64(lf->rbase + CPT_LF_INPROG);
plt_delay_us(2);
@@ -1205,7 +1205,7 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr,
void *sa_cptr,
if (lf->roc_cpt == NULL) {
if (roc_cpt_has_ie_engines())
- egrp = ROC_CPT_DFLT_ENG_GRP_SE_IE;
+ egrp = ROC_LEGACY_CPT_DFLT_ENG_GRP_SE_IE;
else
egrp = ROC_CPT_DFLT_ENG_GRP_SE;
} else {
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index ac27479371..30bd2a094d 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -15,10 +15,14 @@
#define ROC_LOADFVC_MAJOR_OP 0x01UL
#define ROC_LOADFVC_MINOR_OP 0x08UL
+/* Default engine groups for CN9K, CN10K */
+#define ROC_LEGACY_CPT_DFLT_ENG_GRP_SE 0UL
+#define ROC_LEGACY_CPT_DFLT_ENG_GRP_SE_IE 1UL
+#define ROC_LEGACY_CPT_DFLT_ENG_GRP_AE 2UL
+
/* Default engine groups */
-#define ROC_CPT_DFLT_ENG_GRP_SE 0UL
-#define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL
-#define ROC_CPT_DFLT_ENG_GRP_AE 2UL
+#define ROC_CPT_DFLT_ENG_GRP_SE 0UL
+#define ROC_CPT_DFLT_ENG_GRP_AE 1UL
#define ROC_CPT_MAX_LFS 64
#define ROC_CPT_MAX_BLKS 2
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 88d5a678b1..6b7532b1f0 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -811,7 +811,10 @@ nix_inl_eng_caps_get(struct nix *nix)
inst.rptr = (uint64_t)rptr;
inst.w4.s.opcode_major = ROC_LOADFVC_MAJOR_OP;
inst.w4.s.opcode_minor = ROC_LOADFVC_MINOR_OP;
- inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;
+ if (roc_model_is_cn9k() || roc_model_is_cn10k())
+ inst.w7.s.egrp = ROC_LEGACY_CPT_DFLT_ENG_GRP_SE;
+ else
+ inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;
/* Use 1 min timeout for the poll */
const uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz();
@@ -1053,10 +1056,14 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
ctx_ilen_valid = true;
}
+ if (roc_model_is_cn9k() || roc_model_is_cn10k())
+ eng_grpmask = (1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_SE |
+ 1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_SE_IE |
+ 1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_AE);
+ else
+ eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE | 1ULL <<
ROC_CPT_DFLT_ENG_GRP_AE);
+
/* Alloc CPT LF */
- eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
- 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
- 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr,
!roc_nix->ipsec_out_sso_pffunc, ctx_ilen_valid,
ctx_ilen,
rx_inj, nb_lf - 1);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index d26cbee0cc..da28b22bcc 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -179,15 +179,19 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool
inl_dev_sso)
if (!inl_dev->attach_cptlf)
return 0;
- /* Alloc CPT LF */
- eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
- 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
- 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
+ if (roc_model_is_cn9k() || roc_model_is_cn10k())
+ eng_grpmask = (1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_SE |
+ 1ULL << ROC_LEGACY_CPT_DFLT_ENG_GRP_SE_IE |
+
[PATCH v3 32/33] net/cnxk: update MC address list configure API
From: Satha Rao
Return -ENOSPC when there is no space to update the complete MC address
list, without flushing the existing list of addresses.
Signed-off-by: Satha Rao
---
drivers/net/cnxk/cnxk_ethdev_ops.c | 32 ++
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c
b/drivers/net/cnxk/cnxk_ethdev_ops.c
index 5b0948e07a..9970c5ff5c 100644
--- a/drivers/net/cnxk/cnxk_ethdev_ops.c
+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c
@@ -1117,17 +1117,14 @@ cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
return 0;
}
-int
-cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,
- struct rte_ether_addr *mc_addr_set,
- uint32_t nb_mc_addr)
+static inline int
+nix_mc_addr_list_flush(struct rte_eth_dev *eth_dev)
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
struct rte_eth_dev_data *data = eth_dev->data;
struct rte_ether_addr null_mac_addr;
struct roc_nix *nix = &dev->nix;
- int rc, index;
- uint32_t i;
+ int i, rc = 0;
memset(&null_mac_addr, 0, sizeof(null_mac_addr));
@@ -1148,15 +1145,34 @@ cnxk_nix_mc_addr_list_configure(struct rte_eth_dev
*eth_dev,
}
}
+ return rc;
+}
+
+int
+cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev, struct
rte_ether_addr *mc_addr_set,
+ uint32_t nb_mc_addr)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct rte_eth_dev_data *data = eth_dev->data;
+ struct roc_nix *nix = &dev->nix;
+ int index, mc_addr_cnt = 0;
+ uint32_t i;
+
if (!mc_addr_set || !nb_mc_addr)
- return 0;
+ return nix_mc_addr_list_flush(eth_dev);
+
+ /* Count multicast MAC addresses in list */
+ for (i = 0; i < dev->max_mac_entries; i++)
+ if (rte_is_multicast_ether_addr(&data->mac_addrs[i]))
+ mc_addr_cnt++;
/* Check for available space */
if (nb_mc_addr >
- ((uint32_t)(dev->max_mac_entries - dev->dmac_filter_count))) {
+ ((uint32_t)(dev->max_mac_entries - (dev->dmac_filter_count -
mc_addr_cnt {
plt_err("No space is available to add multicast filters");
return -ENOSPC;
}
+ nix_mc_addr_list_flush(eth_dev);
/* Multicast addresses are to be installed */
for (i = 0; i < nb_mc_addr; i++) {
--
2.34.1
[PATCH v3 31/33] common/cnxk: change the error log to a debug log
From: Srujana Challa
This patch updates the error log to a debug log since
it is not needed.
Signed-off-by: Srujana Challa
---
drivers/common/cnxk/roc_nix_inl_dev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index 2e753440b7..376582f5db 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -1250,7 +1250,7 @@ roc_nix_inl_dev_qptr_get(uint8_t qid)
inl_dev = idev->nix_inl_dev;
if (!inl_dev) {
- plt_err("Inline Device could not be detected");
+ plt_nix_dbg("Inline Device could not be detected");
return NULL;
}
if (!inl_dev->attach_cptlf) {
--
2.34.1
[PATCH v3 12/33] common/cnxk: support for cn20k IPsec session
Add support for cn20k IPsec session create/destroy.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/cnxk_security.c | 546 +++-
drivers/common/cnxk/cnxk_security.h | 12 +-
drivers/common/cnxk/version.map | 2 +
3 files changed, 557 insertions(+), 3 deletions(-)
diff --git a/drivers/common/cnxk/cnxk_security.c
b/drivers/common/cnxk/cnxk_security.c
index 8953e901a1..3a747ed441 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -4,10 +4,10 @@
#include
-#include "cnxk_security.h"
-
#include "roc_api.h"
+#include "cnxk_security.h"
+
static int
ot_ipsec_sa_common_param_fill(union roc_ot_ipsec_sa_word2 *w2, uint8_t
*cipher_key,
uint8_t *salt_key, uint8_t *hmac_opad_ipad,
@@ -1183,3 +1183,545 @@ cnxk_on_ipsec_inb_sa_create(struct
rte_security_ipsec_xform *ipsec,
return ctx_len;
}
+
+static int
+ow_ipsec_sa_common_param_fill(union roc_ow_ipsec_sa_word2 *w2, uint8_t
*cipher_key,
+ uint8_t *salt_key, uint8_t *hmac_opad_ipad,
+ struct rte_security_ipsec_xform *ipsec_xfrm,
+ struct rte_crypto_sym_xform *crypto_xfrm)
+{
+ struct rte_crypto_sym_xform *auth_xfrm, *cipher_xfrm;
+ const uint8_t *key = NULL;
+ uint8_t ccm_flag = 0;
+ uint32_t *tmp_salt;
+ uint64_t *tmp_key;
+ int i, length = 0;
+
+ /* Set direction */
+ if (ipsec_xfrm->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS)
+ w2->s.dir = ROC_IE_SA_DIR_OUTBOUND;
+ else
+ w2->s.dir = ROC_IE_SA_DIR_INBOUND;
+
+ if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
+ auth_xfrm = crypto_xfrm;
+ cipher_xfrm = crypto_xfrm->next;
+ } else {
+ cipher_xfrm = crypto_xfrm;
+ auth_xfrm = crypto_xfrm->next;
+ }
+
+ /* Set protocol - ESP vs AH */
+ switch (ipsec_xfrm->proto) {
+ case RTE_SECURITY_IPSEC_SA_PROTO_ESP:
+ w2->s.protocol = ROC_IE_SA_PROTOCOL_ESP;
+ break;
+ case RTE_SECURITY_IPSEC_SA_PROTO_AH:
+ w2->s.protocol = ROC_IE_SA_PROTOCOL_AH;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Set mode - transport vs tunnel */
+ switch (ipsec_xfrm->mode) {
+ case RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT:
+ w2->s.mode = ROC_IE_SA_MODE_TRANSPORT;
+ break;
+ case RTE_SECURITY_IPSEC_SA_MODE_TUNNEL:
+ w2->s.mode = ROC_IE_SA_MODE_TUNNEL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Set encryption algorithm */
+ if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
+ key = crypto_xfrm->aead.key.data;
+ length = crypto_xfrm->aead.key.length;
+
+ switch (crypto_xfrm->aead.algo) {
+ case RTE_CRYPTO_AEAD_AES_GCM:
+ w2->s.enc_type = ROC_IE_SA_ENC_AES_GCM;
+ w2->s.auth_type = ROC_IE_SA_AUTH_NULL;
+ memcpy(salt_key, &ipsec_xfrm->salt, 4);
+ tmp_salt = (uint32_t *)salt_key;
+ *tmp_salt = rte_be_to_cpu_32(*tmp_salt);
+ break;
+ case RTE_CRYPTO_AEAD_AES_CCM:
+ w2->s.enc_type = ROC_IE_SA_ENC_AES_CCM;
+ w2->s.auth_type = ROC_IE_SA_AUTH_NULL;
+ ccm_flag = 0x07 & ~ROC_CPT_AES_CCM_CTR_LEN;
+ *salt_key = ccm_flag;
+ memcpy(PLT_PTR_ADD(salt_key, 1), &ipsec_xfrm->salt, 3);
+ tmp_salt = (uint32_t *)salt_key;
+ *tmp_salt = rte_be_to_cpu_32(*tmp_salt);
+ break;
+ default:
+ return -ENOTSUP;
+ }
+ } else {
+ if (cipher_xfrm != NULL) {
+ switch (cipher_xfrm->cipher.algo) {
+ case RTE_CRYPTO_CIPHER_NULL:
+ w2->s.enc_type = ROC_IE_SA_ENC_NULL;
+ break;
+ case RTE_CRYPTO_CIPHER_AES_CBC:
+ w2->s.enc_type = ROC_IE_SA_ENC_AES_CBC;
+ break;
+ case RTE_CRYPTO_CIPHER_AES_CTR:
+ w2->s.enc_type = ROC_IE_SA_ENC_AES_CTR;
+ break;
+ case RTE_CRYPTO_CIPHER_3DES_CBC:
+ w2->s.enc_type = ROC_IE_SA_ENC_3DES_CBC;
+ break;
+ default:
+ return -ENOTSUP;
+ }
+
+ key = cipher_xfrm->cipher.key.data;
+ length = cipher_xfrm->cipher.key.length
[PATCH v3 09/33] common/cnxk: add CPT LMT defines
From: Anoob Joseph add CPT LMT defines Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_cpt.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index c8cf9354da..ac27479371 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -60,6 +60,9 @@ ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 13) | \ ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 14)) +#define ROC_CN20K_CPT_LMT_ARG ROC_CN10K_CPT_LMT_ARG +#define ROC_CN20K_DUAL_CPT_LMT_ARG ROC_CN10K_DUAL_CPT_LMT_ARG + /* CPT helper macros */ #define ROC_CPT_AH_HDR_LEN 12 #define ROC_CPT_AES_GCM_IV_LEN 8 -- 2.34.1
[PATCH v3 13/33] common/cnxk: add cn20k meta pkt structs
From: Rahul Bhansali
Adds below structures for cn20k,
- cpt_parse_hdr_s
- cpt_rxc_sg_s
- cpt_rxc_ptr_info_s
Signed-off-by: Rahul Bhansali
---
drivers/common/cnxk/hw/cpt.h| 211 +---
drivers/common/cnxk/roc_cpt.h | 2 +-
drivers/common/cnxk/roc_cpt_debug.c | 143 +--
drivers/net/cnxk/cn10k_ethdev.c | 5 +-
drivers/net/cnxk/cn10k_rx.h | 21 +--
drivers/net/cnxk/cn20k_ethdev.c | 4 +-
6 files changed, 304 insertions(+), 82 deletions(-)
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index b308a18f0d..f2c222a920 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -322,60 +322,124 @@ union cpt_res_s {
};
/* [CN10K, .) */
-struct cpt_parse_hdr_s {
- /* WORD 0 */
- union {
- uint64_t u64;
- struct {
- uint8_t pad_len : 3;
- uint8_t num_frags : 3;
- uint8_t pkt_out : 2;
-
- uint8_t err_sum : 1;
- uint8_t reas_sts : 4;
- uint8_t reserved_53 : 1;
- uint8_t et_owr : 1;
- uint8_t pkt_fmt : 1;
-
- uint16_t match_id : 16;
-
- uint32_t cookie : 32;
- };
- } w0;
-
- /* WORD 1 */
- uint64_t wqe_ptr;
-
- /* WORD 2 */
- union {
- uint64_t u64;
- struct {
- uint8_t fi_pad : 3;
- uint8_t fi_offset : 5;
- uint8_t il3_off;
- uint16_t orig_pf_func;
- uint16_t reserved_145_160;
- uint16_t frag_age;
- };
- } w2;
-
- /* WORD 3 */
- union {
- uint64_t u64;
- struct {
- uint32_t spi;
- uint16_t reserved_209_224;
- uint8_t uc_ccode;
- uint8_t hw_ccode;
+union cpt_parse_hdr_u {
+ struct cpt_parse_hdr_s {
+ /* WORD 0 */
+ union {
+ uint64_t u64;
+ struct {
+ uint64_t cookie : 32;
+ uint64_t match_id : 16;
+ uint64_t err_sum : 1;
+ uint64_t reas_sts : 4;
+ uint64_t pad_len : 3;
+ uint64_t et_owr : 1;
+ uint64_t pkt_fmt : 1;
+ uint64_t num_frags : 4;
+ uint64_t pkt_out : 2;
+ };
+ } w0;
+
+ /* WORD 1 */
+ uint64_t wqe_ptr;
+
+ /* WORD 2 */
+ union {
+ uint64_t u64;
+ struct {
+ uint64_t rsvd_134_128 : 7;
+ uint64_t pkt_inline : 1;
+ uint64_t new_pkt_aura : 20;
+ uint64_t orig_pkt_aura : 20;
+ uint64_t il3_off : 8;
+ uint64_t ptr_pad : 3;
+ uint64_t ptr_offset : 5;
+ };
+ } w2;
+
+ /* WORD 3 */
+ union {
+ uint64_t u64;
+ struct {
+ uint8_t hw_ccode;
+ uint8_t uc_ccode;
+ uint16_t frag_age;
+ uint16_t pf_func;
+ uint16_t rlen;
+ };
+ } w3;
+
+ /* WORD 4 */
+ union {
+ uint64_t u64;
+ struct {
+ uint32_t l4_chksum;
+ uint32_t l4_chksum_type : 1;
+ uint32_t rsvd_298_289 : 10;
+ uint32_t channel : 12;
+ uint32_t sctr_size : 4;
+ uint32_t gthr_size : 5;
+ };
+ } w4;
+ } s;
+
+ struct cpt_cn10k_parse_hdr_s {
+ /* WORD 0 */
+ union {
+ uint64_t u64;
+ struct {
+ uint8_t pad_len : 3;
+ uint8_t num_frags : 3;
+ uint8_t pkt_out : 2;
+
+ uint8_t err_sum : 1;
+ uint8_t reas_sts : 4;
+ uint8_t reserved_53 : 1;
+ uint8_t et_owr : 1;
+ uint8_t pkt_
[PATCH v3 18/33] common/cnxk: support for inline inbound queue
In CN20k, since we have 16 Inline inbound queues possible, add
support to attach inline inbound queue directly to the application
instead of getting it attached to CPT PF.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/roc_features.h | 12 +
drivers/common/cnxk/roc_mbox.h | 82 ++
drivers/common/cnxk/roc_nix.h | 1 +
drivers/common/cnxk/roc_nix_fc.c | 24 +-
drivers/common/cnxk/roc_nix_inl.c | 281
drivers/common/cnxk/roc_nix_inl.h | 6 +-
drivers/common/cnxk/roc_nix_inl_dev.c | 347 +
drivers/common/cnxk/roc_nix_inl_priv.h | 28 +-
drivers/common/cnxk/roc_nix_priv.h | 6 +
drivers/common/cnxk/roc_platform.h | 1 +
drivers/net/cnxk/cnxk_ethdev.h | 2 +-
drivers/net/cnxk/cnxk_ethdev_sec.c | 9 +-
12 files changed, 686 insertions(+), 113 deletions(-)
diff --git a/drivers/common/cnxk/roc_features.h
b/drivers/common/cnxk/roc_features.h
index 59c09fbc85..49a563ef95 100644
--- a/drivers/common/cnxk/roc_features.h
+++ b/drivers/common/cnxk/roc_features.h
@@ -102,4 +102,16 @@ roc_feature_dpi_has_priority(void)
return roc_model_is_cn10k();
}
+static inline bool
+roc_feature_nix_has_inl_multi_queue(void)
+{
+ return roc_model_is_cn20k();
+}
+
+static inline bool
+roc_feature_nix_has_inl_profile(void)
+{
+ return roc_model_is_cn20k();
+}
+
#endif
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index beb7fb6e62..fbea15690b 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -183,11 +183,19 @@ struct mbox_msghdr {
msg_rsp) \
M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
+ M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req,
\
+ cpt_flt_eng_info_rsp)
\
+ M(CPT_RX_INLINE_QALLOC, 0xA0A, cpt_rx_inline_qalloc, msg_req,
\
+ cpt_rx_inline_qalloc_rsp)
\
+ M(CPT_RX_INL_QUEUE_CFG, 0xA0B, cpt_rx_inl_queue_cfg,
\
+ cpt_rx_inline_qcfg_req, msg_rsp)\
M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
cpt_rx_inline_lf_cfg_msg, msg_rsp) \
M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)\
M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,\
cpt_eng_grp_rsp) \
+ M(CPT_SET_QUEUE_PRI, 0xBFB, cpt_set_que_pri, cpt_queue_pri_req_msg,
\
+ msg_rsp) \
/* REE mbox IDs (range 0xE00 - 0xFFF) */ \
M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)\
M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,\
@@ -343,6 +351,8 @@ struct mbox_msghdr {
nix_rx_inl_profile_cfg_rsp)
\
M(NIX_RX_INLINE_LF_CFG, 0x8032, nix_rx_inl_lf_cfg,
nix_rx_inl_lf_cfg_req, \
msg_rsp)
\
+ M(NIX_RX_INL_QUEUE_CFG, 0x8033, nix_rx_inl_queue_cfg,
\
+ nix_rx_inline_qcfg_req, msg_rsp) \
/* MCS mbox IDs (range 0xa000 - 0xbFFF) */
\
M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,
\
mcs_alloc_rsrc_rsp)
\
@@ -1966,6 +1976,34 @@ struct nix_mcast_grp_update_rsp {
uint32_t __io mce_start_index;
};
+#define IPSEC_GEN_CFG_EGRP GENMASK_ULL(50, 48)
+#define IPSEC_GEN_CFG_OPCODE GENMASK_ULL(47, 32)
+#define IPSEC_GEN_CFG_PARAM1 GENMASK_ULL(31, 16)
+#define IPSEC_GEN_CFG_PARAM2 GENMASK_ULL(15, 0)
+
+#define CPT_INST_QSEL_BLOCK GENMASK_ULL(28, 24)
+#define CPT_INST_QSEL_PF_FUNC GENMASK_ULL(23, 8)
+#define CPT_INST_QSEL_SLOTGENMASK_ULL(7, 0)
+
+#define CPT_INST_CREDIT_HYST GENMASK_ULL(61, 56)
+#define CPT_INST_CREDIT_TH GENMASK_ULL(53, 32)
+#define CPT_INST_CREDIT_BPID GENMASK_ULL(30, 22)
+#define CPT_INST_CREDIT_CNT GENMASK_ULL(21, 0)
+
+/* Per queue NIX inline IPSec configuration */
+struct nix_rx_inline_qcfg_req {
+ struct mbox_msghdr hdr;
+ uint32_t __io cpt_credit;
+ uint32_t __io credit_th;
+ uint16_t __io cpt_pf_func;
+ uint16_t __io bpid;
+ uint8_t __io cpt_slot;
+ uint8_t __io rx_queue_id;
+ uint8_t __io enable;
+ uint8_t __io hysteresis;
+ uint
[PATCH v3 25/33] net/cnxk: store pool buffer size in lookup memory
From: Rahul Bhansali
Store the pool buffer size in lookup memory to calculate
mbuf start address for reassembly case in fastpath.
Also, restructured lookup memory data per port.
Signed-off-by: Rahul Bhansali
---
drivers/net/cnxk/cn20k_ethdev.c | 17 +
drivers/net/cnxk/cn20k_rxtx.h | 1 +
drivers/net/cnxk/cnxk_ethdev.h| 2 +
drivers/net/cnxk/cnxk_ethdev_dp.h | 29 ---
drivers/net/cnxk/cnxk_lookup.c| 61 +++
5 files changed, 98 insertions(+), 12 deletions(-)
diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c
index db8d08cb2a..740fdb7f76 100644
--- a/drivers/net/cnxk/cn20k_ethdev.c
+++ b/drivers/net/cnxk/cn20k_ethdev.c
@@ -319,6 +319,8 @@ cn20k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev,
uint16_t qid, uint16_t nb_
/* Data offset from data to start of mbuf is first_skip */
rxq->data_off = rq->first_skip;
rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev);
+ rxq->mp_buf_sz = (mp->elt_size + mp->header_size + mp->trailer_size) &
0x;
+ rxq->mp_buf_sz |= (uint64_t)mp->header_size << 32;
/* Setup security related info */
if (dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F) {
@@ -358,6 +360,18 @@ cn20k_nix_rx_queue_meta_aura_update(struct rte_eth_dev
*eth_dev)
cnxk_nix_lookup_mem_metapool_set(dev);
}
+static void
+cn20k_nix_rx_queue_bufsize_update(struct rte_eth_dev *eth_dev)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct cn20k_eth_rxq *rxq;
+
+ rxq = eth_dev->data->rx_queues[0];
+
+ /* Store bufsize in lookup mem */
+ cnxk_nix_lookup_mem_bufsize_set(dev, rxq->mp_buf_sz);
+}
+
static int
cn20k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
{
@@ -590,6 +604,9 @@ cn20k_nix_dev_start(struct rte_eth_dev *eth_dev)
if (roc_idev_nix_rx_inject_get(nix->port_id))
dev->rx_offload_flags |= NIX_RX_SEC_REASSEMBLY_F;
+ if (dev->rx_offload_flags & NIX_RX_REAS_F)
+ cn20k_nix_rx_queue_bufsize_update(eth_dev);
+
cn20k_eth_set_tx_function(eth_dev);
cn20k_eth_set_rx_function(eth_dev);
return 0;
diff --git a/drivers/net/cnxk/cn20k_rxtx.h b/drivers/net/cnxk/cn20k_rxtx.h
index e40edba69d..f23c16ec07 100644
--- a/drivers/net/cnxk/cn20k_rxtx.h
+++ b/drivers/net/cnxk/cn20k_rxtx.h
@@ -82,6 +82,7 @@ struct cn20k_eth_rxq {
uint64_t meta_aura;
uintptr_t meta_pool;
uint16_t rq;
+ uint64_t mp_buf_sz;
struct cnxk_timesync_info *tstamp;
} __plt_cache_aligned;
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 9b85927f48..daf80be51b 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -727,6 +727,8 @@ int cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev
*dev);
int cnxk_nix_lookup_mem_sa_base_clear(struct cnxk_eth_dev *dev);
int cnxk_nix_lookup_mem_metapool_set(struct cnxk_eth_dev *dev);
int cnxk_nix_lookup_mem_metapool_clear(struct cnxk_eth_dev *dev);
+int cnxk_nix_lookup_mem_bufsize_set(struct cnxk_eth_dev *dev, uint64_t size);
+int cnxk_nix_lookup_mem_bufsize_clear(struct cnxk_eth_dev *dev);
__rte_internal
int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev);
__rte_internal
diff --git a/drivers/net/cnxk/cnxk_ethdev_dp.h
b/drivers/net/cnxk/cnxk_ethdev_dp.h
index 100d22e759..b5836b491e 100644
--- a/drivers/net/cnxk/cnxk_ethdev_dp.h
+++ b/drivers/net/cnxk/cnxk_ethdev_dp.h
@@ -35,8 +35,11 @@
#define ERRCODE_ERRLEN_WIDTH 12
#define ERR_ARRAY_SZ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t))
-#define SA_BASE_TBL_SZ (RTE_MAX_ETHPORTS * sizeof(uintptr_t))
-#define MEMPOOL_TBL_SZ (RTE_MAX_ETHPORTS * sizeof(uintptr_t))
+#define SA_BASE_OFFSET 8 /* offset in bytes */
+#define MEMPOOL_OFFSET 8 /* offset in bytes */
+#define BUFLEN_OFFSET 8 /* offset in bytes */
+#define LOOKUP_MEM_PORTDATA_SZ (SA_BASE_OFFSET + MEMPOOL_OFFSET +
BUFLEN_OFFSET)
+#define LOOKUP_MEM_PORTDATA_TOTAL_SZ (RTE_MAX_ETHPORTS *
LOOKUP_MEM_PORTDATA_SZ)
#define CNXK_NIX_UDP_TUN_BITMASK
\
((1ull << (RTE_MBUF_F_TX_TUNNEL_VXLAN >> 45)) |
\
@@ -174,20 +177,36 @@ static __rte_always_inline uintptr_t
cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem)
{
uintptr_t sa_base_tbl;
+ uint32_t offset;
sa_base_tbl = (uintptr_t)lookup_mem;
sa_base_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ;
- return *((const uintptr_t *)sa_base_tbl + port);
+ offset = port * LOOKUP_MEM_PORTDATA_SZ;
+ return *((const uintptr_t *)sa_base_tbl + offset / 8);
}
static __rte_always_inline uintptr_t
cnxk_nix_inl_metapool_get(uint16_t port, const void *lookup_mem)
{
uintptr_t metapool_tbl;
+ uint32_t offset;
metapool_tbl = (uintptr_t)lookup_mem;
- metapool_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ +
[PATCH v3 22/33] common/cnxk: support for NPC inline rule for cn20k
Use UCAST_CPT in cn20k as opposed to UCAST_IPSEC in cn10k
for inline IPsec rule.
Signed-off-by: Nithin Dabilpuram
---
drivers/common/cnxk/hw/nix.h| 1 +
drivers/common/cnxk/roc_npc.c | 15 +++
drivers/common/cnxk/roc_npc_mcam.c | 7 ---
drivers/common/cnxk/roc_npc_mcam_dump.c | 5 +
drivers/common/cnxk/roc_npc_priv.h | 8
5 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
index e4d8d285d5..d16fa3b3ec 100644
--- a/drivers/common/cnxk/hw/nix.h
+++ b/drivers/common/cnxk/hw/nix.h
@@ -645,6 +645,7 @@
#define NIX_RX_ACTIONOP_RSS (0x4ull)
#define NIX_RX_ACTIONOP_PF_FUNC_DROP (0x5ull)
#define NIX_RX_ACTIONOP_MIRROR (0x6ull)
+#define NIX_RX_ACTIONOP_UCAST_CPT(0x7ull)
#define NIX_RX_ACTIONOP_DEFAULT (0xfull)
#define NIX_RX_VTAGACTION_VTAG0_RELPTR (0x0ull)
diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index 138f12f6d8..94d5cc84f8 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -568,6 +568,7 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct
roc_npc_attr *attr,
struct npc *npc = roc_npc_to_npc_priv(roc_npc);
const struct roc_npc_action *sec_action = NULL;
const struct roc_npc_action_sample *act_sample;
+ struct roc_nix *roc_nix = roc_npc->roc_nix;
const struct roc_npc_action_mark *act_mark;
const struct roc_npc_action_meter *act_mtr;
const struct roc_npc_action_queue *act_q;
@@ -576,7 +577,6 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct
roc_npc_attr *attr,
uint8_t has_spi_to_sa_act = 0;
int sel_act, req_act = 0;
uint16_t pf_func, vf_id;
- struct roc_nix *roc_nix;
int errcode = 0;
int mark = 0;
int rq = 0;
@@ -885,8 +885,15 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct
roc_npc_attr *attr,
} else if (req_act & ROC_NPC_ACTION_TYPE_RSS) {
flow->npc_action = NIX_RX_ACTIONOP_UCAST;
} else if (req_act & ROC_NPC_ACTION_TYPE_SEC) {
- flow->npc_action = NIX_RX_ACTIONOP_UCAST_IPSEC;
- flow->npc_action |= (uint64_t)rq << 20;
+ if (roc_model_is_cn20k()) {
+ flow->npc_action = NIX_RX_ACTIONOP_UCAST_CPT;
+ flow->npc_action |= (uint64_t)rq << 20;
+ flow->npc_action2 =
+ roc_nix_inl_inb_ipsec_profile_id_get(roc_nix,
true) << 8;
+ } else {
+ flow->npc_action = NIX_RX_ACTIONOP_UCAST_IPSEC;
+ flow->npc_action |= (uint64_t)rq << 20;
+ }
} else if (req_act & (ROC_NPC_ACTION_TYPE_FLAG |
ROC_NPC_ACTION_TYPE_MARK)) {
flow->npc_action = NIX_RX_ACTIONOP_UCAST;
} else if (req_act & ROC_NPC_ACTION_TYPE_COUNT) {
@@ -1550,7 +1557,7 @@ npc_inline_dev_ipsec_action_free(struct npc *npc, struct
roc_npc_flow *flow)
inl_dev = idev->nix_inl_dev;
if (flow->nix_intf == NIX_INTF_RX && inl_dev && inl_dev->ipsec_index &&
- ((flow->npc_action & 0xF) == NIX_RX_ACTIONOP_UCAST_IPSEC)) {
+ roc_npc_action_is_rx_inline(flow->npc_action)) {
inl_dev->curr_ipsec_idx--;
inl_dev->ipsec_index[inl_dev->curr_ipsec_idx] = flow->mcam_id;
flow->enable = 0;
diff --git a/drivers/common/cnxk/roc_npc_mcam.c
b/drivers/common/cnxk/roc_npc_mcam.c
index 5db72c22ae..3aa7ff56a9 100644
--- a/drivers/common/cnxk/roc_npc_mcam.c
+++ b/drivers/common/cnxk/roc_npc_mcam.c
@@ -747,7 +747,7 @@ npc_mcam_set_channel(struct roc_npc_flow *flow, struct
npc_cn20k_mcam_write_entr
chan = (channel | NIX_CHAN_CPT_CH_START);
mask = (chan_mask | NIX_CHAN_CPT_CH_START);
} else {
- if (!(flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) {
+ if (!roc_npc_action_is_rx_inline(flow->npc_action)) {
/*
* Clear bits 10 & 11 corresponding to CPT
* channel. By default, rules should match
@@ -951,6 +951,7 @@ npc_mcam_alloc_and_write(struct npc *npc, struct
roc_npc_flow *flow, struct npc_
if (flow->nix_intf == NIX_INTF_RX)
flow->npc_action |= (uint64_t)flow->recv_queue << 20;
req.entry_data.action = flow->npc_action;
+ req.entry_data.action2 = flow->npc_action2;
/*
* Driver sets vtag action on per interface basis, not
@@ -973,7 +974,7 @@ npc_mcam_alloc_and_write(struct npc *npc, struct
roc_npc_flow *flow, struct npc_
if (flow->nix_intf == NIX_INTF_RX) {
if (inl_dev && inl_dev->is_multi_channel &&
- (flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) {
+ roc_npc_action
[PATCH v3 30/33] common/cnxk: add stats reset for inline device
From: Monendra Singh Kushwaha
This patch adds support to reset inline device stats.
Signed-off-by: Monendra Singh Kushwaha
---
drivers/common/cnxk/roc_nix_inl.h | 1 +
drivers/common/cnxk/roc_nix_inl_dev.c | 27 +++
drivers/common/cnxk/version.map | 1 +
3 files changed, 29 insertions(+)
diff --git a/drivers/common/cnxk/roc_nix_inl.h
b/drivers/common/cnxk/roc_nix_inl.h
index 2db3a0d0f2..dab4918535 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -130,6 +130,7 @@ void __roc_api roc_nix_inl_dev_lock(void);
void __roc_api roc_nix_inl_dev_unlock(void);
int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);
int __roc_api roc_nix_inl_dev_stats_get(struct roc_nix_stats *stats);
+int __roc_api roc_nix_inl_dev_stats_reset(void);
int __roc_api roc_nix_inl_dev_cpt_setup(bool use_inl_dev_sso);
int __roc_api roc_nix_inl_dev_cpt_release(void);
bool __roc_api roc_nix_inl_dev_is_multi_channel(void);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index 041ccd9c13..2e753440b7 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -1295,6 +1295,33 @@ roc_nix_inl_dev_stats_get(struct roc_nix_stats *stats)
return 0;
}
+int
+roc_nix_inl_dev_stats_reset(void)
+{
+ struct idev_cfg *idev = idev_get_cfg();
+ struct nix_inl_dev *inl_dev = NULL;
+ struct mbox *mbox;
+ int rc;
+
+ if (idev && idev->nix_inl_dev)
+ inl_dev = idev->nix_inl_dev;
+
+ if (!inl_dev)
+ return -EINVAL;
+
+ mbox = mbox_get((&inl_dev->dev)->mbox);
+
+ if (mbox_alloc_msg_nix_stats_rst(mbox) == NULL) {
+ rc = -ENOMEM;
+ goto exit;
+ }
+
+ rc = mbox_process(mbox);
+exit:
+ mbox_put(mbox);
+ return rc;
+}
+
int
roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
{
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 36eb46e3a1..cdbfc1d39a 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -252,6 +252,7 @@ INTERNAL {
roc_nix_inl_dev_is_multi_channel;
roc_nix_inl_dev_is_probed;
roc_nix_inl_dev_stats_get;
+ roc_nix_inl_dev_stats_reset;
roc_nix_inl_dev_lock;
roc_nix_inl_dev_rq;
roc_nix_inl_dev_rq_get;
--
2.34.1
[PATCH v3 28/33] common/cnxk: enable allmulti mode on rpm/cgx VF
From: Monendra Singh Kushwaha
This patch enables allmulti mode on rpm/cgx vf devices.
Signed-off-by: Monendra Singh Kushwaha
---
.mailmap | 1 +
drivers/common/cnxk/roc_mbox.h| 1 +
drivers/common/cnxk/roc_nix_npc.c | 10 +++---
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/.mailmap b/.mailmap
index a03d3cfb59..d5eb506ad5 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1059,6 +1059,7 @@ Mohammed Gamal
Mohsin Kazmi
Mohsin Mazhar Shaikh
Mohsin Shaikh
+Monendra Singh Kushwaha
Morten Brørup
Moti Haimovsky
Muhammad Ahmad
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 6d927c7972..a82d120d1d 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1848,6 +1848,7 @@ struct nix_rx_mode {
#define NIX_RX_MODE_UCASTBIT(0)
#define NIX_RX_MODE_PROMISC BIT(1)
#define NIX_RX_MODE_ALLMULTI BIT(2)
+#define NIX_RX_MODE_USE_MCE BIT(3)
uint16_t __io mode;
};
diff --git a/drivers/common/cnxk/roc_nix_npc.c
b/drivers/common/cnxk/roc_nix_npc.c
index 8c4a5753ee..1d445c0d92 100644
--- a/drivers/common/cnxk/roc_nix_npc.c
+++ b/drivers/common/cnxk/roc_nix_npc.c
@@ -101,7 +101,7 @@ roc_nix_npc_mcast_config(struct roc_nix *roc_nix, bool
mcast_enable,
struct nix_rx_mode *req;
int rc = -ENOSPC;
- if (roc_nix_is_vf_or_sdp(roc_nix)) {
+ if (roc_nix_is_sdp(roc_nix) || roc_nix_is_lbk(roc_nix)) {
rc = 0;
goto exit;
}
@@ -110,9 +110,13 @@ roc_nix_npc_mcast_config(struct roc_nix *roc_nix, bool
mcast_enable,
if (req == NULL)
goto exit;
- if (mcast_enable)
+ if (mcast_enable) {
req->mode = NIX_RX_MODE_ALLMULTI;
- if (prom_enable)
+ if (dev_is_vf(&nix->dev))
+ req->mode |= NIX_RX_MODE_USE_MCE;
+ }
+
+ if (prom_enable && !dev_is_vf(&nix->dev))
req->mode = NIX_RX_MODE_PROMISC;
rc = mbox_process(mbox);
--
2.34.1
[PATCH v3 02/33] common/cnxk: remove unused param in SA init
From: Anoob Joseph
Remove unused param in SA init.
Signed-off-by: Anoob Joseph
---
drivers/common/cnxk/cnxk_security.c | 5 ++---
drivers/common/cnxk/cnxk_security.h | 3 +--
drivers/common/cnxk/roc_ie_ot.c | 4 +---
drivers/common/cnxk/roc_ie_ot.h | 3 +--
drivers/common/cnxk/roc_nix_inl.c | 2 +-
drivers/common/cnxk/roc_nix_inl_dev.c | 2 +-
drivers/crypto/cnxk/cn10k_ipsec.c | 5 ++---
drivers/net/cnxk/cn10k_ethdev_sec.c | 8 +++-
8 files changed, 12 insertions(+), 20 deletions(-)
diff --git a/drivers/common/cnxk/cnxk_security.c
b/drivers/common/cnxk/cnxk_security.c
index 9446c14ac8..8953e901a1 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -304,8 +304,7 @@ ot_ipsec_inb_tunnel_hdr_fill(struct roc_ot_ipsec_inb_sa *sa,
int
cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
struct rte_security_ipsec_xform *ipsec_xfrm,
- struct rte_crypto_sym_xform *crypto_xfrm,
- bool is_inline)
+ struct rte_crypto_sym_xform *crypto_xfrm)
{
uint16_t sport = 4500, dport = 4500;
union roc_ot_ipsec_sa_word2 w2;
@@ -314,7 +313,7 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
int rc;
/* Initialize the SA */
- roc_ot_ipsec_inb_sa_init(sa, is_inline);
+ roc_ot_ipsec_inb_sa_init(sa);
w2.u64 = 0;
rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->w8.s.salt,
diff --git a/drivers/common/cnxk/cnxk_security.h
b/drivers/common/cnxk/cnxk_security.h
index 19eb9bb03d..cd78b283f0 100644
--- a/drivers/common/cnxk/cnxk_security.h
+++ b/drivers/common/cnxk/cnxk_security.h
@@ -39,8 +39,7 @@ cnxk_ipsec_outb_roundup_byte(enum rte_crypto_cipher_algorithm
c_algo,
int __roc_api
cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
struct rte_security_ipsec_xform *ipsec_xfrm,
- struct rte_crypto_sym_xform *crypto_xfrm,
- bool is_inline);
+ struct rte_crypto_sym_xform *crypto_xfrm);
int __roc_api
cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
struct rte_security_ipsec_xform *ipsec_xfrm,
diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c
index 1b436dba72..b906834672 100644
--- a/drivers/common/cnxk/roc_ie_ot.c
+++ b/drivers/common/cnxk/roc_ie_ot.c
@@ -6,7 +6,7 @@
#include "roc_priv.h"
void
-roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline)
+roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa)
{
size_t offset;
@@ -18,8 +18,6 @@ roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool
is_inline)
sa->w0.s.et_ovrwr = 1;
sa->w2.s.l3hdr_on_err = 1;
- PLT_SET_USED(is_inline);
-
offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index 1420e3d586..26616be901 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -554,7 +554,6 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa,
ctx) ==
#define ROC_OT_IPSEC_SA_SZ_MAX \
(PLT_MAX(sizeof(struct roc_ot_ipsec_inb_sa), sizeof(struct
roc_ot_ipsec_outb_sa)))
-void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa,
- bool is_inline);
+void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa);
void __roc_api roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa);
#endif /* __ROC_IE_OT_H__ */
diff --git a/drivers/common/cnxk/roc_nix_inl.c
b/drivers/common/cnxk/roc_nix_inl.c
index 5b79bc2266..88d5a678b1 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -423,7 +423,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
if (roc_model_is_cn10k()) {
for (i = 0; i < max_sa; i++) {
sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
- roc_ot_ipsec_inb_sa_init(sa, true);
+ roc_ot_ipsec_inb_sa_init(sa);
}
}
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c
b/drivers/common/cnxk/roc_nix_inl_dev.c
index ffe6eef81f..d26cbee0cc 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -440,7 +440,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
for (i = 0; i < max_sa; i++) {
sa = ((uint8_t *)inl_dev->inb_sa_base) +
(i * inb_sa_sz);
- roc_ot_ipsec_inb_sa_init(sa, true);
+ roc_ot_ipsec_inb_sa_init(sa);
}
}
/* Setup device specific inb SA table */
diff --git
[PATCH v3 33/33] common/cnxk: move interrupt handling to platform-specific
From: Satha Rao
This change refactors the interrupt handling to be platform-specific.
Some platforms directly call ioctls, while others provide a library API
for the same functionality. Moving the interrupt handling to
platform-specific implementations enhances clarity and maintainability.
Signed-off-by: Satha Rao
---
drivers/common/cnxk/roc_irq.c | 239 +++--
drivers/common/cnxk/roc_platform.c | 231
drivers/common/cnxk/roc_platform.h | 7 +
3 files changed, 259 insertions(+), 218 deletions(-)
diff --git a/drivers/common/cnxk/roc_irq.c b/drivers/common/cnxk/roc_irq.c
index 0b21b9e2d9..b1d41346c0 100644
--- a/drivers/common/cnxk/roc_irq.c
+++ b/drivers/common/cnxk/roc_irq.c
@@ -7,243 +7,37 @@
#if defined(__linux__)
-#include
-#include
-#include
-#include
-#include
-
-#define MSIX_IRQ_SET_BUF_LEN
\
- (sizeof(struct vfio_irq_set) + sizeof(int) * \
- ((uint32_t)plt_intr_max_intr_get(intr_handle)))
-
-static int
-irq_get_info(struct plt_intr_handle *intr_handle)
-{
- struct vfio_irq_info irq = {.argsz = sizeof(irq)};
- int rc, vfio_dev_fd;
-
- irq.index = VFIO_PCI_MSIX_IRQ_INDEX;
-
- vfio_dev_fd = plt_intr_dev_fd_get(intr_handle);
- rc = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
- if (rc < 0) {
- plt_err("Failed to get IRQ info rc=%d errno=%d", rc, errno);
- return rc;
- }
-
- plt_base_dbg("Flags=0x%x index=0x%x count=0x%x max_intr_vec_id=0x%x",
-irq.flags, irq.index, irq.count, PLT_MAX_RXTX_INTR_VEC_ID);
-
- if (irq.count == 0) {
- plt_err("HW max=%d > PLT_MAX_RXTX_INTR_VEC_ID: %d", irq.count,
- PLT_MAX_RXTX_INTR_VEC_ID);
- plt_intr_max_intr_set(intr_handle, PLT_MAX_RXTX_INTR_VEC_ID);
- } else {
- if (plt_intr_max_intr_set(intr_handle, irq.count))
- return -1;
- }
-
- return 0;
-}
-
-static int
-irq_config(struct plt_intr_handle *intr_handle, unsigned int vec)
-{
- char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
- struct vfio_irq_set *irq_set;
- int len, rc, vfio_dev_fd;
- int32_t *fd_ptr;
-
- if (vec > (uint32_t)plt_intr_max_intr_get(intr_handle)) {
- plt_err("vector=%d greater than max_intr=%d", vec,
- plt_intr_max_intr_get(intr_handle));
- return -EINVAL;
- }
-
- len = sizeof(struct vfio_irq_set) + sizeof(int32_t);
-
- irq_set = (struct vfio_irq_set *)irq_set_buf;
- irq_set->argsz = len;
-
- irq_set->start = vec;
- irq_set->count = 1;
- irq_set->flags =
- VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
- irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
-
- /* Use vec fd to set interrupt vectors */
- fd_ptr = (int32_t *)&irq_set->data[0];
- fd_ptr[0] = plt_intr_efds_index_get(intr_handle, vec);
-
- vfio_dev_fd = plt_intr_dev_fd_get(intr_handle);
- rc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
- if (rc)
- plt_err("Failed to set_irqs vector=0x%x rc=%d", vec, rc);
-
- return rc;
-}
-
-static int
-irq_init(struct plt_intr_handle *intr_handle)
-{
- char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
- struct vfio_irq_set *irq_set;
- int len, rc, vfio_dev_fd;
- int32_t *fd_ptr;
- uint32_t i;
-
- len = sizeof(struct vfio_irq_set) +
- sizeof(int32_t) * plt_intr_max_intr_get(intr_handle);
-
- irq_set = (struct vfio_irq_set *)irq_set_buf;
- irq_set->argsz = len;
- irq_set->start = 0;
- irq_set->count = plt_intr_max_intr_get(intr_handle);
- irq_set->flags =
- VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
- irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
-
- fd_ptr = (int32_t *)&irq_set->data[0];
- for (i = 0; i < irq_set->count; i++)
- fd_ptr[i] = -1;
-
- vfio_dev_fd = plt_intr_dev_fd_get(intr_handle);
- rc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
- if (rc)
- plt_err("Failed to set irqs vector rc=%d", rc);
-
- return rc;
-}
-
int
dev_irqs_disable(struct plt_intr_handle *intr_handle)
{
- /* Clear max_intr to indicate re-init next time */
- plt_intr_max_intr_set(intr_handle, 0);
- return plt_intr_disable(intr_handle);
+ return plt_irq_disable(intr_handle);
}
int
dev_irq_reconfigure(struct plt_intr_handle *intr_handle, uint16_t max_intr)
{
- /* Disable interrupts if enabled. */
- if (plt_intr_max_intr_get(intr_handle))
- dev_irqs_disable(intr_handle);
-
- plt_intr_max_intr_set(intr_handle, max_intr);
- return irq_init(intr_handle);
+ return plt_irq_reconfigure(intr_handle, max_intr);
}
int
[PATCH v3 03/33] net/cnxk: remove unnecessary delay on stats read
Remove unnecessary delay on security stats read as application is expected to poll if stats are not updated as expected. It is expected that there would be a delay in stats to show up like any other ethdev stats get API. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_ethdev_sec.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 3f81913d41..68691d2bfe 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -1243,7 +1243,6 @@ cn10k_eth_sec_session_stats_get(void *device, struct rte_security_session *sess, ROC_NIX_INL_SA_OP_FLUSH); if (rc) return -EINVAL; - rte_delay_ms(1); stats->protocol = RTE_SECURITY_PROTOCOL_IPSEC; -- 2.34.1
[PATCH v3 01/33] net/cnxk: allow duplicate SPI in outbound IPsec
Since outbound IPsec is not really dependent on SPI,
allow duplicate SPI in outbound inline IPsec sessions.
Signed-off-by: Nithin Dabilpuram
---
v3:
- Add cc stable to 29/33 patch
v2:
- Rebased on top of latest code
- Fixed build issue with 26/33
- Updated release notes
drivers/net/cnxk/cn10k_ethdev_sec.c | 14 +++---
drivers/net/cnxk/cn9k_ethdev_sec.c | 14 +++---
drivers/net/cnxk/cnxk_ethdev.h | 4 ++--
drivers/net/cnxk/cnxk_ethdev_sec.c | 8 ++--
4 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 6acab8afa0..41dfba36d3 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -793,13 +793,6 @@ cn10k_eth_sec_session_create(void *device,
inbound = !!(ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS);
inl_dev = !!dev->inb.inl_dev;
- /* Search if a session already exits */
- if (cnxk_eth_sec_sess_get_by_spi(dev, ipsec->spi, inbound)) {
- plt_err("%s SA with SPI %u already in use",
- inbound ? "Inbound" : "Outbound", ipsec->spi);
- return -EEXIST;
- }
-
memset(eth_sec, 0, sizeof(struct cnxk_eth_sec_sess));
sess_priv.u64 = 0;
@@ -821,6 +814,13 @@ cn10k_eth_sec_session_create(void *device,
spi_mask = roc_nix_inl_inb_spi_range(nix, inl_dev, NULL, NULL);
+ /* Search if a session already exits */
+ if (cnxk_eth_sec_sess_get_by_sa_idx(dev, ipsec->spi & spi_mask,
true)) {
+ plt_err("Inbound SA with SPI/SA index %u already in
use", ipsec->spi);
+ rc = -EEXIST;
+ goto err;
+ }
+
/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE */
sa = roc_nix_inl_inb_sa_get(nix, inl_dev, ipsec->spi);
if (!sa && dev->inb.inl_dev) {
diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c
b/drivers/net/cnxk/cn9k_ethdev_sec.c
index 390853c728..5e13dc862e 100644
--- a/drivers/net/cnxk/cn9k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn9k_ethdev_sec.c
@@ -604,13 +604,6 @@ cn9k_eth_sec_session_create(void *device,
crypto = conf->crypto_xform;
inbound = !!(ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS);
- /* Search if a session already exists */
- if (cnxk_eth_sec_sess_get_by_spi(dev, ipsec->spi, inbound)) {
- plt_err("%s SA with SPI %u already in use",
- inbound ? "Inbound" : "Outbound", ipsec->spi);
- return -EEXIST;
- }
-
lock = inbound ? &dev->inb.lock : &dev->outb.lock;
rte_spinlock_lock(lock);
@@ -633,6 +626,13 @@ cn9k_eth_sec_session_create(void *device,
spi_mask = roc_nix_inl_inb_spi_range(nix, false, NULL, NULL);
+ /* Search if a session already exits */
+ if (cnxk_eth_sec_sess_get_by_sa_idx(dev, ipsec->spi & spi_mask,
true)) {
+ plt_err("Inbound SA with SPI/SA index %u already in
use", ipsec->spi);
+ rc = -EEXIST;
+ goto err;
+ }
+
/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE. Assume no inline
* device always for CN9K.
*/
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 350adc1161..eae5336a9b 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -729,8 +729,8 @@ typedef void (*cnxk_ethdev_rx_offload_cb_t)(uint16_t
port_id, uint64_t flags);
__rte_internal
void cnxk_ethdev_rx_offload_cb_register(cnxk_ethdev_rx_offload_cb_t cb);
-struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev
*dev,
- uint32_t spi, bool inb);
+struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_sa_idx(struct cnxk_eth_dev
*dev,
+ uint32_t sa_idx, bool
inb);
struct cnxk_eth_sec_sess *
cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev,
struct rte_security_session *sess);
diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c
b/drivers/net/cnxk/cnxk_ethdev_sec.c
index ef75e5f0f1..2c649c985a 100644
--- a/drivers/net/cnxk/cnxk_ethdev_sec.c
+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c
@@ -231,6 +231,10 @@ cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev,
uint32_t *idx_p,
if (spi > dev->outb.max_sa)
return -ENOTSUP;
idx = spi;
+ if (!plt_bitmap_get(dev->outb.sa_bmap, idx)) {
+ plt_err("Outbound SA index %u already in use", idx);
+ return -EEXIST;
+ }
} else {
/* Scan bitmap to get the free sa index */
rc = plt_bitmap_scan(dev->outb.sa_bmap, &pos, &slab);
@@ -265,14 +269
[PATCH 0/2] Wangxun bug fixes
Fix some bugs for txgbe and ngbe. Zaiyu Wang (2): net/ngbe: fix WOL and NCSI capability error net/txgbe: remove meaningless choice for SW-FW sync drivers/net/ngbe/base/ngbe_hw.c| 8 +--- drivers/net/txgbe/base/txgbe_phy.c | 8 ++-- 2 files changed, 7 insertions(+), 9 deletions(-) -- 2.21.0.windows.1
RE: [PATCH v5 08/10] test-pmd: declare lcore_count atomic
> Subject: [PATCH v5 08/10] test-pmd: declare lcore_count atomic
As a nit, the changes are not in testpmd, bit in the UT.
Acked-by: Konstantin Ananyev
> Compiling with MSVC results in the error below:
>
> app/test/test_ring_perf.c(197): error C7712: address argument to atomic
> operation must be a pointer to an atomic integer,
> 'volatile unsigned int *' is not valid
>
> The fix is to mark lcore_count as atomic.
>
> Signed-off-by: Andre Muezerie
> Signed-off-by: Chengwen Feng
> ---
> app/test/test_ring_perf.c | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
> index 57cd04a124..921aa902c5 100644
> --- a/app/test/test_ring_perf.c
> +++ b/app/test/test_ring_perf.c
> @@ -34,7 +34,7 @@ struct lcore_pair {
> unsigned c1, c2;
> };
>
> -static volatile unsigned lcore_count = 0;
> +static volatile RTE_ATOMIC(unsigned int) lcore_count;
>
> static void
> test_ring_print_test_string(unsigned int api_type, int esize,
> @@ -193,11 +193,7 @@ enqueue_dequeue_bulk_helper(const unsigned int flag,
> struct thread_params *p)
> unsigned int n_remaining;
> const unsigned int bulk_n = bulk_sizes[p->ring_params->bulk_sizes_i];
>
> -#ifdef RTE_USE_C11_MEM_MODEL
> if (rte_atomic_fetch_add_explicit(&lcore_count, 1,
> rte_memory_order_relaxed) + 1 != 2)
> -#else
> - if (__sync_add_and_fetch(&lcore_count, 1) != 2)
> -#endif
> while(lcore_count != 2)
> rte_pause();
>
> --
> 2.48.1.vfs.0.0
>
[PATCH 1/2] net/ngbe: fix WOL and NCSI capability error
When determining NIC's WOL and NCSI capability via sub-system ID,
flag matching must be exact, not inclusive. Misidentifying WOL/NCSI
capability will skip PHY configuration, causing link-up failure.
Fixes: 5f1ab0d529fc ("net/ngbe: add WOL and NCSI capability")
Cc: sta...@dpdk.org
Signed-off-by: Zaiyu Wang
---
drivers/net/ngbe/base/ngbe_hw.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c
index e29a1946e5..6688ae6a31 100644
--- a/drivers/net/ngbe/base/ngbe_hw.c
+++ b/drivers/net/ngbe/base/ngbe_hw.c
@@ -1922,6 +1922,8 @@ void ngbe_read_efuse(struct ngbe_hw *hw)
void ngbe_map_device_id(struct ngbe_hw *hw)
{
u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
+ u16 ncsi = hw->sub_system_id & NGBE_NCSI_SUP_MASK;
+ u16 wol = hw->sub_system_id & NGBE_WOL_SUP_MASK;
hw->is_pf = true;
@@ -1982,9 +1984,9 @@ void ngbe_map_device_id(struct ngbe_hw *hw)
oem == NGBE_LY_YT8521S_SFP)
hw->gpio_ctl = true;
- hw->wol_enabled = (hw->sub_system_id & NGBE_WOL_SUP_MASK) ? true :
false;
- hw->ncsi_enabled = (hw->sub_system_id & NGBE_NCSI_SUP_MASK ||
- hw->sub_system_id & NGBE_OCP_CARD) ? true : false;
+ hw->wol_enabled = (wol == NGBE_WOL_SUP_MASK) ? true : false;
+ hw->ncsi_enabled = (ncsi == NGBE_NCSI_SUP_MASK ||
+ oem == NGBE_OCP_CARD) ? true : false;
}
/**
--
2.21.0.windows.1
[PATCH 2/2] net/txgbe: remove meaningless choice for SW-FW sync
Remove superfluous 'if' and 'else' for SW-FW sync.
Bugzilla ID: 1581
Fixes: 5364a1ce30df ("net/txgbe: add PHY init")
Cc: sta...@dpdk.org
Signed-off-by: Zaiyu Wang
---
drivers/net/txgbe/base/txgbe_phy.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_phy.c
b/drivers/net/txgbe/base/txgbe_phy.c
index d87af656d5..ce6882e262 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -80,12 +80,8 @@ static s32 txgbe_read_phy_if(struct txgbe_hw *hw)
if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT)
hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel);
- if (!hw->phy.phy_semaphore_mask) {
- if (hw->bus.lan_id)
- hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
- else
- hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
- }
+ if (!hw->phy.phy_semaphore_mask)
+ hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
return 0;
}
--
2.21.0.windows.1
[v5 0/5] vhost: add RSA support
This patch series supports asymmetric RSA in vhost crypto library. It also includes changes to improve vhost crypto library: * support newer QEMU versions. * fix broken vhost_crypto example application. * stabilize crypto fastpath operations. v5: - added docs. Gowrishankar Muthukrishnan (5): vhost: skip crypto op fetch before vring init vhost: update vhost_user crypto session parameters examples/vhost_crypto: fix user callbacks vhost: support asymmetric RSA crypto ops examples/vhost_crypto: support asymmetric crypto doc/guides/rel_notes/release_25_03.rst| 3 + doc/guides/sample_app_ug/vhost_crypto.rst | 5 + examples/vhost_crypto/main.c | 54 ++- lib/vhost/vhost_crypto.c | 508 -- lib/vhost/vhost_user.h| 33 +- lib/vhost/virtio_crypto.h | 67 +++ 6 files changed, 611 insertions(+), 59 deletions(-) -- 2.25.1
[v5 1/5] vhost: skip crypto op fetch before vring init
Until virtio avail ring is initialized (by VHOST_USER_SET_VRING_ADDR),
worker thread should not try to fetch crypto op, which would lead to
memory fault.
Fixes: 939066d96563 ("vhost/crypto: add public function implementation")
Cc: sta...@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Akhil Goyal
---
lib/vhost/vhost_crypto.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/lib/vhost/vhost_crypto.c b/lib/vhost/vhost_crypto.c
index 3dc41a3bd5..55ea24710e 100644
--- a/lib/vhost/vhost_crypto.c
+++ b/lib/vhost/vhost_crypto.c
@@ -1580,6 +1580,16 @@ rte_vhost_crypto_fetch_requests(int vid, uint32_t qid,
vq = dev->virtqueue[qid];
+ if (unlikely(vq == NULL)) {
+ VC_LOG_ERR("Invalid virtqueue %u", qid);
+ return 0;
+ }
+
+ if (unlikely(vq->avail == NULL)) {
+ VC_LOG_DBG("Virtqueue ring not yet initialized %u", qid);
+ return 0;
+ }
+
avail_idx = *((volatile uint16_t *)&vq->avail->idx);
start_idx = vq->last_used_idx;
count = avail_idx - start_idx;
--
2.25.1
[v5 2/5] vhost: update vhost_user crypto session parameters
As per requirements on vhost_user spec, session id should be
located at the end of session parameter.
Update VhostUserCryptoSessionParam structure to support newer QEMU
versions (v9). Due to additional parameters added in QEMU,
received payload from QEMU would be larger than existing payload.
Hence, it would break parsing vhost_user messages.
This patch addresses both of the above problems.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Akhil Goyal
---
v5:
- updated patch description for QEMU version.
---
lib/vhost/vhost_crypto.c | 12 ++--
lib/vhost/vhost_user.h | 33 +
2 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/lib/vhost/vhost_crypto.c b/lib/vhost/vhost_crypto.c
index 55ea24710e..05f3c85884 100644
--- a/lib/vhost/vhost_crypto.c
+++ b/lib/vhost/vhost_crypto.c
@@ -237,7 +237,7 @@ struct vhost_crypto_data_req {
static int
transform_cipher_param(struct rte_crypto_sym_xform *xform,
- VhostUserCryptoSessionParam *param)
+ VhostUserCryptoSymSessionParam *param)
{
int ret;
@@ -273,7 +273,7 @@ transform_cipher_param(struct rte_crypto_sym_xform *xform,
static int
transform_chain_param(struct rte_crypto_sym_xform *xforms,
- VhostUserCryptoSessionParam *param)
+ VhostUserCryptoSymSessionParam *param)
{
struct rte_crypto_sym_xform *xform_cipher, *xform_auth;
int ret;
@@ -341,10 +341,10 @@ vhost_crypto_create_sess(struct vhost_crypto *vcrypto,
struct rte_cryptodev_sym_session *session;
int ret;
- switch (sess_param->op_type) {
+ switch (sess_param->u.sym_sess.op_type) {
case VIRTIO_CRYPTO_SYM_OP_NONE:
case VIRTIO_CRYPTO_SYM_OP_CIPHER:
- ret = transform_cipher_param(&xform1, sess_param);
+ ret = transform_cipher_param(&xform1, &sess_param->u.sym_sess);
if (unlikely(ret)) {
VC_LOG_ERR("Error transform session msg (%i)", ret);
sess_param->session_id = ret;
@@ -352,7 +352,7 @@ vhost_crypto_create_sess(struct vhost_crypto *vcrypto,
}
break;
case VIRTIO_CRYPTO_SYM_OP_ALGORITHM_CHAINING:
- if (unlikely(sess_param->hash_mode !=
+ if (unlikely(sess_param->u.sym_sess.hash_mode !=
VIRTIO_CRYPTO_SYM_HASH_MODE_AUTH)) {
sess_param->session_id = -VIRTIO_CRYPTO_NOTSUPP;
VC_LOG_ERR("Error transform session message (%i)",
@@ -362,7 +362,7 @@ vhost_crypto_create_sess(struct vhost_crypto *vcrypto,
xform1.next = &xform2;
- ret = transform_chain_param(&xform1, sess_param);
+ ret = transform_chain_param(&xform1, &sess_param->u.sym_sess);
if (unlikely(ret)) {
VC_LOG_ERR("Error transform session message (%i)", ret);
sess_param->session_id = ret;
diff --git a/lib/vhost/vhost_user.h b/lib/vhost/vhost_user.h
index 9a905ee5f4..ef486545ba 100644
--- a/lib/vhost/vhost_user.h
+++ b/lib/vhost/vhost_user.h
@@ -99,11 +99,10 @@ typedef struct VhostUserLog {
/* Comply with Cryptodev-Linux */
#define VHOST_USER_CRYPTO_MAX_HMAC_KEY_LENGTH 512
#define VHOST_USER_CRYPTO_MAX_CIPHER_KEY_LENGTH64
+#define VHOST_USER_CRYPTO_MAX_KEY_LENGTH 1024
/* Same structure as vhost-user backend session info */
-typedef struct VhostUserCryptoSessionParam {
- int64_t session_id;
- uint32_t op_code;
+typedef struct VhostUserCryptoSymSessionParam {
uint32_t cipher_algo;
uint32_t cipher_key_len;
uint32_t hash_algo;
@@ -114,10 +113,36 @@ typedef struct VhostUserCryptoSessionParam {
uint8_t dir;
uint8_t hash_mode;
uint8_t chaining_dir;
- uint8_t *ciphe_key;
+ uint8_t *cipher_key;
uint8_t *auth_key;
uint8_t cipher_key_buf[VHOST_USER_CRYPTO_MAX_CIPHER_KEY_LENGTH];
uint8_t auth_key_buf[VHOST_USER_CRYPTO_MAX_HMAC_KEY_LENGTH];
+} VhostUserCryptoSymSessionParam;
+
+
+typedef struct VhostUserCryptoAsymRsaParam {
+ uint32_t padding_algo;
+ uint32_t hash_algo;
+} VhostUserCryptoAsymRsaParam;
+
+typedef struct VhostUserCryptoAsymSessionParam {
+ uint32_t algo;
+ uint32_t key_type;
+ uint32_t key_len;
+ uint8_t *key;
+ union {
+ VhostUserCryptoAsymRsaParam rsa;
+ } u;
+ uint8_t key_buf[VHOST_USER_CRYPTO_MAX_KEY_LENGTH];
+} VhostUserCryptoAsymSessionParam;
+
+typedef struct VhostUserCryptoSessionParam {
+ uint32_t op_code;
+ union {
+ VhostUserCryptoSymSessionParam sym_sess;
+ VhostUserCryptoAsymSessionParam asym_sess;
+ } u;
+ int64_t session_id;
} VhostUserCryptoSessionParam;
typedef struct VhostUserVringArea {
--
2.25.1
[v5 3/5] examples/vhost_crypto: fix user callbacks
In order to handle new vhost user connection, use new_connection
and destroy_connection callbacks.
Fixes: f5188211c721 ("examples/vhost_crypto: add sample application")
Cc: sta...@dpdk.org
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Akhil Goyal
---
examples/vhost_crypto/main.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/examples/vhost_crypto/main.c b/examples/vhost_crypto/main.c
index 558c09a60f..b1fe4120b9 100644
--- a/examples/vhost_crypto/main.c
+++ b/examples/vhost_crypto/main.c
@@ -362,8 +362,8 @@ destroy_device(int vid)
}
static const struct rte_vhost_device_ops virtio_crypto_device_ops = {
- .new_device = new_device,
- .destroy_device = destroy_device,
+ .new_connection = new_device,
+ .destroy_connection = destroy_device,
};
static int
--
2.25.1
[v5 4/5] vhost: support asymmetric RSA crypto ops
Support asymmetric RSA crypto operations in vhost-user.
Signed-off-by: Gowrishankar Muthukrishnan
Acked-by: Akhil Goyal
---
v5:
- release notes
---
doc/guides/rel_notes/release_25_03.rst | 3 +
lib/vhost/vhost_crypto.c | 486 +++--
lib/vhost/virtio_crypto.h | 67
3 files changed, 521 insertions(+), 35 deletions(-)
diff --git a/doc/guides/rel_notes/release_25_03.rst
b/doc/guides/rel_notes/release_25_03.rst
index 8867a4bd74..087a407337 100644
--- a/doc/guides/rel_notes/release_25_03.rst
+++ b/doc/guides/rel_notes/release_25_03.rst
@@ -151,6 +151,9 @@ New Features
See the :doc:`../compressdevs/zsda` guide for more details on the new driver.
+* **Updated vhost library.**
+
+ Updated vhost library to support RSA crypto operations.
Removed Items
-
diff --git a/lib/vhost/vhost_crypto.c b/lib/vhost/vhost_crypto.c
index 05f3c85884..ba577605c2 100644
--- a/lib/vhost/vhost_crypto.c
+++ b/lib/vhost/vhost_crypto.c
@@ -54,6 +54,14 @@ RTE_LOG_REGISTER_SUFFIX(vhost_crypto_logtype, crypto, INFO);
*/
#define vhost_crypto_desc vring_desc
+struct vhost_crypto_session {
+ union {
+ struct rte_cryptodev_asym_session *asym;
+ struct rte_cryptodev_sym_session *sym;
+ };
+ enum rte_crypto_op_type type;
+};
+
static int
cipher_algo_transform(uint32_t virtio_cipher_algo,
enum rte_crypto_cipher_algorithm *algo)
@@ -206,8 +214,10 @@ struct __rte_cache_aligned vhost_crypto {
uint64_t last_session_id;
- uint64_t cache_session_id;
- struct rte_cryptodev_sym_session *cache_session;
+ uint64_t cache_sym_session_id;
+ struct rte_cryptodev_sym_session *cache_sym_session;
+ uint64_t cache_asym_session_id;
+ struct rte_cryptodev_asym_session *cache_asym_session;
/** socket id for the device */
int socket_id;
@@ -334,10 +344,11 @@ transform_chain_param(struct rte_crypto_sym_xform *xforms,
}
static void
-vhost_crypto_create_sess(struct vhost_crypto *vcrypto,
+vhost_crypto_create_sym_sess(struct vhost_crypto *vcrypto,
VhostUserCryptoSessionParam *sess_param)
{
struct rte_crypto_sym_xform xform1 = {0}, xform2 = {0};
+ struct vhost_crypto_session *vhost_session;
struct rte_cryptodev_sym_session *session;
int ret;
@@ -384,42 +395,277 @@ vhost_crypto_create_sess(struct vhost_crypto *vcrypto,
return;
}
- /* insert hash to map */
- if (rte_hash_add_key_data(vcrypto->session_map,
- &vcrypto->last_session_id, session) < 0) {
+ vhost_session = rte_zmalloc(NULL, sizeof(*vhost_session), 0);
+ if (vhost_session == NULL) {
+ VC_LOG_ERR("Failed to alloc session memory");
+ goto error_exit;
+ }
+
+ vhost_session->type = RTE_CRYPTO_OP_TYPE_SYMMETRIC;
+ vhost_session->sym = session;
+
+ /* insert session to map */
+ if ((rte_hash_add_key_data(vcrypto->session_map,
+ &vcrypto->last_session_id, vhost_session) < 0)) {
VC_LOG_ERR("Failed to insert session to hash table");
+ goto error_exit;
+ }
+
+ VC_LOG_INFO("Session %"PRIu64" created for vdev %i.",
+ vcrypto->last_session_id, vcrypto->dev->vid);
+
+ sess_param->session_id = vcrypto->last_session_id;
+ vcrypto->last_session_id++;
+ return;
+
+error_exit:
+ if (rte_cryptodev_sym_session_free(vcrypto->cid, session) < 0)
+ VC_LOG_ERR("Failed to free session");
+
+ sess_param->session_id = -VIRTIO_CRYPTO_ERR;
+ rte_free(vhost_session);
+}
+
+static int
+tlv_decode(uint8_t *tlv, uint8_t type, uint8_t **data, size_t *data_len)
+{
+ size_t tlen = -EINVAL, len;
+
+ if (tlv[0] != type)
+ return -EINVAL;
- if (rte_cryptodev_sym_session_free(vcrypto->cid, session) < 0)
- VC_LOG_ERR("Failed to free session");
+ if (tlv[1] == 0x82) {
+ len = (tlv[2] << 8) | tlv[3];
+ *data = &tlv[4];
+ tlen = len + 4;
+ } else if (tlv[1] == 0x81) {
+ len = tlv[2];
+ *data = &tlv[3];
+ tlen = len + 3;
+ } else {
+ len = tlv[1];
+ *data = &tlv[2];
+ tlen = len + 2;
+ }
+
+ *data_len = len;
+ return tlen;
+}
+
+static int
+virtio_crypto_asym_rsa_der_to_xform(uint8_t *der, size_t der_len,
+ struct rte_crypto_asym_xform *xform)
+{
+ uint8_t *n = NULL, *e = NULL, *d = NULL, *p = NULL, *q = NULL, *dp =
NULL,
+ *dq = NULL, *qinv = NULL, *v = NULL, *tlv;
+ size_t nlen, elen, dlen, plen, qlen, dplen, dqlen, qinvlen, vlen;
+ int len;
+
+ RTE_SET_USED(der_len);
+
+ if (der[0] != 0x30)
+ return -EINVAL;
+
+ if (der[1] == 0x82)
+
