Re: Bihash Support in DPDK

[rajesh goel]

Thanks Stephen , Vladimir,
Let me explore DPDK RCU more, if it helps my application.

Will get back with my results.

Regards.
Rajesh

On Wed, Aug 28, 2024 at 10:53 PM Stephen Hemminger <
step...@networkplumber.org> wrote:

> On Wed, 28 Aug 2024 15:54:27 +
> "Medvedkin, Vladimir"  wrote:
>
> > Thanks for the reply.
> >
> > Bihash I mean bounded index what Vpp supports.
> >
> > Iam looking for the bucket level lock support. Currently Iam using hash
> table shared by multiple process or multiple core/threads. So I have to
> take the write lock by single core and then read lock by multiple cores to
> read the value wrote in this hash table. Multiple readers are getting
> blocked due to this. I want to avoid this to increase performance.
> >
> > Let me know your thoughts on this.
> >
> > Regards
> > Rajesh
>
> RCU is always faster than reader/writer locks.
> Reader/Writer locks are slower than simple spin lock unless reader holds
> for a long time.
>

Re: memif insufficient padding

[Mattias Rönnblom]

On 2024-08-28 23:04, Morten Brørup wrote:

Jakub,

While browsing virtual interfaces in DPDK, I noticed a possible performance 
issue in the memif driver:

If "head" and "tail" are accessed by different lcores, they are not sufficiently far away from each other (and other 
hot fields) to prevent false sharing-like effects on systems with a next-N-lines hardware prefetcher, which will prefetch "tail" 
when fetching "head", and prefetch "head" when fetching "flags".

I suggest updating the structure somewhat like this:

-#define MEMIF_CACHELINE_ALIGN_MARK(mark) \
-   alignas(RTE_CACHE_LINE_SIZE) RTE_MARKER mark;
-
-typedef struct {
-   MEMIF_CACHELINE_ALIGN_MARK(cacheline0);
+typedef struct __rte_cache_aligned {
uint32_t cookie;/**< MEMIF_COOKIE */
uint16_t flags; /**< flags */
#define MEMIF_RING_FLAG_MASK_INT 1  /**< disable interrupt mode */
+   RTE_CACHE_GUARD; /* isolate head from flags */


Wouldn't it be better to cache align the 'head' (or cache-aligned 'head' 
*and* add a RTE_CACHE_GUARD)? In other words, isn't the purpose of 
RTE_CACHE_GUARD to provide zero or more cache line of extra padding, 
rather than a mechanism to avoid same-cache line false sharing?



RTE_ATOMIC(uint16_t) head;  /**< pointer to ring 
buffer head */
-   MEMIF_CACHELINE_ALIGN_MARK(cacheline1);
+   RTE_CACHE_GUARD; /* isolate tail from head */
RTE_ATOMIC(uint16_t) tail;  /**< pointer to ring 
buffer tail */
-   MEMIF_CACHELINE_ALIGN_MARK(cacheline2);
+   RTE_CACHE_GUARD; /* isolate descriptors from tail */
-   memif_desc_t desc[0];   /**< buffer descriptors */
+   memif_desc_t desc[];/**< buffer descriptors */
} memif_ring_t;


Med venlig hilsen / Kind regards,
-Morten Brørup

Re: [PATCH v1 1/3] bbdev: new k0 parameter for LDPC decoder operation

[Maxime Coquelin]

Hi,

On 7/1/24 23:27, Nicolas Chautru wrote:

In latest 3GPP 38.212, the k0 value is not necessaraly directly


necessarily*


derived from rv_index, in that case a value can be provided in
API. When this value is non null this would override the value
which would be computed purely from rv_index.

Signed-off-by: Nicolas Chautru 
---
  doc/guides/prog_guide/bbdev.rst | 2 ++
  lib/bbdev/rte_bbdev_op.h| 4 
  2 files changed, 6 insertions(+)

diff --git a/doc/guides/prog_guide/bbdev.rst b/doc/guides/prog_guide/bbdev.rst
index 09e5f0d990..e3f356450b 100644
--- a/doc/guides/prog_guide/bbdev.rst
+++ b/doc/guides/prog_guide/bbdev.rst
@@ -1021,6 +1021,8 @@ The LDPC decode parameters are set out in the table below.
  
+++---+
  ||eb  |Eb, length of the RM output sequence in bits  r 
>= cab |
  
+++---+
+||k0  |Optional k0 Rate matching starting position 
override   |
++++---+
  
  The mbuf input ``input`` encoded CB data is mandatory for all BBDEV PMDs

  and is the Virtual Circular Buffer data stream with null padding.
diff --git a/lib/bbdev/rte_bbdev_op.h b/lib/bbdev/rte_bbdev_op.h
index 459631d0d0..b5dde116ab 100644
--- a/lib/bbdev/rte_bbdev_op.h
+++ b/lib/bbdev/rte_bbdev_op.h
@@ -562,6 +562,10 @@ struct rte_bbdev_op_ldpc_dec {
/** Struct which stores Transport Block specific parameters */
struct rte_bbdev_op_dec_ldpc_tb_params tb_params;
};
+   /** Optional k0 Rate matching starting position, overrides rv_index 
when non null
+*  [3GPP TS38.212, section 5.4.2.1]
+*/
+   uint16_t k0;
  };
  /* >8 End of structure rte_bbdev_op_ldpc_dec. */
  


Will fix the typo while applying.

Reviewed-by: Maxime Coquelin 

Also reporting Hemant's Ack on the cover letter as patchwork doesn't
report them:
Acked-by: Hemant Agrawal 

Thanks,
Maxime

Re: [PATCH v1 2/3] test/bbdev: add support for k0 parameter

[Maxime Coquelin]

On 7/1/24 23:27, Nicolas Chautru wrote:

New k0 added in LDPC decoder structure can be parsed
by the bbdev test application.

Signed-off-by: Nicolas Chautru 
---
  app/test-bbdev/test_bbdev_perf.c   | 7 +--
  app/test-bbdev/test_bbdev_vector.c | 4 
  app/test-bbdev/test_bbdev_vector.h | 1 +
  3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 3a94f15a30..67c55605fd 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -1923,6 +1923,7 @@ copy_reference_ldpc_dec_op(struct rte_bbdev_dec_op **ops, 
unsigned int n,
ops[i]->ldpc_dec.n_cb = ldpc_dec->n_cb;
ops[i]->ldpc_dec.iter_max = ldpc_dec->iter_max;
ops[i]->ldpc_dec.rv_index = ldpc_dec->rv_index;
+   ops[i]->ldpc_dec.k0 = ldpc_dec->k0;
ops[i]->ldpc_dec.op_flags = ldpc_dec->op_flags;
ops[i]->ldpc_dec.code_block_mode = ldpc_dec->code_block_mode;
  
@@ -2171,8 +2172,10 @@ validate_op_chain(struct rte_bbdev_op_data *op,

   * As per definition in 3GPP 38.212 Table 5.4.2.1-2
   */
  static inline uint16_t
-get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index)
+get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index, uint16_t k0)
  {
+   if (k0 > 0)
+   return k0;
if (rv_index == 0)
return 0;
uint16_t n = (bg == 1 ? N_ZC_1 : N_ZC_2) * z_c;
@@ -2202,7 +2205,7 @@ compute_harq_len(struct rte_bbdev_op_ldpc_dec *ops_ld)
  {
uint16_t k0 = 0;
uint8_t max_rv = (ops_ld->rv_index == 1) ? 3 : ops_ld->rv_index;
-   k0 = get_k0(ops_ld->n_cb, ops_ld->z_c, ops_ld->basegraph, max_rv);
+   k0 = get_k0(ops_ld->n_cb, ops_ld->z_c, ops_ld->basegraph, max_rv, 
ops_ld->k0);
/* Compute RM out size and number of rows */
uint16_t parity_offset = (ops_ld->basegraph == 1 ? 20 : 8)
* ops_ld->z_c - ops_ld->n_filler;
diff --git a/app/test-bbdev/test_bbdev_vector.c 
b/app/test-bbdev/test_bbdev_vector.c
index e48947b211..8b32850982 100644
--- a/app/test-bbdev/test_bbdev_vector.c
+++ b/app/test-bbdev/test_bbdev_vector.c
@@ -865,6 +865,10 @@ parse_ldpc_decoder_params(const char *key_token, char 
*token,
vector->mask |= TEST_BBDEV_VF_RV_INDEX;
ldpc_dec->rv_index = (uint8_t) strtoul(token, &err, 0);
ret = ((err == NULL) || (*err != '\0')) ? -1 : 0;
+   } else if (!strcmp(key_token, "k0")) {
+   vector->mask |= TEST_BBDEV_VF_K0;
+   ldpc_dec->k0 = (uint16_t) strtoul(token, &err, 0);
+   ret = ((err == NULL) || (*err != '\0')) ? -1 : 0;
} else if (!strcmp(key_token, "n_cb")) {
vector->mask |= TEST_BBDEV_VF_NCB;
ldpc_dec->n_cb = (uint16_t) strtoul(token, &err, 0);
diff --git a/app/test-bbdev/test_bbdev_vector.h 
b/app/test-bbdev/test_bbdev_vector.h
index ba1d0d20f9..9a2942132b 100644
--- a/app/test-bbdev/test_bbdev_vector.h
+++ b/app/test-bbdev/test_bbdev_vector.h
@@ -34,6 +34,7 @@ enum {
TEST_BBDEV_VF_CODE_BLOCK_MODE = (1ULL << 23),
TEST_BBDEV_VF_OP_FLAGS = (1ULL << 24),
TEST_BBDEV_VF_EXPECTED_STATUS = (1ULL << 25),
+   TEST_BBDEV_VF_K0 = (1ULL << 26),
  };
  
  enum op_data_type {



Reviewed-by: Maxime Coquelin 

Also reporting Hemant's Ack on the cover letter as patchwork doesn't
report them:
Acked-by: Hemant Agrawal 

Thanks,
Maxime

Re: [PATCH v1 3/3] baseband/acc: add support for k0 parameter

[Maxime Coquelin]

On 7/1/24 23:27, Nicolas Chautru wrote:

The k0 may be provided to the PMD, which would be used
as the circular buffer starting position instead of value
which would be computed from legacy rv_index derived
computation.

Signed-off-by: Nicolas Chautru 
---
  drivers/baseband/acc/acc_common.h | 6 --
  drivers/baseband/acc/rte_acc100_pmd.c | 2 +-
  drivers/baseband/acc/rte_vrb_pmd.c| 4 ++--
  3 files changed, 7 insertions(+), 5 deletions(-)



Reviewed-by: Maxime Coquelin 

Also reporting Hemant's Ack on the cover letter as patchwork doesn't
report them:
Acked-by: Hemant Agrawal 

Thanks,
Maxime

Re: [PATCH] bus/pci: don't open uio device in secondary process

[Chenbo Xia]

> On Aug 28, 2024, at 18:40, Konrad Sztyber  wrote:
> 
> External email: Use caution opening links or attachments
> 
> 
> The uio_pci_generic driver clears the bus master bit when the device
> file is closed.  So, when the secondary process terminates after probing

Should be one space before ‘So'

> a device, that device becomes unusable in the primary process.
> 
> To avoid that, the device file is now opened only in the primary
> process.  The commit that introduced this regression, 847d78fb95
> ("bus/pci: fix FD in secondary process"), only mentioned enabling access
> to config space from secondary process, which still works, as it doesn't
> rely on the device file.
> 
> Fixes: 847d78fb95 ("bus/pci: fix FD in secondary process")

Besides the cc stable tag mentioned by Chaoyong, commit ID should be 12-digit.

Please also fix the coding style:

WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#176: FILE: drivers/bus/pci/linux/pci_uio.c:265:
+ * closed, so open it only in the primary process */

With above fixed:

Reviewed-by: Chenbo Xia 

> 
> Signed-off-by: Konrad Sztyber 
> ---
> drivers/bus/pci/linux/pci_uio.c | 25 +
> 1 file changed, 13 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c
> index 4c1d3327a9..432316afcc 100644
> --- a/drivers/bus/pci/linux/pci_uio.c
> +++ b/drivers/bus/pci/linux/pci_uio.c
> @@ -232,18 +232,6 @@ pci_uio_alloc_resource(struct rte_pci_device *dev,
>loc->domain, loc->bus, loc->devid, loc->function);
>return 1;
>}
> -   snprintf(devname, sizeof(devname), "/dev/uio%u", uio_num);
> -
> -   /* save fd */
> -   fd = open(devname, O_RDWR);
> -   if (fd < 0) {
> -   PCI_LOG(ERR, "Cannot open %s: %s", devname, strerror(errno));
> -   goto error;
> -   }
> -
> -   if (rte_intr_fd_set(dev->intr_handle, fd))
> -   goto error;
> -
>snprintf(cfgname, sizeof(cfgname),
>"/sys/class/uio/uio%u/device/config", uio_num);
> 
> @@ -273,6 +261,19 @@ pci_uio_alloc_resource(struct rte_pci_device *dev,
>if (rte_eal_process_type() != RTE_PROC_PRIMARY)
>return 0;
> 
> +   /* the uio_pci_generic driver clears the bus master enable bit when 
> the device file is
> +* closed, so open it only in the primary process */
> +   snprintf(devname, sizeof(devname), "/dev/uio%u", uio_num);
> +   /* save fd */
> +   fd = open(devname, O_RDWR);
> +   if (fd < 0) {
> +   PCI_LOG(ERR, "Cannot open %s: %s", devname, strerror(errno));
> +   goto error;
> +   }
> +
> +   if (rte_intr_fd_set(dev->intr_handle, fd))
> +   goto error;
> +
>/* allocate the mapping details for secondary processes*/
>*uio_res = rte_zmalloc("UIO_RES", sizeof(**uio_res), 0);
>if (*uio_res == NULL) {
> --
> 2.45.0
> 

Re: [PATCH v1 1/2] bbdev: add new function to dump debug information

[Maxime Coquelin]

On 7/2/24 20:55, Chautru, Nicolas wrote:

Hi Hemant,


-Original Message-
From: Hemant Agrawal 
Sent: Tuesday, July 2, 2024 3:54 AM
To: Chautru, Nicolas ; dev@dpdk.org;
maxime.coque...@redhat.com
Cc: hemant.agra...@nxp.com; Marchand, David
; Vargas, Hernan

Subject: Re: [PATCH v1 1/2] bbdev: add new function to dump debug
information

Hi Nicolas,

      Few comments inline.

On 02-07-2024 04:04, Nicolas Chautru wrote:

This provides a new API to dump more debug information related to the
status on a given bbdev queue.
Some of this information is visible at bbdev level.
This also provides a new option dev op, to print more information at
the lower PMD level.
This helps user to troubleshoot issues related to previous operations
provided into a queue causing possible hard-to-debug negative
scenarios.

Signed-off-by: Nicolas Chautru 
---
   lib/bbdev/rte_bbdev.c | 214

++

   lib/bbdev/rte_bbdev.h |  41 
   lib/bbdev/rte_bbdev_pmd.h |   9 ++
   lib/bbdev/version.map |   4 +
   4 files changed, 268 insertions(+)

diff --git a/lib/bbdev/rte_bbdev.c b/lib/bbdev/rte_bbdev.c index
13bde3c25b..81c031fc09 100644
--- a/lib/bbdev/rte_bbdev.c
+++ b/lib/bbdev/rte_bbdev.c
@@ -1190,3 +1190,217 @@ rte_bbdev_enqueue_status_str(enum

rte_bbdev_enqueue_status status)

rte_bbdev_log(ERR, "Invalid enqueue status");
return NULL;
   }
+
+
+int
+rte_bbdev_queue_ops_dump(uint16_t dev_id, uint16_t queue_id, FILE

*f)

+{
+   struct rte_bbdev_queue_data *q_data;
+   struct rte_bbdev_stats *stats;
+   uint16_t i;
+   struct rte_bbdev *dev = get_dev(dev_id);
+
+   VALID_DEV_OR_RET_ERR(dev, dev_id);
+   VALID_QUEUE_OR_RET_ERR(queue_id, dev);
+   VALID_DEV_OPS_OR_RET_ERR(dev, dev_id);
+   VALID_FUNC_OR_RET_ERR(dev->dev_ops->queue_ops_dump,

dev_id);

+
+   q_data = &dev->data->queues[queue_id];
+
+   if (f == NULL)
+   return -EINVAL;
+
+   fprintf(f, "Dump of operations on %s queue %d\n",
+   dev->data->name, queue_id);
+   fprintf(f, "  Last Enqueue Status %s\n",
+   rte_bbdev_enqueue_status_str(q_data-
enqueue_status));
+   for (i = 0; i < 4; i++)


It shall be RTE_BBDEV_ENQ_STATUS_SIZE_MAX instead of 4 ?


Thanks, I can update this in the v2.



Hi Nicolas,

could you please send a v2 addressing Hemant's comments?

Thanks,
Maxime

Re: [PATCH v3] net/iavf: support rte flow with mask for FDIR

[David Marchand]

Hello,

On Fri, Dec 15, 2023 at 4:19 AM Zhichao Zeng  wrote:
>
> This patch supports rte flow with mask for FDIR, including
> eth/ipv4/ipv6/tcp/udp flow items, where src/dst for ipv4/ipv6
> and sport/dport for tcp/udp are realized by switch filter.
>
> Signed-off-by: Zhichao Zeng 

Is this supposed to work with an upstream kernel?
Is this patch supposed to get merged at some point in DPDK?


-- 
David Marchand

Re: [PATCH v2 1/3] app/testpmd: add register keyword

[Varghese, Vipin]

On 8/27/2024 11:09 PM, Stephen Hemminger wrote:

not sure why compiler would not decide to already use a register here?


Hi Stephen, I totally agree with your point, but in practice it did not 
use registers for code generation.

RE: 23.11.2 patches review and test

[Ali Alnubani]

> -Original Message-
> From: Xueming Li 
> Sent: Thursday, August 22, 2024 3:07 PM
> To: sta...@dpdk.org
> Cc: dev@dpdk.org; Abhishek Marathe ; Ali
> Alnubani ; David Christensen ;
> Hemant Agrawal ; Ian Stokes
> ; Jerin Jacob ; John McNamara
> ; Ju-Hyoung Lee ; Kevin
> Traynor ; Luca Boccassi ; Pei Zhang
> ; Raslan Darawsheh ; NBU-
> Contact-Thomas Monjalon (EXTERNAL) ; Yanghang Liu
> ; benjamin.wal...@intel.com; qian.q...@intel.com;
> yuan.p...@intel.com; zhaoyan.c...@intel.com
> Subject: 23.11.2 patches review and test
> 
> Hi all,
> 
> Here is a list of patches targeted for stable release 23.11.2.
> 
> The planned date for the final release is 31th August.
> 
> Please help with testing and validation of your use cases and report
> any issues/results with reply-all to this mail. For the final release
> the fixes and reported validations will be added to the release notes.
> 
> A release candidate tarball can be found at:
> 
> https://dpdk.org/browse/dpdk-stable/tag/?id=v23.11.2-rc2
> 
> These patches are located at branch 23.11 of dpdk-stable repo:
> https://dpdk.org/browse/dpdk-stable/
> 
> Thanks.
> 
> Xueming Li 
> 
> ---

Hello,

We ran the following functional tests with Nvidia hardware on v23.11.2-rc2:
- Basic functionality:
  Send and receive multiple types of traffic.
- testpmd xstats counter test.
- testpmd timestamp test.
- Changing/checking link status through testpmd.
- rte_flow tests 
(https://doc.dpdk.org/guides/nics/mlx5.html#supported-hardware-offloads)
- RSS tests.
- VLAN filtering, stripping, and insertion tests.
- Checksum and TSO tests.
- ptype tests.
- link_status_interrupt example application tests.
- l3fwd-power example application tests.
- Multi-process example applications tests.
- Hardware LRO tests.
- Buffer Split tests.
- Tx scheduling tests.

Functional tests ran on:
- NIC: ConnectX-6 Dx / OS: Ubuntu 20.04 / Driver: MLNX_OFED_LINUX-24.07-0.6.1.0 
/ Firmware: 22.42.1000
- NIC: ConnectX-7 / OS: Ubuntu 20.04 / Driver: MLNX_OFED_LINUX-24.07-0.6.1.0 / 
Firmware: 28.42.1000
- DPU: BlueField-2 / DOCA SW version: 2.8 / Firmware: 24.42.1000


Additionally, we ran build tests with multiple configurations on the following 
OS/driver combinations (all passed):
- Debian 12 with MLNX_OFED_LINUX-24.04-0.7.0.0.
- Ubuntu 20.04.6 with MLNX_OFED_LINUX-24.07-0.6.1.0.
- Ubuntu 20.04.6 with rdma-core master (dd9c687).
- Ubuntu 20.04.6 with rdma-core v28.0.
- Fedora 40 with rdma-core v48.0.
- Fedora 42 (Rawhide) with rdma-core v51.0.
- OpenSUSE Leap 15.6 with rdma-core v49.1.

We don't see new issues caused by the changes in this release.

Thanks,
Ali

RE: memif insufficient padding

[Morten Brørup]

> From: Mattias Rönnblom [mailto:hof...@lysator.liu.se]
> 
> On 2024-08-28 23:04, Morten Brørup wrote:
> > Jakub,
> >
> > While browsing virtual interfaces in DPDK, I noticed a possible performance
> issue in the memif driver:
> >
> > If "head" and "tail" are accessed by different lcores, they are not
> sufficiently far away from each other (and other hot fields) to prevent false
> sharing-like effects on systems with a next-N-lines hardware prefetcher, which
> will prefetch "tail" when fetching "head", and prefetch "head" when fetching
> "flags".
> >
> > I suggest updating the structure somewhat like this:
> >
> > -#define MEMIF_CACHELINE_ALIGN_MARK(mark) \
> > -   alignas(RTE_CACHE_LINE_SIZE) RTE_MARKER mark;
> > -
> > -typedef struct {
> > -   MEMIF_CACHELINE_ALIGN_MARK(cacheline0);
> > +typedef struct __rte_cache_aligned {
> > uint32_t cookie;/**< MEMIF_COOKIE */
> > uint16_t flags; /**< flags */
> > #define MEMIF_RING_FLAG_MASK_INT 1  /**< disable interrupt mode */
> > +   RTE_CACHE_GUARD; /* isolate head from flags */
> 
> Wouldn't it be better to cache align the 'head' (or cache-aligned 'head'
> *and* add a RTE_CACHE_GUARD)? In other words, isn't the purpose of
> RTE_CACHE_GUARD to provide zero or more cache line of extra padding,
> rather than a mechanism to avoid same-cache line false sharing?

IMO the general purpose of RTE_CACHE_GUARD is to prevent false cache line 
sharing; both sharing of the same cache line (on systems with or without 
speculative prefetching) and sharing of the next cache lines (on systems with 
speculative prefetching).

RTE_CACHE_GUARD provides two things:
1. Zero or more bytes of padding up to cache alignment, which prevents 
same-cache line sharing. This effectively cache aligns the field that follows 
the RTE_CACHE_GUARD, here the "head".
2. Zero or more cache lines of extra padding (configured by 
RTE_CACHE_GUARD_LINES in rte_config.h), which prevents sharing of the next 
cache lines on systems with speculative prefetching.

My description failed to mention the reason for the RTE_CACHE_GUARD between 
"flags" and "head":

The lcore updating "tail" also reads "flags", and if reading "flags" causes 
that lcore to prefetch the next cache line, it will thereby read the cache line 
holding "head", causing false cache line sharing with the other lcore updating 
"head".

> 
> > RTE_ATOMIC(uint16_t) head;  /**< pointer to ring 
> > buffer head
> */
> > -   MEMIF_CACHELINE_ALIGN_MARK(cacheline1);
> > +   RTE_CACHE_GUARD; /* isolate tail from head */
> > RTE_ATOMIC(uint16_t) tail;  /**< pointer to ring 
> > buffer tail
> */
> > -   MEMIF_CACHELINE_ALIGN_MARK(cacheline2);
> > +   RTE_CACHE_GUARD; /* isolate descriptors from tail */
> > -   memif_desc_t desc[0];   /**< buffer descriptors */
> > +   memif_desc_t desc[];/**< buffer descriptors */
> > } memif_ring_t;
> >
> >
> > Med venlig hilsen / Kind regards,
> > -Morten Brørup
> >

[PATCH v2] bus/pci: don't open uio device in secondary process

[Konrad Sztyber]

The uio_pci_generic driver clears the bus master bit when the device
file is closed. So, when the secondary process terminates after probing
a device, that device becomes unusable in the primary process.

To avoid that, the device file is now opened only in the primary
process. The commit that introduced this regression, 847d78fb9530
("bus/pci: fix FD in secondary process"), only mentioned enabling access
to config space from secondary process, which still works, as it doesn't
rely on the device file.

Fixes: 847d78fb9530 ("bus/pci: fix FD in secondary process")
Cc: sta...@dpdk.org

Signed-off-by: Konrad Sztyber 
---
 drivers/bus/pci/linux/pci_uio.c | 27 +++
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c
index 4c1d3327a9..5c4ba8098c 100644
--- a/drivers/bus/pci/linux/pci_uio.c
+++ b/drivers/bus/pci/linux/pci_uio.c
@@ -232,18 +232,6 @@ pci_uio_alloc_resource(struct rte_pci_device *dev,
loc->domain, loc->bus, loc->devid, loc->function);
return 1;
}
-   snprintf(devname, sizeof(devname), "/dev/uio%u", uio_num);
-
-   /* save fd */
-   fd = open(devname, O_RDWR);
-   if (fd < 0) {
-   PCI_LOG(ERR, "Cannot open %s: %s", devname, strerror(errno));
-   goto error;
-   }
-
-   if (rte_intr_fd_set(dev->intr_handle, fd))
-   goto error;
-
snprintf(cfgname, sizeof(cfgname),
"/sys/class/uio/uio%u/device/config", uio_num);
 
@@ -273,6 +261,21 @@ pci_uio_alloc_resource(struct rte_pci_device *dev,
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
 
+   /*
+* the uio_pci_generic driver clears the bus master enable bit when the 
device file is
+* closed, so open it only in the primary process
+*/
+   snprintf(devname, sizeof(devname), "/dev/uio%u", uio_num);
+   /* save fd */
+   fd = open(devname, O_RDWR);
+   if (fd < 0) {
+   PCI_LOG(ERR, "Cannot open %s: %s", devname, strerror(errno));
+   goto error;
+   }
+
+   if (rte_intr_fd_set(dev->intr_handle, fd))
+   goto error;
+
/* allocate the mapping details for secondary processes*/
*uio_res = rte_zmalloc("UIO_RES", sizeof(**uio_res), 0);
if (*uio_res == NULL) {
-- 
2.45.0

Re: [PATCH v2] net/mlx5: add metadata split for compatibility API

[Raslan Darawsheh]

hi,

From: Bing Zhao 
Sent: Thursday, July 4, 2024 1:26 PM
To: Slava Ovsiienko; dev@dpdk.org; Raslan Darawsheh
Cc: Ori Kam; Dariusz Sosnowski; Suanming Mou; Matan Azrad
Subject: [PATCH v2] net/mlx5: add metadata split for compatibility API

The method will not create any new flow rule implicitly during split
stage, but only generate needed items, actions and attributes based
on the detection.

All the rules will still be created in the flow_hw_list_create().

In the meanwhile, once the mark action is specified in the FDB rule,
a new rule in the NIC Rx will be created to:
  1. match the mark value on REG_C_x in FDB and set it into Rx
 flow tag field.
  2. copy the metadata in REG_C_x' into the REG_B.

If there is no mark, the default rule with only copying metadata
will be hit if there is Queue or RSS action in the NIC Rx rule.

Regarding the NIC Tx, only the metadata is relevant and it will be
copied in NIC Tx from REG_A into some REG_C_x. The current HWS
implementation already has already supported in the default copy
rule or the default SQ miss rule in the NIC Tx root table.

Signed-off-by: Bing Zhao 
Acked-by: Dariusz Sosnowski 

Patch applied to next-net-mlx,

Kindest regards
Raslan Darawsheh

Re: [PATCH 0/4] non-template fixes set

[Raslan Darawsheh]

Hi,

From: Bing Zhao 
Sent: Tuesday, July 23, 2024 11:15 AM
To: Dariusz Sosnowski; Slava Ovsiienko; dev@dpdk.org; Raslan Darawsheh
Cc: Ori Kam; Suanming Mou; Matan Azrad
Subject: [PATCH 0/4] non-template fixes set

A set for cumulative fixes of non-template API support.

Bing Zhao (4):
  net/mlx5/hws: fix state detection of queue full in polling
  net/mlx5: fix releasing order of compatible matcher
  net/mlx5: fix matcher mask translation
  net/mlx5: fix log error on non-template rule destroy

 drivers/net/mlx5/hws/mlx5dr_bwc.c |  4 +++-
 drivers/net/mlx5/hws/mlx5dr_bwc.h |  1 -
 drivers/net/mlx5/mlx5_flow_dv.c   |  1 +
 drivers/net/mlx5/mlx5_flow_hw.c   | 37 +++
 4 files changed, 17 insertions(+), 26 deletions(-)

Series applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

Re: [PATCH v2] net/mlx5: workaround list management of Rx queue control

[Raslan Darawsheh]

Hi,

From: Bing Zhao 
Sent: Tuesday, July 23, 2024 2:14 PM
To: Dariusz Sosnowski; Slava Ovsiienko; dev@dpdk.org; Raslan Darawsheh
Cc: Ori Kam; Suanming Mou; Matan Azrad
Subject: [PATCH v2] net/mlx5: workaround list management of Rx queue control

The LIST_REMOVE macro only removes the entry from the list and
updates list itself. The pointers of this entry are not reset to
NULL to prevent the accessing for the 2nd time.

In the previous fix for the memory accessing, the "rxq_ctrl" was
removed from the list in a device private data when the "refcnt" was
decreased to 0. Under only shared or non-shared queues scenarios,
this was safe since all the "rxq_ctrl" entries were freed or kept.

There is one case that shared and non-shared Rx queues are configured
simultaneously, for example, a hairpin Rx queue cannot be shared.
When closing the port that allocated the shared Rx queues'
"rxq_ctrl", if the next entry is hairpin "rxq_ctrl", the hairpin
"rxq_ctrl" will be freed directly with other resources. When trying
to close the another port sharing the "rxq_ctrl", the LIST_REMOVE
will be called again and cause some UFA issue. If the memory is no
longer mapped, there will be a SIGSEGV.

Adding a flag in the Rx queue private structure to remove the
"rxq_ctrl" from the list only on the port/queue that allocated it.

Fixes: bcc220cb57d7 ("net/mlx5: fix shared Rx queue list management")

Signed-off-by: Bing Zhao 
Acked-by: Viacheslav Ovsiienko 
---
v2: fix CI code style warning
---

Patch applied to next-net-mlx,


Kindest regards,
Raslan Darawsheh

[PATCH v1 01/15] net/ixgbe/base: remove minsrevs code from DPDK

[Anatoly Burakov]

Commit add44414762c ("net/ixgbe/base: add E610 NVM-related operations") has
added code to read minimum security revision from NVM. This code was not
meant to be included in DPDK, and was only meant for other drivers derived
from shared base code, but was present due to the way shared driver code
snapshot was generated. Remove this code from DPDK driver.

Fixes: add44414762c ("net/ixgbe/base: add E610 NVM-related operations")

Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_e610.c | 54 -
 drivers/net/ixgbe/base/ixgbe_e610.h |  1 -
 2 files changed, 55 deletions(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c 
b/drivers/net/ixgbe/base/ixgbe_e610.c
index ac71980630..3e2be07731 100644
--- a/drivers/net/ixgbe/base/ixgbe_e610.c
+++ b/drivers/net/ixgbe/base/ixgbe_e610.c
@@ -2488,60 +2488,6 @@ static s32 ixgbe_read_nvm_sr_copy(struct ixgbe_hw *hw,
return ixgbe_read_nvm_module(hw, bank, hdr_len + offset, data);
 }
 
-/**
- * ixgbe_get_nvm_minsrevs - Get the minsrevs values from flash
- * @hw: pointer to the HW struct
- * @minsrevs: structure to store NVM and OROM minsrev values
- *
- * Read the Minimum Security Revision TLV and extract
- * the revision values from the flash image
- * into a readable structure for processing.
- *
- * Return: the exit code of the operation.
- */
-s32 ixgbe_get_nvm_minsrevs(struct ixgbe_hw *hw,
-  struct ixgbe_minsrev_info *minsrevs)
-{
-   struct ixgbe_aci_cmd_nvm_minsrev data;
-   s32 status;
-   u16 valid;
-
-   status = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
-   if (status)
-   return status;
-
-   status = ixgbe_aci_read_nvm(hw, IXGBE_ACI_NVM_MINSREV_MOD_ID,
-   0, sizeof(data), &data,
-   true, false);
-
-   ixgbe_release_nvm(hw);
-
-   if (status)
-   return status;
-
-   valid = IXGBE_LE16_TO_CPU(data.validity);
-
-   /* Extract NVM minimum security revision */
-   if (valid & IXGBE_ACI_NVM_MINSREV_NVM_VALID) {
-   u16 minsrev_l = IXGBE_LE16_TO_CPU(data.nvm_minsrev_l);
-   u16 minsrev_h = IXGBE_LE16_TO_CPU(data.nvm_minsrev_h);
-
-   minsrevs->nvm = minsrev_h << 16 | minsrev_l;
-   minsrevs->nvm_valid = true;
-   }
-
-   /* Extract the OROM minimum security revision */
-   if (valid & IXGBE_ACI_NVM_MINSREV_OROM_VALID) {
-   u16 minsrev_l = IXGBE_LE16_TO_CPU(data.orom_minsrev_l);
-   u16 minsrev_h = IXGBE_LE16_TO_CPU(data.orom_minsrev_h);
-
-   minsrevs->orom = minsrev_h << 16 | minsrev_l;
-   minsrevs->orom_valid = true;
-   }
-
-   return IXGBE_SUCCESS;
-}
-
 /**
  * ixgbe_get_nvm_srev - Read the security revision from the NVM CSS header
  * @hw: pointer to the HW struct
diff --git a/drivers/net/ixgbe/base/ixgbe_e610.h 
b/drivers/net/ixgbe/base/ixgbe_e610.h
index 33c683d1c1..4babee821e 100644
--- a/drivers/net/ixgbe/base/ixgbe_e610.h
+++ b/drivers/net/ixgbe/base/ixgbe_e610.h
@@ -85,7 +85,6 @@ s32 ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 
module_typeid, u32 offset,
 s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw);
 s32 ixgbe_nvm_recalculate_checksum(struct ixgbe_hw *hw);
 
-s32 ixgbe_get_nvm_minsrevs(struct ixgbe_hw *hw, struct ixgbe_minsrev_info 
*minsrevs);
 s32 ixgbe_get_inactive_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info 
*nvm);
 s32 ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);
 s32 ixgbe_init_nvm(struct ixgbe_hw *hw);
-- 
2.43.5

[PATCH v1 02/15] net/ixgbe/base: add missing ACI definitions

[Anatoly Burakov]

When adding Admin Command Interface and E610 device support, some ACI
capabilities definition code was missed due to the way shared driver code
snapshot was generated. Add missing code paths.

Fixes: 25b48e569f2f ("net/ixgbe/base: add E610 Admin Command Interface")
Fixes: 7c3bfffda43d ("net/ixgbe/base: detect E610 device capabilities")

Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_e610.c  | 49 
 drivers/net/ixgbe/base/ixgbe_type_e610.h |  4 ++
 2 files changed, 53 insertions(+)

diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c 
b/drivers/net/ixgbe/base/ixgbe_e610.c
index 3e2be07731..1f3a4532da 100644
--- a/drivers/net/ixgbe/base/ixgbe_e610.c
+++ b/drivers/net/ixgbe/base/ixgbe_e610.c
@@ -671,6 +671,9 @@ ixgbe_parse_common_caps(struct ixgbe_hw *hw, struct 
ixgbe_hw_common_caps *caps,
case IXGBE_ACI_CAPS_VALID_FUNCTIONS:
caps->valid_functions = number;
break;
+   case IXGBE_ACI_CAPS_SRIOV:
+   caps->sr_iov_1_1 = (number == 1);
+   break;
case IXGBE_ACI_CAPS_VMDQ:
caps->vmdq = (number == 1);
break;
@@ -833,6 +836,25 @@ ixgbe_parse_valid_functions_cap(struct ixgbe_hw *hw,
hw->logical_pf_id = ixgbe_func_id_to_logical_id(number, hw->pf_id);
 }
 
+/**
+ * ixgbe_parse_vf_dev_caps - Parse IXGBE_ACI_CAPS_VF device caps
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse IXGBE_ACI_CAPS_VF for device capabilities.
+ */
+static void ixgbe_parse_vf_dev_caps(struct ixgbe_hw *hw,
+   struct ixgbe_hw_dev_caps *dev_p,
+   struct ixgbe_aci_cmd_list_caps_elem *cap)
+{
+   u32 number = IXGBE_LE32_TO_CPU(cap->number);
+
+   UNREFERENCED_1PARAMETER(hw);
+
+   dev_p->num_vfs_exposed = number;
+}
+
 /**
  * ixgbe_parse_vsi_dev_caps - Parse IXGBE_ACI_CAPS_VSI device caps
  * @hw: pointer to the HW struct
@@ -944,6 +966,9 @@ static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw,
ixgbe_parse_valid_functions_cap(hw, dev_p,
&cap_resp[i]);
break;
+   case IXGBE_ACI_CAPS_VF:
+   ixgbe_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]);
+   break;
case IXGBE_ACI_CAPS_VSI:
ixgbe_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
break;
@@ -962,6 +987,27 @@ static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw,
 
 }
 
+/**
+ * ixgbe_parse_vf_func_caps - Parse IXGBE_ACI_CAPS_VF function caps
+ * @hw: pointer to the HW struct
+ * @func_p: pointer to function capabilities structure
+ * @cap: pointer to the capability element to parse
+ *
+ * Extract function capabilities for IXGBE_ACI_CAPS_VF.
+ */
+static void ixgbe_parse_vf_func_caps(struct ixgbe_hw *hw,
+struct ixgbe_hw_func_caps *func_p,
+struct ixgbe_aci_cmd_list_caps_elem *cap)
+{
+   u32 logical_id = IXGBE_LE32_TO_CPU(cap->logical_id);
+   u32 number = IXGBE_LE32_TO_CPU(cap->number);
+
+   UNREFERENCED_1PARAMETER(hw);
+
+   func_p->num_allocd_vfs = number;
+   func_p->vf_base_id = logical_id;
+}
+
 /**
  * ixgbe_get_num_per_func - determine number of resources per PF
  * @hw: pointer to the HW structure
@@ -1073,6 +1119,9 @@ static void ixgbe_parse_func_caps(struct ixgbe_hw *hw,
&cap_resp[i], "func caps");
 
switch (cap) {
+   case IXGBE_ACI_CAPS_VF:
+   ixgbe_parse_vf_func_caps(hw, func_p, &cap_resp[i]);
+   break;
case IXGBE_ACI_CAPS_VSI:
ixgbe_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
break;
diff --git a/drivers/net/ixgbe/base/ixgbe_type_e610.h 
b/drivers/net/ixgbe/base/ixgbe_type_e610.h
index 9e72053e2a..dcb874e42e 100644
--- a/drivers/net/ixgbe/base/ixgbe_type_e610.h
+++ b/drivers/net/ixgbe/base/ixgbe_type_e610.h
@@ -672,6 +672,8 @@ struct ixgbe_aci_cmd_list_caps_elem {
__le16 cap;
 #define IXGBE_ACI_CAPS_VALID_FUNCTIONS 0x0005
 #define IXGBE_ACI_MAX_VALID_FUNCTIONS  0x8
+#define IXGBE_ACI_CAPS_SRIOV   0x0012
+#define IXGBE_ACI_CAPS_VF  0x0013
 #define IXGBE_ACI_CAPS_VMDQ0x0014
 #define IXGBE_ACI_CAPS_VSI 0x0017
 #define IXGBE_ACI_CAPS_DCB 0x0018
@@ -1954,6 +1956,8 @@ struct ixgbe_hw_common_caps {
 #define IXGBE_MAX_SUPPORTED_GPIO_SDP   8
u8 led[IXGBE_MAX_SUPPORTED_GPIO_LED];
u8 sdp[IXGBE_MAX_SUPPORTED_GPIO_SDP];
+   /* SR-IOV virtualization */
+   u8 sr_iov_1_1;  /* SR-IOV enabled */

[PATCH v1 03/15] net/ixgbe/base: add missing E610 definitions

[Anatoly Burakov]

When adding support for E610 bringup, some definitions and code paths were
accidentally omitted due to the way the shared driver snapshot was created.
Add missing definitions and code paths.

Fixes: 316637762a5f ("net/ixgbe/base: enable E610 device")

Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_api.c   | 5 +
 drivers/net/ixgbe/base/ixgbe_type.h  | 2 ++
 drivers/net/ixgbe/base/ixgbe_type_e610.h | 3 +++
 3 files changed, 10 insertions(+)

diff --git a/drivers/net/ixgbe/base/ixgbe_api.c 
b/drivers/net/ixgbe/base/ixgbe_api.c
index c8f9a6d9f1..b4920867bc 100644
--- a/drivers/net/ixgbe/base/ixgbe_api.c
+++ b/drivers/net/ixgbe/base/ixgbe_api.c
@@ -87,6 +87,7 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
case ixgbe_mac_X550_vf:
case ixgbe_mac_X550EM_x_vf:
case ixgbe_mac_X550EM_a_vf:
+   case ixgbe_mac_E610_vf:
status = ixgbe_init_ops_vf(hw);
break;
case ixgbe_mac_E610:
@@ -219,6 +220,10 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
hw->mac.type = ixgbe_mac_E610;
hw->mvals = ixgbe_mvals_X550EM_a;
break;
+   case IXGBE_DEV_ID_E610_VF:
+   hw->mac.type = ixgbe_mac_E610_vf;
+   hw->mvals = ixgbe_mvals_X550EM_a;
+   break;
default:
ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
diff --git a/drivers/net/ixgbe/base/ixgbe_type.h 
b/drivers/net/ixgbe/base/ixgbe_type.h
index d86049426e..f6d5052c65 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -130,6 +130,7 @@
 #define IXGBE_DEV_ID_E610_10G_T0x57B0
 #define IXGBE_DEV_ID_E610_2_5G_T   0x57B1
 #define IXGBE_DEV_ID_E610_SGMII0x57B2
+#define IXGBE_DEV_ID_E610_VF   0x57AD
 
 #define IXGBE_CAT(r, m) IXGBE_##r##m
 
@@ -3676,6 +3677,7 @@ enum ixgbe_mac_type {
ixgbe_mac_X550EM_x_vf,
ixgbe_mac_X550EM_a_vf,
ixgbe_mac_E610,
+   ixgbe_mac_E610_vf,
ixgbe_num_macs
 };
 
diff --git a/drivers/net/ixgbe/base/ixgbe_type_e610.h 
b/drivers/net/ixgbe/base/ixgbe_type_e610.h
index dcb874e42e..ab57852f19 100644
--- a/drivers/net/ixgbe/base/ixgbe_type_e610.h
+++ b/drivers/net/ixgbe/base/ixgbe_type_e610.h
@@ -2080,6 +2080,8 @@ struct ixgbe_orom_civd_info {
 /* Function specific capabilities */
 struct ixgbe_hw_func_caps {
struct ixgbe_hw_common_caps common_cap;
+   u32 num_allocd_vfs; /* Number of allocated VFs */
+   u32 vf_base_id; /* Logical ID of the first VF */
u32 guar_num_vsi;
struct ixgbe_ts_func_info ts_func_info;
bool no_drop_policy_ena;
@@ -2088,6 +2090,7 @@ struct ixgbe_hw_func_caps {
 /* Device wide capabilities */
 struct ixgbe_hw_dev_caps {
struct ixgbe_hw_common_caps common_cap;
+   u32 num_vfs_exposed;/* Total number of VFs exposed */
u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
u32 num_flow_director_fltr; /* Number of FD filters available */
struct ixgbe_ts_dev_info ts_dev_info;
-- 
2.43.5

[PATCH v1 04/15] net/ixgbe/base: add missing legacy mailbox API

[Anatoly Burakov]

When the new mailbox API was introduced, the legacy mailbox API was also
provided, but was missing from the patches due to the way the patches were
generated. This patch adds the missing legacy mailbox API to the driver.

Fixes: 6d243d2caf2c ("net/ixgbe/base: introduce new mailbox API")

Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_mbx.c | 44 ++
 drivers/net/ixgbe/base/ixgbe_mbx.h |  1 +
 2 files changed, 45 insertions(+)

diff --git a/drivers/net/ixgbe/base/ixgbe_mbx.c 
b/drivers/net/ixgbe/base/ixgbe_mbx.c
index 444a0d339d..23659266d0 100644
--- a/drivers/net/ixgbe/base/ixgbe_mbx.c
+++ b/drivers/net/ixgbe/base/ixgbe_mbx.c
@@ -169,6 +169,26 @@ s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id)
return ret_val;
 }
 
+/**
+ * ixgbe_clear_mbx - Clear Mailbox Memory
+ * @hw: pointer to the HW structure
+ * @mbx_id: id of mailbox to write
+ *
+ * Set VFMBMEM of given VF to 0x0.
+ **/
+s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 mbx_id)
+{
+   struct ixgbe_mbx_info *mbx = &hw->mbx;
+   s32 ret_val = IXGBE_ERR_CONFIG;
+
+   DEBUGFUNC("ixgbe_clear_mbx");
+
+   if (mbx->ops[mbx_id].clear)
+   ret_val = mbx->ops[mbx_id].clear(hw, mbx_id);
+
+   return ret_val;
+}
+
 /**
  * ixgbe_poll_for_msg - Wait for message notification
  * @hw: pointer to the HW structure
@@ -628,6 +648,7 @@ void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw)
mbx->ops[0].check_for_msg = ixgbe_check_for_msg_vf;
mbx->ops[0].check_for_ack = ixgbe_check_for_ack_vf;
mbx->ops[0].check_for_rst = ixgbe_check_for_rst_vf;
+   mbx->ops[0].clear = NULL;
 
mbx->stats.msgs_tx = 0;
mbx->stats.msgs_rx = 0;
@@ -1024,6 +1045,27 @@ STATIC s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 
*msg, u16 size,
return IXGBE_SUCCESS;
 }
 
+/**
+ * ixgbe_clear_mbx_pf - Clear Mailbox Memory
+ * @hw: pointer to the HW structure
+ * @vf_id: the VF index
+ *
+ * Set VFMBMEM of given VF to 0x0.
+ **/
+STATIC s32 ixgbe_clear_mbx_pf(struct ixgbe_hw *hw, u16 vf_id)
+{
+   u16 mbx_size = hw->mbx.size;
+   u16 i;
+
+   if (vf_id > 63)
+   return IXGBE_ERR_PARAM;
+
+   for (i = 0; i < mbx_size; ++i)
+   IXGBE_WRITE_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_id), i, 0x0);
+
+   return IXGBE_SUCCESS;
+}
+
 /**
  * ixgbe_init_mbx_params_pf_id - set initial values for pf mailbox
  * @hw: pointer to the HW structure
@@ -1042,6 +1084,7 @@ void ixgbe_init_mbx_params_pf_id(struct ixgbe_hw *hw, u16 
vf_id)
mbx->ops[vf_id].check_for_msg = ixgbe_check_for_msg_pf;
mbx->ops[vf_id].check_for_ack = ixgbe_check_for_ack_pf;
mbx->ops[vf_id].check_for_rst = ixgbe_check_for_rst_pf;
+   mbx->ops[vf_id].clear = ixgbe_clear_mbx_pf;
 }
 
 /**
@@ -1119,6 +1162,7 @@ void ixgbe_upgrade_mbx_params_pf(struct ixgbe_hw *hw, u16 
vf_id)
mbx->ops[vf_id].check_for_msg = ixgbe_check_for_msg_pf;
mbx->ops[vf_id].check_for_ack = ixgbe_check_for_ack_pf;
mbx->ops[vf_id].check_for_rst = ixgbe_check_for_rst_pf;
+   mbx->ops[vf_id].clear = ixgbe_clear_mbx_pf;
 
mbx->stats.msgs_tx = 0;
mbx->stats.msgs_rx = 0;
diff --git a/drivers/net/ixgbe/base/ixgbe_mbx.h 
b/drivers/net/ixgbe/base/ixgbe_mbx.h
index 56ab435286..434f7c6a69 100644
--- a/drivers/net/ixgbe/base/ixgbe_mbx.h
+++ b/drivers/net/ixgbe/base/ixgbe_mbx.h
@@ -168,6 +168,7 @@ s32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 
size, u16 mbx_id);
 s32 ixgbe_check_for_msg(struct ixgbe_hw *hw, u16 mbx_id);
 s32 ixgbe_check_for_ack(struct ixgbe_hw *hw, u16 mbx_id);
 s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id);
+s32 ixgbe_clear_mbx(struct ixgbe_hw *hw, u16 vf_number);
 void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw);
 void ixgbe_upgrade_mbx_params_vf(struct ixgbe_hw *hw);
 void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw);
-- 
2.43.5

[PATCH v1 05/15] net/ixgbe/base: add E610 VF HV macro

[Anatoly Burakov]

From: Jedrzej Jagielski 

At this point there is no macro specific for E610 VF HV.
Add it to ixgbe_type.h

Signed-off-by: Jedrzej Jagielski 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_type.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ixgbe/base/ixgbe_type.h 
b/drivers/net/ixgbe/base/ixgbe_type.h
index f6d5052c65..cc49eace91 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -131,6 +131,7 @@
 #define IXGBE_DEV_ID_E610_2_5G_T   0x57B1
 #define IXGBE_DEV_ID_E610_SGMII0x57B2
 #define IXGBE_DEV_ID_E610_VF   0x57AD
+#define IXGBE_SUBDEV_ID_E610_VF_HV 0x0001
 
 #define IXGBE_CAT(r, m) IXGBE_##r##m
 
-- 
2.43.5

[PATCH v1 06/15] net/ixgbe/base: fix unchecked return value

[Anatoly Burakov]

From: Barbara Skobiej 

There was unchecked return value in the ixgbe_stop_mac_link_on_d3_82599
function. Added checking of return value from the called function
ixgbe_read_eeprom.

Signed-off-by: Barbara Skobiej 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_82599.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_82599.c 
b/drivers/net/ixgbe/base/ixgbe_82599.c
index c4ad906f0f..3110477700 100644
--- a/drivers/net/ixgbe/base/ixgbe_82599.c
+++ b/drivers/net/ixgbe/base/ixgbe_82599.c
@@ -556,13 +556,15 @@ enum ixgbe_media_type ixgbe_get_media_type_82599(struct 
ixgbe_hw *hw)
  **/
 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
 {
-   u32 autoc2_reg;
u16 ee_ctrl_2 = 0;
+   u32 autoc2_reg;
+   u32 status;
 
DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
-   ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
+   status = ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
 
-   if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
+   if (status == IXGBE_SUCCESS &&
+   !ixgbe_mng_present(hw) && !hw->wol_enabled &&
ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
-- 
2.43.5

[PATCH v1 07/15] net/ixgbe/base: fix media type handling for E610

[Anatoly Burakov]

From: Krzysztof Galazka 

Media type information should not be updated by ixgbe_aci_get_link_info
function because it will be incorrectly set as unknown when link is down.
Do it only in ixgbe_get_media_type_E610.

Signed-off-by: Krzysztof Galazka 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_e610.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c 
b/drivers/net/ixgbe/base/ixgbe_e610.c
index 1f3a4532da..b9b1ba32c3 100644
--- a/drivers/net/ixgbe/base/ixgbe_e610.c
+++ b/drivers/net/ixgbe/base/ixgbe_e610.c
@@ -1683,7 +1683,6 @@ s32 ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool 
ena_lse,
struct ixgbe_aci_cmd_get_link_status *resp;
struct ixgbe_link_status *li_old, *li;
struct ixgbe_fc_info *hw_fc_info;
-   enum ixgbe_media_type *hw_media_type;
struct ixgbe_aci_desc desc;
bool tx_pause, rx_pause;
u8 cmd_flags;
@@ -1693,7 +1692,6 @@ s32 ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool 
ena_lse,
return IXGBE_ERR_PARAM;
 
li_old = &hw->link.link_info_old;
-   hw_media_type = &hw->phy.media_type;
li = &hw->link.link_info;
hw_fc_info = &hw->fc;
 
@@ -1714,7 +1712,6 @@ s32 ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool 
ena_lse,
li->link_speed = IXGBE_LE16_TO_CPU(link_data.link_speed);
li->phy_type_low = IXGBE_LE64_TO_CPU(link_data.phy_type_low);
li->phy_type_high = IXGBE_LE64_TO_CPU(link_data.phy_type_high);
-   *hw_media_type = ixgbe_get_media_type_from_phy_type(hw);
li->link_info = link_data.link_info;
li->link_cfg_err = link_data.link_cfg_err;
li->an_info = link_data.an_info;
@@ -3664,10 +3661,11 @@ enum ixgbe_media_type ixgbe_get_media_type_E610(struct 
ixgbe_hw *hw)
}
}
 
-   /* Based on search above try to discover media type */
-   hw->phy.media_type = ixgbe_get_media_type_from_phy_type(hw);
}
 
+   /* Based on link status or search above try to discover media type */
+   hw->phy.media_type = ixgbe_get_media_type_from_phy_type(hw);
+
return hw->phy.media_type;
 }
 
-- 
2.43.5

[PATCH v1 08/15] net/ixgbe/base: fix speed autonegotiation on E610

[Anatoly Burakov]

From: Krzysztof Galazka 

When user changed advertised speed settings and link was already up
driver asked FW only for active PHY configuration. This prevented it from
adding speeds, which are supported but was earlier disabled by user. Get
all speeds supported by HW to allow user enabling any of them.

Signed-off-by: Krzysztof Galazka 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_e610.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c 
b/drivers/net/ixgbe/base/ixgbe_e610.c
index b9b1ba32c3..6eaf377f4a 100644
--- a/drivers/net/ixgbe/base/ixgbe_e610.c
+++ b/drivers/net/ixgbe/base/ixgbe_e610.c
@@ -4342,7 +4342,8 @@ s32 ixgbe_setup_phy_link_E610(struct ixgbe_hw *hw)
 {
struct ixgbe_aci_cmd_get_phy_caps_data pcaps;
struct ixgbe_aci_cmd_set_phy_cfg_data pcfg;
-   u8 rmode = IXGBE_ACI_REPORT_ACTIVE_CFG;
+   u8 rmode = IXGBE_ACI_REPORT_TOPO_CAP_MEDIA;
+   u64 sup_phy_type_low, sup_phy_type_high;
s32 rc;
 
rc = ixgbe_aci_get_link_info(hw, false, NULL);
@@ -4359,6 +4360,15 @@ s32 ixgbe_setup_phy_link_E610(struct ixgbe_hw *hw)
goto err;
}
 
+   sup_phy_type_low = pcaps.phy_type_low;
+   sup_phy_type_high = pcaps.phy_type_high;
+
+   /* Get Active configuration to avoid unintended changes */
+   rc = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_ACTIVE_CFG,
+   &pcaps);
+   if (rc) {
+   goto err;
+   }
ixgbe_copy_phy_caps_to_cfg(&pcaps, &pcfg);
 
/* Set default PHY types for a given speed */
@@ -4406,8 +4416,8 @@ s32 ixgbe_setup_phy_link_E610(struct ixgbe_hw *hw)
}
 
/* Mask the set values to avoid requesting unsupported link types */
-   pcfg.phy_type_low &= pcaps.phy_type_low;
-   pcfg.phy_type_high &= pcaps.phy_type_high;
+   pcfg.phy_type_low &= sup_phy_type_low;
+   pcfg.phy_type_high &= sup_phy_type_high;
 
if (pcfg.phy_type_high != pcaps.phy_type_high ||
pcfg.phy_type_low != pcaps.phy_type_low ||
-- 
2.43.5

[PATCH v1 09/15] net/ixgbe/base: FW API version update

[Anatoly Burakov]

From: Pawel Malinowski 

Update FW API version to 1.7.

Signed-off-by: Pawel Malinowski 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_type_e610.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_type_e610.h 
b/drivers/net/ixgbe/base/ixgbe_type_e610.h
index ab57852f19..bad332c6b8 100644
--- a/drivers/net/ixgbe/base/ixgbe_type_e610.h
+++ b/drivers/net/ixgbe/base/ixgbe_type_e610.h
@@ -351,7 +351,7 @@
  */
 #define IXGBE_FW_API_VER_BRANCH0x00
 #define IXGBE_FW_API_VER_MAJOR 0x01
-#define IXGBE_FW_API_VER_MINOR 0x05
+#define IXGBE_FW_API_VER_MINOR 0x07
 #define IXGBE_FW_API_VER_DIFF_ALLOWED  0x02
 
 #define IXGBE_ACI_DESC_SIZE32
-- 
2.43.5

[PATCH v1 10/15] net/ixgbe/base: handle 5G link speed for E610

[Anatoly Burakov]

From: Piotr Kwapulinski 

When detecting the 5G link speed take into account the E610 VF MAC type in
ixgbe_check_mac_link_vf().

Signed-off-by: Piotr Kwapulinski 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_vf.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_vf.c 
b/drivers/net/ixgbe/base/ixgbe_vf.c
index 0d5b29ba50..37556a9300 100644
--- a/drivers/net/ixgbe/base/ixgbe_vf.c
+++ b/drivers/net/ixgbe/base/ixgbe_vf.c
@@ -628,7 +628,8 @@ s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, 
ixgbe_link_speed *speed,
break;
case IXGBE_LINKS_SPEED_100_82599:
*speed = IXGBE_LINK_SPEED_100_FULL;
-   if (hw->mac.type == ixgbe_mac_X550_vf) {
+   if (hw->mac.type == ixgbe_mac_X550_vf ||
+   hw->mac.type == ixgbe_mac_E610_vf) {
if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
*speed = IXGBE_LINK_SPEED_5GB_FULL;
}
-- 
2.43.5

[PATCH v1 11/15] net/ixgbe/base: remove FW API version check

[Anatoly Burakov]

From: Krzysztof Galazka 

Only certain variants of drivers rely on FW API version check in shared
code. Other drivers implement their own logic due to differences in
requirements. DPDK does not require the FW API check.

Signed-off-by: Krzysztof Galazka 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_e610.c | 31 +
 1 file changed, 1 insertion(+), 30 deletions(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c 
b/drivers/net/ixgbe/base/ixgbe_e610.c
index 6eaf377f4a..7ea495db97 100644
--- a/drivers/net/ixgbe/base/ixgbe_e610.c
+++ b/drivers/net/ixgbe/base/ixgbe_e610.c
@@ -3541,32 +3541,7 @@ s32 ixgbe_reset_hw_E610(struct ixgbe_hw *hw)
 reset_hw_out:
return status;
 }
-/**
- * ixgbe_fw_ver_check - Check the reported FW API version
- * @hw: pointer to the hardware structure
- *
- * Checks if the driver should load on a given FW API version.
- *
- * Return: 'true' if the driver should attempt to load. 'false' otherwise.
- */
-static bool ixgbe_fw_ver_check(struct ixgbe_hw *hw)
-{
-   if (hw->api_maj_ver > IXGBE_FW_API_VER_MAJOR) {
-   ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, "The driver for the 
device stopped because the NVM image is newer than expected. You must install 
the most recent version of the network driver.\n");
-   return false;
-   } else if (hw->api_maj_ver == IXGBE_FW_API_VER_MAJOR) {
-   if (hw->api_min_ver >
-   (IXGBE_FW_API_VER_MINOR + IXGBE_FW_API_VER_DIFF_ALLOWED)) {
-   ERROR_REPORT1(IXGBE_ERROR_CAUTION, "The driver for the 
device detected a newer version of the NVM image than expected. Please install 
the most recent version of the network driver.\n");
-   } else if ((hw->api_min_ver + IXGBE_FW_API_VER_DIFF_ALLOWED) <
-  IXGBE_FW_API_VER_MINOR) {
-   ERROR_REPORT1(IXGBE_ERROR_CAUTION, "The driver for the 
device detected an older version of the NVM image than expected. Please update 
the NVM image.\n");
-   }
-   } else {
-   ERROR_REPORT1(IXGBE_ERROR_CAUTION, "The driver for the device 
detected an older version of the NVM image than expected. Please update the NVM 
image.\n");
-   }
-   return true;
-}
+
 /**
  * ixgbe_start_hw_E610 - Prepare hardware for Tx/Rx
  * @hw: pointer to hardware structure
@@ -3584,10 +3559,6 @@ s32 ixgbe_start_hw_E610(struct ixgbe_hw *hw)
if (ret_val)
goto out;
 
-   if (!ixgbe_fw_ver_check(hw)) {
-   ret_val = IXGBE_ERR_FW_API_VER;
-   goto out;
-   }
ret_val = ixgbe_start_hw_generic(hw);
if (ret_val != IXGBE_SUCCESS)
goto out;
-- 
2.43.5

[PATCH v1 12/15] net/ixgbe/base: disable thermal sensor ops for E610

[Anatoly Burakov]

From: Andrzej Wilczynski 

According to data sheet, E610 doesn't expose current reading from thermal
sensors. Currently, E610 sensor ops are the same as for X540, which will
include the unsupported op. This patch disables those ops for E610 to avoid
attempts to read those sensors.

Signed-off-by: Andrzej Wilczynski 
Co-authored-by: RemigiuszX Konca 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_e610.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c 
b/drivers/net/ixgbe/base/ixgbe_e610.c
index 7ea495db97..ab02b11d6a 100644
--- a/drivers/net/ixgbe/base/ixgbe_e610.c
+++ b/drivers/net/ixgbe/base/ixgbe_e610.c
@@ -3431,6 +3431,8 @@ s32 ixgbe_init_ops_E610(struct ixgbe_hw *hw)
mac->ops.get_fw_tsam_mode = ixgbe_get_fw_tsam_mode_E610;
mac->ops.get_fw_version = ixgbe_aci_get_fw_ver;
mac->ops.get_nvm_version = ixgbe_get_active_nvm_ver;
+   mac->ops.get_thermal_sensor_data = NULL;
+   mac->ops.init_thermal_sensor_thresh = NULL;
 
/* PHY */
phy->ops.init = ixgbe_init_phy_ops_E610;
-- 
2.43.5

[PATCH v1 13/15] net/ixgbe/base: fix mailbox ACK handling

[Anatoly Burakov]

From: NorbertX Ciosek 

Check if CTS bit is set in the mailbox message before waiting for ACK.
Otherwise ACK will never be received causing the function to timeout. Add
a note for ixgbe_write_mbx that it should be called while holding a lock.

Signed-off-by: NorbertX Ciosek 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_mbx.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_mbx.c 
b/drivers/net/ixgbe/base/ixgbe_mbx.c
index 23659266d0..fb8ea8ca68 100644
--- a/drivers/net/ixgbe/base/ixgbe_mbx.c
+++ b/drivers/net/ixgbe/base/ixgbe_mbx.c
@@ -82,6 +82,9 @@ s32 ixgbe_poll_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, 
u16 mbx_id)
  *
  * returns SUCCESS if it successfully copied message into the buffer and
  * received an ACK to that message within specified period
+ *
+ * Note that the caller to this function must lock before calling, since
+ * multiple threads can destroy each other messages.
  **/
 s32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
 {
@@ -836,6 +839,11 @@ STATIC s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, 
u16 vf_id)
while (countdown--) {
/* Reserve mailbox for PF use */
pf_mailbox = IXGBE_READ_REG(hw, IXGBE_PFMAILBOX(vf_id));
+
+   /* Check if other thread holds the PF lock already */
+   if (pf_mailbox & IXGBE_PFMAILBOX_PFU)
+   goto retry;
+
pf_mailbox |= IXGBE_PFMAILBOX_PFU;
IXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_id), pf_mailbox);
 
@@ -846,6 +854,7 @@ STATIC s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, 
u16 vf_id)
break;
}
 
+   retry:
/* Wait a bit before trying again */
usec_delay(mbx->usec_delay);
}
@@ -948,13 +957,14 @@ STATIC s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 
*msg, u16 size,
for (i = 0; i < size; i++)
IXGBE_WRITE_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_id), i, msg[i]);
 
-   /* Interrupt VF to tell it a message has been sent */
+   /* interrupt VF to tell it a message has been sent */
pf_mailbox = IXGBE_READ_REG(hw, IXGBE_PFMAILBOX(vf_id));
pf_mailbox |= IXGBE_PFMAILBOX_STS;
IXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_id), pf_mailbox);
 
/* if msg sent wait until we receive an ack */
-   ixgbe_poll_for_ack(hw, vf_id);
+   if (msg[0] & IXGBE_VT_MSGTYPE_CTS)
+   ixgbe_poll_for_ack(hw, vf_id);
 
/* update stats */
hw->mbx.stats.msgs_tx++;
-- 
2.43.5

[PATCH v1 14/15] net/ixgbe/base: correct NVM access type for EEPROM writes on E610

[Anatoly Burakov]

From: Przemyslaw Gierszynski 

NVM acquire function was incorrectly invoked with a read-only access type
when intending to perform a write operation to the EEPROM. This commit
corrects the access type used during the acquisition of the NVM. The
change ensures that the NVM is acquired with write access before
attempting to write to the EEPROM, aligning with the intended operation.

Signed-off-by: Przemyslaw Gierszynski 
Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/base/ixgbe_e610.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c 
b/drivers/net/ixgbe/base/ixgbe_e610.c
index ab02b11d6a..b0d55a2411 100644
--- a/drivers/net/ixgbe/base/ixgbe_e610.c
+++ b/drivers/net/ixgbe/base/ixgbe_e610.c
@@ -2314,7 +2314,7 @@ s32 ixgbe_nvm_recalculate_checksum(struct ixgbe_hw *hw)
struct ixgbe_aci_desc desc;
s32 status;
 
-   status = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);
+   status = ixgbe_acquire_nvm(hw, IXGBE_RES_WRITE);
if (status)
return status;
 
-- 
2.43.5

[PATCH v1 15/15] net/ixgbe: add PCI IDs for new device variants

[Anatoly Burakov]

Include different variants of E610 in the PCI ID table to ensure they are
able to be initialized by DPDK driver.

Fixes: 316637762a5f ("net/ixgbe/base: enable E610 device")

Signed-off-by: Anatoly Burakov 
---
 drivers/net/ixgbe/ixgbe_ethdev.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index d88d4065f1..e4263ef50b 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -449,6 +449,11 @@ static const struct rte_pci_id pci_id_ixgbe_map[] = {
{ RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
{ RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
{ RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
+   { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_10G_T) },
+   { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_2_5G_T) },
+   { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_BACKPLANE) },
+   { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SFP) },
+   { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SGMII) },
 #ifdef RTE_LIBRTE_IXGBE_BYPASS
{ RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 #endif
-- 
2.43.5

Re: [PATCH] net/mlx5: fix NVGRE item validation for template API

[Raslan Darawsheh]

Hi,

From: Jiawei(Jonny) Wang 
Sent: Friday, July 26, 2024 4:49 AM
To: Bing Zhao; Slava Ovsiienko; Dariusz Sosnowski; Ori Kam; Suanming Mou; Matan 
Azrad; Gregory Etelson
Cc: dev@dpdk.org; Raslan Darawsheh; sta...@dpdk.org
Subject: [PATCH] net/mlx5: fix NVGRE item validation for template API

The template API NVGRE item can support full mask.
This patch updates default NVGRE item mask for the template API.

Fixes: 80c676259a04 ("net/mlx5: validate HWS template items")
Cc: sta...@dpdk.org

Signed-off-by: Jiawei Wang 
Acked-by: Bing Zhao 

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

Re: 23.11.2 patches review and test

[Xueming Li]

Hi Ali,

Thanks for the verification and support!

Best regards,
Xueming

From: Ali Alnubani 
Sent: Thursday, August 29, 2024 4:46 PM
To: Xueming Li ; sta...@dpdk.org 
Cc: dev@dpdk.org ; Abhishek Marathe 
; David Christensen ; 
Hemant Agrawal ; Ian Stokes ; 
Jerin Jacob ; John McNamara ; 
Ju-Hyoung Lee ; Kevin Traynor ; Luca 
Boccassi ; Pei Zhang ; Raslan Darawsheh 
; NBU-Contact-Thomas Monjalon (EXTERNAL) 
; Yanghang Liu ; 
benjamin.wal...@intel.com ; qian.q...@intel.com 
; yuan.p...@intel.com ; 
zhaoyan.c...@intel.com 
Subject: RE: 23.11.2 patches review and test

> -Original Message-
> From: Xueming Li 
> Sent: Thursday, August 22, 2024 3:07 PM
> To: sta...@dpdk.org
> Cc: dev@dpdk.org; Abhishek Marathe ; Ali
> Alnubani ; David Christensen ;
> Hemant Agrawal ; Ian Stokes
> ; Jerin Jacob ; John McNamara
> ; Ju-Hyoung Lee ; Kevin
> Traynor ; Luca Boccassi ; Pei Zhang
> ; Raslan Darawsheh ; NBU-
> Contact-Thomas Monjalon (EXTERNAL) ; Yanghang Liu
> ; benjamin.wal...@intel.com; qian.q...@intel.com;
> yuan.p...@intel.com; zhaoyan.c...@intel.com
> Subject: 23.11.2 patches review and test
>
> Hi all,
>
> Here is a list of patches targeted for stable release 23.11.2.
>
> The planned date for the final release is 31th August.
>
> Please help with testing and validation of your use cases and report
> any issues/results with reply-all to this mail. For the final release
> the fixes and reported validations will be added to the release notes.
>
> A release candidate tarball can be found at:
>
> https://dpdk.org/browse/dpdk-stable/tag/?id=v23.11.2-rc2
>
> These patches are located at branch 23.11 of dpdk-stable repo:
> https://dpdk.org/browse/dpdk-stable/
>
> Thanks.
>
> Xueming Li 
>
> ---

Hello,

We ran the following functional tests with Nvidia hardware on v23.11.2-rc2:
- Basic functionality:
  Send and receive multiple types of traffic.
- testpmd xstats counter test.
- testpmd timestamp test.
- Changing/checking link status through testpmd.
- rte_flow tests 
(https://doc.dpdk.org/guides/nics/mlx5.html#supported-hardware-offloads)
- RSS tests.
- VLAN filtering, stripping, and insertion tests.
- Checksum and TSO tests.
- ptype tests.
- link_status_interrupt example application tests.
- l3fwd-power example application tests.
- Multi-process example applications tests.
- Hardware LRO tests.
- Buffer Split tests.
- Tx scheduling tests.

Functional tests ran on:
- NIC: ConnectX-6 Dx / OS: Ubuntu 20.04 / Driver: MLNX_OFED_LINUX-24.07-0.6.1.0 
/ Firmware: 22.42.1000
- NIC: ConnectX-7 / OS: Ubuntu 20.04 / Driver: MLNX_OFED_LINUX-24.07-0.6.1.0 / 
Firmware: 28.42.1000
- DPU: BlueField-2 / DOCA SW version: 2.8 / Firmware: 24.42.1000


Additionally, we ran build tests with multiple configurations on the following 
OS/driver combinations (all passed):
- Debian 12 with MLNX_OFED_LINUX-24.04-0.7.0.0.
- Ubuntu 20.04.6 with MLNX_OFED_LINUX-24.07-0.6.1.0.
- Ubuntu 20.04.6 with rdma-core master (dd9c687).
- Ubuntu 20.04.6 with rdma-core v28.0.
- Fedora 40 with rdma-core v48.0.
- Fedora 42 (Rawhide) with rdma-core v51.0.
- OpenSUSE Leap 15.6 with rdma-core v49.1.

We don't see new issues caused by the changes in this release.

Thanks,
Ali

[DPDK/ethdev Bug 1529] "net_txgbe" have not implemented outer UDP checksum offload, but the capability flag has been set.

[bugzilla]

https://bugs.dpdk.org/show_bug.cgi?id=1529

Bug ID: 1529
   Summary: "net_txgbe" have not implemented outer UDP checksum
offload, but the capability flag has been set.
   Product: DPDK
   Version: 24.07
  Hardware: All
OS: All
Status: UNCONFIRMED
  Severity: normal
  Priority: Normal
 Component: ethdev
  Assignee: dev@dpdk.org
  Reporter: junwan...@cestc.cn
  Target Milestone: ---

In OVS-DPDK, when using the Wangxun RP1000 network card, I found that the card
supports outer UDP checksum offload according to the capabilities retrieved by
OVS-DPDK. However, in actual testing, the outer UDP checksum of the transmitted
packets is incorrect. After I manually disabled
RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM in the OVS code, the traffic was normal. So,
does this mean that the card does not actually support outer UDP checksum
offload, but the capability is enabled in the DPDK code? Or is there a bug in
the implementation logic?

Before modification in OVS:

status  : {bus_info="bus_name=pci, vendor_id=8088, device_id=1001",
driver_name=net_txgbe, if_descr="DPDK 23.11.0 net_txgbe", if_type="6",
link_speed="10Gbps", max_hash_mac_addrs="4096", max_mac_addrs="128",
max_rx_pktlen="1618", max_rx_queues="128", max_tx_queues="128", max_vfs="0",
max_vmdq_pools="64", min_rx_bufsize="1024", n_rxq="2", n_txq="5", numa_id="0",
port_no="0", rx-steering=rss, rx_csum_offload="true",
tx_geneve_tso_offload="true", tx_ip_csum_offload="true",
tx_out_ip_csum_offload="true", tx_out_udp_csum_offload="true",
tx_sctp_csum_offload="true", tx_tcp_csum_offload="true",
tx_tcp_seg_offload="true", tx_udp_csum_offload="true",
tx_vxlan_tso_offload="true"}


After modification in OVS:

status  : {bus_info="bus_name=pci, vendor_id=8088, device_id=1001",
driver_name=net_txgbe, if_descr="DPDK 23.11.0 net_txgbe", if_type="6",
link_speed="10Gbps", max_hash_mac_addrs="4096", max_mac_addrs="128",
max_rx_pktlen="1618", max_rx_queues="128", max_tx_queues="128", max_vfs="0",
max_vmdq_pools="64", min_rx_bufsize="1024", n_rxq="2", n_txq="5", numa_id="0",
port_no="0", rx-steering=rss, rx_csum_offload="true",
tx_geneve_tso_offload="true", tx_ip_csum_offload="true",
tx_out_ip_csum_offload="true", tx_out_udp_csum_offload="false",
tx_sctp_csum_offload="true", tx_tcp_csum_offload="true",
tx_tcp_seg_offload="true", tx_udp_csum_offload="true",
tx_vxlan_tso_offload="true"}


diff --git a/lib/netdev-dpdk.c b/lib/netdev-dpdk.c
index
d7f0aa1f5835b5c51ed0a2c8cd84079f388ca9ce..1f50676e55687f6ccdaccb7f5403c82569fb2041
100644
--- a/lib/netdev-dpdk.c
+++ b/lib/netdev-dpdk.c
@@ -2050,12 +2050,13 @@ dpdk_eth_offload_config(struct netdev_dpdk *dev,
 }

 if (!strcmp(info->driver_name, "net_i40e")
-|| !strcmp(info->driver_name, "net_iavf")) {
+|| !strcmp(info->driver_name, "net_iavf")
+|| !strcmp(info->driver_name, "net_txgbe")) {
 /* FIXME: Driver advertises the capability but doesn't seem
  * to actually support it correctly.  Can remove this once
  * the driver is fixed on DPDK side. */
 VLOG_INFO("%s: disabled Tx outer udp checksum offloads for a "
-  "net/i40e or net/iavf port.",
+  "net/i40e or net/iavf or net_txgbe port.",
   netdev_get_name(&dev->up));
 info->tx_offload_capa &= ~RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 }

-- 
You are receiving this mail because:
You are the assignee for the bug.

[PATCH] dts: add RSS functions to testpmd

[Alex Chapman]

This patch adds the required functionality for the RSS key_update,
RETA, and hash test suites. This includes:
The setting of custom RETA values for routing packets to specific
queues.
The setting of the RSS mode on all ports, to specify how to hash
the packets.
The updating of the RSS hash key used during the hashing process.

Alongside this, there is the addition of a __str__ method to the
RSSOffloadTypesFlags class, so that when flag names are cast to
a string they will use '-' as separators, instead of '_'.
This allows them to be directly used within testpmd RSS commands
without any further changes.

Signed-off-by: Alex Chapman 
Reviewed-by: Luca Vizzarro 
---
 dts/framework/remote_session/testpmd_shell.py | 84 ++-
 1 file changed, 83 insertions(+), 1 deletion(-)

diff --git a/dts/framework/remote_session/testpmd_shell.py 
b/dts/framework/remote_session/testpmd_shell.py
index 43e9f56517..7b66901f6e 100644
--- a/dts/framework/remote_session/testpmd_shell.py
+++ b/dts/framework/remote_session/testpmd_shell.py
@@ -23,7 +23,7 @@
 
 from typing_extensions import Self, Unpack
 
-from framework.exception import InteractiveCommandExecutionError
+from framework.exception import InteractiveCommandExecutionError, InternalError
 from framework.params.testpmd import SimpleForwardingModes, TestPmdParams
 from framework.params.types import TestPmdParamsDict
 from framework.parser import ParserFn, TextParser
@@ -305,6 +305,12 @@ def make_parser(cls) -> ParserFn:
 RSSOffloadTypesFlag.from_list_string,
 )
 
+def __str__(self):
+"""Stringifies the flag name."""
+if self.name is None:
+return ""
+return self.name.replace("_", "-")
+
 
 class DeviceCapabilitiesFlag(Flag):
 """Flag representing the device capabilities."""
@@ -723,6 +729,82 @@ def set_forward_mode(self, mode: SimpleForwardingModes, 
verify: bool = True):
 f"Test pmd failed to set fwd mode to {mode.value}"
 )
 
+def port_config_rss_reta(
+self, port_id: int, hash_index: int, queue_id: int, verify: bool = True
+) -> None:
+"""Configures a port's RSS redirection table.
+
+Args:
+port_id: Port where redirection table will be configured.
+hash_index: The index into the redirection table associated with 
the destination queue.
+queue_id: The destination queue of the packet.
+verify: If :data:`True`, it verifies if a port's redirection table
+was correctly configured.
+
+Raises:
+InteractiveCommandExecutionError: If `verify` is :data:`True`
+Testpmd failed to config RSS reta.
+"""
+out = self.send_command(f"port config {port_id} rss reta 
({hash_index},{queue_id})")
+if verify:
+if f"The reta size of port {port_id} is" not in out:
+self._logger.debug(f"Failed to config RSS reta: \n{out}")
+raise InteractiveCommandExecutionError("Testpmd failed to 
config RSS reta.")
+
+def port_config_all_rss_offload_type(
+self, flag: RSSOffloadTypesFlag, verify: bool = True
+) -> None:
+"""Set the RSS mode on all ports.
+
+Args:
+rss_offload_type: The RSS iptype all ports will be configured to.
+verify: If :data:`True`, it verifies if all ports RSS offload type
+was correctly configured.
+
+Raises:
+InternalError: Offload Flag has contradictory values set.
+InteractiveCommandExecutionError: If `verify` is :data:`True`
+Testpmd failed to config the RSS mode on all ports.
+"""
+if not flag.name:
+raise InternalError("Offload Flag has contradictory values set")
+
+out = self.send_command(f"port config all rss {flag.name}")
+
+if verify:
+if "error" in out:
+self._logger.debug(f"Failed to config the RSS mode on all 
ports: \n{out}")
+raise InteractiveCommandExecutionError(
+"Testpmd failed to config the RSS mode on all ports"
+)
+
+def port_config_rss_hash_key(
+self, port_id: int, offload_type: RSSOffloadTypesFlag, hex_str: str, 
verify: bool = True
+) -> str:
+"""Set the RSS hash key for the specified port.
+
+Args:
+port_id: Port the hash key will be set.
+offload_type: The offload type the hash key will be applied to.
+hex_str: The new hash key.
+verify: If :data:`True`, RSS hash key has been correctly set.
+
+Raises:
+InteractiveCommandExecutionError: If `verify` is :data:`True`
+Testpmd failed to set the RSS hash key.
+"""
+output = self.send_command(f"port config {port_id} rss-hash-key 
{offload_type} {hex_str}")
+
+if verify:
+if (
+"invalid - key must be a string of" in

Re: [PATCH v8 2/3] eventdev: add support for independent enqueue

[Jerin Jacob]

On Wed, Aug 28, 2024 at 10:29 PM Sevincer, Abdullah
 wrote:
>
> Thanks Mattias,
>
> Hi Jerin,
>
> Are you okay with the changes so far?

The overall outlook is OK. Send next version with release note changes
from 24.07 to 24.11.

Re: [PATCH v3 11/12] dts: add Rx offload capabilities

[Jeremy Spewock]

On Wed, Aug 28, 2024 at 1:44 PM Jeremy Spewock  wrote:
>
> On Wed, Aug 21, 2024 at 10:53 AM Juraj Linkeš
>  wrote:
> 
> > diff --git a/dts/framework/remote_session/testpmd_shell.py 
> > b/dts/framework/remote_session/testpmd_shell.py
> > index 48c31124d1..f83569669e 100644
> > --- a/dts/framework/remote_session/testpmd_shell.py
> > +++ b/dts/framework/remote_session/testpmd_shell.py
> > @@ -659,6 +659,103 @@ class TestPmdPortStats(TextParser):
> >  tx_bps: int = field(metadata=TextParser.find_int(r"Tx-bps:\s+(\d+)"))
> >
> >
> > +class RxOffloadCapability(Flag):
> > +"""Rx offload capabilities of a device."""
> > +
> > +#:
> > +RX_OFFLOAD_VLAN_STRIP = auto()
>
> One other thought that I had about this; was there a specific reason
> that you decided to prefix all of these with `RX_OFFLOAD_`? I am
> working on a test suite right now that uses both RX and TX offloads
> and thought that it would be a great use of capabilities, so I am
> working on adding a TxOffloadCapability flag as well and, since the
> output is essentially the same, it made a lot of sense to make it a
> sibling class of this one with similar parsing functionality. In what
> I was writing, I found it much easier to remove this prefix so that
> the parsing method can be the same for both RX and TX, and I didn't
> have to restate some options that are shared between both (like
> IPv4_CKSUM, UDP_CKSUM, etc.). Is there a reason you can think of why
> removing this prefix is a bad idea? Hopefully I will have a patch out
> soon that shows this extension that I've made so that you can see
> in-code what I was thinking.

I see now that you actually already answered this question, I was just
looking too much at that piece of code, and clearly not looking
further down at the helper-method mapping or the commit message that
you left :).

"The Flag members correspond to NIC
capability names so a convenience function that looks for the supported
Flags in a testpmd output is also added."

Having it prefixed with RX_OFFLOAD_ in NicCapability makes a lot of
sense since it is more explicit. Since there is a good reason to have
it like this, then the redundancy makes sense I think. There are some
ways to potentially avoid this like creating a StrFlag class that
overrides the __str__ method, or something like an additional type
that would contain a toString method, but it feels very situational
and specific to this one use-case so it probably isn't going to be
super valuable. Another thing I could think of to do would be allowing
the user to pass in a function or something to the helper-method that
mapped Flag names to their respective NicCapability name, or just
doing it in the method that gets the offloads instead of using a
helper at all, but this also just makes it more complicated and maybe
it isn't worth it.

I apologize for asking you about something that you already explained,
but maybe something we can get out of this is that, since these names
have to be consistent, it might be worth putting that in the
doc-strings of the flag for when people try to make further expansions
or changes in the future. Or it could also be generally clear that
flags used for capabilities should follow this idea, let me know what
you think.

>
> > +#: Device supports L3 checksum offload.
> > +RX_OFFLOAD_IPV4_CKSUM = auto()
> > +#: Device supports L4 checksum offload.
> > +RX_OFFLOAD_UDP_CKSUM = auto()
> > +#: Device supports L4 checksum offload.
> > +RX_OFFLOAD_TCP_CKSUM = auto()
> > +#: Device supports Large Receive Offload.
> > +RX_OFFLOAD_TCP_LRO = auto()
> > +#: Device supports QinQ (queue in queue) offload.
> > +RX_OFFLOAD_QINQ_STRIP = auto()
> > +#: Device supports inner packet L3 checksum.
> > +RX_OFFLOAD_OUTER_IPV4_CKSUM = auto()
> > +#: Device supports MACsec.
> > +RX_OFFLOAD_MACSEC_STRIP = auto()
> > +#: Device supports filtering of a VLAN Tag identifier.
> > +RX_OFFLOAD_VLAN_FILTER = 1 << 9
> > +#: Device supports VLAN offload.
> > +RX_OFFLOAD_VLAN_EXTEND = auto()
> > +#: Device supports receiving segmented mbufs.
> > +RX_OFFLOAD_SCATTER = 1 << 13
> > +#: Device supports Timestamp.
> > +RX_OFFLOAD_TIMESTAMP = auto()
> > +#: Device supports crypto processing while packet is received in NIC.
> > +RX_OFFLOAD_SECURITY = auto()
> > +#: Device supports CRC stripping.
> > +RX_OFFLOAD_KEEP_CRC = auto()
> > +#: Device supports L4 checksum offload.
> > +RX_OFFLOAD_SCTP_CKSUM = auto()
> > +#: Device supports inner packet L4 checksum.
> > +RX_OFFLOAD_OUTER_UDP_CKSUM = auto()
> > +#: Device supports RSS hashing.
> > +RX_OFFLOAD_RSS_HASH = auto()
> > +#: Device supports
> > +RX_OFFLOAD_BUFFER_SPLIT = auto()
> > +#: Device supports all checksum capabilities.
> > +RX_OFFLOAD_CHECKSUM = RX_OFFLOAD_IPV4_CKSUM | RX_OFFLOAD_UDP_CKSUM | 
> > RX_OFFLOAD_TCP_CKSUM
> > +#: Device supports all VLAN capabilities.
> > +RX_

[PATCH v9 0/3] Independent Enqueue Support

[Abdullah Sevincer]

v8: Address build issues.
v7: Address documentation reviews.
v6: Update patch with more documentation
v5: Address build issues
v4: Address comments
v3: Fix CI/build issues
v2: Fix CI/build issues
v1: Initial patchset

Abdullah Sevincer (3):
  event/dlb2: add support for independent enqueue
  eventdev: add support for independent enqueue
  event/dsw: add capability for independent enqueue

 doc/guides/eventdevs/dlb2.rst |  41 ++
 doc/guides/eventdevs/features/default.ini |   1 +
 doc/guides/eventdevs/features/dlb2.ini|   1 +
 doc/guides/rel_notes/release_24_11.rst|  34 +-
 drivers/event/dlb2/dlb2.c | 492 ++
 drivers/event/dlb2/dlb2_avx512.c  |  27 +-
 drivers/event/dlb2/dlb2_inline_fns.h  |   8 +
 drivers/event/dlb2/dlb2_priv.h|  25 +-
 drivers/event/dlb2/rte_pmd_dlb2.h |  10 +
 drivers/event/dsw/dsw_evdev.c |   3 +-
 lib/eventdev/rte_eventdev.h   |  37 ++
 11 files changed, 463 insertions(+), 216 deletions(-)

-- 
2.25.1

[PATCH v9 1/3] event/dlb2: add support for independent enqueue

[Abdullah Sevincer]

DLB devices need events to be enqueued in the same order they are
dequeued. Applications are not suppose to change event order between
dequeue and to enqueue. Since Eventdev standard does not add such
restrictions independent enqueue support is needed for DLB PMD so that
it restores dequeue order on enqueue if applications happen to change
it. It also adds missing releases in places where events are dropped
by the application and it expects implicit release to handle it.

By default the feature will be off on all DLB ports and they will
behave the same as older releases. To enable reordering feature,
applications need to add the flag RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ
to port configuration if only the device advertises the capability
RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ.

Signed-off-by: Abdullah Sevincer 
---
 doc/guides/eventdevs/dlb2.rst  |  41 +++
 doc/guides/rel_notes/release_24_11.rst |  33 +-
 drivers/event/dlb2/dlb2.c  | 492 -
 drivers/event/dlb2/dlb2_avx512.c   |  27 +-
 drivers/event/dlb2/dlb2_inline_fns.h   |   8 +
 drivers/event/dlb2/dlb2_priv.h |  25 +-
 drivers/event/dlb2/rte_pmd_dlb2.h  |  10 +
 7 files changed, 417 insertions(+), 219 deletions(-)

diff --git a/doc/guides/eventdevs/dlb2.rst b/doc/guides/eventdevs/dlb2.rst
index 2532d92888..8b973cf81e 100644
--- a/doc/guides/eventdevs/dlb2.rst
+++ b/doc/guides/eventdevs/dlb2.rst
@@ -456,6 +456,47 @@ Example command to enable QE Weight feature:
 
--allow ea:00.0,enable_cq_weight=
 
+Independent Enqueue Capability
+~~
+
+DLB2 hardware device expects all forwarded events to be enqueued in the same
+order as they are dequeued. For dropped events, their releases should come at
+the same location as the original event was expected. Hardware has this
+restriction as it uses the order to retrieve information about the original
+event that was sent to the CPU.  This contains information like atomic flow
+ID to release the flow lock and ordered events sequence number to restore the
+original order.
+
+Some applications, like those based on the DPDK dispatcher library, want
+enqueue order independence. To support this, DLB2 PMD supports the
+``RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ`` capability.
+
+This capability applies to Eventdevs supporting burst mode. On ports where
+the application is going to change enqueue order,
+``RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ`` support should be enabled.
+
+Example code to inform PMD that the application plans to use independent 
enqueue
+order on a port:
+
+.. code-block:: c
+
+   if (capability & RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ)
+ port_config = port_config | RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ;
+
+This code example enables enqueue event reordering inside DLB2 PMD before the 
events
+are sent to the DLB2 hardware. If the application is not going to change the 
enqueue
+order, this flag should not be enabled to get better performance. DLB2 PMD 
saves
+ordering information inside the impl_opaque field of the event, and this field 
should
+be preserved for all FORWARD or RELEASE events. Following MACROs are provided 
to get
+and set this field inside the event in case the same event is not used for 
forwarding
+(e.g., a new RELEASE event is created when the original event is dropped 
instead of
+reusing the same event).
+
+.. code-block:: c
+
+   #define RTE_EVENT_GET_IMPL_OPAQUE(ev)  (ev->impl_opaque)
+   #define RTE_EVENT_SET_IMPL_OPAQUE(ev, val)  (ev->impl_opaque = val)
+
 Running Eventdev Applications with DLB Device
 -
 
diff --git a/doc/guides/rel_notes/release_24_11.rst 
b/doc/guides/rel_notes/release_24_11.rst
index 0ff70d9057..f0ec07c263 100644
--- a/doc/guides/rel_notes/release_24_11.rst
+++ b/doc/guides/rel_notes/release_24_11.rst
@@ -24,36 +24,11 @@ DPDK Release 24.11
 New Features
 
 
-.. This section should contain new features added in this release.
-   Sample format:
+* **Updated DLB2 Driver for independent enqueue feature**
 
-   * **Add a title in the past tense with a full stop.**
-
- Add a short 1-2 sentence description in the past tense.
- The description should be enough to allow someone scanning
- the release notes to understand the new feature.
-
- If the feature adds a lot of sub-features you can use a bullet list
- like this:
-
- * Added feature foo to do something.
- * Enhanced feature bar to do something else.
-
- Refer to the previous release notes for examples.
-
- Suggested order in release notes items:
- * Core libs (EAL, mempool, ring, mbuf, buses)
- * Device abstraction libs and PMDs (ordered alphabetically by vendor name)
-   - ethdev (lib, PMDs)
-   - cryptodev (lib, PMDs)
-   - eventdev (lib, PMDs)
-   - etc
- * Other libs
- * Apps, Examples, Tools (if significant)
-
- This section is a comment. Do not overwrite or remove it.
- Also, make

[PATCH v9 2/3] eventdev: add support for independent enqueue

[Abdullah Sevincer]

This commit adds support for independent enqueue feature
and updates Event Device and PMD feature list.

A new capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ is introduced. It
allows out-of-order enqueuing of RTE_EVENT_OP_FORWARD or RELEASE type
events on an event port where this capability is enabled.

To use this capability applications need to set flag
RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ during port setup only if the
capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ exists.

Signed-off-by: Abdullah Sevincer 
---
 doc/guides/eventdevs/features/default.ini |  1 +
 doc/guides/eventdevs/features/dlb2.ini|  1 +
 doc/guides/rel_notes/release_24_11.rst|  5 +++
 lib/eventdev/rte_eventdev.h   | 37 +++
 4 files changed, 44 insertions(+)

diff --git a/doc/guides/eventdevs/features/default.ini 
b/doc/guides/eventdevs/features/default.ini
index 1cc4303fe5..7c4ee99238 100644
--- a/doc/guides/eventdevs/features/default.ini
+++ b/doc/guides/eventdevs/features/default.ini
@@ -22,6 +22,7 @@ carry_flow_id  =
 maintenance_free   =
 runtime_queue_attr =
 profile_links  =
+independent_enq=
 
 ;
 ; Features of a default Ethernet Rx adapter.
diff --git a/doc/guides/eventdevs/features/dlb2.ini 
b/doc/guides/eventdevs/features/dlb2.ini
index 7b80286927..c7193b47c1 100644
--- a/doc/guides/eventdevs/features/dlb2.ini
+++ b/doc/guides/eventdevs/features/dlb2.ini
@@ -15,6 +15,7 @@ implicit_release_disable   = Y
 runtime_port_link  = Y
 multiple_queue_port= Y
 maintenance_free   = Y
+independent_enq= Y
 
 [Eth Rx adapter Features]
 
diff --git a/doc/guides/rel_notes/release_24_11.rst 
b/doc/guides/rel_notes/release_24_11.rst
index f0ec07c263..04f389876a 100644
--- a/doc/guides/rel_notes/release_24_11.rst
+++ b/doc/guides/rel_notes/release_24_11.rst
@@ -30,6 +30,11 @@ New Features
   ``RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ`` to enable the feature if the 
capability
   ``RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ`` exists.
 
+* **Updated Event Device Library for independent enqueue feature**
+
+  * Added support for independent enqueue feature. Updated Event Device and
+PMD feature list.
+
 
 Removed Items
 -
diff --git a/lib/eventdev/rte_eventdev.h b/lib/eventdev/rte_eventdev.h
index 08e5f9320b..3e3142d4a6 100644
--- a/lib/eventdev/rte_eventdev.h
+++ b/lib/eventdev/rte_eventdev.h
@@ -446,6 +446,31 @@ struct rte_event;
  * @see RTE_SCHED_TYPE_PARALLEL
  */
 
+#define RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ  (1ULL << 16)
+/**< Event device is capable of independent enqueue.
+ * A new capability, RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ, will indicate that 
Eventdev
+ * supports the enqueue in any order or specifically in a different order than 
the
+ * dequeue. Eventdev PMD can either transmit events in the changed order in 
which
+ * they are enqueued or restore the original order before sending them to the
+ * underlying hardware device. A flag is provided during the port 
configuration to
+ * inform Eventdev PMD that the application intends to use an independent 
enqueue
+ * order on a particular port. Note that this capability only matters for 
Eventdevs
+ * supporting burst mode.
+ *
+ * To Inform PMD that the application plans to use independent enqueue order 
on a port
+ * this code example can be used:
+ *
+ *  if (capability & RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ)
+ * port_config = port_config | RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ;
+ *
+ * When an implicit release is enabled on a port, Eventdev PMD will also handle
+ * the insertion of RELEASE events in place of dropped events. The independent 
enqueue
+ * feature only applies to FORWARD and RELEASE events. New events 
(op=RTE_EVENT_OP_NEW)
+ * will be transmitted in the order the application enqueues them and do not 
maintain
+ * any order relative to FORWARD/RELEASE events. FORWARD vs NEW relaxed 
ordering
+ * only applies to ports that have enabled independent enqueue feature.
+ */
+
 /* Event device priority levels */
 #define RTE_EVENT_DEV_PRIORITY_HIGHEST   0
 /**< Highest priority level for events and queues.
@@ -1072,6 +1097,18 @@ rte_event_queue_attr_set(uint8_t dev_id, uint8_t 
queue_id, uint32_t attr_id,
  *
  *  @see rte_event_port_setup()
  */
+#define RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ   (1ULL << 5)
+/**< Flag to enable independent enqueue. Must not be set if the device
+ * is not RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ capable. This feature
+ * allows an application to enqueue RTE_EVENT_OP_FORWARD or
+ * RTE_EVENT_OP_RELEASE in an order different than the order the
+ * events were dequeued from the event device, while maintaining
+ * RTE_SCHED_TYPE_ATOMIC or RTE_SCHED_TYPE_ORDERED semantics.
+ *
+ * Note that this flag only matters for Eventdevs supporting burst mode.
+ *
+ *  @see rte_event_port_setup()
+ */
 
 /** Event port configuration structure */
 struct rte_event_port_conf {
-- 
2.25.1

[PATCH v9 3/3] event/dsw: add capability for independent enqueue

[Abdullah Sevincer]

To use independent enqueue capability applications need to set flag
RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ during port setup only if the
capability RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ exists. Hence, this
commit adds the capability of independent enqueue to the DSW driver.

Signed-off-by: Abdullah Sevincer 
---
 doc/guides/rel_notes/release_24_11.rst | 4 
 drivers/event/dsw/dsw_evdev.c  | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/doc/guides/rel_notes/release_24_11.rst 
b/doc/guides/rel_notes/release_24_11.rst
index 04f389876a..b8d1f36e54 100644
--- a/doc/guides/rel_notes/release_24_11.rst
+++ b/doc/guides/rel_notes/release_24_11.rst
@@ -35,6 +35,10 @@ New Features
   * Added support for independent enqueue feature. Updated Event Device and
 PMD feature list.
 
+* **Updated DSW Driver for independent enqueue feature**
+
+  * Added capability flag for DSW to advertise independent enqueue feature.
+
 
 Removed Items
 -
diff --git a/drivers/event/dsw/dsw_evdev.c b/drivers/event/dsw/dsw_evdev.c
index 0dea1091e3..5c483d869c 100644
--- a/drivers/event/dsw/dsw_evdev.c
+++ b/drivers/event/dsw/dsw_evdev.c
@@ -230,7 +230,8 @@ dsw_info_get(struct rte_eventdev *dev __rte_unused,
RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE|
RTE_EVENT_DEV_CAP_NONSEQ_MODE|
RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT|
-   RTE_EVENT_DEV_CAP_CARRY_FLOW_ID
+   RTE_EVENT_DEV_CAP_CARRY_FLOW_ID |
+   RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ
};
 }
 
-- 
2.25.1

Re: [RFC PATCH v3 2/2] dts: Initial Implementation For Jumbo Frames Test Suite

[Nicholas Pratte]

Hi Alex, thanks for the review!

See my comments below.


> > +IP_HEADER_LEN = 20
> > +ETHER_STANDARD_FRAME = 1500
> > +ETHER_JUMBO_FRAME_MTU = 9000
>
> For these constants, I am confused why one is "FRAME" and the other is
> "MTU". The value of 'ETHER_STANDARD_FRAME' is 1500 (the standard MTU
> size), it would make sense to rename it to 'ETHER_STANDARD_MTU', to keep
> naming consistent.
>
> If the value was 1518 instead of 1500, then `ETHER_STANDARD_FRAME` would
> be appropriate.

You are correct! I will make the changes.
>

> Renaming 'ETHER_STANDARD_FRAME' to 'ETHER_STANDARD_MTU' would reduce
> confusion here too.
> e.g.
> `testpmd.configure_port_mtu_all(ETHER_STANDARD_MTU)`
>
> Additionally, you state you are sending packets of sizes 1517 and 1518.
> but you then call:
> `self.send_packet_and_verify(ETHER_STANDARD_FRAME - 5)`
> `self.send_packet_and_verify(ETHER_STANDARD_FRAME)`

Ack. I must have missed the docstring when I adjusted the boundaries
at which we test jumbo frame sizes ethernet overhead issues we've been
having. Adding the +5, -5 bytes is sort of a temporary
measure/placeholder while we wait to gather more information on how to
properly assess and test the ethernet overhead issue. See my next
comment for more clarification.
>
> Calculating to:
> `self.send_packet_and_verify(1495)`
> `self.send_packet_and_verify(1500)`
>
> Which is confusing.
> I believe this is because you are accounting for the 4 bytes of VLAN's
> in your calculations, but you might want to explain this.

What the +5 bytes situation really is for, currently, is to assess the
boundaries of a set MTU size, sorry for the confusion there. For
example, if we have a MTU of 1500, some vendors assume an ethernet
overhead of +22 bytes on top of the 1500 byte MTU (for a total frame
size of 1522 bytes), and other vendors, such as Mellanox, add +18
bytes of ethernet overhead +1500 byte MTU (for a total frame size of
1518). The +5 tries to compensate for this by adding +5 or -5 bytes to
properly test greater than or less than a 1500 byte MTU for all
vendors, but this gets tricky when you are trying to run tests at the
MTU size itself. If you look back to the oldest version I have of this
suite, you'll see that each test case was originally sending 1499 byte
packets, 1501 packets, and 1500 packets in some cases, but we can't
run tests like this because of the differing assumptions from vendor
to vendor (you can find the old suite in a different email thread, I
messed up the sending of the series so I apologize for that).

Here's the original version of this patch:
https://inbox.dpdk.org/dev/20240524183604.6925-2-npra...@iol.unh.edu/

The calculation of ethernet overhead basically comes down to a single
'if' statement in testpmd's code. You can find this method in
testpmd.c and do some digging if you're interested (look under
'app/test-pmd/testpmd.c' and search for 'get_eth_overhead')

>
>
> Overall very solid and clean test suite, just wanted to get
> clarification on a few areas 🙂.
> Alex

I wrote this test suite a while back when I was just starting out, and
a lot of this information was new to me at the time, so it's not
surprising to see some of the misuse of definitions you've laid out
here; I appreciate the feedback!

-Nicholas

Re: [PATCH v3 1/4] dts: add send_packets to test suites and rework packet addressing

[Nicholas Pratte]

Hi Jeremy, sorry for the delay! See my comments below.


> > >  Assumptions:
> > >  Two links between SUT and TG, one link is TG -> SUT, the 
> > > other SUT -> TG.
> > >
> > >  Args:
> > > -packet: The packet to modify.
> > > +packets: The packets to modify.
> > >  expected: If :data:`True`, the direction is SUT -> TG,
> > >  otherwise the direction is TG -> SUT.
> > >  """
> > > -if expected:
> > > -# The packet enters the TG from SUT
> > > -# update l2 addresses
> > > -packet.src = self._sut_port_egress.mac_address
> > > -packet.dst = self._tg_port_ingress.mac_address
> > > +ret_packets = []
> > > +for packet in packets:
> > > +default_pkt_src = type(packet)().src
> > > +default_pkt_dst = type(packet)().dst
> >
> > This is really just a probing question for my sake, but what is the
> > difference between the solution you have above type(packet)().src and
> > Ether().src? Is there a preferred means of doing this?
>
> There isn't really a functional difference at all under the assumption
> that every packet we send will start with an Ethernet header. This
> obviously isn't an unreasonable assumption to make, so maybe I was
> reaching for flexibility that isn't really needed here by making it
> work with any theoretical first layer that has a source address. I
> wanted to do the same thing for the payload, but that causes issues
> when the following layer with an address isn't the very next layer
> after Ether.

Makes sense to me! It's probably best to not to make the Ether
assumption regardless of whether or not it will likely always be
present.

>
> >
> > > +default_pkt_payload_src = IP().src if 
> > > hasattr(packet.payload, "src") else None
> > > +default_pkt_payload_dst = IP().dst if 
> > > hasattr(packet.payload, "dst") else None
> > > +# If `expected` is :data:`True`, the packet enters the TG 
> > > from SUT, otherwise the
> > > +# packet leaves the TG towards the SUT
> > >
> > > -# The packet is routed from TG egress to TG ingress
> > > -# update l3 addresses
> > > -packet.payload.src = self._tg_ip_address_egress.ip.exploded
> > > -packet.payload.dst = self._tg_ip_address_ingress.ip.exploded
> >
> > This is where it gets a little tricky. There will be circumstances,
> > albeit probably infrequently, where a user-created packet has more
> > than one IP layer, such as the ones I am using in the ipgre and nvgre
> > test suites that I am writing. In these cases, you need to specify an
> > index of the IP layer you want to modify, otherwise it will modify the
> > outermost IP layer in the packet (the IP layer outside the GRE layer.
> > See my previous comment for an example packet). Should be pretty easy
> > to fix, you just need to check if a packet contains an GRE layer, and
> > if it does, modify the packet by doing something like
> > packet[IP][1].src = self._tg_ip_address_egress.ip.exploded.
>
> I'm not as familiar with how GRE affects the packets, do you need to
> have the address on the inner IP layer at all times, or are you saying
> you need it on both IP layers?

Basically, GRE is a header that encapsulates a traditional packet.
Practically speaking, this means that a scapy packet with GRE will
look something like 'Ether() / IP() / GRE() / IP() / UDP() / Raw()'.
If you try to modify layer 3 addresses in the way the framework does
it now (packet.payload.src), and more than one IP layer is present in
a given packet, it will modify the the front-most IP layer (in this
case, the IP layer before the GRE layer is the packet I listed
before). If there are multiple IP layers, you can choose which layer
you want to modify by doing something like 'packet[IP][1] = address'
to modify the inner IP layer.

It is my understanding that GRE packets need to have an inner IP layer
as well as an outer IP layer. Here is a quick readup on what GRE is
(scroll to the bottom of the article and look at the diagram of a
regular datagram vs a GRE datagram as the rest of the article isn't
super important).

https://ipwithease.com/generic-routing-encapsulation-gre/


-Nicholas

[PATCH v2 0/2] bbdev: dump debug information

[Nicolas Chautru]

v2: updated with comments from Hemant and rebased.


v1: Hi Maxime. 

Adding new support to support troubleshooting. This provides
to the application an API to dump into file information
to help troubleshoot issue on a queue. Some of it is tracked
at bbdev level and some extra information can be tracked
as an option at PMD level. This is for 24.11. 
In practive logging is not enabled at run time, but information
can be dump into file when an issue happens and requires extra
information. This collates now multiple source of errors detected
notably at driver level made more explicit.

Thanks,
Nic


Nicolas Chautru (2):
  bbdev: add new function to dump debug information
  baseband/acc: improvement to logging mechanism

 drivers/baseband/acc/acc_common.h  |  37 +
 drivers/baseband/acc/rte_vrb_pmd.c | 128 +
 lib/bbdev/rte_bbdev.c  | 214 +
 lib/bbdev/rte_bbdev.h  |  41 ++
 lib/bbdev/rte_bbdev_pmd.h  |   9 ++
 lib/bbdev/version.map  |   4 +
 6 files changed, 406 insertions(+), 27 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] bbdev: add new function to dump debug information

[Nicolas Chautru]

This provides a new API to dump more debug information
related to the status on a given bbdev queue.
Some of this information is visible at bbdev level.
This also provides a new option dev op, to print more
information at the lower PMD level.
This helps user to troubleshoot issues related to
previous operations provided into a queue causing
possible hard-to-debug negative scenarios.

Signed-off-by: Nicolas Chautru 
---
 lib/bbdev/rte_bbdev.c | 214 ++
 lib/bbdev/rte_bbdev.h |  41 
 lib/bbdev/rte_bbdev_pmd.h |   9 ++
 lib/bbdev/version.map |   4 +
 4 files changed, 268 insertions(+)

diff --git a/lib/bbdev/rte_bbdev.c b/lib/bbdev/rte_bbdev.c
index 13bde3c25b..9087862c76 100644
--- a/lib/bbdev/rte_bbdev.c
+++ b/lib/bbdev/rte_bbdev.c
@@ -1190,3 +1190,217 @@ rte_bbdev_enqueue_status_str(enum 
rte_bbdev_enqueue_status status)
rte_bbdev_log(ERR, "Invalid enqueue status");
return NULL;
 }
+
+
+int
+rte_bbdev_queue_ops_dump(uint16_t dev_id, uint16_t queue_id, FILE *f)
+{
+   struct rte_bbdev_queue_data *q_data;
+   struct rte_bbdev_stats *stats;
+   uint16_t i;
+   struct rte_bbdev *dev = get_dev(dev_id);
+
+   VALID_DEV_OR_RET_ERR(dev, dev_id);
+   VALID_QUEUE_OR_RET_ERR(queue_id, dev);
+   VALID_DEV_OPS_OR_RET_ERR(dev, dev_id);
+   VALID_FUNC_OR_RET_ERR(dev->dev_ops->queue_ops_dump, dev_id);
+
+   q_data = &dev->data->queues[queue_id];
+
+   if (f == NULL)
+   return -EINVAL;
+
+   fprintf(f, "Dump of operations on %s queue %d\n",
+   dev->data->name, queue_id);
+   fprintf(f, "  Last Enqueue Status %s\n",
+   rte_bbdev_enqueue_status_str(q_data->enqueue_status));
+   for (i = 0; i < RTE_BBDEV_ENQ_STATUS_SIZE_MAX; i++)
+   if (q_data->queue_stats.enqueue_status_count[i] > 0)
+   fprintf(f, "  Enqueue Status Counters %s %" PRIu64 "\n",
+   rte_bbdev_enqueue_status_str(i),
+   
q_data->queue_stats.enqueue_status_count[i]);
+   stats = &dev->data->queues[queue_id].queue_stats;
+
+   fprintf(f, "  Enqueue Count %" PRIu64 " Warning %" PRIu64 " Error %" 
PRIu64 "\n",
+   stats->enqueued_count, stats->enqueue_warn_count,
+   stats->enqueue_err_count);
+   fprintf(f, "  Dequeue Count %" PRIu64 " Warning %" PRIu64 " Error %" 
PRIu64 "\n",
+   stats->dequeued_count, stats->dequeue_warn_count,
+   stats->dequeue_err_count);
+
+   return dev->dev_ops->queue_ops_dump(dev, queue_id, f);
+}
+
+char *
+rte_bbdev_ops_param_string(void *op, enum rte_bbdev_op_type op_type)
+{
+   static char str[1024];
+   static char partial[1024];
+   struct rte_bbdev_dec_op *op_dec;
+   struct rte_bbdev_enc_op *op_enc;
+   struct rte_bbdev_fft_op *op_fft;
+   struct rte_bbdev_mldts_op *op_mldts;
+
+   rte_iova_t add0 = 0, add1 = 0, add2 = 0, add3 = 0, add4 = 0;
+
+   if (op == NULL) {
+   snprintf(str, sizeof(str), "Invalid Operation pointer\n");
+   return str;
+   }
+
+   if (op_type == RTE_BBDEV_OP_LDPC_DEC) {
+   op_dec = op;
+   if (op_dec->ldpc_dec.code_block_mode == 
RTE_BBDEV_TRANSPORT_BLOCK)
+   snprintf(partial, sizeof(partial), "C %d Cab %d Ea %d 
Eb %d r %d",
+   op_dec->ldpc_dec.tb_params.c,
+   op_dec->ldpc_dec.tb_params.cab,
+   op_dec->ldpc_dec.tb_params.ea,
+   op_dec->ldpc_dec.tb_params.eb,
+   op_dec->ldpc_dec.tb_params.r);
+   else
+   snprintf(partial, sizeof(partial), "E %d", 
op_dec->ldpc_dec.cb_params.e);
+   if (op_dec->ldpc_dec.input.data != NULL)
+   add0 = 
rte_pktmbuf_iova_offset(op_dec->ldpc_dec.input.data, 0);
+   if (op_dec->ldpc_dec.hard_output.data != NULL)
+   add1 = 
rte_pktmbuf_iova_offset(op_dec->ldpc_dec.hard_output.data, 0);
+   if (op_dec->ldpc_dec.soft_output.data != NULL)
+   add2 = 
rte_pktmbuf_iova_offset(op_dec->ldpc_dec.soft_output.data, 0);
+   if (op_dec->ldpc_dec.harq_combined_input.data != NULL)
+   add3 = 
rte_pktmbuf_iova_offset(op_dec->ldpc_dec.harq_combined_input.data,
+   0);
+   if (op_dec->ldpc_dec.harq_combined_output.data != NULL)
+   add4 = 
rte_pktmbuf_iova_offset(op_dec->ldpc_dec.harq_combined_output.data,
+   0);
+   snprintf(str, sizeof(str), "op %x st %x BG %d Zc %d Ncb %d qm 
%d F %d Rv %d It %d It %d "
+   "HARQin %d in %" PRIx64 " ho %"

[PATCH v2 2/2] baseband/acc: improvement to logging mechanism

[Nicolas Chautru]

Support the new dev op to dump operations information
related to a given queue and information on previous errors
detected by the driver and tracked internally in PMD.

Signed-off-by: Nicolas Chautru 
---
 drivers/baseband/acc/acc_common.h  |  37 +
 drivers/baseband/acc/rte_vrb_pmd.c | 128 +++--
 2 files changed, 138 insertions(+), 27 deletions(-)

diff --git a/drivers/baseband/acc/acc_common.h 
b/drivers/baseband/acc/acc_common.h
index e249f37e38..c8914b23e0 100644
--- a/drivers/baseband/acc/acc_common.h
+++ b/drivers/baseband/acc/acc_common.h
@@ -149,6 +149,8 @@
 #define VRB2_VF_ID_SHIFT 6
 
 #define ACC_MAX_FFT_WIN  16
+#define ACC_MAX_LOGLEN256
+#define ACC_MAX_BUFFERLEN 256
 
 extern int acc_common_logtype;
 
@@ -646,8 +648,43 @@ struct __rte_cache_aligned acc_queue {
rte_iova_t fcw_ring_addr_iova;
int8_t *derm_buffer; /* interim buffer for de-rm in SDK */
struct acc_device *d;
+   char error_bufs[ACC_MAX_BUFFERLEN][ACC_MAX_LOGLEN]; /**< Buffer for 
error log. */
+   uint16_t error_head;  /**< Head - Buffer for error log. */
+   uint16_t  error_wrap; /**< Wrap Counter - Buffer for error log. */
 };
 
+/**
+ * @brief Report error both through RTE logging and into internal driver 
memory.
+ *
+ * This function is used to log an error for a specific ACC queue and 
operation.
+ *
+ * @param q   Pointer to the ACC queue.
+ * @param op  Pointer to the operation.
+ * @param fmt Format string for the error message.
+ * @param ... Additional arguments for the format string.
+ */
+__rte_format_printf(3, 4)
+static inline void
+acc_error_log(struct acc_queue *q, void *op, const char *fmt, ...)
+{
+   va_list args, args2;
+
+   va_start(args, fmt);
+   va_copy(args2, args);
+   rte_vlog(RTE_LOG_ERR, acc_common_logtype, fmt, args);
+   vsnprintf(q->error_bufs[q->error_head], ACC_MAX_LOGLEN, fmt, args2);
+   q->error_head++;
+   snprintf(q->error_bufs[q->error_head], ACC_MAX_LOGLEN,
+   "%s", rte_bbdev_ops_param_string(op, q->op_type));
+   q->error_head++;
+   if (q->error_head == ACC_MAX_LOGLEN) {
+   q->error_head = 0;
+   q->error_wrap++;
+   }
+   va_end(args);
+   va_end(args2);
+}
+
 /* Write to MMIO register address */
 static inline void
 mmio_write(void *addr, uint32_t value)
diff --git a/drivers/baseband/acc/rte_vrb_pmd.c 
b/drivers/baseband/acc/rte_vrb_pmd.c
index 585dc49bd6..9d0145d09b 100644
--- a/drivers/baseband/acc/rte_vrb_pmd.c
+++ b/drivers/baseband/acc/rte_vrb_pmd.c
@@ -1022,6 +1022,10 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
q->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base,
d->queue_offset(d->pf_device, q->vf_id, q->qgrp_id, 
q->aq_id));
 
+   /** initialize the error buffer. */
+   q->error_head = 0;
+   q->error_wrap = 0;
+
rte_bbdev_log_debug(
"Setup dev%u q%u: qgrp_id=%u, vf_id=%u, aq_id=%u, 
aq_depth=%u, mmio_reg_enqueue=%p base %p\n",
dev->data->dev_id, queue_id, q->qgrp_id, q->vf_id,
@@ -1434,6 +1438,74 @@ vrb_queue_intr_disable(struct rte_bbdev *dev, uint16_t 
queue_id)
return 0;
 }
 
+
+static int
+vrb_queue_ops_dump(struct rte_bbdev *dev, uint16_t queue_id, FILE *f)
+{
+   struct acc_queue *q = dev->data->queues[queue_id].queue_private;
+   struct rte_bbdev_dec_op *op;
+   uint16_t start_err, end_err, i, int_nb;
+   volatile union acc_info_ring_data *ring_data;
+   uint16_t info_ring_head = q->d->info_ring_head;
+
+   if (f == NULL) {
+   rte_bbdev_log(ERR, "Invalid File input");
+   return -EINVAL;
+   }
+
+   /** Print generic information on queue status. */
+   fprintf(f, "Dump of operations %s on Queue %d by %s\n",
+   rte_bbdev_op_type_str(q->op_type), queue_id, 
dev->device->driver->name);
+   fprintf(f, "AQ Enqueued %d Dequeued %d Depth %d - Available Enq %d 
Deq %d\n",
+   q->aq_enqueued, q->aq_dequeued, q->aq_depth,
+   acc_ring_avail_enq(q), acc_ring_avail_deq(q));
+
+   /** Print information captured in the error buffer. */
+   if (q->error_wrap == 0) {
+   start_err = 0;
+   end_err = q->error_head;
+   } else {
+   start_err = q->error_head;
+   end_err = q->error_head + ACC_MAX_BUFFERLEN;
+   }
+   fprintf(f, "Error Buffer - Head %d Wrap %d\n", q->error_head, 
q->error_wrap);
+   for (i = start_err; i < end_err; ++i)
+   fprintf(f, "  %d\t%s", i, q->error_bufs[i % ACC_MAX_BUFFERLEN]);
+
+   /** Print information captured in the info ring. */
+   if (q->d->info_ring != NULL) {
+   fprintf(f, "Info Ring Buffer - Head %d\n", 
q->d->info_ring_head);
+   ring_data = q->d->info_ring + (q->d->info_ring_head & 
ACC_INFO_RING_MASK);
+  

[PATCH 0/3] Increase the queue number of representor port

[Chaoyong He]

This patch series increase rxq/txq number of representor ports, aims to
increase the speed of slow path.

Long Wu (3):
  net/nfp: remove restrictions on port queue number
  net/nfp: increase representor port rxq number
  net/nfp: increase representor port txq number

 drivers/net/nfp/flower/nfp_flower.c   |  8 +--
 drivers/net/nfp/flower/nfp_flower.h   |  2 +-
 .../net/nfp/flower/nfp_flower_representor.c   | 59 +++
 .../net/nfp/flower/nfp_flower_representor.h   |  2 +-
 drivers/net/nfp/nfp_rxtx.c|  4 +-
 5 files changed, 40 insertions(+), 35 deletions(-)

-- 
2.39.1

[PATCH 1/3] net/nfp: remove restrictions on port queue number

[Chaoyong He]

From: Long Wu 

The flower firmware can support multi-queue for representor port now,
so remove restrictions on queue number of representor port.

Signed-off-by: Long Wu 
Reviewed-by: Chaoyong He 
Reviewed-by: Peng Zhang 
---
 drivers/net/nfp/flower/nfp_flower_representor.c | 12 ++--
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/net/nfp/flower/nfp_flower_representor.c 
b/drivers/net/nfp/flower/nfp_flower_representor.c
index b1589cf78c..130795357d 100644
--- a/drivers/net/nfp/flower/nfp_flower_representor.c
+++ b/drivers/net/nfp/flower/nfp_flower_representor.c
@@ -56,8 +56,8 @@ nfp_flower_repr_dev_infos_get(__rte_unused struct rte_eth_dev 
*dev,
pf_hw = repr->app_fw_flower->pf_hw;
 
/* Hardcoded pktlen and queues for now */
-   dev_info->max_rx_queues = 1;
-   dev_info->max_tx_queues = 1;
+   dev_info->max_rx_queues = (uint16_t)pf_hw->max_rx_queues;
+   dev_info->max_tx_queues = (uint16_t)pf_hw->max_tx_queues;
dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
dev_info->max_rx_pktlen = 9000;
 
@@ -581,10 +581,6 @@ nfp_flower_pf_repr_init(struct rte_eth_dev *eth_dev,
/* This backer port is that of the eth_device created for the PF vNIC */
eth_dev->data->backer_port_id = 0;
 
-   /* Only single queues for representor devices */
-   eth_dev->data->nb_rx_queues = 1;
-   eth_dev->data->nb_tx_queues = 1;
-
/* Allocating memory for mac addr */
eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", RTE_ETHER_ADDR_LEN, 
0);
if (eth_dev->data->mac_addrs == NULL) {
@@ -662,10 +658,6 @@ nfp_flower_repr_init(struct rte_eth_dev *eth_dev,
/* This backer port is that of the eth_device created for the PF vNIC */
eth_dev->data->backer_port_id = 0;
 
-   /* Only single queues for representor devices */
-   eth_dev->data->nb_rx_queues = 1;
-   eth_dev->data->nb_tx_queues = 1;
-
/* Allocating memory for mac addr */
eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", RTE_ETHER_ADDR_LEN, 
0);
if (eth_dev->data->mac_addrs == NULL) {
-- 
2.39.1

[PATCH 2/3] net/nfp: increase representor port rxq number

[Chaoyong He]

From: Long Wu 

This commit supports configuring multiple Rx queues for flower
representor port.

Signed-off-by: Long Wu 
Reviewed-by: Chaoyong He 
Reviewed-by: Peng Zhang 
---
 drivers/net/nfp/flower/nfp_flower.c   |  8 ++--
 drivers/net/nfp/flower/nfp_flower.h   |  2 +-
 .../net/nfp/flower/nfp_flower_representor.c   | 40 +--
 .../net/nfp/flower/nfp_flower_representor.h   |  2 +-
 drivers/net/nfp/nfp_rxtx.c|  4 +-
 5 files changed, 35 insertions(+), 21 deletions(-)

diff --git a/drivers/net/nfp/flower/nfp_flower.c 
b/drivers/net/nfp/flower/nfp_flower.c
index fa272790bc..8d781658ea 100644
--- a/drivers/net/nfp/flower/nfp_flower.c
+++ b/drivers/net/nfp/flower/nfp_flower.c
@@ -126,24 +126,24 @@ nfp_flower_get_repr(struct nfp_net_hw_priv *hw_priv,
 }
 
 bool
-nfp_flower_pf_dispatch_pkts(struct nfp_net_hw_priv *hw_priv,
+nfp_flower_pf_dispatch_pkts(struct nfp_net_rxq *rxq,
struct rte_mbuf *mbuf,
uint32_t port_id)
 {
struct nfp_flower_representor *repr;
 
-   repr = nfp_flower_get_repr(hw_priv, port_id);
+   repr = nfp_flower_get_repr(rxq->hw_priv, port_id);
if (repr == NULL) {
PMD_RX_LOG(ERR, "Can not get repr for port %u", port_id);
return false;
}
 
-   if (repr->ring == NULL) {
+   if (repr->ring == NULL || repr->ring[rxq->qidx] == NULL) {
PMD_RX_LOG(ERR, "No ring available for repr_port %s", 
repr->name);
return false;
}
 
-   if (rte_ring_enqueue(repr->ring, (void *)mbuf) != 0)
+   if (rte_ring_enqueue(repr->ring[rxq->qidx], (void *)mbuf) != 0)
return false;
 
return true;
diff --git a/drivers/net/nfp/flower/nfp_flower.h 
b/drivers/net/nfp/flower/nfp_flower.h
index b0d8fb0ed4..1dc868fb68 100644
--- a/drivers/net/nfp/flower/nfp_flower.h
+++ b/drivers/net/nfp/flower/nfp_flower.h
@@ -110,7 +110,7 @@ nfp_flower_support_decap_v2(const struct nfp_app_fw_flower 
*app_fw_flower)
 int nfp_init_app_fw_flower(struct nfp_net_hw_priv *hw_priv);
 void nfp_uninit_app_fw_flower(struct nfp_net_hw_priv *hw_priv);
 int nfp_secondary_init_app_fw_flower(struct nfp_net_hw_priv *hw_priv);
-bool nfp_flower_pf_dispatch_pkts(struct nfp_net_hw_priv *hw_priv,
+bool nfp_flower_pf_dispatch_pkts(struct nfp_net_rxq *rxq,
struct rte_mbuf *mbuf,
uint32_t port_id);
 uint16_t nfp_flower_pf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
diff --git a/drivers/net/nfp/flower/nfp_flower_representor.c 
b/drivers/net/nfp/flower/nfp_flower_representor.c
index 130795357d..96433b9f87 100644
--- a/drivers/net/nfp/flower/nfp_flower_representor.c
+++ b/drivers/net/nfp/flower/nfp_flower_representor.c
@@ -138,13 +138,14 @@ nfp_flower_repr_dev_stop(struct rte_eth_dev *dev)
 static int
 nfp_flower_repr_rx_queue_setup(struct rte_eth_dev *dev,
uint16_t rx_queue_id,
-   __rte_unused uint16_t nb_rx_desc,
+   uint16_t nb_rx_desc,
unsigned int socket_id,
__rte_unused const struct rte_eth_rxconf *rx_conf,
__rte_unused struct rte_mempool *mb_pool)
 {
struct nfp_net_rxq *rxq;
struct nfp_net_hw *pf_hw;
+   char ring_name[RTE_RING_NAMESIZE];
struct nfp_flower_representor *repr;
 
repr = dev->data->dev_private;
@@ -156,6 +157,15 @@ nfp_flower_repr_rx_queue_setup(struct rte_eth_dev *dev,
if (rxq == NULL)
return -ENOMEM;
 
+   snprintf(ring_name, sizeof(ring_name), "%s-%s-%u", repr->name, "Rx", 
rx_queue_id);
+   repr->ring[rx_queue_id] = rte_ring_create(ring_name, nb_rx_desc,
+   rte_socket_id(), 0);
+   if (repr->ring[rx_queue_id] == NULL) {
+   PMD_DRV_LOG(ERR, "rte_ring_create failed for rx queue %u", 
rx_queue_id);
+   rte_free(rxq);
+   return -ENOMEM;
+   }
+
rxq->hw = pf_hw;
rxq->qidx = rx_queue_id;
rxq->port_id = dev->data->port_id;
@@ -249,18 +259,18 @@ nfp_flower_repr_rx_burst(void *rx_queue,
 
dev = &rte_eth_devices[rxq->port_id];
repr = dev->data->dev_private;
-   if (unlikely(repr->ring == NULL)) {
+   if (unlikely(repr->ring == NULL) ||
+   unlikely(repr->ring[rxq->qidx] == NULL)) {
PMD_RX_LOG(ERR, "representor %s has no ring configured!",
repr->name);
return 0;
}
 
-   total_dequeue = rte_ring_dequeue_burst(repr->ring, (void *)rx_pkts,
-   nb_pkts, &available);
+   total_dequeue = rte_ring_dequeue_burst(repr->ring[rxq->qidx],
+   (void *)rx_pkts, nb_pkts, &available);
if (total_dequeue != 0) {
-   PMD_RX_LOG(DEBUG, "Representor Rx burst for %s, port_id: %#x, "
-   "received: %u, available: %u", repr->name,
-   repr->por

[PATCH 3/3] net/nfp: increase representor port txq number

[Chaoyong He]

From: Long Wu 

This commit supports configuring multiple Tx queues for flower
representor port.

Signed-off-by: Long Wu 
Reviewed-by: Chaoyong He 
Reviewed-by: Peng Zhang 
---
 drivers/net/nfp/flower/nfp_flower_representor.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/net/nfp/flower/nfp_flower_representor.c 
b/drivers/net/nfp/flower/nfp_flower_representor.c
index 96433b9f87..872b8a6db4 100644
--- a/drivers/net/nfp/flower/nfp_flower_representor.c
+++ b/drivers/net/nfp/flower/nfp_flower_representor.c
@@ -315,12 +315,11 @@ nfp_flower_repr_tx_burst(void *tx_queue,
/* This points to the PF vNIC that owns this representor */
dev = repr->app_fw_flower->pf_ethdev;
 
-   /* Only using Tx queue 0 for now. */
-   pf_tx_queue = dev->data->tx_queues[0];
+   pf_tx_queue = dev->data->tx_queues[txq->qidx];
sent = nfp_flower_pf_xmit_pkts(pf_tx_queue, tx_pkts, nb_pkts);
if (sent != 0) {
-   PMD_TX_LOG(DEBUG, "Representor Tx burst for %s, port_id: %#x 
transmitted: %hu",
-   repr->name, repr->port_id, sent);
+   PMD_TX_LOG(DEBUG, "Port: %#x transmitted: %hu queue: %u",
+   repr->port_id, sent, txq->qidx);
 
data_len = 0;
for (i = 0; i < sent; i++)
-- 
2.39.1

[PATCH 0/2] Support match flow rule Ethernet type field

[Chaoyong He]

This patch series add support of match flow rule Ethernet type field,
also do some needed refactor.

Long Wu (2):
  net/nfp: refactor flow item calculate function arguments
  net/nfp: flow rule supports match Ethernet type

 drivers/net/nfp/flower/nfp_flower_cmsg.h | 14 +
 drivers/net/nfp/flower/nfp_flower_flow.c | 78 ++--
 2 files changed, 74 insertions(+), 18 deletions(-)

-- 
2.39.1

[PATCH 1/2] net/nfp: refactor flow item calculate function arguments

[Chaoyong He]

From: Long Wu 

Refactor the flow item calculate function, unify the arguments
of item check and calculate function, make the Ethernet item
calculate function more readable.

Signed-off-by: Long Wu 
Reviewed-by: Chaoyong He 
---
 drivers/net/nfp/flower/nfp_flower_flow.c | 46 ++--
 1 file changed, 27 insertions(+), 19 deletions(-)

diff --git a/drivers/net/nfp/flower/nfp_flower_flow.c 
b/drivers/net/nfp/flower/nfp_flower_flow.c
index 0078455658..50b0742b18 100644
--- a/drivers/net/nfp/flower/nfp_flower_flow.c
+++ b/drivers/net/nfp/flower/nfp_flower_flow.c
@@ -1044,14 +1044,14 @@ static nfp_flow_key_check_item_fn check_item_fns[] = {
 };
 
 static int
-nfp_flow_key_layers_check_items(const struct rte_flow_item items[])
+nfp_flow_key_layers_check_items(const struct rte_flow_item items[],
+   struct nfp_item_calculate_param *param)
 {
int ret;
struct nfp_item_flag flag = {};
const struct rte_flow_item *item;
-   struct nfp_item_calculate_param param = {
-   .flag = &flag,
-   };
+
+   param->flag = &flag;
 
for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; ++item) {
if (item->type >= RTE_DIM(check_item_fns)) {
@@ -1062,8 +1062,8 @@ nfp_flow_key_layers_check_items(const struct 
rte_flow_item items[])
if (check_item_fns[item->type] == NULL)
continue;
 
-   param.item = item;
-   ret = check_item_fns[item->type](¶m);
+   param->item = item;
+   ret = check_item_fns[item->type](param);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Flow item %d check fail", item->type);
return ret;
@@ -1081,10 +1081,17 @@ nfp_flow_item_calculate_stub(struct 
nfp_item_calculate_param *param __rte_unused
 static void
 nfp_flow_item_calculate_eth(struct nfp_item_calculate_param *param)
 {
-   if (param->item->spec != NULL) {
-   param->key_ls->key_layer |= NFP_FLOWER_LAYER_MAC;
-   param->key_ls->key_size += sizeof(struct nfp_flower_mac_mpls);
-   }
+   struct nfp_fl_key_ls *key_ls;
+   const struct rte_flow_item_eth *spec;
+
+   spec = param->item->spec;
+   if (spec == NULL)
+   return;
+
+   key_ls = param->key_ls;
+
+   key_ls->key_layer |= NFP_FLOWER_LAYER_MAC;
+   key_ls->key_size += sizeof(struct nfp_flower_mac_mpls);
 }
 
 static void
@@ -1238,14 +1245,12 @@ static nfp_flow_key_calculate_item_fn item_fns[] = {
 
 static int
 nfp_flow_key_layers_calculate_items(const struct rte_flow_item items[],
-   struct nfp_fl_key_ls *key_ls)
+   struct nfp_item_calculate_param *param)
 {
struct nfp_item_flag flag = {};
const struct rte_flow_item *item;
-   struct nfp_item_calculate_param param = {
-   .key_ls = key_ls,
-   .flag = &flag,
-   };
+
+   param->flag = &flag;
 
for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; ++item) {
if (item->type >= RTE_DIM(item_fns) || item_fns[item->type] == 
NULL) {
@@ -1253,8 +1258,8 @@ nfp_flow_key_layers_calculate_items(const struct 
rte_flow_item items[],
return -ERANGE;
}
 
-   param.item = item;
-   item_fns[item->type](¶m);
+   param->item = item;
+   item_fns[item->type](param);
}
 
return 0;
@@ -1799,6 +1804,7 @@ nfp_flow_key_layers_calculate(struct rte_eth_dev *dev,
struct nfp_fl_key_ls *key_ls)
 {
int ret;
+   struct nfp_item_calculate_param param = {};
 
key_ls->key_layer_two = 0;
key_ls->key_layer = NFP_FLOWER_LAYER_PORT;
@@ -1809,13 +1815,15 @@ nfp_flow_key_layers_calculate(struct rte_eth_dev *dev,
key_ls->vlan = 0;
key_ls->tun_type = NFP_FL_TUN_NONE;
 
-   ret = nfp_flow_key_layers_check_items(items);
+   param.key_ls = key_ls;
+
+   ret = nfp_flow_key_layers_check_items(items, ¶m);
if (ret != 0) {
PMD_DRV_LOG(ERR, "flow items check failed");
return ret;
}
 
-   ret = nfp_flow_key_layers_calculate_items(items, key_ls);
+   ret = nfp_flow_key_layers_calculate_items(items, ¶m);
if (ret != 0) {
PMD_DRV_LOG(ERR, "flow items calculate failed");
return ret;
-- 
2.39.1

[PATCH 2/2] net/nfp: flow rule supports match Ethernet type

[Chaoyong He]

From: Long Wu 

Add the support of match ethernet type item when
using flower firmware, with a limit that it can
only be used alone.

Signed-off-by: Long Wu 
Reviewed-by: Chaoyong He 
---
 drivers/net/nfp/flower/nfp_flower_cmsg.h | 14 ++
 drivers/net/nfp/flower/nfp_flower_flow.c | 34 
 2 files changed, 48 insertions(+)

diff --git a/drivers/net/nfp/flower/nfp_flower_cmsg.h 
b/drivers/net/nfp/flower/nfp_flower_cmsg.h
index 5d23227c24..5fc4210d8b 100644
--- a/drivers/net/nfp/flower/nfp_flower_cmsg.h
+++ b/drivers/net/nfp/flower/nfp_flower_cmsg.h
@@ -708,6 +708,20 @@ struct nfp_flower_ipv6_gre_tun {
rte_be32_t reserved2;
 };
 
+/*
+ * L3 other (1W/4B)
+ *3   2   1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |reserved   |   ethertype   |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * Note: This is only used when no specific L3 header available.
+ */
+struct nfp_flower_l3_other {
+   rte_be16_t reserved;
+   rte_be16_t ethertype;
+};
+
 struct nfp_fl_act_head {
uint8_t jump_id;
uint8_t len_lw;
diff --git a/drivers/net/nfp/flower/nfp_flower_flow.c 
b/drivers/net/nfp/flower/nfp_flower_flow.c
index 50b0742b18..21a53eab68 100644
--- a/drivers/net/nfp/flower/nfp_flower_flow.c
+++ b/drivers/net/nfp/flower/nfp_flower_flow.c
@@ -26,6 +26,7 @@
 #define NFP_FLOWER_LAYER_VXLAN  RTE_BIT32(7)
 
 #define NFP_FLOWER_LAYER2_GRE   RTE_BIT32(0)
+#define NFP_FLOWER_LAYER2_L3_OTHER  RTE_BIT32(3)
 #define NFP_FLOWER_LAYER2_QINQ  RTE_BIT32(4)
 #define NFP_FLOWER_LAYER2_GENEVERTE_BIT32(5)
 #define NFP_FLOWER_LAYER2_GENEVE_OP RTE_BIT32(6)
@@ -962,10 +963,15 @@ struct nfp_item_flag {
bool outer_ip6_flag;
 };
 
+struct nfp_item_shared_flag {
+   bool l3_other_flag;
+};
+
 struct nfp_item_calculate_param {
const struct rte_flow_item *item;
struct nfp_fl_key_ls *key_ls;
struct nfp_item_flag *flag;
+   struct nfp_item_shared_flag shared_flag;
 };
 
 typedef int (*nfp_flow_key_check_item_fn)(struct nfp_item_calculate_param 
*param);
@@ -1068,6 +1074,9 @@ nfp_flow_key_layers_check_items(const struct 
rte_flow_item items[],
PMD_DRV_LOG(ERR, "Flow item %d check fail", item->type);
return ret;
}
+
+   if (item->type != RTE_FLOW_ITEM_TYPE_ETH)
+   param->shared_flag.l3_other_flag = true;
}
 
return 0;
@@ -1092,6 +1101,13 @@ nfp_flow_item_calculate_eth(struct 
nfp_item_calculate_param *param)
 
key_ls->key_layer |= NFP_FLOWER_LAYER_MAC;
key_ls->key_size += sizeof(struct nfp_flower_mac_mpls);
+
+   if (!param->shared_flag.l3_other_flag && spec->type != 0) {
+   key_ls->key_layer |= NFP_FLOWER_LAYER_EXT_META;
+   key_ls->key_size += sizeof(struct nfp_flower_ext_meta);
+   key_ls->key_layer_two |= NFP_FLOWER_LAYER2_L3_OTHER;
+   key_ls->key_size += sizeof(struct nfp_flower_l3_other);
+   }
 }
 
 static void
@@ -1873,6 +1889,9 @@ nfp_flow_merge_eth(struct nfp_flow_merge_param *param)
const struct rte_flow_item *item;
const struct rte_flow_item_eth *spec;
const struct rte_flow_item_eth *mask;
+   struct nfp_flower_l3_other *l3_other;
+   struct nfp_flower_meta_tci *meta_tci;
+   struct nfp_flower_ext_meta *ext_meta = NULL;
 
item = param->item;
spec = item->spec;
@@ -1895,6 +1914,21 @@ nfp_flow_merge_eth(struct nfp_flow_merge_param *param)
eth->mpls_lse = 0;
*param->mbuf_off += sizeof(struct nfp_flower_mac_mpls);
 
+   meta_tci = (struct nfp_flower_meta_tci 
*)param->nfp_flow->payload.unmasked_data;
+   if ((meta_tci->nfp_flow_key_layer & NFP_FLOWER_LAYER_EXT_META) != 0)
+   ext_meta = (struct nfp_flower_ext_meta *)(meta_tci + 1);
+
+   if (ext_meta != NULL &&
+   (ext_meta->nfp_flow_key_layer2 & 
NFP_FLOWER_LAYER2_L3_OTHER) != 0) {
+   l3_other = (void *)(*param->mbuf_off);
+   if (param->is_mask)
+   l3_other->ethertype = mask->type;
+   else
+   l3_other->ethertype = spec->type;
+
+   *param->mbuf_off += sizeof(struct nfp_flower_l3_other);
+   }
+
 eth_end:
return 0;
 }
-- 
2.39.1

Re: [PATCH v2] bus/pci: don't open uio device in secondary process

[Chenbo Xia]

> On Aug 29, 2024, at 16:57, Konrad Sztyber  wrote:
> 
> External email: Use caution opening links or attachments
> 
> 
> The uio_pci_generic driver clears the bus master bit when the device
> file is closed. So, when the secondary process terminates after probing
> a device, that device becomes unusable in the primary process.
> 
> To avoid that, the device file is now opened only in the primary
> process. The commit that introduced this regression, 847d78fb9530
> ("bus/pci: fix FD in secondary process"), only mentioned enabling access
> to config space from secondary process, which still works, as it doesn't
> rely on the device file.
> 
> Fixes: 847d78fb9530 ("bus/pci: fix FD in secondary process")
> Cc: sta...@dpdk.org
> 
> Signed-off-by: Konrad Sztyber 
> ---
> drivers/bus/pci/linux/pci_uio.c | 27 +++
> 1 file changed, 15 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c
> index 4c1d3327a9..5c4ba8098c 100644
> --- a/drivers/bus/pci/linux/pci_uio.c
> +++ b/drivers/bus/pci/linux/pci_uio.c
> @@ -232,18 +232,6 @@ pci_uio_alloc_resource(struct rte_pci_device *dev,
>   loc->domain, loc->bus, loc->devid, loc->function);
>   return 1;
>   }
> -   snprintf(devname, sizeof(devname), "/dev/uio%u", uio_num);
> -
> -   /* save fd */
> -   fd = open(devname, O_RDWR);
> -   if (fd < 0) {
> -   PCI_LOG(ERR, "Cannot open %s: %s", devname, strerror(errno));
> -   goto error;
> -   }
> -
> -   if (rte_intr_fd_set(dev->intr_handle, fd))
> -   goto error;
> -
>   snprintf(cfgname, sizeof(cfgname),
>   "/sys/class/uio/uio%u/device/config", uio_num);
> 
> @@ -273,6 +261,21 @@ pci_uio_alloc_resource(struct rte_pci_device *dev,
>   if (rte_eal_process_type() != RTE_PROC_PRIMARY)
>   return 0;
> 
> +   /*
> +* the uio_pci_generic driver clears the bus master enable bit when 
> the device file is
> +* closed, so open it only in the primary process
> +*/
> +   snprintf(devname, sizeof(devname), "/dev/uio%u", uio_num);
> +   /* save fd */
> +   fd = open(devname, O_RDWR);
> +   if (fd < 0) {
> +   PCI_LOG(ERR, "Cannot open %s: %s", devname, strerror(errno));
> +   goto error;
> +   }
> +
> +   if (rte_intr_fd_set(dev->intr_handle, fd))
> +   goto error;
> +
>   /* allocate the mapping details for secondary processes*/
>   *uio_res = rte_zmalloc("UIO_RES", sizeof(**uio_res), 0);
>   if (*uio_res == NULL) {
> --
> 2.45.0
> 

Reviewed-by: Chenbo Xia 

v4_acl lookup failed after rte_pktmbuf_adj in dpdk pipeline

[Balakrishnan K]

Hi All,
I using dpdk pipeline and performing table lookup to decide the packet 
forwarding.
One of my use case v4_acl lookup failing could not find the reason.

Scenario:
pipeline test_pipe1 table match v4_acl ipv4 offset 274 size 1K action test.

Acl table offset is set to 274. In coming packets contains vlan header.
When normal packet received src and ds tip matching according  to the rules I 
pushed into the table.
Packets with GRE header and outer ip header src and dst ip also matching.

I wanted to do lookup for inner IP header src and dst fields , to achieve this 
used rte_pktmbuf_adj to remove the gre and outer ip header.
Again I placed eth_header and vlan header at the start position.

Code snippet:

rte_memcpy(&temp_hdr, eth_header,
(sizeof(struct rte_ether_hdr) + sizeof(struct 
rte_vlan_hdr) +
 sizeof(struct rte_ipv4_hdr) +
 sizeof(gre_hdr_t)));

rte_pktmbuf_adj (mb, (sizeof(struct rte_ether_hdr) + 
sizeof(struct rte_vlan_hdr) +
sizeof(struct rte_ipv4_hdr) +
sizeof(gre_hdr_t)));
rte_pktmbuf_prepend (mb,
sizeof (struct rte_ether_hdr) + sizeof(struct 
rte_vlan_hdr) );
pkt = rte_pktmbuf_mtod(mb, uint8_t *);

rte_memcpy (pkt, &temp_hdr,
sizeof(struct rte_ether_hdr) + sizeof(struct 
rte_vlan_hdr) ) ;
ip = (struct rte_ipv4_hdr*) (pkt + sizeof(struct rte_ether_hdr) 
+ sizeof(struct rte_vlan_hdr));


My expectation is inner header lookup will work because now I moved the inner 
header in place of outer header position.
But lookup failed could not find the reason for failure.

Could any one help on this to solve the issue.

Why the table offset is set to 274 to match the IP header fields?
Is mbuf ip header will be at offset 274 always, I know mbuf headroom is 128 
byte long
Could any one explain point me the document to refer the offset calculation for 
mbuf and acl table?


Regards,
Bala

[PATCH v3 2/8] zsda: add support for zsdadev operations

[Hanxiao Li]

Add support for zsdadev operations such as dev_start and dev_stop.

Signed-off-by: Hanxiao Li 
---
 drivers/common/zsda/zsda_device.c | 476 ++
 drivers/common/zsda/zsda_device.h | 103 +++
 2 files changed, 579 insertions(+)
 create mode 100644 drivers/common/zsda/zsda_device.c
 create mode 100644 drivers/common/zsda/zsda_device.h

diff --git a/drivers/common/zsda/zsda_device.c 
b/drivers/common/zsda/zsda_device.c
new file mode 100644
index 00..de8894f5a3
--- /dev/null
+++ b/drivers/common/zsda/zsda_device.c
@@ -0,0 +1,476 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 ZTE Corporation
+ */
+
+
+#include 
+#include 
+
+#include "zsda_device.h"
+
+/* per-process array of device data */
+struct zsda_device_info zsda_devs[RTE_PMD_ZSDA_MAX_PCI_DEVICES];
+static int zsda_nb_pci_devices;
+uint8_t zsda_num_used_qps;
+
+/*
+ * The set of PCI devices this driver supports
+ */
+static const struct rte_pci_id pci_id_zsda_map[] = {
+   {
+   RTE_PCI_DEVICE(0x1cf2, 0x8050),
+   },
+   {
+   RTE_PCI_DEVICE(0x1cf2, 0x8051),
+   },
+   {.device_id = 0},
+};
+
+static int
+zsda_check_write(uint8_t *addr, const uint32_t dst_value)
+{
+   int times = ZSDA_TIME_NUM;
+   uint32_t val;
+
+   val = ZSDA_CSR_READ32(addr);
+
+   while ((val != dst_value) && times--) {
+   val = ZSDA_CSR_READ32(addr);
+   rte_delay_us_sleep(ZSDA_TIME_SLEEP_US);
+   }
+   if (val == dst_value)
+   return ZSDA_SUCCESS;
+   else
+   return ZSDA_FAILED;
+}
+
+static uint8_t
+zsda_get_num_used_qps(const struct rte_pci_device *pci_dev)
+{
+   uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+   uint8_t num_used_qps;
+
+   num_used_qps = ZSDA_CSR_READ8(mmio_base + 0);
+
+   return num_used_qps;
+}
+
+int
+zsda_admin_q_start(const struct rte_pci_device *pci_dev)
+{
+   uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+   int ret = 0;
+
+   ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_START, 0);
+
+   ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_START, ZSDA_Q_START);
+   ret = zsda_check_write(mmio_base + ZSDA_ADMIN_Q_START, ZSDA_Q_START);
+
+   return ret;
+}
+
+int
+zsda_admin_q_stop(const struct rte_pci_device *pci_dev)
+{
+   uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+   int ret = 0;
+
+   ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_STOP_RESP, ZSDA_RESP_INVALID);
+   ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_STOP, ZSDA_Q_STOP);
+
+   ret = zsda_check_write(mmio_base + ZSDA_ADMIN_Q_STOP_RESP,
+  ZSDA_RESP_VALID);
+
+   if (ret)
+   ZSDA_LOG(INFO, "Failed! zsda_admin q stop");
+
+   return ret;
+}
+
+int
+zsda_admin_q_clear(const struct rte_pci_device *pci_dev)
+{
+   uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+   int ret = 0;
+
+   ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_CLR_RESP, ZSDA_RESP_INVALID);
+   ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_CLR, ZSDA_RESP_VALID);
+
+   ret = zsda_check_write(mmio_base + ZSDA_ADMIN_Q_CLR_RESP,
+  ZSDA_RESP_VALID);
+
+   if (ret)
+   ZSDA_LOG(INFO, "Failed! zsda_admin q clear");
+
+   return ret;
+}
+
+static int
+zsda_queue_stop_single(uint8_t *mmio_base, const uint8_t id)
+{
+   int ret = 0;
+   uint8_t *addr_stop = mmio_base + ZSDA_IO_Q_STOP + (4 * id);
+   uint8_t *addr_resp = mmio_base + ZSDA_IO_Q_STOP_RESP + (4 * id);
+
+   ZSDA_CSR_WRITE32(addr_resp, ZSDA_RESP_INVALID);
+   ZSDA_CSR_WRITE32(addr_stop, ZSDA_Q_STOP);
+
+   ret = zsda_check_write(addr_resp, ZSDA_RESP_VALID);
+   ZSDA_CSR_WRITE32(addr_resp, ZSDA_RESP_INVALID);
+
+   return ret;
+}
+
+int
+zsda_queue_stop(const struct rte_pci_device *pci_dev)
+{
+   uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+   uint8_t id;
+   int ret = 0;
+
+   for (id = 0; id < zsda_num_used_qps; id++)
+   ret |= zsda_queue_stop_single(mmio_base, id);
+
+   return ret;
+}
+
+static int
+zsda_queue_start_single(uint8_t *mmio_base, const uint8_t id)
+{
+   uint8_t *addr_start = mmio_base + ZSDA_IO_Q_START + (4 * id);
+
+   ZSDA_CSR_WRITE32(addr_start, ZSDA_Q_START);
+   return zsda_check_write(addr_start, ZSDA_Q_START);
+}
+
+int
+zsda_queue_start(const struct rte_pci_device *pci_dev)
+{
+   uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+   uint8_t id;
+   int ret = 0;
+
+   for (id = 0; id < zsda_num_used_qps; id++)
+   ret |= zsda_queue_start_single(mmio_base, id);
+
+   return ret;
+}
+
+static int
+zsda_queue_clear_single(uint8_t *mmio_base, const uint8_t id)
+{
+   int ret = 0;
+   uint8_t *addr_clear = mmio_base + ZSDA_IO_Q_CLR + (4 * id);
+   uint8_t *addr_resp = mmio_base + ZSDA_IO_Q_CLR_RESP + (4 * id);
+
+   ZSDA_CSR_WRITE32(addr_resp, ZSDA_RESP_INVALID);
+   ZSDA_C

[PATCH v3 4/8] zsda: add zsda compressdev driver and interface

[Hanxiao Li]

Add zsda compressdev driver and enqueue, dequeue interface.

Signed-off-by: Hanxiao Li 
---
 drivers/compress/zsda/zsda_comp.c | 320 ++
 drivers/compress/zsda/zsda_comp.h |  27 ++
 drivers/compress/zsda/zsda_comp_pmd.c | 453 ++
 drivers/compress/zsda/zsda_comp_pmd.h |  39 +++
 drivers/meson.build   |   1 +
 5 files changed, 840 insertions(+)
 create mode 100644 drivers/compress/zsda/zsda_comp.c
 create mode 100644 drivers/compress/zsda/zsda_comp.h
 create mode 100644 drivers/compress/zsda/zsda_comp_pmd.c
 create mode 100644 drivers/compress/zsda/zsda_comp_pmd.h

diff --git a/drivers/compress/zsda/zsda_comp.c 
b/drivers/compress/zsda/zsda_comp.c
new file mode 100644
index 00..0429c02855
--- /dev/null
+++ b/drivers/compress/zsda/zsda_comp.c
@@ -0,0 +1,320 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 ZTE Corporation
+ */
+
+#include "zsda_comp.h"
+
+#include 
+
+#define ZLIB_HEADER_SIZE 2
+#define ZLIB_TRAILER_SIZE 4
+#define GZIP_HEADER_SIZE 10
+#define GZIP_TRAILER_SIZE 8
+#define CHECKSUM_SIZE 4
+
+static uint32_t zsda_read_chksum(uint8_t *data_addr, uint8_t op_code,
+uint32_t produced);
+
+int
+zsda_comp_match(const void *op_in)
+{
+   const struct rte_comp_op *op = (const struct rte_comp_op *)op_in;
+   const struct zsda_comp_xform *xform =
+   (struct zsda_comp_xform *)op->private_xform;
+
+   if (op->op_type != RTE_COMP_OP_STATELESS)
+   return 0;
+
+   if (xform->type != RTE_COMP_COMPRESS)
+   return 0;
+
+   return 1;
+}
+
+static uint8_t
+get_opcode(const struct zsda_comp_xform *xform)
+{
+   if (xform->type == RTE_COMP_COMPRESS) {
+   if (xform->checksum_type == RTE_COMP_CHECKSUM_NONE ||
+   xform->checksum_type == RTE_COMP_CHECKSUM_CRC32)
+   return ZSDA_OPC_COMP_GZIP;
+   else if (xform->checksum_type == RTE_COMP_CHECKSUM_ADLER32)
+   return ZSDA_OPC_COMP_ZLIB;
+   }
+   if (xform->type == RTE_COMP_DECOMPRESS) {
+   if (xform->checksum_type == RTE_COMP_CHECKSUM_CRC32 ||
+   xform->checksum_type == RTE_COMP_CHECKSUM_NONE)
+   return ZSDA_OPC_DECOMP_GZIP;
+   else if (xform->checksum_type == RTE_COMP_CHECKSUM_ADLER32)
+   return ZSDA_OPC_DECOMP_ZLIB;
+   }
+
+   return ZSDA_OPC_INVALID;
+}
+
+int
+zsda_build_comp_request(void *op_in, const struct zsda_queue *queue,
+  void **op_cookies, const uint16_t new_tail)
+{
+   struct rte_comp_op *op = op_in;
+   struct zsda_comp_xform *xform =
+   (struct zsda_comp_xform *)op->private_xform;
+   struct zsda_wqe_comp *wqe =
+   (struct zsda_wqe_comp *)(queue->base_addr +
+(new_tail * queue->msg_size));
+
+   struct zsda_op_cookie *cookie =
+   (struct zsda_op_cookie *)op_cookies[new_tail];
+   struct zsda_sgl *sgl_src = (struct zsda_sgl *)&cookie->sgl_src;
+   struct zsda_sgl *sgl_dst = (struct zsda_sgl *)&cookie->sgl_dst;
+   struct comp_head_info comp_head_info;
+
+   uint8_t opcode;
+   int ret = 0;
+   uint32_t op_offset;
+   uint32_t op_src_len;
+   uint32_t op_dst_len;
+   uint32_t head_len;
+
+   if ((op->m_dst == NULL) || (op->m_dst == op->m_src)) {
+   ZSDA_LOG(ERR, "Failed! m_dst");
+   return -EINVAL;
+   }
+
+   opcode = get_opcode(xform);
+   if (opcode == ZSDA_OPC_INVALID) {
+   ZSDA_LOG(ERR, E_CONFIG);
+   return -EINVAL;
+   }
+
+   cookie->used = true;
+   cookie->sid = new_tail;
+   cookie->op = op;
+
+   if (opcode == ZSDA_OPC_COMP_GZIP)
+   head_len = GZIP_HEADER_SIZE;
+   else if (opcode == ZSDA_OPC_COMP_ZLIB)
+   head_len = ZLIB_HEADER_SIZE;
+   else {
+   ZSDA_LOG(ERR, "Comp, op_code error!");
+   return -EINVAL;
+   }
+
+   comp_head_info.head_len = head_len;
+   comp_head_info.head_phys_addr = cookie->comp_head_phys_addr;
+
+   op_offset = op->src.offset;
+   op_src_len = op->src.length;
+   ret = zsda_fill_sgl(op->m_src, op_offset, sgl_src,
+  cookie->sgl_src_phys_addr, op_src_len, NULL);
+
+   op_offset = op->dst.offset;
+   op_dst_len = op->m_dst->pkt_len - op_offset;
+   op_dst_len += head_len;
+   ret |= zsda_fill_sgl(op->m_dst, op_offset, sgl_dst,
+   cookie->sgl_dst_phys_addr, op_dst_len,
+   &comp_head_info);
+
+   if (ret) {
+   ZSDA_LOG(ERR, E_FUNC);
+   return ret;
+   }
+
+   memset(wqe, 0, sizeof(struct zsda_wqe_comp));
+   wqe->rx_length = op_src_len;
+   wqe->tx_length = op_dst_len;
+   wqe->valid

[PATCH v3 5/8] zsda: modify files for introducing zsda cryptodev

[Hanxiao Li]

It is necessary to make necessary modifications to
existing files based on the newly introduced content

Signed-off-by: Hanxiao Li 
---
 MAINTAINERS   |  3 ++
 drivers/common/zsda/zsda_common.h | 50 +
 drivers/common/zsda/zsda_device.c | 54 +--
 drivers/common/zsda/zsda_device.h | 20 +++--
 drivers/common/zsda/zsda_qp.c | 72 +--
 lib/cryptodev/rte_crypto_sym.h|  4 +-
 6 files changed, 151 insertions(+), 52 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index ea245fc61b..9e66c72c45 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1221,6 +1221,9 @@ F: drivers/crypto/virtio/
 F: doc/guides/cryptodevs/virtio.rst
 F: doc/guides/cryptodevs/features/virtio.ini
 
+ZTE Storage Data Accelerator
+M: Hanxiao Li 
+F: drivers/crypto/zsda/
 
 Compression Drivers
 ---
diff --git a/drivers/common/zsda/zsda_common.h 
b/drivers/common/zsda/zsda_common.h
index 5a89244119..119676790e 100644
--- a/drivers/common/zsda/zsda_common.h
+++ b/drivers/common/zsda/zsda_common.h
@@ -97,17 +97,39 @@
 enum zsda_service_type {
ZSDA_SERVICE_COMPRESSION = 0,
ZSDA_SERVICE_DECOMPRESSION,
+   ZSDA_SERVICE_SYMMETRIC_ENCRYPT,
+   ZSDA_SERVICE_SYMMETRIC_DECRYPT,
+   ZSDA_SERVICE_HASH_ENCODE = 6,
ZSDA_SERVICE_INVALID,
 };
 
 #define ZSDA_MAX_SERVICES (ZSDA_SERVICE_INVALID)
 
+#define ZSDA_OPC_EC_AES_XTS_256 0x0  /* Encry AES-XTS-256 */
+#define ZSDA_OPC_EC_AES_XTS_512 0x01 /* Encry AES-XTS-512 */
+#define ZSDA_OPC_EC_SM4_XTS_256 0x02 /* Encry SM4-XTS-256 */
+#define ZSDA_OPC_DC_AES_XTS_256 0x08 /* Decry AES-XTS-256 */
+#define ZSDA_OPC_DC_AES_XTS_512 0x09 /* Decry AES-XTS-512 */
+#define ZSDA_OPC_DC_SM4_XTS_256 0x0A /* Decry SM4-XTS-256 */
 #define ZSDA_OPC_COMP_GZIP 0x10 /* Encomp deflate-Gzip */
 #define ZSDA_OPC_COMP_ZLIB 0x11 /* Encomp deflate-Zlib */
 #define ZSDA_OPC_DECOMP_GZIP   0x18 /* Decompinfalte-Gzip */
 #define ZSDA_OPC_DECOMP_ZLIB   0x19 /* Decompinfalte-Zlib */
+#define ZSDA_OPC_HASH_SHA1 0x20 /* Hash-SHA1 */
+#define ZSDA_OPC_HASH_SHA2_224 0x21 /* Hash-SHA2-224 */
+#define ZSDA_OPC_HASH_SHA2_256 0x22 /* Hash-SHA2-256 */
+#define ZSDA_OPC_HASH_SHA2_384 0x23 /* Hash-SHA2-384 */
+#define ZSDA_OPC_HASH_SHA2_512 0x24 /* Hash-SHA2-512 */
+#define ZSDA_OPC_HASH_SM3  0x25 /* Hash-SM3 */
 #define ZSDA_OPC_INVALID   0xff
 
+#define ZSDA_DIGEST_SIZE_SHA1(20)
+#define ZSDA_DIGEST_SIZE_SHA2_224 (28)
+#define ZSDA_DIGEST_SIZE_SHA2_256 (32)
+#define ZSDA_DIGEST_SIZE_SHA2_384 (48)
+#define ZSDA_DIGEST_SIZE_SHA2_512 (64)
+#define ZSDA_DIGEST_SIZE_SM3 (32)
+
 #define SET_CYCLE0xff
 #define SET_HEAD_INTI0x0
 
@@ -237,9 +259,34 @@ struct zsda_op_cookie {
uint8_t comp_head[COMP_REMOVE_SPACE_LEN];
 } __rte_packed;
 
+#define ZSDA_CIPHER_KEY_MAX_LEN 64
+struct crypto_cfg {
+   uint8_t slba_L[8];
+   uint8_t key[ZSDA_CIPHER_KEY_MAX_LEN];
+   uint8_t lbads : 4;
+   uint8_t resv1 : 4;
+   uint8_t resv2[7];
+   uint8_t slba_H[8];
+   uint8_t resv3[8];
+} __rte_packed;
+
 struct compress_cfg {
 } __rte_packed;
 
+struct zsda_wqe_crpt {
+   uint8_t valid;
+   uint8_t op_code;
+   uint16_t sid;
+   uint8_t resv[3];
+   uint8_t rx_sgl_type : 4;
+   uint8_t tx_sgl_type : 4;
+   uint64_t rx_addr;
+   uint32_t rx_length;
+   uint64_t tx_addr;
+   uint32_t tx_length;
+   struct crypto_cfg cfg;
+} __rte_packed;
+
 struct zsda_wqe_comp {
uint8_t valid;
uint8_t op_code;
@@ -281,6 +328,9 @@ struct zsda_common_stat {
 enum zsda_algo_core {
ZSDA_CORE_COMP,
ZSDA_CORE_DECOMP,
+   ZSDA_CORE_ENCRY,
+   ZSDA_CORE_DECRY,
+   ZSDA_CORE_HASH,
ZSDA_CORE_INVALID,
 };
 
diff --git a/drivers/common/zsda/zsda_device.c 
b/drivers/common/zsda/zsda_device.c
index de8894f5a3..4a855ddf03 100644
--- a/drivers/common/zsda/zsda_device.c
+++ b/drivers/common/zsda/zsda_device.c
@@ -7,6 +7,7 @@
 #include 
 
 #include "zsda_device.h"
+#include "zsda_qp.h"
 
 /* per-process array of device data */
 struct zsda_device_info zsda_devs[RTE_PMD_ZSDA_MAX_PCI_DEVICES];
@@ -59,7 +60,7 @@ int
 zsda_admin_q_start(const struct rte_pci_device *pci_dev)
 {
uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
-   int ret = 0;
+   int ret;
 
ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_START, 0);
 
@@ -73,7 +74,7 @@ int
 zsda_admin_q_stop(const struct rte_pci_device *pci_dev)
 {
uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
-   int ret = 0;
+   int ret;
 
ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_STOP_RESP, ZSDA_RESP_INVALID);
ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_STOP, ZSDA_Q_STOP);
@@ -91,7 +92,7 @@ int
 zsda_admin_q_clear(const struct rte_pci_device *pci_dev)
 {
uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
-   int ret = 0;
+   int ret;
 
ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_Q_CLR_RESP, ZSDA_RE

[PATCH v3 6/8] zsda: add zsda crypto-pmd

[Hanxiao Li]

Add new file zsda_sym_pmd.c, zsda_sym_pmd.h in drivers/crypto/zsda

Signed-off-by: Hanxiao Li 
---
 drivers/crypto/zsda/zsda_sym_capabilities.h | 112 +
 drivers/crypto/zsda/zsda_sym_pmd.c  | 429 
 drivers/crypto/zsda/zsda_sym_pmd.h  |  35 ++
 3 files changed, 576 insertions(+)
 create mode 100644 drivers/crypto/zsda/zsda_sym_capabilities.h
 create mode 100644 drivers/crypto/zsda/zsda_sym_pmd.c
 create mode 100644 drivers/crypto/zsda/zsda_sym_pmd.h

diff --git a/drivers/crypto/zsda/zsda_sym_capabilities.h 
b/drivers/crypto/zsda/zsda_sym_capabilities.h
new file mode 100644
index 00..dd387b36ad
--- /dev/null
+++ b/drivers/crypto/zsda/zsda_sym_capabilities.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 ZTE Corporation
+ */
+
+#ifndef _ZSDA_SYM_CAPABILITIES_H_
+#define _ZSDA_SYM_CAPABILITIES_H_
+
+static const struct rte_cryptodev_capabilities zsda_crypto_sym_capabilities[] 
= {
+   {/* SHA1 */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   { .sym = {.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   { .auth = {
+   .algo = RTE_CRYPTO_AUTH_SHA1,
+   .block_size = 64,
+   .key_size = {.min = 0, .max = 0, .increment = 
0},
+   .digest_size = {.min = 20, .max = 20, 
.increment = 2},
+   .iv_size = {0} },
+   }   },
+   }
+   },
+   {/* SHA224 */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   { .sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   { .auth = {
+   .algo = RTE_CRYPTO_AUTH_SHA224,
+   .block_size = 64,
+   .key_size = {.min = 0, .max = 0, .increment = 
0},
+   .digest_size = {.min = 28, .max = 28, 
.increment = 0},
+   .iv_size = {0} },
+   }   },
+   }
+   },
+   {/* SHA256 */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   { .sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   { .auth = {
+   .algo = RTE_CRYPTO_AUTH_SHA256,
+   .block_size = 64,
+   .key_size = {.min = 0, .max = 0, .increment = 
0},
+   .digest_size = {.min = 32, .max = 32, 
.increment = 0},
+   .iv_size = {0} },
+   } },
+   }
+   },
+   {/* SHA384 */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   { .sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   { .auth = {
+   .algo = RTE_CRYPTO_AUTH_SHA384,
+   .block_size = 128,
+   .key_size = {.min = 0, .max = 0, .increment = 
0},
+   .digest_size = {.min = 48, .max = 48, 
.increment = 0},
+   .iv_size = {0} },
+   } },
+   }
+   },
+   {/* SHA512 */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   { .sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   { .auth = {
+   .algo = RTE_CRYPTO_AUTH_SHA512,
+   .block_size = 128,
+   .key_size = {.min = 0, .max = 0, .increment = 
0},
+   .digest_size = {.min = 64, .max = 64, 
.increment = 0},
+   .iv_size = {0} },
+   } },
+   }
+   },
+   {/* SM3 */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   { .sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   { .auth = {
+   .algo = RTE_CRYPTO_AUTH_SM3,
+   .block_size = 64,
+   .key_size = {.min = 0, .max = 0, .increment = 
0},
+   .digest_size = {.min = 32, .max = 32, 
.increment = 0},
+   .iv_size = {0} },
+   } },
+   }
+   },
+   {/* AES XTS */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   { .sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+   { .cipher = {
+   .algo = RTE_CRYPTO_CIPHER_AES_XTS,
+   .block_size = 16,
+   .key_size = {.min = 16, .max = 32, .increment = 
16},
+   .iv_size = {.min = 16, .max = 16, .i

[PATCH v3 1/8] zsda: Introduce zsda device drivers

[Hanxiao Li]

Introduce driver support for ZSDA which can
help to accelerate storage data process.

Signed-off-by: Hanxiao Li 
---
 MAINTAINERS   |   4 +
 config/rte_config.h   |   4 +
 drivers/common/zsda/meson.build   |  25 +++
 drivers/common/zsda/zsda_common.c | 168 +++
 drivers/common/zsda/zsda_common.h | 328 ++
 drivers/common/zsda/zsda_logs.c   |  21 ++
 drivers/common/zsda/zsda_logs.h   |  32 +++
 usertools/dpdk-devbind.py |   5 +-
 8 files changed, 586 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/zsda/meson.build
 create mode 100644 drivers/common/zsda/zsda_common.c
 create mode 100644 drivers/common/zsda/zsda_common.h
 create mode 100644 drivers/common/zsda/zsda_logs.c
 create mode 100644 drivers/common/zsda/zsda_logs.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c5a703b5c0..ea245fc61b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1268,6 +1268,10 @@ F: drivers/compress/zlib/
 F: doc/guides/compressdevs/zlib.rst
 F: doc/guides/compressdevs/features/zlib.ini
 
+ZTE Storage Data Accelerator
+M: Hanxiao Li 
+F: drivers/compress/zsda/
+F: drivers/common/zsda/
 
 DMAdev Drivers
 --
diff --git a/config/rte_config.h b/config/rte_config.h
index dd7bb0d35b..acfbe5b0f7 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -108,6 +108,10 @@
 
 /** driver defines /
 
+/* ZSDA device */
+/* Max. number of ZSDA devices which can be attached */
+#define RTE_PMD_ZSDA_MAX_PCI_DEVICES 256
+
 /* Packet prefetching in PMDs */
 #define RTE_PMD_PACKET_PREFETCH 1
 
diff --git a/drivers/common/zsda/meson.build b/drivers/common/zsda/meson.build
new file mode 100644
index 00..b12ef17476
--- /dev/null
+++ b/drivers/common/zsda/meson.build
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2024 ZTE Corporation
+
+config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
+
+deps += ['bus_pci', 'compressdev']
+sources += files(
+   'zsda_common.c',
+   'zsda_logs.c',
+   'zsda_device.c',
+   'zsda_qp.c',
+   )
+
+zsda_compress = true
+zsda_compress_path = 'compress/zsda'
+zsda_compress_relpath = '../../' + zsda_compress_path
+includes += include_directories(zsda_compress_relpath)
+
+if zsda_compress
+zlib = dependency('zlib', required: false, method: 'pkg-config')
+   foreach f: ['zsda_comp_pmd.c', 'zsda_comp.c']
+   sources += files(join_paths(zsda_compress_relpath, f))
+   endforeach
+   ext_deps += zlib
+endif
diff --git a/drivers/common/zsda/zsda_common.c 
b/drivers/common/zsda/zsda_common.c
new file mode 100644
index 00..33ea8a42fe
--- /dev/null
+++ b/drivers/common/zsda/zsda_common.c
@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 ZTE Corporation
+ */
+
+#include "zsda_common.h"
+
+#include "bus_pci_driver.h"
+
+#define MAGIC_SEND 0xab
+#define MAGIC_RECV 0xcd
+#define ADMIN_VER 1
+
+static const uint8_t crc8_table[256] = {
+   0x00, 0x41, 0x13, 0x52, 0x26, 0x67, 0x35, 0x74, 0x4c, 0x0d, 0x5f, 0x1e,
+   0x6a, 0x2b, 0x79, 0x38, 0x09, 0x48, 0x1a, 0x5b, 0x2f, 0x6e, 0x3c, 0x7d,
+   0x45, 0x04, 0x56, 0x17, 0x63, 0x22, 0x70, 0x31, 0x12, 0x53, 0x01, 0x40,
+   0x34, 0x75, 0x27, 0x66, 0x5e, 0x1f, 0x4d, 0x0c, 0x78, 0x39, 0x6b, 0x2a,
+   0x1b, 0x5a, 0x08, 0x49, 0x3d, 0x7c, 0x2e, 0x6f, 0x57, 0x16, 0x44, 0x05,
+   0x71, 0x30, 0x62, 0x23, 0x24, 0x65, 0x37, 0x76, 0x02, 0x43, 0x11, 0x50,
+   0x68, 0x29, 0x7b, 0x3a, 0x4e, 0x0f, 0x5d, 0x1c, 0x2d, 0x6c, 0x3e, 0x7f,
+   0x0b, 0x4a, 0x18, 0x59, 0x61, 0x20, 0x72, 0x33, 0x47, 0x06, 0x54, 0x15,
+   0x36, 0x77, 0x25, 0x64, 0x10, 0x51, 0x03, 0x42, 0x7a, 0x3b, 0x69, 0x28,
+   0x5c, 0x1d, 0x4f, 0x0e, 0x3f, 0x7e, 0x2c, 0x6d, 0x19, 0x58, 0x0a, 0x4b,
+   0x73, 0x32, 0x60, 0x21, 0x55, 0x14, 0x46, 0x07, 0x48, 0x09, 0x5b, 0x1a,
+   0x6e, 0x2f, 0x7d, 0x3c, 0x04, 0x45, 0x17, 0x56, 0x22, 0x63, 0x31, 0x70,
+   0x41, 0x00, 0x52, 0x13, 0x67, 0x26, 0x74, 0x35, 0x0d, 0x4c, 0x1e, 0x5f,
+   0x2b, 0x6a, 0x38, 0x79, 0x5a, 0x1b, 0x49, 0x08, 0x7c, 0x3d, 0x6f, 0x2e,
+   0x16, 0x57, 0x05, 0x44, 0x30, 0x71, 0x23, 0x62, 0x53, 0x12, 0x40, 0x01,
+   0x75, 0x34, 0x66, 0x27, 0x1f, 0x5e, 0x0c, 0x4d, 0x39, 0x78, 0x2a, 0x6b,
+   0x6c, 0x2d, 0x7f, 0x3e, 0x4a, 0x0b, 0x59, 0x18, 0x20, 0x61, 0x33, 0x72,
+   0x06, 0x47, 0x15, 0x54, 0x65, 0x24, 0x76, 0x37, 0x43, 0x02, 0x50, 0x11,
+   0x29, 0x68, 0x3a, 0x7b, 0x0f, 0x4e, 0x1c, 0x5d, 0x7e, 0x3f, 0x6d, 0x2c,
+   0x58, 0x19, 0x4b, 0x0a, 0x32, 0x73, 0x21, 0x60, 0x14, 0x55, 0x07, 0x46,
+   0x77, 0x36, 0x64, 0x25, 0x51, 0x10, 0x42, 0x03, 0x3b, 0x7a, 0x28, 0x69,
+   0x1d, 0x5c, 0x0e, 0x4f};
+
+static uint8_t
+zsda_crc8(const uint8_t *message, const int length)
+{
+   uint8_t crc = 0;
+   int i;
+
+   for (i = 0; i < length; i++)
+   crc = crc8_table[crc ^ message[i]];
+   return crc;
+}
+
+uint32_t
+zsda_set_reg_8(void *addr

[PATCH v3 3/8] zsda: add support for queue operation

[Hanxiao Li]

Add queue initialization, release, enqueue, dequeue and other interface.

Signed-off-by: Hanxiao Li 
---
 drivers/common/zsda/zsda_qp.c | 720 ++
 drivers/common/zsda/zsda_qp.h | 160 
 2 files changed, 880 insertions(+)
 create mode 100644 drivers/common/zsda/zsda_qp.c
 create mode 100644 drivers/common/zsda/zsda_qp.h

diff --git a/drivers/common/zsda/zsda_qp.c b/drivers/common/zsda/zsda_qp.c
new file mode 100644
index 00..d36fb60de3
--- /dev/null
+++ b/drivers/common/zsda/zsda_qp.c
@@ -0,0 +1,720 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 ZTE Corporation
+ */
+
+#include 
+
+#include 
+
+#include "zsda_common.h"
+#include "zsda_logs.h"
+#include "zsda_device.h"
+#include "zsda_qp.h"
+
+#define RING_DIR_TX 0
+#define RING_DIR_RX 1
+
+struct ring_size {
+   uint16_t tx_msg_size;
+   uint16_t rx_msg_size;
+};
+
+struct ring_size zsda_qp_hw_ring_size[ZSDA_MAX_SERVICES] = {
+   [ZSDA_SERVICE_COMPRESSION] = {32, 16},
+   [ZSDA_SERVICE_DECOMPRESSION] = {32, 16},
+};
+
+static void
+zsda_set_queue_head_tail(const struct zsda_pci_device *zsda_pci_dev,
+const uint8_t qid)
+{
+   struct rte_pci_device *pci_dev =
+   zsda_devs[zsda_pci_dev->zsda_dev_id].pci_dev;
+   uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+
+   ZSDA_CSR_WRITE32(mmio_base + IO_DB_INITIAL_CONFIG + (qid * 4),
+SET_HEAD_INTI);
+}
+
+int
+zsda_get_queue_cfg(struct zsda_pci_device *zsda_pci_dev)
+{
+   uint8_t i;
+   uint32_t index;
+   enum zsda_service_type type;
+   struct zsda_qp_hw *zsda_hw_qps = zsda_pci_dev->zsda_hw_qps;
+   struct qinfo qcfg;
+   int ret = 0;
+
+   for (i = 0; i < zsda_num_used_qps; i++) {
+   zsda_set_queue_head_tail(zsda_pci_dev, i);
+   ret = zsda_get_queue_cfg_by_id(zsda_pci_dev, i, &qcfg);
+   type = qcfg.q_type;
+   if (ret) {
+   ZSDA_LOG(ERR, "get queue cfg!");
+   return ret;
+   }
+   if (type >= ZSDA_SERVICE_INVALID)
+   continue;
+
+   index = zsda_pci_dev->zsda_qp_hw_num[type];
+   zsda_hw_qps[type].data[index].used = true;
+   zsda_hw_qps[type].data[index].tx_ring_num = i;
+   zsda_hw_qps[type].data[index].rx_ring_num = i;
+   zsda_hw_qps[type].data[index].tx_msg_size =
+   zsda_qp_hw_ring_size[type].tx_msg_size;
+   zsda_hw_qps[type].data[index].rx_msg_size =
+   zsda_qp_hw_ring_size[type].rx_msg_size;
+
+   zsda_pci_dev->zsda_qp_hw_num[type]++;
+   }
+
+   return ret;
+}
+
+struct zsda_qp_hw *
+zsda_qps_hw_per_service(struct zsda_pci_device *zsda_pci_dev,
+   const enum zsda_service_type service)
+{
+   struct zsda_qp_hw *qp_hw = NULL;
+
+   if (service < ZSDA_SERVICE_INVALID)
+   qp_hw = &(zsda_pci_dev->zsda_hw_qps[service]);
+
+   return qp_hw;
+}
+
+uint16_t
+zsda_qps_per_service(const struct zsda_pci_device *zsda_pci_dev,
+const enum zsda_service_type service)
+{
+   uint16_t qp_hw_num = 0;
+
+   if (service < ZSDA_SERVICE_INVALID)
+   qp_hw_num = zsda_pci_dev->zsda_qp_hw_num[service];
+
+   return qp_hw_num;
+}
+
+uint16_t
+zsda_comp_max_nb_qps(const struct zsda_pci_device *zsda_pci_dev)
+{
+   uint16_t comp =
+   zsda_qps_per_service(zsda_pci_dev, ZSDA_SERVICE_COMPRESSION);
+   uint16_t decomp =
+   zsda_qps_per_service(zsda_pci_dev, ZSDA_SERVICE_DECOMPRESSION);
+   uint16_t min = 0;
+
+   if ((comp == MAX_QPS_ON_FUNCTION) ||
+   (decomp == MAX_QPS_ON_FUNCTION))
+   min = MAX_QPS_ON_FUNCTION;
+   else
+   min = (comp < decomp) ? comp : decomp;
+   if (min == 0)
+   return MAX_QPS_ON_FUNCTION;
+   return min;
+}
+
+
+void
+zsda_stats_get(void **queue_pairs, const uint32_t nb_queue_pairs,
+ struct zsda_common_stat *stats)
+{
+   enum zsda_service_type type;
+   uint32_t i;
+   struct zsda_qp *qp;
+
+   if ((stats == NULL) || (queue_pairs == NULL)) {
+   ZSDA_LOG(ERR, E_NULL);
+   return;
+   }
+
+   for (i = 0; i < nb_queue_pairs; i++) {
+   qp = (struct zsda_qp *)queue_pairs[i];
+
+   if (qp == NULL) {
+   ZSDA_LOG(ERR, E_NULL);
+   break;
+   }
+
+   for (type = 0; type < ZSDA_SERVICE_INVALID; type++) {
+   if (qp->srv[type].used) {
+   stats->enqueued_count +=
+   qp->srv[type].stats.enqueued_count;
+   stats->dequeued_count +=
+   qp->srv[type].stats.dequeued_count;
+

[PATCH v3 7/8] zsda: add zsda crypto-sym

[Hanxiao Li]

Add new file zsda_sym.c, zsda_sym.h in drivers/crypto/zsda

Signed-off-by: Hanxiao Li 
---
 drivers/crypto/zsda/zsda_sym.c | 286 +
 drivers/crypto/zsda/zsda_sym.h |  25 +++
 2 files changed, 311 insertions(+)
 create mode 100644 drivers/crypto/zsda/zsda_sym.c
 create mode 100644 drivers/crypto/zsda/zsda_sym.h

diff --git a/drivers/crypto/zsda/zsda_sym.c b/drivers/crypto/zsda/zsda_sym.c
new file mode 100644
index 00..b4001476a6
--- /dev/null
+++ b/drivers/crypto/zsda/zsda_sym.c
@@ -0,0 +1,286 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 ZTE Corporation
+ */
+
+#include "cryptodev_pmd.h"
+
+#include "zsda_logs.h"
+#include "zsda_sym.h"
+#include "zsda_sym_pmd.h"
+#include "zsda_sym_session.h"
+
+#define choose_dst_mbuf(mbuf_src, mbuf_dst) ((mbuf_dst) == NULL ? (mbuf_src) : 
(mbuf_dst))
+#define LBADS_MAX_REMAINDER (16 - 1)
+
+void
+zsda_reverse_memcpy(uint8_t *dst, const uint8_t *src, size_t n)
+{
+   size_t i;
+
+   for (i = 0; i < n; ++i)
+   dst[n - 1 - i] = src[i];
+}
+
+static uint8_t
+zsda_get_opcode_hash(struct zsda_sym_session *sess)
+{
+   switch (sess->auth.algo) {
+   case RTE_CRYPTO_AUTH_SHA1:
+   return ZSDA_OPC_HASH_SHA1;
+
+   case RTE_CRYPTO_AUTH_SHA224:
+   return ZSDA_OPC_HASH_SHA2_224;
+
+   case RTE_CRYPTO_AUTH_SHA256:
+   return ZSDA_OPC_HASH_SHA2_256;
+
+   case RTE_CRYPTO_AUTH_SHA384:
+   return ZSDA_OPC_HASH_SHA2_384;
+
+   case RTE_CRYPTO_AUTH_SHA512:
+   return ZSDA_OPC_HASH_SHA2_512;
+
+   case RTE_CRYPTO_AUTH_SM3:
+   return ZSDA_OPC_HASH_SM3;
+   default:
+   break;
+   }
+
+   return ZSDA_OPC_INVALID;
+}
+
+static uint8_t
+zsda_get_opcode_crypto(struct zsda_sym_session *sess)
+{
+
+   if (sess->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) {
+   if (sess->cipher.algo == RTE_CRYPTO_CIPHER_AES_XTS &&
+   sess->cipher.key_encry.length == 16)
+   return ZSDA_OPC_EC_AES_XTS_256;
+   else if (sess->cipher.algo == RTE_CRYPTO_CIPHER_AES_XTS &&
+sess->cipher.key_encry.length == 32)
+   return ZSDA_OPC_EC_AES_XTS_512;
+   else if (sess->cipher.algo == RTE_CRYPTO_CIPHER_SM4_XTS)
+   return ZSDA_OPC_EC_SM4_XTS_256;
+   } else if (sess->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT) {
+   if (sess->cipher.algo == RTE_CRYPTO_CIPHER_AES_XTS &&
+   sess->cipher.key_decry.length == 16)
+   return ZSDA_OPC_DC_AES_XTS_256;
+   else if (sess->cipher.algo == RTE_CRYPTO_CIPHER_AES_XTS &&
+sess->cipher.key_decry.length == 32)
+   return ZSDA_OPC_DC_AES_XTS_512;
+   else if (sess->cipher.algo == RTE_CRYPTO_CIPHER_SM4_XTS)
+   return ZSDA_OPC_DC_SM4_XTS_256;
+   }
+   return ZSDA_OPC_INVALID;
+}
+
+int
+zsda_encry_match(const void *op_in)
+{
+   const struct rte_crypto_op *op = (const struct rte_crypto_op *)op_in;
+   struct rte_cryptodev_sym_session *session = op->sym->session;
+   struct zsda_sym_session *sess =
+   (struct zsda_sym_session *)session->driver_priv_data;
+
+   if (sess->chain_order == ZSDA_SYM_CHAIN_ONLY_CIPHER &&
+   sess->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
+   return 1;
+   else
+   return 0;
+}
+
+int
+zsda_decry_match(const void *op_in)
+{
+   const struct rte_crypto_op *op = (const struct rte_crypto_op *)op_in;
+   struct rte_cryptodev_sym_session *session = op->sym->session;
+   struct zsda_sym_session *sess =
+   (struct zsda_sym_session *)session->driver_priv_data;
+
+   if (sess->chain_order == ZSDA_SYM_CHAIN_ONLY_CIPHER &&
+   sess->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
+   return 1;
+   else
+   return 0;
+}
+
+int
+zsda_hash_match(const void *op_in)
+{
+   const struct rte_crypto_op *op = (const struct rte_crypto_op *)op_in;
+   struct rte_cryptodev_sym_session *session = op->sym->session;
+   struct zsda_sym_session *sess =
+   (struct zsda_sym_session *)session->driver_priv_data;
+
+   if (sess->chain_order == ZSDA_SYM_CHAIN_ONLY_AUTH)
+   return 1;
+   else
+   return 0;
+}
+
+static int
+zsda_check_len_lbads(uint32_t data_len, uint32_t lbads_size)
+{
+   if (data_len < 16) {
+   ZSDA_LOG(ERR, "data_len wrong!");
+   return ZSDA_FAILED;
+   }
+   if (lbads_size != 0) {
+   if (!(((data_len % lbads_size) == 0) ||
+ ((data_len % lbads_size) > LBADS_MAX_REMAINDER))) {
+   ZSDA_LOG(ERR, "data_len wrong!");
+   return ZSDA_FAILED;
+   }
+   }
+
+   return 0;
+}
+
+int
+zsda_build_

[PATCH v3 8/8] zsda: add zsda crypto-session and compile file

[Hanxiao Li]

Add new file zsda_sym_session.c, zsda_symsession.h
and modify drivers/common/zsda/meson.build

Signed-off-by: Hanxiao Li 
---
 drivers/common/zsda/meson.build|  17 +-
 drivers/common/zsda/zsda_device.h  |   1 -
 drivers/crypto/zsda/zsda_sym_session.c | 500 +
 drivers/crypto/zsda/zsda_sym_session.h |  82 
 4 files changed, 597 insertions(+), 3 deletions(-)
 create mode 100644 drivers/crypto/zsda/zsda_sym_session.c
 create mode 100644 drivers/crypto/zsda/zsda_sym_session.h

diff --git a/drivers/common/zsda/meson.build b/drivers/common/zsda/meson.build
index b12ef17476..57b54201f2 100644
--- a/drivers/common/zsda/meson.build
+++ b/drivers/common/zsda/meson.build
@@ -3,7 +3,7 @@
 
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 
-deps += ['bus_pci', 'compressdev']
+deps += ['bus_pci', 'cryptodev', 'compressdev']
 sources += files(
'zsda_common.c',
'zsda_logs.c',
@@ -15,7 +15,6 @@ zsda_compress = true
 zsda_compress_path = 'compress/zsda'
 zsda_compress_relpath = '../../' + zsda_compress_path
 includes += include_directories(zsda_compress_relpath)
-
 if zsda_compress
 zlib = dependency('zlib', required: false, method: 'pkg-config')
foreach f: ['zsda_comp_pmd.c', 'zsda_comp.c']
@@ -23,3 +22,17 @@ zlib = dependency('zlib', required: false, method: 
'pkg-config')
endforeach
ext_deps += zlib
 endif
+
+
+zsda_crypto = true
+zsda_crypto_path = 'crypto/zsda'
+zsda_crypto_relpath = '../../' + zsda_crypto_path
+if zsda_crypto
+libcrypto = dependency('libcrypto', required: false, method: 'pkg-config')
+   foreach f: ['zsda_sym_pmd.c', 'zsda_sym_session.c', 'zsda_sym.c']
+   sources += files(join_paths(zsda_crypto_relpath, f))
+   endforeach
+   deps += ['security']
+   ext_deps += libcrypto
+   cflags += ['-DBUILD_ZSDA_SYM']
+endif
diff --git a/drivers/common/zsda/zsda_device.h 
b/drivers/common/zsda/zsda_device.h
index 07dca183ab..51ff741840 100644
--- a/drivers/common/zsda/zsda_device.h
+++ b/drivers/common/zsda/zsda_device.h
@@ -18,7 +18,6 @@ struct zsda_device_info {
 
struct rte_pci_device *pci_dev;
 
-   // struct rte_device sym_rte_dev;
struct rte_device sym_rte_dev;
/**< This represents the crypto sym subset of this pci device.
 * Register with this rather than with the one in
diff --git a/drivers/crypto/zsda/zsda_sym_session.c 
b/drivers/crypto/zsda/zsda_sym_session.c
new file mode 100644
index 00..47ae76791a
--- /dev/null
+++ b/drivers/crypto/zsda/zsda_sym_session.c
@@ -0,0 +1,500 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 ZTE Corporation
+ */
+
+#include "cryptodev_pmd.h"
+
+#include "zsda_sym_session.h"
+#include "zsda_logs.h"
+
+/ AES KEY EXPANSION /
+/**
+ * AES S-boxes
+ * Sbox table: 8bits input convert to 8bits output
+ **/
+static const unsigned char aes_sbox[256] = {
+   // 0 12  3 45 6 7  89 A  B
+   // C D E F
+   0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b,
+   0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
+   0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26,
+   0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+   0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2,
+   0xeb, 0x27, 0xb2, 0x75, 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
+   0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed,
+   0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+   0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f,
+   0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
+   0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, 0x13, 0xec,
+   0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
+   0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14,
+   0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
+   0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d,
+   0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
+   0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f,
+   0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
+   0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11,
+   0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
+   0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f,
+   0xb0, 0x54, 0xbb, 0x16};
+
+/**
+ * The round constant word array, Rcon[i]
+ *
+ * From Wikipedia's article on the Rijndael key schedule @
+ * https://en.wikipedia.org/wiki/Rijndael_key_schedule#Rcon "Only the first 
some
+ * of these constants are actually