Re: [PATCH v4 1/7] ethdev: support report register names and filter

[fengchengwen]

Hi Jie,

On 2024/2/26 11:07, Jie Hai wrote:
> This patch adds "filter" and "names" fields to "rte_dev_reg_info"
> structure. Names of registers in data fields can be reported and
> the registers can be filtered by their names.
> 
> The new API rte_eth_dev_get_reg_info_ext() is added to support
> reporting names and filtering by names. And the original API
> rte_eth_dev_get_reg_info() does not use the name and filter fields.
> A local variable is used in rte_eth_dev_get_reg_info for
> compatibility. If the drivers does not report the names, set them
> to "offset_XXX".
> 
> Signed-off-by: Jie Hai 
> ---
>  doc/guides/rel_notes/release_24_03.rst |  8 ++
>  lib/ethdev/rte_dev_info.h  | 11 +
>  lib/ethdev/rte_ethdev.c| 34 ++
>  lib/ethdev/rte_ethdev.h| 28 +
>  lib/ethdev/version.map |  1 +
>  5 files changed, 82 insertions(+)
> 
> diff --git a/doc/guides/rel_notes/release_24_03.rst 
> b/doc/guides/rel_notes/release_24_03.rst
> index 32d0ad8cf6a7..fa46da427dca 100644
> --- a/doc/guides/rel_notes/release_24_03.rst
> +++ b/doc/guides/rel_notes/release_24_03.rst
> @@ -132,6 +132,11 @@ New Features
>  to support TLS v1.2, TLS v1.3 and DTLS v1.2.
>* Added PMD API to allow raw submission of instructions to CPT.
>  
> +  * **Added support for dumping registers with names and filter.**
> +
> +* Added new API functions ``rte_eth_dev_get_reg_info_ext()`` to and 
> filter
> +  the registers by their names and get the information of 
> registers(names,
> +  values and other attributes).
>  
>  Removed Items
>  -
> @@ -197,6 +202,9 @@ ABI Changes
>  
>  * No ABI change that would break compatibility with 23.11.
>  
> +* ethdev: Added ``filter`` and ``names`` fields to ``rte_dev_reg_info``
> +  structure for reporting names of registers and filtering them by names.
> +
>  
>  Known Issues
>  
> diff --git a/lib/ethdev/rte_dev_info.h b/lib/ethdev/rte_dev_info.h
> index 67cf0ae52668..0ad4a43b9526 100644
> --- a/lib/ethdev/rte_dev_info.h
> +++ b/lib/ethdev/rte_dev_info.h
> @@ -11,6 +11,11 @@ extern "C" {
>  
>  #include 
>  
> +#define RTE_ETH_REG_NAME_SIZE 128

Almost all stats name size is 64, why not keep consistent?

> +struct rte_eth_reg_name {
> + char name[RTE_ETH_REG_NAME_SIZE];
> +};
> +
>  /*
>   * Placeholder for accessing device registers
>   */
> @@ -20,6 +25,12 @@ struct rte_dev_reg_info {
>   uint32_t length; /**< Number of registers to fetch */
>   uint32_t width; /**< Size of device register */
>   uint32_t version; /**< Device version */
> + /**
> +  * Filter for target subset of registers.
> +  * This field could affects register selection for data/length/names.
> +  */
> + const char *filter;
> + struct rte_eth_reg_name *names; /**< Registers name saver */
>  };
>  
>  /*
> diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c
> index f1c658f49e80..9ef50c633ce3 100644
> --- a/lib/ethdev/rte_ethdev.c
> +++ b/lib/ethdev/rte_ethdev.c
> @@ -6388,8 +6388,37 @@ rte_eth_read_clock(uint16_t port_id, uint64_t *clock)
>  
>  int
>  rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info)
> +{
> + struct rte_dev_reg_info reg_info = { 0 };
> + int ret;
> +
> + if (info == NULL) {
> + RTE_ETHDEV_LOG_LINE(ERR,
> + "Cannot get ethdev port %u register info to NULL",
> + port_id);
> + return -EINVAL;
> + }
> +
> + reg_info.length = info->length;
> + reg_info.data = info->data;
> +
> + ret = rte_eth_dev_get_reg_info_ext(port_id, ®_info);
> + if (ret != 0)
> + return ret;
> +
> + info->length = reg_info.length;
> + info->width = reg_info.width;
> + info->version = reg_info.version;
> + info->offset = reg_info.offset;
> +
> + return 0;
> +}
> +
> +int
> +rte_eth_dev_get_reg_info_ext(uint16_t port_id, struct rte_dev_reg_info *info)
>  {
>   struct rte_eth_dev *dev;
> + uint32_t i;
>   int ret;
>  
>   RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
> @@ -6408,6 +6437,11 @@ rte_eth_dev_get_reg_info(uint16_t port_id, struct 
> rte_dev_reg_info *info)
>  
>   rte_ethdev_trace_get_reg_info(port_id, info, ret);
>  
> + /* Report the default names if drivers not report. */
> + if (info->names != NULL && strlen(info->names[0].name) == 0)
> + for (i = 0; i < info->length; i++)
> + snprintf(info->names[i].name, RTE_ETH_REG_NAME_SIZE,
> + "offset_%x", info->offset + i * info->width);

%x has no prefix "0x", may lead to confused.
How about use %u ?

Another question, if app don't zero names' memory, then its value is random, so 
it will not enter this logic.
Suggest memset item[0]'s name memory before invoke PMD ops.

>   return ret;
>  }
>  
> diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_et

[PATCH v1] app/test: fix segfault in Tx adapter autotest

[Ganapati Kundapura]

Uninitialized mbufs are enqueued to eventdev which causes segfault
on freeing the mbuf in tx adapter.
Fixed by initializing mbufs before enqueuing to eventdev.

Fixes: 46cf97e4bbfa ("eventdev: add test for eth Tx adapter")

Signed-off-by: Ganapati Kundapura 

diff --git a/app/test/test_event_eth_tx_adapter.c 
b/app/test/test_event_eth_tx_adapter.c
index dbd22f6..482b8e6 100644
--- a/app/test/test_event_eth_tx_adapter.c
+++ b/app/test/test_event_eth_tx_adapter.c
@@ -484,6 +484,10 @@ tx_adapter_service(void)
int internal_port;
uint32_t cap;
 
+   /* Initialize mbufs */
+   for (i = 0; i < RING_SIZE; i++)
+   rte_pktmbuf_reset(&bufs[i]);
+
memset(&dev_conf, 0, sizeof(dev_conf));
err = rte_event_eth_tx_adapter_caps_get(TEST_DEV_ID, TEST_ETHDEV_ID,
&cap);
-- 
2.6.4

Re: [PATCH v9] net/bnx2x: fix warnings about rte_memcpy lengths

[Jerin Jacob]

On Fri, Feb 23, 2024 at 7:30 PM Morten Brørup  
wrote:
>
> Bugfix: The vlan in the bulletin does not contain a VLAN header, only the
> VLAN ID, so only copy 2 byte, not 4. The target structure has padding
> after the field, so copying 2 byte too many is effectively harmless.
> There is no need to backport this patch.
>
> Use RTE_PTR_ADD where copying arrays to the offset of a first field in a
> structure holding multiple fields, to avoid compiler warnings with
> decorated rte_memcpy.
>
> Bugzilla ID: 1146
>
> Fixes: 540a211084a7695a1c7bc43068934c140d6989be ("bnx2x: driver core")
> Cc: step...@networkplumber.org
> Cc: rm...@marvell.com
> Cc: shsha...@marvell.com
> Cc: pa...@marvell.com
>
> Signed-off-by: Morten Brørup 
> Acked-by: Devendra Singh Rawat 
> ---
> v9:
> * Fix checkpatch warning about spaces.

Fixed the following issues[1] and updated the git commit as follows
and applied to dpdk-next-net-mrvl/for-main. Thanks

net/bnx2x: fix warnings about memcpy lengths

The vlan in the bulletin does not contain a VLAN header, only the
VLAN ID, so only copy 2 byte, not 4. The target structure has padding
after the field, so copying 2 byte too many is effectively harmless.
Fix it by using generic memcpy version instead of specialized
rte version as it not used in fast path.

Also, Use RTE_PTR_ADD where copying arrays to the offset of a first field
in a structure holding multiple fields, to avoid compiler warnings with
decorated memcpy.

Bugzilla ID: 1146
Fixes: 540a211084a7 ("bnx2x: driver core")
Cc: sta...@dpdk.org

Signed-off-by: Morten Brørup 
Acked-by: Devendra Singh Rawat 


[1]
Wrong headline format:
net/bnx2x: fix warnings about rte_memcpy lengths
Wrong tag:
Bugfix: The vlan in the bulletin does not contain a VLAN
header, only the
Is it candidate for Cc: sta...@dpdk.org backport?
net/bnx2x: fix warnings about rte_memcpy lengths

Invalid patch(es) found - checked 1 patch
check-git-log failed

### [PATCH] net/bnx2x: fix warnings about rte_memcpy lengths

WARNING:BAD_FIXES_TAG: Please use correct Fixes: style 'Fixes: <12
chars of sha1> ("")' - ie: 'Fixes: 540a211084a7 ("bnx2x:
driver core")'
#20:
Fixes: 540a211084a7695a1c7bc43068934c140d6989be ("bnx2x: driver core")

total: 0 errors, 1 warnings, 0 checks, 76 lines checked

0/1 valid patch
checkpatch failed

[PATCH v2 1/1] net/octeon_ep: use devarg to enable ISM accesses

[Vamsi Attunuru]

Adds a devarg option to enable/disable ISM memory accesses
for reading packet count details. This option is disabled
by default, as ISM memory accesses effect throughput of
bigger size packets.

Signed-off-by: Vamsi Attunuru 
---
V2 changes:
- Updated release notes and documentation
- Added missing degarg string

 doc/guides/nics/octeon_ep.rst  | 14 
 doc/guides/rel_notes/release_24_03.rst |  2 ++
 drivers/net/octeon_ep/cnxk_ep_rx.h | 42 
 drivers/net/octeon_ep/cnxk_ep_tx.c | 42 
 drivers/net/octeon_ep/cnxk_ep_vf.c |  4 +--
 drivers/net/octeon_ep/otx2_ep_vf.c |  4 +--
 drivers/net/octeon_ep/otx_ep_common.h  | 14 ++--
 drivers/net/octeon_ep/otx_ep_ethdev.c  | 45 ++
 drivers/net/octeon_ep/otx_ep_rxtx.c| 15 +
 drivers/net/octeon_ep/otx_ep_rxtx.h|  2 ++
 10 files changed, 159 insertions(+), 25 deletions(-)

diff --git a/doc/guides/nics/octeon_ep.rst b/doc/guides/nics/octeon_ep.rst
index b5040aeee2..db2ff0e7c1 100644
--- a/doc/guides/nics/octeon_ep.rst
+++ b/doc/guides/nics/octeon_ep.rst
@@ -11,6 +11,20 @@ and **Cavium OCTEON** families of adapters in SR-IOV context.
 More information can be found at `Marvell Official Website
 
`_.
 
+Runtime Config Options
+--
+
+- ``Rx&Tx ISM memory accesses enable`` (default ``0``)
+
+   PMD supports two modes for checking Rx & Tx packet count, PMD may read the 
packet count directly
+   from hardware registers or it may read from ISM memory, this may be 
selected at runtime using
+   ``ism_enable`` ``devargs`` parameter. Performance is higher for bigger size 
packets with default
+   value(ism_enable = 0). Use this runtime option to enable ISM memory 
accesses to get better
+   performance for lower size packets.
+
+   For example::
+
+  -a 0002:02:00.0,ism_enable=1
 
 Prerequisites
 -
diff --git a/doc/guides/rel_notes/release_24_03.rst 
b/doc/guides/rel_notes/release_24_03.rst
index 4b3e26ebf6..74ec43ca64 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -121,6 +121,8 @@ New Features
   * Added optimized SSE Rx routines.
   * Added optimized AVX2 Rx routines.
   * Added optimized NEON Rx routines.
+  * Added devarg to enable/disable ISM memory accesses which gives better 
performance
+for lower packet sizes when enabled.
 
 * **Updated NVIDIA mlx5 driver.**
 
diff --git a/drivers/net/octeon_ep/cnxk_ep_rx.h 
b/drivers/net/octeon_ep/cnxk_ep_rx.h
index 61263e651e..ecf95cd961 100644
--- a/drivers/net/octeon_ep/cnxk_ep_rx.h
+++ b/drivers/net/octeon_ep/cnxk_ep_rx.h
@@ -88,8 +88,9 @@ cnxk_ep_rx_refill(struct otx_ep_droq *droq)
 }
 
 static inline uint32_t
-cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq)
+cnxk_ep_check_rx_ism_mem(void *rx_queue)
 {
+   struct otx_ep_droq *droq = (struct otx_ep_droq *)rx_queue;
uint32_t new_pkts;
uint32_t val;
 
@@ -98,8 +99,9 @@ cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq)
 * number of PCIe writes.
 */
val = __atomic_load_n(droq->pkts_sent_ism, __ATOMIC_RELAXED);
-   new_pkts = val - droq->pkts_sent_ism_prev;
-   droq->pkts_sent_ism_prev = val;
+
+   new_pkts = val - droq->pkts_sent_prev;
+   droq->pkts_sent_prev = val;
 
if (val > RTE_BIT32(31)) {
/* Only subtract the packet count in the HW counter
@@ -113,11 +115,34 @@ cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq)
rte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);
rte_mb();
}
-
-   droq->pkts_sent_ism_prev = 0;
+   droq->pkts_sent_prev = 0;
}
+
rte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);
-   droq->pkts_pending += new_pkts;
+
+   return new_pkts;
+}
+
+static inline uint32_t
+cnxk_ep_check_rx_pkt_reg(void *rx_queue)
+{
+   struct otx_ep_droq *droq = (struct otx_ep_droq *)rx_queue;
+   uint32_t new_pkts;
+   uint32_t val;
+
+   val = rte_read32(droq->pkts_sent_reg);
+
+   new_pkts = val - droq->pkts_sent_prev;
+   droq->pkts_sent_prev = val;
+
+   if (val > RTE_BIT32(31)) {
+   /* Only subtract the packet count in the HW counter
+* when count above halfway to saturation.
+*/
+   rte_write64((uint64_t)val, droq->pkts_sent_reg);
+   rte_mb();
+   droq->pkts_sent_prev = 0;
+   }
 
return new_pkts;
 }
@@ -125,8 +150,11 @@ cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq)
 static inline int16_t __rte_hot
 cnxk_ep_rx_pkts_to_process(struct otx_ep_droq *droq, uint16_t nb_pkts)
 {
+   const otx_ep_check_pkt_count_t cnxk_rx_pkt_count[2] = { 
cnxk_ep_check_rx_pkt_reg,
+   
cnxk_ep

Re: [PATCH 4/4] dts: log stderr with failed remote commands

[Juraj Linkeš]

On Fri, Feb 23, 2024 at 8:19 PM Luca Vizzarro  wrote:
>
> On 29/01/2024 13:10, Juraj Linkeš wrote:
> > Here's I'd add logged additionally as an error, as this sounds as if
> > we're changing debug to error
>
> That is also a way of doing this, but an error is an error. If we wanted
> to log the same thing in debug and error, then when we go read the debug
> we get duplicates... making it less readable. What do you say?
>

I meant let's change the commit message wording to better reflect what
the patch does - it adds stderr to the exception, not doing something
instead of logging it as debug (it could be understood this way). But
it doesn't really matter much. Maybe a better wording of the second
sentence would be "So that, instead of logging it just as debug, it is
also stored in an error, ."

> > I'd change the order here (and all other places) so that stderr is
> > before the return code.
> Ack.
>
> > We should mention that the last string is the stderr output. Maybe we
> > just add 'Stderr:' before {self._command_stderr}. And maybe we should
> > put quotes around {self._command_stderr}.
>
> Since you mentioned "quotes", I'd think that it'd be even better to
> indent it as if it's a quote. With logs as busy as the ones DTS prints,
> adding some quotes may not change much as it's all already very crowded.
> Can prefix with 'Stderr: ' though.

The prefix is essential so that we know what the output actually is.
Indenting it sounds great.

Re: [PATCH v4 2/7] ethdev: add telemetry cmd for registers

[fengchengwen]

Hi Jie,

On 2024/2/26 11:07, Jie Hai wrote:
> This patch adds a telemetry command for registers dump,
> and supports get registers with specified names.
> The length of the string exported by telemetry is limited
> by MAX_OUTPUT_LEN. Therefore, the filter should be more
> precise.
> 
> An example usage is shown below:
> --> /ethdev/regs,0,INTR
> {
>   "/ethdev/regs": {
> "registers_length": 318,
> "registers_width": 4,
> "register_offset": "0x0",
> "version": "0x1140011",
> "group_0": {
>   "HNS3_CMDQ_INTR_STS_REG": "0x0",
>   "HNS3_CMDQ_INTR_EN_REG": "0x2",
>   "HNS3_CMDQ_INTR_GEN_REG": "0x0",
>   "queue_0_HNS3_TQP_INTR_CTRL_REG": "0x0",
>   "queue_0_HNS3_TQP_INTR_GL0_REG": "0xa",
>   "queue_0_HNS3_TQP_INTR_GL1_REG": "0xa",
>   "queue_0_HNS3_TQP_INTR_GL2_REG": "0x0",
>   ...
>   },
> "group_1": {
> ...
> },
> ...
> }
> 
> or as below if the number of registers not exceed the
> RTE_TEL_MAX_DICT_ENTRIES:
> --> /ethdev/regs,0,ppp
> {
>   "/ethdev/regs": {
> "registers_length": 156,
> "registers_width": 4,
> "register_offset": "0x0",
> "version": "0x1140011",
> "ppp_key_drop_num": "0x0",
> "ppp_rlt_drop_num": "0x0",
> "ssu_ppp_mac_key_num_l": "0x1",
> "ssu_ppp_mac_key_num_h": "0x0",
> "ssu_ppp_host_key_num_l": "0x1",
> "ssu_ppp_host_key_num_h": "0x0",
> "ppp_ssu_mac_rlt_num_l": "0x1",
> ...
>}
> }
> 
> Signed-off-by: Jie Hai 
> ---
>  lib/ethdev/rte_ethdev_telemetry.c | 126 ++
>  1 file changed, 126 insertions(+)
> 
> diff --git a/lib/ethdev/rte_ethdev_telemetry.c 
> b/lib/ethdev/rte_ethdev_telemetry.c
> index 6b873e7abe68..f1ebb2fae632 100644
> --- a/lib/ethdev/rte_ethdev_telemetry.c
> +++ b/lib/ethdev/rte_ethdev_telemetry.c
> @@ -5,6 +5,7 @@
>  #include 
>  #include 
>  
> +#include 
>  #include 
>  #include 
>  
> @@ -1395,6 +1396,129 @@ eth_dev_handle_port_tm_node_caps(const char *cmd 
> __rte_unused,
>   return ret;
>  }
>  
> +static int
> +eth_dev_store_regs(struct rte_tel_data *d, struct rte_dev_reg_info *reg_info)
> +{
> + struct rte_tel_data *groups[RTE_TEL_MAX_DICT_ENTRIES] = {NULL};

no need zero.

> + char group_name[RTE_TEL_MAX_STRING_LEN] = {0};
> + struct rte_tel_data *group = NULL;
> + uint32_t grp_num = 0;
> + uint32_t *data;
> + int ret = 0;
> + uint32_t i;
> +
> + rte_tel_data_start_dict(d);
> + rte_tel_data_add_dict_uint(d, "register_length", reg_info->length);
> + rte_tel_data_add_dict_uint(d, "register_width", reg_info->width);
> + rte_tel_data_add_dict_uint_hex(d, "register_offset", reg_info->offset, 
> 0);
> + rte_tel_data_add_dict_uint_hex(d, "version", reg_info->version, 0);
> +
> + data = reg_info->data;
> + if (reg_info->length <= RTE_TEL_MAX_DICT_ENTRIES) {
> + for (i = 0; i < reg_info->length; i++, data++)
> + rte_tel_data_add_dict_uint_hex(d,
> + reg_info->names[i].name, *data, 0);

The above format is OK for reg_info->width==4.
There maybe reg_info->width == 8, pls support it.

> + return 0;
> + }
> +
> + for (i = 0; i < reg_info->length; i++, data++) {
> + if (i % RTE_TEL_MAX_DICT_ENTRIES == 0) {
> + if (i != 0)
> + rte_tel_data_add_dict_container(d, group_name,
> + group, 0);
> +
> + group = rte_tel_data_alloc();
> + if (group == NULL) {
> + ret = -ENOMEM;
> + goto out;
> + }
> + rte_tel_data_start_dict(group);
> + snprintf(group_name, RTE_TEL_MAX_STRING_LEN,
> + "group_%u", grp_num);

grp_num + 1 ?

> + if (grp_num >= RTE_TEL_MAX_DICT_ENTRIES) {
> + RTE_ETHDEV_LOG_LINE(NOTICE,
> + "Too many regs, please filter");

how about add more descrip: stop format!

> + return 0;

this group's memory was leak.

How about move the extream case before for loop:

uint32_t length = reg_info->lenght;
if (length > RTE_TEL_MAX_DICT_ENTRIES * RTE_TEL_MAX_DICT_ENTRIES) {
LOG(xxx);
length = RTE_TEL_MAX_DICT_ENTRIES * RTE_TEL_MAX_DICT_ENTRIES;
}

> + }
> + groups[grp_num++] = group;
> + }
> + rte_tel_data_add_dict_uint_hex(group, reg_info->names[i].name,
> + *data, 0);
> + }
> + if (i % RTE_TEL_MAX_DICT_ENTRIES != 0)
> + rte_tel_data_add_dict_container(d, group_name, group, 0);

how about move all add dict in here.
for (i = 0; i < grp_num; i++) {
snprintf(group_name, xxx);
rte_tel_data_add_dict_container(d, group_name, group[i], 0);
}

> +
> + 

Re: [PATCH 2/4] dts: customise argparse error message

[Juraj Linkeš]

On Fri, Feb 23, 2024 at 8:12 PM Luca Vizzarro  wrote:
>
> On 29/01/2024 13:04, Juraj Linkeš wrote:
> > I'm curious, what exactly is confusing about the message?
>
> Unfortunately a bit too much time has passed... but if I remember
> correctly I think that given the great amount of arguments, whenever the
> message is printed a bit too much information is given to the user. So
> bottomline, too crowded

The original message is:
./main.py -wdghf
usage: main.py [-h] [--config-file CONFIG_FILE] [--output-dir
OUTPUT_DIR] [-t TIMEOUT] [-v] [-s] [--tarball TARBALL]
[--compile-timeout COMPILE_TIMEOUT] [--test-suite TEST_SUITE
[TEST_CASES ...]] [--re-run RE_RUN]
main.py: error: unrecognized arguments: -wdghf

So this is what's confusing. I guess it doesn't mention that the user
should use the help argument and that's where the confusion was? From
my point of view that's just standard (to run a command with -h in
case of an error such as the one above), but maybe it is better to
state it explicitly.

[DPDK/ethdev Bug 1384] PCAP PMD reconfiguration failure

[bugzilla]

https://bugs.dpdk.org/show_bug.cgi?id=1384

Bug ID: 1384
   Summary: PCAP PMD reconfiguration failure
   Product: DPDK
   Version: 22.11
  Hardware: All
OS: All
Status: UNCONFIRMED
  Severity: normal
  Priority: Normal
 Component: ethdev
  Assignee: dev@dpdk.org
  Reporter: matias@nokia.com
  Target Milestone: ---

Created attachment 275
  --> https://bugs.dpdk.org/attachment.cgi?id=275&action=edit
l2fwd patch to demonstrate issue

When a PCAP PMD Ethernet device is first configured, the selected number of RX
and TX queues overrides the max values initially returned by
rte_eth_dev_info_get() (max_rx_queues, max_tx_queues). Now, if one tries to
reconfigure the device with a larger queue count(s), rte_eth_dev_configure()
will fail to an internal capability check. Reconfiguring devices this way is
useful for example in CI usage.

The issue can be reproduced with the attached simple patch to l2fwd example.

Example output from patched l2fwd (v22.11.4):

$ sudo ./examples/dpdk-l2fwd --no-pci --vdev net_pcap0,iface=lo -- -p 0x1
EAL: Detected CPU lcores: 48
EAL: Detected NUMA nodes: 1
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: VFIO support initialized
TELEMETRY: No legacy callbacks, legacy socket not created
MAC updating enabled
Notice: odd number of ports in portmask.
Lcore 0: RX port 0 TX port 0
Initializing port 0... 
  orig. max_rx_queues: 1
  orig. max_tx_queues: 1
  after conf max_rx_queues: 0
  after conf max_tx_queues: 1
Ethdev port_id=0 nb_rx_queues=1 > 0
EAL: Error - exiting with code: 1
  Cause: Cannot configure device: err=-22, port=0

-- 
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You are the assignee for the bug.

[PATCH v3 1/3] common/cnxk: dma result to an offset of the event

[Amit Prakash Shukla]

Adds support to configure writing result to offset of the DMA
response event.

Signed-off-by: Amit Prakash Shukla 
---
v3:
- Rebased and fixed compilation error.

v2:
- Added dual workslot enqueue support.
- Fixed compilation error.

 drivers/common/cnxk/roc_dpi.c   |  6 +-
 drivers/common/cnxk/roc_dpi.h   |  2 +-
 drivers/common/cnxk/roc_dpi_priv.h  |  4 
 drivers/common/cnxk/roc_idev.c  | 20 
 drivers/common/cnxk/roc_idev_priv.h |  3 +++
 drivers/dma/cnxk/cnxk_dmadev.c  |  2 +-
 6 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c
index c241168294..1ee777d779 100644
--- a/drivers/common/cnxk/roc_dpi.c
+++ b/drivers/common/cnxk/roc_dpi.c
@@ -83,6 +83,9 @@ roc_dpi_configure(struct roc_dpi *roc_dpi, uint32_t chunk_sz, 
uint64_t aura, uin
mbox_msg.s.aura = aura;
mbox_msg.s.sso_pf_func = idev_sso_pffunc_get();
mbox_msg.s.npa_pf_func = idev_npa_pffunc_get();
+   mbox_msg.s.wqecsoff = idev_dma_cs_offset_get();
+   if (mbox_msg.s.wqecsoff)
+   mbox_msg.s.wqecs = 1;
 
rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
sizeof(dpi_mbox_msg_t));
@@ -94,7 +97,7 @@ roc_dpi_configure(struct roc_dpi *roc_dpi, uint32_t chunk_sz, 
uint64_t aura, uin
 }
 
 int
-roc_dpi_dev_init(struct roc_dpi *roc_dpi)
+roc_dpi_dev_init(struct roc_dpi *roc_dpi, uint8_t offset)
 {
struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
uint16_t vfid;
@@ -103,6 +106,7 @@ roc_dpi_dev_init(struct roc_dpi *roc_dpi)
vfid = ((pci_dev->addr.devid & 0x1F) << 3) | (pci_dev->addr.function & 
0x7);
vfid -= 1;
roc_dpi->vfid = vfid;
+   idev_dma_cs_offset_set(offset);
 
return 0;
 }
diff --git a/drivers/common/cnxk/roc_dpi.h b/drivers/common/cnxk/roc_dpi.h
index 4ebde5b8a6..978e2badb2 100644
--- a/drivers/common/cnxk/roc_dpi.h
+++ b/drivers/common/cnxk/roc_dpi.h
@@ -11,7 +11,7 @@ struct roc_dpi {
uint16_t vfid;
 } __plt_cache_aligned;
 
-int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi);
+int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi, uint8_t offset);
 int __roc_api roc_dpi_dev_fini(struct roc_dpi *roc_dpi);
 
 int __roc_api roc_dpi_configure(struct roc_dpi *dpi, uint32_t chunk_sz, 
uint64_t aura,
diff --git a/drivers/common/cnxk/roc_dpi_priv.h 
b/drivers/common/cnxk/roc_dpi_priv.h
index 518a3e7351..52962c8bc0 100644
--- a/drivers/common/cnxk/roc_dpi_priv.h
+++ b/drivers/common/cnxk/roc_dpi_priv.h
@@ -31,6 +31,10 @@ typedef union dpi_mbox_msg_t {
uint64_t sso_pf_func : 16;
/* NPA PF function */
uint64_t npa_pf_func : 16;
+   /* WQE queue DMA completion status enable */
+   uint64_t wqecs : 1;
+   /* WQE queue DMA completion status offset */
+   uint64_t wqecsoff : 8;
} s;
 } dpi_mbox_msg_t;
 
diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c
index 48df3518b0..d0307c666c 100644
--- a/drivers/common/cnxk/roc_idev.c
+++ b/drivers/common/cnxk/roc_idev.c
@@ -301,6 +301,26 @@ idev_sso_set(struct roc_sso *sso)
__atomic_store_n(&idev->sso, sso, __ATOMIC_RELEASE);
 }
 
+void
+idev_dma_cs_offset_set(uint8_t offset)
+{
+   struct idev_cfg *idev = idev_get_cfg();
+
+   if (idev != NULL)
+   idev->dma_cs_offset = offset;
+}
+
+uint8_t
+idev_dma_cs_offset_get(void)
+{
+   struct idev_cfg *idev = idev_get_cfg();
+
+   if (idev != NULL)
+   return idev->dma_cs_offset;
+
+   return 0;
+}
+
 uint64_t
 roc_idev_nix_inl_meta_aura_get(void)
 {
diff --git a/drivers/common/cnxk/roc_idev_priv.h 
b/drivers/common/cnxk/roc_idev_priv.h
index 8dc1cb25bf..6628b18152 100644
--- a/drivers/common/cnxk/roc_idev_priv.h
+++ b/drivers/common/cnxk/roc_idev_priv.h
@@ -43,6 +43,7 @@ struct idev_cfg {
struct idev_nix_inl_rx_inj_cfg inl_rx_inj_cfg;
plt_spinlock_t nix_inl_dev_lock;
plt_spinlock_t npa_dev_lock;
+   uint8_t dma_cs_offset;
 };
 
 /* Generic */
@@ -61,6 +62,8 @@ void idev_sso_pffunc_set(uint16_t sso_pf_func);
 uint16_t idev_sso_pffunc_get(void);
 struct roc_sso *idev_sso_get(void);
 void idev_sso_set(struct roc_sso *sso);
+void idev_dma_cs_offset_set(uint8_t offset);
+uint8_t idev_dma_cs_offset_get(void);
 
 /* idev lmt */
 uint16_t idev_lmt_pffunc_get(void);
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 1e7f49792c..48ab09cc38 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -592,7 +592,7 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv 
__rte_unused, struct rte_pci_de
rdpi = &dpivf->rdpi;
 
rdpi->pci_dev = pci_dev;
-   rc = roc_dpi_dev_init(rdpi);
+   rc = roc_dpi_dev_init(rdpi, 0);
if (rc < 0)
goto err_out_free;
 
-- 
2.34.1

[PATCH v3 2/3] dma/cnxk: support for DMA event enqueue dequeue

[Amit Prakash Shukla]

Added cnxk driver support for dma event enqueue and dequeue.
Also added changes for work queue entry completion status and
dual workslot DMA event enqueue.

Signed-off-by: Pavan Nikhilesh 
Signed-off-by: Amit Prakash Shukla 
---
v3:
- Rebased and fixed compilation error.

v2:
- Added dual workslot enqueue support.
- Fixed compilation error.

 doc/guides/eventdevs/cnxk.rst|   5 +
 drivers/dma/cnxk/cnxk_dma_event_dp.h |  24 +++
 drivers/dma/cnxk/cnxk_dmadev.c   |   3 +-
 drivers/dma/cnxk/cnxk_dmadev.h   |  20 +-
 drivers/dma/cnxk/cnxk_dmadev_fp.c| 290 +++
 drivers/dma/cnxk/meson.build |   9 +-
 drivers/dma/cnxk/version.map |  10 +
 drivers/event/cnxk/cn9k_eventdev.c   |   2 +
 8 files changed, 360 insertions(+), 3 deletions(-)
 create mode 100644 drivers/dma/cnxk/cnxk_dma_event_dp.h
 create mode 100644 drivers/dma/cnxk/version.map

diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst
index cccb8a0304..9ff1052c53 100644
--- a/doc/guides/eventdevs/cnxk.rst
+++ b/doc/guides/eventdevs/cnxk.rst
@@ -227,3 +227,8 @@ ethernet devices connected to event device to override this 
applications can
 use `force_rx_bp=1` device arguments.
 Using unique mempool per each ethernet device is recommended when they are
 connected to event device.
+
+DMA adapter new mode support
+
+
+DMA driver does not support DMA adapter configured in new mode.
diff --git a/drivers/dma/cnxk/cnxk_dma_event_dp.h 
b/drivers/dma/cnxk/cnxk_dma_event_dp.h
new file mode 100644
index 00..5f890ab18b
--- /dev/null
+++ b/drivers/dma/cnxk/cnxk_dma_event_dp.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2023 Marvell.
+ */
+
+#ifndef _CNXK_DMA_EVENT_DP_H_
+#define _CNXK_DMA_EVENT_DP_H_
+
+#include 
+
+#include 
+#include 
+
+__rte_internal
+uint16_t cn10k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t 
nb_events);
+
+__rte_internal
+uint16_t cn9k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t 
nb_events);
+
+__rte_internal
+uint16_t cn9k_dma_adapter_dual_enqueue(void *ws, struct rte_event ev[], 
uint16_t nb_events);
+
+__rte_internal
+uintptr_t cnxk_dma_adapter_dequeue(uintptr_t get_work1);
+#endif /* _CNXK_DMA_EVENT_DP_H_ */
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 48ab09cc38..4ab3cfbdf2 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -589,10 +589,11 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv 
__rte_unused, struct rte_pci_de
dmadev->fp_obj->copy_sg = cn10k_dmadev_copy_sg;
}
 
+   dpivf->mcs_lock = NULL;
rdpi = &dpivf->rdpi;
 
rdpi->pci_dev = pci_dev;
-   rc = roc_dpi_dev_init(rdpi, 0);
+   rc = roc_dpi_dev_init(rdpi, offsetof(struct cnxk_dpi_compl_s, wqecs));
if (rc < 0)
goto err_out_free;
 
diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
index 350ae73b5c..610a360ba2 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.h
+++ b/drivers/dma/cnxk/cnxk_dmadev.h
@@ -14,11 +14,14 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
 #include 
 
+#include "cnxk_dma_event_dp.h"
+
 #define CNXK_DPI_MAX_POINTER   15
 #define CNXK_DPI_STRM_INC(s, var)  ((s).var = ((s).var + 1) & 
(s).max_cnt)
 #define CNXK_DPI_STRM_DEC(s, var)  ((s).var = ((s).var - 1) == -1 ? 
(s).max_cnt :  \
@@ -40,6 +43,11 @@
  */
 #define CNXK_DPI_REQ_CDATA 0xFF
 
+/* Set Completion data to 0xDEADBEEF when request submitted for SSO.
+ * This helps differentiate if the dequeue is called after cnxk enueue.
+ */
+#define CNXK_DPI_REQ_SSO_CDATA0xDEADBEEF
+
 union cnxk_dpi_instr_cmd {
uint64_t u;
struct cn9k_dpi_instr_cmd {
@@ -85,7 +93,10 @@ union cnxk_dpi_instr_cmd {
 
 struct cnxk_dpi_compl_s {
uint64_t cdata;
-   void *cb_data;
+   void *op;
+   uint16_t dev_id;
+   uint16_t vchan;
+   uint32_t wqecs;
 };
 
 struct cnxk_dpi_cdesc_data_s {
@@ -95,6 +106,11 @@ struct cnxk_dpi_cdesc_data_s {
uint16_t tail;
 };
 
+struct cnxk_dma_adapter_info {
+   bool enabled;   /* Set if vchan queue is added to dma 
adapter. */
+   struct rte_mempool *req_mp; /* DMA inflight request mempool. */
+};
+
 struct cnxk_dpi_conf {
union cnxk_dpi_instr_cmd cmd;
struct cnxk_dpi_cdesc_data_s c_desc;
@@ -103,6 +119,7 @@ struct cnxk_dpi_conf {
uint16_t desc_idx;
struct rte_dma_stats stats;
uint64_t completed_offset;
+   struct cnxk_dma_adapter_info adapter_info;
 };
 
 struct cnxk_dpi_vf_s {
@@ -112,6 +129,7 @@ struct cnxk_dpi_vf_s {
uint16_t chunk_size_m1;
struct rte_mempool *chunk_pool;
struct cnxk_dpi_conf conf[CNXK_DPI_MAX_VCHANS_PER_QUEUE];
+   RTE_ATOMIC(rte_mcslock_t *) mcs_lock;
/* Slow path */
struct roc_dpi rdpi;
uint32_t aura;
diff --git a/drive

[PATCH v3 3/3] event/cnxk: support DMA event functions

[Amit Prakash Shukla]

Added support of dma driver callback assignment to eventdev
enqueue and dequeue. The change also defines dma adapter
capabilities function.

Depends-on: series-30612 ("lib/dmadev: get DMA device using device ID")

Signed-off-by: Amit Prakash Shukla 
---
v3:
- Rebased and fixed compilation error.

v2:
- Added dual workslot enqueue support.
- Fixed compilation error.

 drivers/event/cnxk/cn10k_eventdev.c  | 70 +
 drivers/event/cnxk/cn10k_worker.h|  3 +
 drivers/event/cnxk/cn9k_eventdev.c   | 67 
 drivers/event/cnxk/cn9k_worker.h |  3 +
 drivers/event/cnxk/cnxk_eventdev.h   |  3 +
 drivers/event/cnxk/cnxk_eventdev_adptr.c | 97 
 drivers/event/cnxk/meson.build   |  3 +-
 7 files changed, 244 insertions(+), 2 deletions(-)

diff --git a/drivers/event/cnxk/cn10k_eventdev.c 
b/drivers/event/cnxk/cn10k_eventdev.c
index 221f419055..18f3b402c9 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -8,6 +8,9 @@
 #include "cn10k_cryptodev_ops.h"
 #include "cnxk_eventdev.h"
 #include "cnxk_worker.h"
+#include "cnxk_dma_event_dp.h"
+
+#include 
 
 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops)   
\
deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)]
@@ -477,6 +480,8 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
else
event_dev->ca_enqueue = 
cn10k_cpt_sg_ver1_crypto_adapter_enqueue;
 
+   event_dev->dma_enqueue = cn10k_dma_adapter_enqueue;
+
if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue, 
sso_hws_tx_adptr_enq_seg);
else
@@ -1020,6 +1025,67 @@ cn10k_crypto_adapter_vec_limits(const struct 
rte_eventdev *event_dev,
return 0;
 }
 
+static int
+cn10k_dma_adapter_caps_get(const struct rte_eventdev *event_dev,
+  const int16_t dma_dev_id, uint32_t *caps)
+{
+   struct rte_dma_dev *dma_dev;
+
+   RTE_SET_USED(event_dev);
+
+   dma_dev = rte_dma_pmd_get_dev_by_id(dma_dev_id);
+   if (dma_dev == NULL)
+   return -EINVAL;
+
+   CNXK_VALID_DEV_OR_ERR_RET(dma_dev->device, "cnxk_dmadev_pci_driver", 
EINVAL);
+
+   *caps = RTE_EVENT_DMA_ADAPTER_CAP_INTERNAL_PORT_OP_FWD;
+
+   return 0;
+}
+
+static int
+cn10k_dma_adapter_vchan_add(const struct rte_eventdev *event_dev,
+   const int16_t dma_dev_id, uint16_t vchan_id,
+   const struct rte_event *event)
+{
+   struct rte_dma_dev *dma_dev;
+   int ret;
+
+   RTE_SET_USED(event);
+   dma_dev = rte_dma_pmd_get_dev_by_id(dma_dev_id);
+   if (dma_dev == NULL)
+   return -EINVAL;
+
+   CNXK_VALID_DEV_OR_ERR_RET(dma_dev->device, "cnxk_dmadev_pci_driver", 
EINVAL);
+
+   cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
+
+   ret = cnxk_dma_adapter_vchan_add(event_dev, dma_dev_id, vchan_id);
+   cn10k_sso_set_priv_mem(event_dev, NULL);
+
+   return ret;
+}
+
+static int
+cn10k_dma_adapter_vchan_del(const struct rte_eventdev *event_dev,
+   const int16_t dma_dev_id, uint16_t vchan_id)
+{
+   struct rte_dma_dev *dma_dev;
+
+   RTE_SET_USED(event_dev);
+
+   dma_dev = rte_dma_pmd_get_dev_by_id(dma_dev_id);
+   if (dma_dev == NULL)
+   return -EINVAL;
+
+   CNXK_VALID_DEV_OR_ERR_RET(dma_dev->device, "cnxk_dmadev_pci_driver", 
EINVAL);
+
+   return cnxk_dma_adapter_vchan_del(dma_dev_id, vchan_id);
+}
+
+
+
 static struct eventdev_ops cn10k_sso_dev_ops = {
.dev_infos_get = cn10k_sso_info_get,
.dev_configure = cn10k_sso_dev_configure,
@@ -1061,6 +1127,10 @@ static struct eventdev_ops cn10k_sso_dev_ops = {
.crypto_adapter_queue_pair_del = cn10k_crypto_adapter_qp_del,
.crypto_adapter_vector_limits_get = cn10k_crypto_adapter_vec_limits,
 
+   .dma_adapter_caps_get = cn10k_dma_adapter_caps_get,
+   .dma_adapter_vchan_add = cn10k_dma_adapter_vchan_add,
+   .dma_adapter_vchan_del = cn10k_dma_adapter_vchan_del,
+
.xstats_get = cnxk_sso_xstats_get,
.xstats_reset = cnxk_sso_xstats_reset,
.xstats_get_names = cnxk_sso_xstats_get_names,
diff --git a/drivers/event/cnxk/cn10k_worker.h 
b/drivers/event/cnxk/cn10k_worker.h
index 8aa916fa12..0036495d98 100644
--- a/drivers/event/cnxk/cn10k_worker.h
+++ b/drivers/event/cnxk/cn10k_worker.h
@@ -7,6 +7,7 @@
 
 #include 
 #include "cn10k_cryptodev_event_dp.h"
+#include "cnxk_dma_event_dp.h"
 #include "cn10k_rx.h"
 #include "cnxk_worker.h"
 #include "cn10k_eventdev.h"
@@ -236,6 +237,8 @@ cn10k_sso_hws_post_process(struct cn10k_sso_hws *ws, 
uint64_t *u64,
/* Mark vector mempool object as get */
RTE_MEMPOOL_CHECK_COOKIES(rte_mempool_from_obj((void *)u64[1]),
  (void **)&u64[1], 1, 1);
+   } else if (C

[DPDK/core Bug 1385] rt_bitops.h fails to give implied atomicity guarantees

[bugzilla]

https://bugs.dpdk.org/show_bug.cgi?id=1385

Bug ID: 1385
   Summary: rt_bitops.h fails to give implied atomicity guarantees
   Product: DPDK
   Version: 23.11
  Hardware: All
OS: All
Status: UNCONFIRMED
  Severity: normal
  Priority: Normal
 Component: core
  Assignee: dev@dpdk.org
  Reporter: mattias.ronnb...@ericsson.com
  Target Milestone: ---

The documentation (and the naming) for the rte_bit_relaxed_*() functions in
rte_bitops.h makes clear that all such functions have a relaxed memory order.

The use of the term "relaxed", which most C programmers likely are familiar
with from the C11 memory model specification, itself implies that the
operations are supposed to be atomic. Why otherwise mention the memory
operations are relaxed? Relaxed is the default for non-atomic loads and stores.
In addition, why otherwise declare the address as volatile?

An even stronger indication are the test-and-set family of "relaxed"
rte_bitops.h functions. "Test-and-set" in the low-level C programming context
always implies an atomic operation. A non-atomic test-and-set does not make
sense.

In summary, a perfectly valid interpretation of the API contract is that the
functions are atomic.

However, their implementation is not, which may not be obvious to the causal
API user.

-- 
You are receiving this mail because:
You are the assignee for the bug.

Re: [EXT] [PATCH v4 01/12] eventdev: improve doxygen introduction text

[Bruce Richardson]

On Mon, Feb 26, 2024 at 04:51:25AM +, Pavan Nikhilesh Bhagavatula wrote:
> > Make some textual improvements to the introduction to eventdev and event
> > devices in the eventdev header file. This text appears in the doxygen
> > output for the header file, and introduces the key concepts, for
> > example: events, event devices, queues, ports and scheduling.
> > 
> > This patch makes the following improvements:
> > * small textual fixups, e.g. correcting use of singular/plural
> > * rewrites of some sentences to improve clarity
> > * using doxygen markdown to split the whole large block up into
> >   sections, thereby making it easier to read.
> > 
> > No large-scale changes are made, and blocks are not reordered
> > 
> > Signed-off-by: Bruce Richardson 
> > 
> 
> Acked-by: Pavan Nikhilesh 
> 
> > ---
> > V4: reworked following review by Jerin
> > V3: reworked following feedback from Mattias
> > ---
> >  lib/eventdev/rte_eventdev.h | 140 ++--
> >  1 file changed, 86 insertions(+), 54 deletions(-)
> > 


> > + * In contrast, in an event-driver model, as supported by this "eventdev"
> 
> Should be event-driven model.
> 

Yes, good spot. Jerin, can you just fix this typo on apply, please?

[PATCH] net/virtio-user: support IOVA as PA mode for vDPA backend

[Srujana Challa]

Disable use_va flag for VDPA backend type and fixes the issues
with shadow control command processing, when it is disabled.
This will help to make virtio user driver works in IOVA
as PA mode for vDPA backend.

Signed-off-by: Srujana Challa 
---
 drivers/net/virtio/virtio_ring.h  | 12 ++-
 .../net/virtio/virtio_user/virtio_user_dev.c  | 86 ++-
 drivers/net/virtio/virtio_user_ethdev.c   | 10 ++-
 drivers/net/virtio/virtqueue.c|  4 +-
 4 files changed, 65 insertions(+), 47 deletions(-)

diff --git a/drivers/net/virtio/virtio_ring.h b/drivers/net/virtio/virtio_ring.h
index e848c0b73b..998605dbb5 100644
--- a/drivers/net/virtio/virtio_ring.h
+++ b/drivers/net/virtio/virtio_ring.h
@@ -83,6 +83,7 @@ struct vring_packed_desc_event {
 
 struct vring_packed {
unsigned int num;
+   rte_iova_t desc_iova;
struct vring_packed_desc *desc;
struct vring_packed_desc_event *driver;
struct vring_packed_desc_event *device;
@@ -90,6 +91,7 @@ struct vring_packed {
 
 struct vring {
unsigned int num;
+   rte_iova_t desc_iova;
struct vring_desc  *desc;
struct vring_avail *avail;
struct vring_used  *used;
@@ -149,11 +151,12 @@ vring_size(struct virtio_hw *hw, unsigned int num, 
unsigned long align)
return size;
 }
 static inline void
-vring_init_split(struct vring *vr, uint8_t *p, unsigned long align,
-unsigned int num)
+vring_init_split(struct vring *vr, uint8_t *p, rte_iova_t iova,
+unsigned long align, unsigned int num)
 {
vr->num = num;
vr->desc = (struct vring_desc *) p;
+   vr->desc_iova = iova;
vr->avail = (struct vring_avail *) (p +
num * sizeof(struct vring_desc));
vr->used = (void *)
@@ -161,11 +164,12 @@ vring_init_split(struct vring *vr, uint8_t *p, unsigned 
long align,
 }
 
 static inline void
-vring_init_packed(struct vring_packed *vr, uint8_t *p, unsigned long align,
-unsigned int num)
+vring_init_packed(struct vring_packed *vr, uint8_t *p, rte_iova_t iova,
+ unsigned long align, unsigned int num)
 {
vr->num = num;
vr->desc = (struct vring_packed_desc *)p;
+   vr->desc_iova = iova;
vr->driver = (struct vring_packed_desc_event *)(p +
vr->num * sizeof(struct vring_packed_desc));
vr->device = (struct vring_packed_desc_event *)
diff --git a/drivers/net/virtio/virtio_user/virtio_user_dev.c 
b/drivers/net/virtio/virtio_user/virtio_user_dev.c
index d395fc1676..55e71e4842 100644
--- a/drivers/net/virtio/virtio_user/virtio_user_dev.c
+++ b/drivers/net/virtio/virtio_user/virtio_user_dev.c
@@ -62,6 +62,7 @@ virtio_user_kick_queue(struct virtio_user_dev *dev, uint32_t 
queue_sel)
struct vhost_vring_state state;
struct vring *vring = &dev->vrings.split[queue_sel];
struct vring_packed *pq_vring = &dev->vrings.packed[queue_sel];
+   uint64_t desc_addr, avail_addr, used_addr;
struct vhost_vring_addr addr = {
.index = queue_sel,
.log_guest_addr = 0,
@@ -81,16 +82,23 @@ virtio_user_kick_queue(struct virtio_user_dev *dev, 
uint32_t queue_sel)
}
 
if (dev->features & (1ULL << VIRTIO_F_RING_PACKED)) {
-   addr.desc_user_addr =
-   (uint64_t)(uintptr_t)pq_vring->desc;
-   addr.avail_user_addr =
-   (uint64_t)(uintptr_t)pq_vring->driver;
-   addr.used_user_addr =
-   (uint64_t)(uintptr_t)pq_vring->device;
+   desc_addr = pq_vring->desc_iova;
+   avail_addr = desc_addr + pq_vring->num * sizeof(struct 
vring_packed_desc);
+   used_addr =  RTE_ALIGN_CEIL(avail_addr + sizeof(struct 
vring_packed_desc_event),
+   VIRTIO_VRING_ALIGN);
+
+   addr.desc_user_addr = desc_addr;
+   addr.avail_user_addr = avail_addr;
+   addr.used_user_addr = used_addr;
} else {
-   addr.desc_user_addr = (uint64_t)(uintptr_t)vring->desc;
-   addr.avail_user_addr = (uint64_t)(uintptr_t)vring->avail;
-   addr.used_user_addr = (uint64_t)(uintptr_t)vring->used;
+   desc_addr = vring->desc_iova;
+   avail_addr = desc_addr + vring->num * sizeof(struct vring_desc);
+   used_addr = 
RTE_ALIGN_CEIL((uintptr_t)(&vring->avail->ring[vring->num]),
+  VIRTIO_VRING_ALIGN);
+
+   addr.desc_user_addr = desc_addr;
+   addr.avail_user_addr = avail_addr;
+   addr.used_user_addr = used_addr;
}
 
state.index = queue_sel;
@@ -885,11 +893,11 @@ static uint32_t
 virtio_user_handle_ctrl_msg_split(struct virtio_user_dev *dev, struct vring 
*vring,
uint16_t idx_hdr)
 {
-   struct virtio_net_ctrl_hdr *hdr;
virt

RE: [v2 01/10] net/mlx5/hws: skip RTE item when inserting rules by index

[Raslan Darawsheh]

Hi,

> -Original Message-
> From: Itamar Gozlan 
> Sent: Sunday, February 18, 2024 7:11 AM
> To: Itamar Gozlan ; Erez Shitrit ;
> Hamdan Agbariya ; Yevgeny Kliteynik
> ; Slava Ovsiienko ; NBU-
> Contact-Thomas Monjalon (EXTERNAL) ; Suanming
> Mou ; Dariusz Sosnowski
> ; Ori Kam ; Matan Azrad
> ; Alex Vesker 
> Cc: dev@dpdk.org
> Subject: [v2 01/10] net/mlx5/hws: skip RTE item when inserting rules by index
> 
> The location of indexed rules is determined by the index, not the item hash. A
> matcher test is added to prevent access to non-existent items.
> This avoids unnecessary processing and potential segmentation faults.
> 
> Fixes: 405242c ("net/mlx5/hws: add rule object")
> Signed-off-by: Itamar Gozlan 
> Acked-by: Matan Azrad 


Fixed few fixes tags, 
Series applied to next-net-mlx,

Kindest regards
Raslan Darawsheh

[PATCH v3] examples/ipsec-secgw: fix cryptodev to SA mapping

[Radu Nicolau]

There are use cases where a SA should be able to use different cryptodevs on
different lcores, for example there can be cryptodevs with just 1 qp per VF.
For this purpose this patch relaxes the check in create lookaside session 
function.
Also add a check to verify that a CQP is available for the current lcore.

Fixes: a8ade12123c3 ("examples/ipsec-secgw: create lookaside sessions at init")
Cc: sta...@dpdk.org
Cc: vfia...@marvell.com

Signed-off-by: Radu Nicolau 
Tested-by: Ting-Kai Ku 
Acked-by: Ciara Power 
Acked-by: Kai Ji 
---
v3: check if the cryptodev are not of the same type

 examples/ipsec-secgw/ipsec.c | 25 -
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/examples/ipsec-secgw/ipsec.c b/examples/ipsec-secgw/ipsec.c
index f5cec4a928..b59576c049 100644
--- a/examples/ipsec-secgw/ipsec.c
+++ b/examples/ipsec-secgw/ipsec.c
@@ -288,10 +288,21 @@ create_lookaside_session(struct ipsec_ctx 
*ipsec_ctx_lcore[],
if (cdev_id == RTE_CRYPTO_MAX_DEVS)
cdev_id = ipsec_ctx->tbl[cdev_id_qp].id;
else if (cdev_id != ipsec_ctx->tbl[cdev_id_qp].id) {
-   RTE_LOG(ERR, IPSEC,
-   "SA mapping to multiple cryptodevs is "
-   "not supported!");
-   return -EINVAL;
+   struct rte_cryptodev_info dev_info_1, dev_info_2;
+   rte_cryptodev_info_get(cdev_id, &dev_info_1);
+   rte_cryptodev_info_get(ipsec_ctx->tbl[cdev_id_qp].id,
+   &dev_info_2);
+   if (dev_info_1.driver_id == dev_info_2.driver_id) {
+   RTE_LOG(WARNING, IPSEC,
+   "SA mapped to multiple cryptodevs for 
SPI %d\n",
+   sa->spi);
+
+   } else {
+   RTE_LOG(WARNING, IPSEC,
+   "SA mapped to multiple cryptodevs of 
different types for SPI %d\n",
+   sa->spi);
+
+   }
}
 
/* Store per core queue pair information */
@@ -908,7 +919,11 @@ ipsec_enqueue(ipsec_xform_fn xform_func, struct ipsec_ctx 
*ipsec_ctx,
continue;
}
 
-   enqueue_cop(sa->cqp[ipsec_ctx->lcore_id], &priv->cop);
+   if (likely(sa->cqp[ipsec_ctx->lcore_id]))
+   enqueue_cop(sa->cqp[ipsec_ctx->lcore_id], &priv->cop);
+   else
+   RTE_LOG(ERR, IPSEC, "No CQP available for lcore %d\n",
+   ipsec_ctx->lcore_id);
}
 }
 
-- 
2.34.1

Re: [PATCH v1] app/testpmd : return if no packets in GRO heavy weight mode

[Ferruh Yigit]

On 2/25/2024 6:16 AM, Kumara Parameshwaran wrote:
> If there are no packets flushed in GRO heavy weight mode,
> return false as this fall through code would return true
> indicating that packets are available
> 
> Fixes: 461c287ab553 ("app/testpmd: fix GRO packets flush on timeout")
> Cc: sta...@dpdk.org
> 
> Signed-off-by: Kumara Parameshwaran 
> 
Reviewed-by: Ferruh Yigit 
Applied to dpdk-next-net/main, thanks.

Re: [PATCH 1/2] baseband/fpga_5gnr_fec: use new barrier API

[Maxime Coquelin]

Hello,

On 2/22/24 19:05, Chautru, Nicolas wrote:

Hi Maxime,

Why would we change this here and now? Is the intent not to use new suggested 
semantics for new patches only?


The pull request was rejected because of the use of such barrier, which 
is reported by checkpatch.


### [PATCH] baseband/fpga_5gnr_fec: add AGX100 support
Warning in drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c:
Using rte_smp_[r/w]mb


Are all DPDK drivers being changed?


My understanding is that for now, only new occurrences are prohibited,
can you confirm Tyler?

If so we could only change for now the patch adding ACX100.
But... I preferred doing the changes for all bbdev drivers for
consistency.


I am unsure we would want to change these drivers, this is kind of risk 
introduced by code churn that gets ecosystem unwilling to move to latest 
version.


I think it is better to change now that we are far from the next LTS.


These memory barriers issues are awful to troubleshoot or properly validate, so 
personally quite reluctant to change.


If I disassemble fpga_dequeue_enc() with and without the patch, I cannot
spot a difference.

Thomas, are you waiting for this series to be applied to take the pull
request that was initially for -rc1?

Thanks,
Maxime


Thanks
Nic


-Original Message-
From: Maxime Coquelin 
Sent: Thursday, February 22, 2024 8:21 AM
To: dev@dpdk.org; Chautru, Nicolas ; Vargas,
Hernan ; Marchand, David
; tho...@monjalon.net;
roret...@linux.microsoft.com
Cc: Maxime Coquelin 
Subject: [PATCH 1/2] baseband/fpga_5gnr_fec: use new barrier API

rte_smp_rmb() is deprecated, use the new API instead as suggested in
rte_atomic header.

Signed-off-by: Maxime Coquelin 
---
  drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
index efc1d3a772..314c87350e 100644
--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
@@ -2661,7 +2661,7 @@ vc_5gnr_dequeue_ldpc_enc_one_op_cb(struct
fpga_5gnr_queue *q, struct rte_bbdev_e
return -1;

/* make sure the response is read atomically */
-   rte_smp_rmb();
+   rte_atomic_thread_fence(rte_memory_order_acquire);

rte_bbdev_log_debug("DMA response desc %p", desc);

@@ -2690,7 +2690,7 @@ agx100_dequeue_ldpc_enc_one_op_cb(struct
fpga_5gnr_queue *q, struct rte_bbdev_en
return -1;

/* make sure the response is read atomically. */
-   rte_smp_rmb();
+   rte_atomic_thread_fence(rte_memory_order_acquire);

rte_bbdev_log_debug("DMA response desc %p", desc);

@@ -2722,7 +2722,7 @@ vc_5gnr_dequeue_ldpc_dec_one_op_cb(struct
fpga_5gnr_queue *q, struct rte_bbdev_d
return -1;

/* make sure the response is read atomically */
-   rte_smp_rmb();
+   rte_atomic_thread_fence(rte_memory_order_acquire);

  #ifdef RTE_LIBRTE_BBDEV_DEBUG
vc_5gnr_print_dma_dec_desc_debug_info(desc);
@@ -2768,7 +2768,7 @@ agx100_dequeue_ldpc_dec_one_op_cb(struct
fpga_5gnr_queue *q, struct rte_bbdev_de
return -1;

/* make sure the response is read atomically. */
-   rte_smp_rmb();
+   rte_atomic_thread_fence(rte_memory_order_acquire);

  #ifdef RTE_LIBRTE_BBDEV_DEBUG
agx100_print_dma_dec_desc_debug_info(desc);
--
2.43.0

Re: [PATCH v5 01/39] eal: use C11 alignas

[Bruce Richardson]

On Fri, Feb 23, 2024 at 11:03:36AM -0800, Tyler Retzlaff wrote:
> The current location used for __rte_aligned(a) for alignment of types
> and variables is not compatible with MSVC. There is only a single
> location accepted by both toolchains.
> 
> For variables standard C11 offers alignas(a) supported by conformant
> compilers i.e. both MSVC and GCC.
> 
> For types the standard offers no alignment facility that compatibly
> interoperates with C and C++ but may be achieved by relocating the
> placement of __rte_aligned(a) to the aforementioned location accepted
> by all currently supported toolchains.
> 
> To allow alignment for both compilers do the following:
> 
> * Expand __rte_aligned(a) to __declspec(align(a)) when building
>   with MSVC.
> 
> * Move __rte_aligned from the end of {struct,union} definitions to
>   be between {struct,union} and tag.
> 
>   The placement between {struct,union} and the tag allows the desired
>   alignment to be imparted on the type regardless of the toolchain being
>   used for all of GCC, LLVM, MSVC compilers building both C and C++.
> 
> * Replace use of __rte_aligned(a) on variables/fields with alignas(a).
> 
> Signed-off-by: Tyler Retzlaff 
> Acked-by: Morten Brørup 
> ---
>  lib/eal/arm/include/rte_vect.h   |  4 ++--
>  lib/eal/common/malloc_elem.h |  4 ++--
>  lib/eal/common/malloc_heap.h |  4 ++--
>  lib/eal/common/rte_keepalive.c   |  3 ++-
>  lib/eal/common/rte_random.c  |  4 ++--
>  lib/eal/common/rte_service.c |  8 
>  lib/eal/include/generic/rte_atomic.h |  4 ++--
>  lib/eal/include/rte_common.h | 23 +++
>  lib/eal/loongarch/include/rte_vect.h |  8 
>  lib/eal/ppc/include/rte_vect.h   |  4 ++--
>  lib/eal/riscv/include/rte_vect.h |  4 ++--
>  lib/eal/x86/include/rte_vect.h   |  4 ++--
>  lib/eal/x86/rte_power_intrinsics.c   | 10 ++
>  13 files changed, 47 insertions(+), 37 deletions(-)
> 
Just to chime in with one additional benefit of this change - it will
prevent static analysers, IDEs and doxygen[1] from ever mistaking the
__rte_aligned tag at the end of a struct define as being a variable
definition. In the absence of a macro definition from our DPDK header files
this defines a variable called __rte_cache_aligned (as in [1]!):

   struct xyz {
   } __rte_cache_aligned;

while this just gives an error to let you know the definiton is missing:

  struct __rte_cache_aligned xyz {
  };

Acked-by: Bruce Richardson 

[1] 
http://doc.dpdk.org/api/structrte__ring.html#a43d0b019eced25dc6c357f3b4f0f47e5

[PATCH] net/virtio-user: support IOVA as PA mode for vDPA backend

[Srujana Challa]

Disable use_va flag for VDPA backend type and fixes the issues
with shadow control command processing, when it is disabled.
This will help to make virtio user driver works in IOVA
as PA mode for vDPA backend.

Signed-off-by: Srujana Challa 
---
 drivers/net/virtio/virtio_ring.h  | 12 ++-
 .../net/virtio/virtio_user/virtio_user_dev.c  | 86 ++-
 drivers/net/virtio/virtio_user_ethdev.c   | 10 ++-
 drivers/net/virtio/virtqueue.c|  4 +-
 4 files changed, 65 insertions(+), 47 deletions(-)

diff --git a/drivers/net/virtio/virtio_ring.h b/drivers/net/virtio/virtio_ring.h
index e848c0b73b..998605dbb5 100644
--- a/drivers/net/virtio/virtio_ring.h
+++ b/drivers/net/virtio/virtio_ring.h
@@ -83,6 +83,7 @@ struct vring_packed_desc_event {
 
 struct vring_packed {
unsigned int num;
+   rte_iova_t desc_iova;
struct vring_packed_desc *desc;
struct vring_packed_desc_event *driver;
struct vring_packed_desc_event *device;
@@ -90,6 +91,7 @@ struct vring_packed {
 
 struct vring {
unsigned int num;
+   rte_iova_t desc_iova;
struct vring_desc  *desc;
struct vring_avail *avail;
struct vring_used  *used;
@@ -149,11 +151,12 @@ vring_size(struct virtio_hw *hw, unsigned int num, 
unsigned long align)
return size;
 }
 static inline void
-vring_init_split(struct vring *vr, uint8_t *p, unsigned long align,
-unsigned int num)
+vring_init_split(struct vring *vr, uint8_t *p, rte_iova_t iova,
+unsigned long align, unsigned int num)
 {
vr->num = num;
vr->desc = (struct vring_desc *) p;
+   vr->desc_iova = iova;
vr->avail = (struct vring_avail *) (p +
num * sizeof(struct vring_desc));
vr->used = (void *)
@@ -161,11 +164,12 @@ vring_init_split(struct vring *vr, uint8_t *p, unsigned 
long align,
 }
 
 static inline void
-vring_init_packed(struct vring_packed *vr, uint8_t *p, unsigned long align,
-unsigned int num)
+vring_init_packed(struct vring_packed *vr, uint8_t *p, rte_iova_t iova,
+ unsigned long align, unsigned int num)
 {
vr->num = num;
vr->desc = (struct vring_packed_desc *)p;
+   vr->desc_iova = iova;
vr->driver = (struct vring_packed_desc_event *)(p +
vr->num * sizeof(struct vring_packed_desc));
vr->device = (struct vring_packed_desc_event *)
diff --git a/drivers/net/virtio/virtio_user/virtio_user_dev.c 
b/drivers/net/virtio/virtio_user/virtio_user_dev.c
index d395fc1676..c8d28cdd35 100644
--- a/drivers/net/virtio/virtio_user/virtio_user_dev.c
+++ b/drivers/net/virtio/virtio_user/virtio_user_dev.c
@@ -62,6 +62,7 @@ virtio_user_kick_queue(struct virtio_user_dev *dev, uint32_t 
queue_sel)
struct vhost_vring_state state;
struct vring *vring = &dev->vrings.split[queue_sel];
struct vring_packed *pq_vring = &dev->vrings.packed[queue_sel];
+   uint64_t desc_addr, avail_addr, used_addr;
struct vhost_vring_addr addr = {
.index = queue_sel,
.log_guest_addr = 0,
@@ -81,16 +82,23 @@ virtio_user_kick_queue(struct virtio_user_dev *dev, 
uint32_t queue_sel)
}
 
if (dev->features & (1ULL << VIRTIO_F_RING_PACKED)) {
-   addr.desc_user_addr =
-   (uint64_t)(uintptr_t)pq_vring->desc;
-   addr.avail_user_addr =
-   (uint64_t)(uintptr_t)pq_vring->driver;
-   addr.used_user_addr =
-   (uint64_t)(uintptr_t)pq_vring->device;
+   desc_addr = pq_vring->desc_iova;
+   avail_addr = desc_addr + pq_vring->num * sizeof(struct 
vring_packed_desc);
+   used_addr =  RTE_ALIGN_CEIL(avail_addr + sizeof(struct 
vring_packed_desc_event),
+   VIRTIO_VRING_ALIGN);
+
+   addr.desc_user_addr = desc_addr;
+   addr.avail_user_addr = avail_addr;
+   addr.used_user_addr = used_addr;
} else {
-   addr.desc_user_addr = (uint64_t)(uintptr_t)vring->desc;
-   addr.avail_user_addr = (uint64_t)(uintptr_t)vring->avail;
-   addr.used_user_addr = (uint64_t)(uintptr_t)vring->used;
+   desc_addr = vring->desc_iova;
+   avail_addr = desc_addr + vring->num * sizeof(struct vring_desc);
+   used_addr = 
RTE_ALIGN_CEIL((uintptr_t)(&vring->avail->ring[vring->num]),
+  VIRTIO_VRING_ALIGN);
+
+   addr.desc_user_addr = desc_addr;
+   addr.avail_user_addr = avail_addr;
+   addr.used_user_addr = used_addr;
}
 
state.index = queue_sel;
@@ -885,11 +893,11 @@ static uint32_t
 virtio_user_handle_ctrl_msg_split(struct virtio_user_dev *dev, struct vring 
*vring,
uint16_t idx_hdr)
 {
-   struct virtio_net_ctrl_hdr *hdr;
virt

[PATCH] net/mlx5: link status change for bonding cases

[Haifei Luo]

The current implementation of mlx5_dev_interrupt_nl_cb routine first
compares if event netlink if_index belongs to the same device.
This is not fully correct for the bonding device since the bonding
master and slave interface netlink events indicate the bonding link
status change as well. Add check for if_index is related to the
bonding's master/slave.

The following step is that it compares the device link status before
and after the netlink event handling. There are also the bonding specifics
and it should compare the link status of the bonding master to detect
the actual status change.

Signed-off-by: Haifei Luo 
---
 drivers/net/mlx5/linux/mlx5_ethdev_os.c | 55 ++---
 1 file changed, 50 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c 
b/drivers/net/mlx5/linux/mlx5_ethdev_os.c
index dd5a0c5..a9b94f8 100644
--- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c
+++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c
@@ -768,6 +768,47 @@ struct ethtool_link_settings {
}
 }
 
+static bool
+mlx5_dev_nl_ifindex_verify(uint32_t if_index, struct mlx5_priv *priv)
+{
+   struct mlx5_bond_info *bond = &priv->sh->bond;
+   int i;
+
+   if (bond->n_port == 0)
+   return (if_index == priv->if_index);
+
+   if (if_index == bond->ifindex)
+   return true;
+   for (i = 0; i < bond->n_port; i++) {
+   if (i >= MLX5_BOND_MAX_PORTS)
+   return false;
+   if (if_index == bond->ports[i].ifindex)
+   return true;
+   }
+
+   return false;
+}
+
+static void
+mlx5_link_update_bond(struct rte_eth_dev *dev)
+{
+   struct mlx5_priv *priv = dev->data->dev_private;
+   struct mlx5_bond_info *bond = &priv->sh->bond;
+   struct ifreq ifr = (struct ifreq) {
+   .ifr_flags = 0,
+   };
+   int ret;
+
+   ret = mlx5_ifreq_by_ifname(bond->ifname, SIOCGIFFLAGS, &ifr);
+   if (ret) {
+   DRV_LOG(WARNING, "ifname %s ioctl(SIOCGIFFLAGS) failed: %s",
+   bond->ifname, strerror(rte_errno));
+   return;
+   }
+   dev->data->dev_link.link_status =
+   ((ifr.ifr_flags & IFF_UP) && (ifr.ifr_flags & IFF_RUNNING));
+}
+
 static void
 mlx5_dev_interrupt_nl_cb(struct nlmsghdr *hdr, void *cb_arg)
 {
@@ -790,16 +831,20 @@ struct ethtool_link_settings {
!dev->data->dev_conf.intr_conf.lsc)
break;
priv = dev->data->dev_private;
-   if (priv->if_index == if_index) {
+   if (mlx5_dev_nl_ifindex_verify(if_index, priv)) {
/* Block logical LSC events. */
uint16_t prev_status = dev->data->dev_link.link_status;
 
-   if (mlx5_link_update(dev, 0) < 0)
+   if (mlx5_link_update(dev, 0) < 0) {
DRV_LOG(ERR, "Failed to update link status: %s",
rte_strerror(rte_errno));
-   else if (prev_status != dev->data->dev_link.link_status)
-   rte_eth_dev_callback_process
-   (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
+   } else {
+   if (priv->sh->bond.n_port)
+   mlx5_link_update_bond(dev);
+   if (prev_status != 
dev->data->dev_link.link_status)
+   rte_eth_dev_callback_process
+   (dev, RTE_ETH_EVENT_INTR_LSC, 
NULL);
+   }
break;
}
}
-- 
1.8.3.1

RE: [PATCH v3 0/2] net/mlx5: update pattern validations

[Raslan Darawsheh]

Hi,


> -Original Message-
> From: Gregory Etelson 
> Sent: Monday, February 12, 2024 3:59 PM
> To: dev@dpdk.org
> Cc: Gregory Etelson ; Maayan Kashani
> ; Dariusz Sosnowski 
> Subject: [PATCH v3 0/2] net/mlx5: update pattern validations
> 
> PMD updates `rte_errno` if pattern template validation failed:
> E2BIG - pattern too big for PMD
> ENOTSUP - pattern not supported by PMD
> ENOMEM - PMD allocation failure
> 
> Gregory Etelson (2):
>   net/mlx5/hws: definer, update pattern validations
>   net/mlx5: improve pattern template validation
> 
>  drivers/net/mlx5/hws/mlx5dr_definer.c |   4 +-
>  drivers/net/mlx5/mlx5.h   |   1 +
>  drivers/net/mlx5/mlx5_flow_hw.c   | 121
> ++
>  3 files changed, 125 insertions(+), 1 deletion(-)
> 
> Acked-by: Dariusz Sosnowski 
> --
> 2.39.2

Series applied to next-net-mlx

Kindest regards
Raslan Darawsheh

RE: [PATCH v5 02/39] eal: redefine macro to be integer literal for MSVC

[Konstantin Ananyev]

> MSVC __declspec(align(#)) is limited and accepts only integer literals
> as opposed to constant expressions. define XMM_SIZE to be 16 instead of
> sizeof(xmm_t) and static_assert that sizeof(xmm_t) == 16 for
> compatibility.
> 
> Signed-off-by: Tyler Retzlaff 
> Acked-by: Morten Brørup 
> ---
>  lib/eal/x86/include/rte_vect.h | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/eal/x86/include/rte_vect.h b/lib/eal/x86/include/rte_vect.h
> index a1a537e..441f1a0 100644
> --- a/lib/eal/x86/include/rte_vect.h
> +++ b/lib/eal/x86/include/rte_vect.h
> @@ -11,6 +11,7 @@
>   * RTE SSE/AVX related header.
>   */
> 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -33,9 +34,11 @@
> 
>  typedef __m128i xmm_t;
> 
> -#define  XMM_SIZE(sizeof(xmm_t))
> +#define  XMM_SIZE16
>  #define  XMM_MASK(XMM_SIZE - 1)
> 
> +static_assert(sizeof(xmm_t) == 16, "");

I think it is better be:
static_assert(sizeof(xmm_t) == XMM_SIZE, "");


BTW, is there any chance that in future versions MSVC would accept 
align()?

> +
>  typedef union rte_xmm {
>   xmm_tx;
>   uint8_t  u8[XMM_SIZE / sizeof(uint8_t)];
> --
> 1.8.3.1

RE: [EXT] [PATCH v1] app/test: fix segfault in Tx adapter autotest

[Pavan Nikhilesh Bhagavatula]

> Uninitialized mbufs are enqueued to eventdev which causes segfault
> on freeing the mbuf in tx adapter.
> Fixed by initializing mbufs before enqueuing to eventdev.
> 
> Fixes: 46cf97e4bbfa ("eventdev: add test for eth Tx adapter")
> 
> Signed-off-by: Ganapati Kundapura 

Acked-by: Pavan Nikhilesh 

> 
> diff --git a/app/test/test_event_eth_tx_adapter.c
> b/app/test/test_event_eth_tx_adapter.c
> index dbd22f6..482b8e6 100644
> --- a/app/test/test_event_eth_tx_adapter.c
> +++ b/app/test/test_event_eth_tx_adapter.c
> @@ -484,6 +484,10 @@ tx_adapter_service(void)
>   int internal_port;
>   uint32_t cap;
> 
> + /* Initialize mbufs */
> + for (i = 0; i < RING_SIZE; i++)
> + rte_pktmbuf_reset(&bufs[i]);
> +
>   memset(&dev_conf, 0, sizeof(dev_conf));
>   err = rte_event_eth_tx_adapter_caps_get(TEST_DEV_ID,
> TEST_ETHDEV_ID,
>   &cap);
> --
> 2.6.4

[PATCH v2 0/4] add QAT GEN LCE device

[Nishikant Nayak]

This patchset adds a new QAT LCE device.
The device currently only supports symmetric crypto,
and only the AES-GCM algorithm.

v2:
   - Renamed device from GEN 5 to GEN LCE.
   - Removed unused code.
   - Updated macro names.

Nishikant Nayak (4):
  common/qat: add files specific to GEN LCE
  common/qat: update common driver to support GEN LCE
  crypto/qat: update headers for GEN LCE support
  test/cryptodev: add tests for GCM with AAD

 .mailmap  |   1 +
 app/test/test_cryptodev.c |  48 ++-
 app/test/test_cryptodev_aead_test_vectors.h   |  62 
 drivers/common/qat/dev/qat_dev_gen_lce.c  | 306 
 drivers/common/qat/meson.build|   2 +
 .../qat/qat_adf/adf_transport_access_macros.h |   1 +
 .../adf_transport_access_macros_gen_lce.h |  51 +++
 .../adf_transport_access_macros_gen_lcevf.h   |  48 +++
 drivers/common/qat/qat_adf/icp_qat_fw.h   |  34 ++
 drivers/common/qat/qat_adf/icp_qat_fw_la.h|  59 +++-
 drivers/common/qat/qat_common.h   |   1 +
 drivers/common/qat/qat_device.c   |   9 +
 .../crypto/qat/dev/qat_crypto_pmd_gen_lce.c   | 329 ++
 drivers/crypto/qat/qat_sym.c  |  16 +-
 drivers/crypto/qat/qat_sym.h  |  66 +++-
 drivers/crypto/qat/qat_sym_session.c  |  62 +++-
 drivers/crypto/qat/qat_sym_session.h  |  10 +-
 17 files changed, 1089 insertions(+), 16 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen_lce.c
 create mode 100644 
drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lce.h
 create mode 100644 
drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lcevf.h
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen_lce.c

-- 
2.25.1

[PATCH v2 1/4] common/qat: add files specific to GEN LCE

[Nishikant Nayak]

Adding GEN5 files for handling GEN LCE specific operaions.
These files are inherited from the existing files/APIs
which has some changes specific GEN5 requirements
Also updated the mailmap file.

Signed-off-by: Nishikant Nayak 
---
v2:
- Renamed device from GEN 5 to GEN LCE.
- Removed unused code.
- Updated macro names.
---
---
 .mailmap  |   1 +
 drivers/common/qat/dev/qat_dev_gen_lce.c  | 306 
 drivers/common/qat/meson.build|   2 +
 .../adf_transport_access_macros_gen_lce.h |  51 +++
 .../adf_transport_access_macros_gen_lcevf.h   |  48 +++
 drivers/common/qat/qat_adf/icp_qat_fw_la.h|  14 +
 drivers/common/qat/qat_common.h   |   1 +
 .../crypto/qat/dev/qat_crypto_pmd_gen_lce.c   | 329 ++
 drivers/crypto/qat/qat_sym.h  |   6 +
 9 files changed, 758 insertions(+)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen_lce.c
 create mode 100644 
drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lce.h
 create mode 100644 
drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lcevf.h
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen_lce.c

diff --git a/.mailmap b/.mailmap
index 58cca13ef6..8008e5a899 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1036,6 +1036,7 @@ Ning Li  
 Nipun Gupta  
 Nir Efrati 
 Nirmoy Das 
+Nishikant Nayak 
 Nithin Dabilpuram  

 Nitin Saxena 
 Nitzan Weller 
diff --git a/drivers/common/qat/dev/qat_dev_gen_lce.c 
b/drivers/common/qat/dev/qat_dev_gen_lce.c
new file mode 100644
index 00..4cef0b8be2
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen_lce.c
@@ -0,0 +1,306 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Intel Corporation
+ */
+
+#include 
+#include 
+
+#include "qat_device.h"
+#include "qat_qp.h"
+#include "adf_transport_access_macros_gen_lcevf.h"
+#include "adf_pf2vf_msg.h"
+#include "qat_pf2vf.h"
+
+#include 
+#include 
+#include 
+#include 
+
+#define BITS_PER_ULONG (sizeof(unsigned long) * 8)
+
+#define VFIO_PCI_LCE_DEVICE_CFG_REGION_INDEX   VFIO_PCI_NUM_REGIONS
+#define VFIO_PCI_LCE_CY_CFG_REGION_INDEX   (VFIO_PCI_NUM_REGIONS + 2)
+#define VFIO_PCI_LCE_RING_CFG_REGION_INDEX (VFIO_PCI_NUM_REGIONS + 4)
+#define LCE_DEVICE_NAME_SIZE   64
+#define LCE_DEVICE_MAX_BANKS   2080
+#define LCE_DEVICE_BITMAP_SIZE  \
+   __KERNEL_DIV_ROUND_UP(LCE_DEVICE_MAX_BANKS, BITS_PER_ULONG)
+
+/* QAT GEN_LCE specific macros */
+#define QAT_GEN_LCE_BUNDLE_NUM LCE_DEVICE_MAX_BANKS
+#define QAT_GEN4_QPS_PER_BUNDLE_NUM1
+
+/**
+ * struct lce_vfio_dev_cap - LCE device capabilities
+ *
+ * Device level capabilities and service level capabilities
+ */
+struct lce_vfio_dev_cap {
+   uint16_t device_num;
+   uint16_t device_type;
+   uint32_t capability_mask;
+   uint32_t extended_capabilities;
+   uint16_t max_banks;
+   uint16_t max_rings_per_bank;
+   uint16_t arb_mask;
+   uint16_t services;
+   uint16_t pkg_id;
+   uint16_t node_id;
+   __u8 device_name[LCE_DEVICE_NAME_SIZE];
+};
+
+/* struct lce_vfio_dev_cy_cap - CY capabilities of LCE device */
+struct lce_vfio_dev_cy_cap {
+   uint32_t nr_banks;
+   unsigned long bitmap[LCE_DEVICE_BITMAP_SIZE];
+};
+
+struct lce_qat_domain {
+   uint32_t nid:3;
+   uint32_t fid:7;
+   uint32_t ftype  :2;
+   uint32_t vfid   :13;
+   uint32_t rid:4;
+   uint32_t vld:1;
+   uint32_t desc_over  :1;
+   uint32_t pasid_vld  :1;
+   uint32_t pasid  :20;
+};
+
+struct lce_qat_buf_domain {
+   uint32_t bank_id:   20;
+   uint32_t type:  4;
+   uint32_t resv:  8;
+   struct lce_qat_domain dom;
+};
+
+struct qat_dev_gen_lce_extra {
+   struct qat_qp_hw_data
+   
qp_gen_lce_data[QAT_GEN_LCE_BUNDLE_NUM][QAT_GEN4_QPS_PER_BUNDLE_NUM];
+};
+
+static struct qat_pf2vf_dev qat_pf2vf_gen_lce = {
+   .pf2vf_offset = ADF_4XXXIOV_PF2VM_OFFSET,
+   .vf2pf_offset = ADF_4XXXIOV_VM2PF_OFFSET,
+   .pf2vf_type_shift = ADF_PFVF_2X_MSGTYPE_SHIFT,
+   .pf2vf_type_mask = ADF_PFVF_2X_MSGTYPE_MASK,
+   .pf2vf_data_shift = ADF_PFVF_2X_MSGDATA_SHIFT,
+   .pf2vf_data_mask = ADF_PFVF_2X_MSGDATA_MASK,
+};
+
+static int
+qat_select_valid_queue_gen_lce(struct qat_pci_device *qat_dev, int qp_id,
+   enum qat_service_type service_type)
+{
+   int i = 0, valid_qps = 0;
+   struct qat_dev_gen_lce_extra *dev_extra = qat_dev->dev_private;
+
+   for (; i < QAT_GEN_LCE_BUNDLE_NUM; i++) {
+   if (dev_extra->qp_gen_lce_data[i][0].service_type ==
+   service_type) {
+   if (valid_qps == qp_id)
+   return i;
+   ++valid_qps;
+   }
+   }
+   return -1;
+}
+
+static const struct qat_qp_hw_data *
+qat_qp_get_hw_data_gen_

[PATCH v2 2/4] common/qat: update common driver to support GEN LCE

[Nishikant Nayak]

Adding GEN LCE specific macros which is required for updating
the support for GEN LCE features.
Also this patch adds other macros which is being used by GEN LCE
Specific APIs.

Signed-off-by: Nishikant Nayak 
---
v2:
- Renamed device from GEN 5 to GEN LCE.
- Removed unused code.
- Updated macro names.
- Fixed code formatting
---
---
 .../qat/qat_adf/adf_transport_access_macros.h |  1 +
 drivers/common/qat/qat_adf/icp_qat_fw.h   | 34 ++
 drivers/common/qat/qat_adf/icp_qat_fw_la.h| 45 ++-
 drivers/common/qat/qat_device.c   |  9 
 4 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h 
b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
index 12a7258c60..19bd812419 100644
--- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h
+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
@@ -47,6 +47,7 @@
 #define ADF_RING_SIZE_512 0x03
 #define ADF_RING_SIZE_4K 0x06
 #define ADF_RING_SIZE_16K 0x08
+#define ADF_RING_SIZE_64K 0x0A
 #define ADF_RING_SIZE_4M 0x10
 #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128
 #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h 
b/drivers/common/qat/qat_adf/icp_qat_fw.h
index 3aa17ae041..b78158e01d 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -57,6 +57,12 @@ struct icp_qat_fw_comn_req_hdr_cd_pars {
} u;
 };
 
+struct lce_key_buff_desc {
+   uint64_t keybuff;
+   uint32_t keybuff_resrvd1;
+   uint32_t keybuff_resrvd2;
+};
+
 struct icp_qat_fw_comn_req_mid {
uint64_t opaque_data;
uint64_t src_data_addr;
@@ -123,6 +129,12 @@ struct icp_qat_fw_comn_resp {
 #define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0
 #define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1
 
+/* GEN_LCE specific Common Header fields */
+#define ICP_QAT_FW_COMN_DESC_LAYOUT_BITPOS 5
+#define ICP_QAT_FW_COMN_DESC_LAYOUT_MASK 0x3
+#define ICP_QAT_FW_COMN_GEN_LCE_DESC_LAYOUT 3
+#define ICP_QAT_FW_COMN_GEN_LCE_STATUS_FLAG_ERROR 0
+
 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_type
 
@@ -168,6 +180,12 @@ struct icp_qat_fw_comn_resp {
(((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)
 
+#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD_GEN_LCE(valid, desc_layout) \
+   valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
+   ICP_QAT_FW_COMN_VALID_FLAG_BITPOS) | \
+   (((desc_layout) & ICP_QAT_FW_COMN_DESC_LAYOUT_MASK) << \
+   ICP_QAT_FW_COMN_DESC_LAYOUT_BITPOS))
+
 #define QAT_COMN_PTR_TYPE_BITPOS 0
 #define QAT_COMN_PTR_TYPE_MASK 0x1
 #define QAT_COMN_CD_FLD_TYPE_BITPOS 1
@@ -180,10 +198,20 @@ struct icp_qat_fw_comn_resp {
 #define QAT_COMN_EXT_FLAGS_MASK 0x1
 #define QAT_COMN_EXT_FLAGS_USED 0x1
 
+/* GEN_LCE specific Common Request Flags fields */
+#define QAT_COMN_KEYBUF_USAGE_BITPOS 1
+#define QAT_COMN_KEYBUF_USAGE_MASK 0x1
+#define QAT_COMN_KEY_BUFFER_USED 1
+
 #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
 | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))
 
+#define ICP_QAT_FW_COMN_FLAGS_BUILD_GEN_LCE(ptr, keybuf) \
+   ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS) | \
+(((keybuf) & QAT_COMN_PTR_TYPE_MASK) << \
+  QAT_COMN_KEYBUF_USAGE_BITPOS))
+
 #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)
 
@@ -249,6 +277,8 @@ struct icp_qat_fw_comn_resp {
 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
 #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
 #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
+#define QAT_COMN_RESP_INVALID_PARAM_BITPOS 1
+#define QAT_COMN_RESP_INVALID_PARAM_MASK 0x1
 #define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
 #define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
 
@@ -280,6 +310,10 @@ struct icp_qat_fw_comn_resp {
QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
 
+#define ICP_QAT_FW_COMN_RESP_INVALID_PARAM_STAT_GET(status) \
+   QAT_FIELD_GET(status, QAT_COMN_RESP_INVALID_PARAM_BITPOS, \
+   QAT_COMN_RESP_INVALID_PARAM_MASK)
+
 #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
 #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h 
b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
index 215b291b74..eba9f96685 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
@@ -22,14 +22,24 @@ enum icp_qat_fw_la_cmd_id {
ICP_QAT_FW_LA_CMD_DELIMITER = 18
 };
 
+/* In GEN_LCE Command ID 4 corresponds to AEAD */
+#define ICP_QAT_FW_LA_CMD_AEAD 4
+
 #define ICP_QAT_F

[PATCH v2 3/4] crypto/qat: update headers for GEN LCE support

[Nishikant Nayak]

This patch handles the changes required for updating the common
header fields specific to GEN LCE, Also added/updated of the response
processing APIs based on GEN LCE requirement.

Signed-off-by: Nishikant Nayak 
---
v2:
- Renamed device from GEN 5 to GEN LCE.
- Removed unused code.
- Updated macro names.
- Added GEN LCE specific API for deque burst.
- Fixed code formatting.
---
---
 drivers/crypto/qat/qat_sym.c | 16 ++-
 drivers/crypto/qat/qat_sym.h | 60 ++-
 drivers/crypto/qat/qat_sym_session.c | 62 +++-
 drivers/crypto/qat/qat_sym_session.h | 10 -
 4 files changed, 140 insertions(+), 8 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
index 6e03bde841..439a3fc00b 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -180,7 +180,15 @@ qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops,
uint16_t nb_ops)
 {
return qat_dequeue_op_burst(qp, (void **)ops,
-   qat_sym_process_response, nb_ops);
+   qat_sym_process_response, nb_ops);
+}
+
+uint16_t
+qat_sym_dequeue_burst_gen_lce(void *qp, struct rte_crypto_op **ops,
+   uint16_t nb_ops)
+{
+   return qat_dequeue_op_burst(qp, (void **)ops,
+   qat_sym_process_response_gen_lce, nb_ops);
 }
 
 int
@@ -200,6 +208,7 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,
char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];
struct rte_cryptodev *cryptodev;
struct qat_cryptodev_private *internals;
+   enum qat_device_gen qat_dev_gen = qat_pci_dev->qat_dev_gen;
const struct qat_crypto_gen_dev_ops *gen_dev_ops =
&qat_sym_gen_dev_ops[qat_pci_dev->qat_dev_gen];
 
@@ -249,7 +258,10 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,
cryptodev->dev_ops = gen_dev_ops->cryptodev_ops;
 
cryptodev->enqueue_burst = qat_sym_enqueue_burst;
-   cryptodev->dequeue_burst = qat_sym_dequeue_burst;
+   if (qat_dev_gen == QAT_GEN_LCE)
+   cryptodev->dequeue_burst = qat_sym_dequeue_burst_gen_lce;
+   else
+   cryptodev->dequeue_burst = qat_sym_dequeue_burst;
 
cryptodev->feature_flags = gen_dev_ops->get_feature_flags(qat_pci_dev);
 
diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h
index f2f197d050..3461113c13 100644
--- a/drivers/crypto/qat/qat_sym.h
+++ b/drivers/crypto/qat/qat_sym.h
@@ -90,7 +90,7 @@
 /*
  * Maximum number of SGL entries
  */
-#define QAT_SYM_SGL_MAX_NUMBER 16
+#define QAT_SYM_SGL_MAX_NUMBER 16
 
 /* Maximum data length for single pass GMAC: 2^14-1 */
 #define QAT_AES_GMAC_SPC_MAX_SIZE 16383
@@ -142,6 +142,10 @@ uint16_t
 qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops,
uint16_t nb_ops);
 
+uint16_t
+qat_sym_dequeue_burst_gen_lce(void *qp, struct rte_crypto_op **ops,
+   uint16_t nb_ops);
+
 #ifdef RTE_QAT_OPENSSL
 /** Encrypt a single partial block
  *  Depends on openssl libcrypto
@@ -390,6 +394,52 @@ qat_sym_process_response(void **op, uint8_t *resp, void 
*op_cookie,
return 1;
 }
 
+static __rte_always_inline int
+qat_sym_process_response_gen_lce(void **op, uint8_t *resp,
+   void *op_cookie __rte_unused,
+   uint64_t *dequeue_err_count __rte_unused)
+{
+   struct icp_qat_fw_comn_resp *resp_msg =
+   (struct icp_qat_fw_comn_resp *)resp;
+   struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)
+   (resp_msg->opaque_data);
+   struct qat_sym_session *sess;
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+   QAT_DP_HEXDUMP_LOG(DEBUG, "qat_response:", (uint8_t *)resp_msg,
+   sizeof(struct icp_qat_fw_comn_resp));
+#endif
+
+   sess = CRYPTODEV_GET_SYM_SESS_PRIV(rx_op->sym->session);
+
+   rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+
+   if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
+   ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(
+   resp_msg->comn_hdr.comn_status))
+   rx_op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;
+
+   else if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
+   ICP_QAT_FW_COMN_RESP_INVALID_PARAM_STAT_GET(
+   resp_msg->comn_hdr.comn_status))
+   rx_op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+
+   if (sess->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
+   if (ICP_QAT_FW_LA_VER_STATUS_FAIL ==
+   ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
+   resp_msg->comn_hdr.comn_status))
+   rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+   }
+
+   *op = (void *)rx_op;
+
+   /*
+* return 1 as dequeue op only move on to the next op
+* if one was ready to return to API
+*/
+   return 1;
+}
+
 int
 

[PATCH v2 4/4] test/cryptodev: add tests for GCM with AAD

[Nishikant Nayak]

Adding one new unit test code for validating the features
added as part of GCM with 64 byte AAD.
The new test case adds one new test for GCM algo for both
encrypt and decrypt operations.

Signed-off-by: Nishikant Nayak 
---
v2:
- Removed unused code.
- Added one new unit test, AAD with GCM for GEN LCE.
---
---
 app/test/test_cryptodev.c   | 48 +---
 app/test/test_cryptodev_aead_test_vectors.h | 62 +
 2 files changed, 103 insertions(+), 7 deletions(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 38a65aa88f..edd23731f7 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -12494,6 +12494,18 @@ test_AES_GCM_auth_decryption_test_case_256_7(void)
return test_authenticated_decryption(&gcm_test_case_256_7);
 }
 
+static int
+test_AES_GCM_auth_decryption_test_case_256_8(void)
+{
+   return test_authenticated_decryption(&gcm_test_case_256_8);
+}
+
+static int
+test_AES_GCM_auth_encryption_test_case_256_8(void)
+{
+   return test_authenticated_encryption(&gcm_test_case_256_8);
+}
+
 static int
 test_AES_GCM_auth_decryption_test_case_aad_1(void)
 {
@@ -12613,10 +12625,16 @@ test_authenticated_encryption_oop(const struct 
aead_test_data *tdata)
 
/* Verify the capabilities */
struct rte_cryptodev_sym_capability_idx cap_idx;
+   const struct rte_cryptodev_symmetric_capability *capability;
cap_idx.type = RTE_CRYPTO_SYM_XFORM_AEAD;
cap_idx.algo.aead = tdata->algo;
-   if (rte_cryptodev_sym_capability_get(ts_params->valid_devs[0],
-   &cap_idx) == NULL)
+   capability = rte_cryptodev_sym_capability_get(ts_params->valid_devs[0],
+   &cap_idx);
+   if (capability == NULL)
+   return TEST_SKIPPED;
+   if (rte_cryptodev_sym_capability_check_aead(
+   capability, tdata->key.len, tdata->auth_tag.len,
+   tdata->aad.len, tdata->iv.len))
return TEST_SKIPPED;
 
rte_cryptodev_info_get(ts_params->valid_devs[0], &dev_info);
@@ -12719,16 +12737,22 @@ test_authenticated_decryption_oop(const struct 
aead_test_data *tdata)
 
/* Verify the capabilities */
struct rte_cryptodev_sym_capability_idx cap_idx;
+   const struct rte_cryptodev_symmetric_capability *capability;
cap_idx.type = RTE_CRYPTO_SYM_XFORM_AEAD;
cap_idx.algo.aead = tdata->algo;
-   if (rte_cryptodev_sym_capability_get(ts_params->valid_devs[0],
-   &cap_idx) == NULL)
-   return TEST_SKIPPED;
+   capability = rte_cryptodev_sym_capability_get(ts_params->valid_devs[0],
+   &cap_idx);
 
/* not supported with CPU crypto and raw data-path APIs*/
if (gbl_action_type == RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO ||
global_api_test_type == CRYPTODEV_RAW_API_TEST)
return TEST_SKIPPED;
+   if (capability == NULL)
+   return TEST_SKIPPED;
+   if (rte_cryptodev_sym_capability_check_aead(
+   capability, tdata->key.len, tdata->auth_tag.len,
+   tdata->aad.len, tdata->iv.len))
+   return TEST_SKIPPED;
 
if ((global_api_test_type == CRYPTODEV_RAW_API_TEST) &&
(!(feat_flags & RTE_CRYPTODEV_FF_SYM_RAW_DP))) {
@@ -15749,10 +15773,16 @@ test_authenticated_encryption_SGL(const struct 
aead_test_data *tdata,
 
/* Verify the capabilities */
struct rte_cryptodev_sym_capability_idx cap_idx;
+   const struct rte_cryptodev_symmetric_capability *capability;
cap_idx.type = RTE_CRYPTO_SYM_XFORM_AEAD;
cap_idx.algo.aead = tdata->algo;
-   if (rte_cryptodev_sym_capability_get(ts_params->valid_devs[0],
-   &cap_idx) == NULL)
+   capability = rte_cryptodev_sym_capability_get(ts_params->valid_devs[0],
+   &cap_idx);
+   if (capability == NULL)
+   return TEST_SKIPPED;
+   if (rte_cryptodev_sym_capability_check_aead(
+   capability, tdata->key.len, tdata->auth_tag.len,
+   tdata->aad.len, tdata->iv.len))
return TEST_SKIPPED;
 
/*
@@ -17392,6 +17422,8 @@ static struct unit_test_suite 
cryptodev_aes_gcm_auth_testsuite  = {
test_AES_GCM_auth_encryption_test_case_256_6),
TEST_CASE_ST(ut_setup, ut_teardown,
test_AES_GCM_auth_encryption_test_case_256_7),
+   TEST_CASE_ST(ut_setup, ut_teardown,
+   test_AES_GCM_auth_encryption_test_case_256_8),
 
/** AES GCM Authenticated Decryption 256 bits key */
TEST_CASE_ST(ut_setup, ut_teardown,
@@ -17408,6 +17440,8 @@ static struct unit_test_suite 
cryptodev_aes_gcm_auth_testsuite  = {
test_AES_GCM_auth_decryption_test_case_256_6),
TEST_CASE_ST(ut_setup, ut_teardown,
tes

[PATCH v6 1/3] net/mlx5/hws: add support for compare matcher

[Michael Baum]

From: Hamdan Igbaria 

Add support for compare matcher, this matcher will allow
direct comparison between two packet fields, or a packet
field and a value, with fully masked DW.
For now this matcher hash table is limited to size 1x1,
thus it supports only 1 rule STE.

Signed-off-by: Hamdan Igbaria 
Signed-off-by: Michael Baum 
Acked-by: Suanming Mou 
---
 drivers/common/mlx5/mlx5_prm.h|  16 ++
 drivers/net/mlx5/hws/mlx5dr_cmd.c |   9 +-
 drivers/net/mlx5/hws/mlx5dr_cmd.h |   1 +
 drivers/net/mlx5/hws/mlx5dr_debug.c   |   4 +-
 drivers/net/mlx5/hws/mlx5dr_debug.h   |   1 +
 drivers/net/mlx5/hws/mlx5dr_definer.c | 243 +-
 drivers/net/mlx5/hws/mlx5dr_definer.h |  33 
 drivers/net/mlx5/hws/mlx5dr_matcher.c |  53 ++
 drivers/net/mlx5/hws/mlx5dr_matcher.h |  12 +-
 9 files changed, 363 insertions(+), 9 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 282e59e52c..aceacb04d0 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -3463,6 +3463,7 @@ enum mlx5_ifc_rtc_ste_format {
MLX5_IFC_RTC_STE_FORMAT_8DW = 0x4,
MLX5_IFC_RTC_STE_FORMAT_11DW = 0x5,
MLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7,
+   MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE = 0x8,
 };
 
 enum mlx5_ifc_rtc_reparse_mode {
@@ -3501,6 +3502,21 @@ struct mlx5_ifc_rtc_bits {
u8 reserved_at_1a0[0x260];
 };
 
+struct mlx5_ifc_ste_match_4dw_range_ctrl_dw_bits {
+   u8 match[0x1];
+   u8 reserved_at_1[0x2];
+   u8 base1[0x1];
+   u8 inverse1[0x1];
+   u8 reserved_at_5[0x1];
+   u8 operator1[0x2];
+   u8 reserved_at_8[0x3];
+   u8 base0[0x1];
+   u8 inverse0[0x1];
+   u8 reserved_at_a[0x1];
+   u8 operator0[0x2];
+   u8 compare_delta[0x10];
+};
+
 struct mlx5_ifc_alias_context_bits {
u8 vhca_id_to_be_accessed[0x10];
u8 reserved_at_10[0xd];
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c 
b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index fd07028e5f..0e0cc479a6 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -370,9 +370,12 @@ mlx5dr_cmd_rtc_create(struct ibv_context *ctx,
 attr, obj_type, MLX5_GENERAL_OBJ_TYPE_RTC);
 
attr = MLX5_ADDR_OF(create_rtc_in, in, rtc);
-   MLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ?
-   MLX5_IFC_RTC_STE_FORMAT_11DW :
-   MLX5_IFC_RTC_STE_FORMAT_8DW);
+   if (rtc_attr->is_compare) {
+   MLX5_SET(rtc, attr, ste_format_0, 
MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE);
+   } else {
+   MLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ?
+MLX5_IFC_RTC_STE_FORMAT_11DW : 
MLX5_IFC_RTC_STE_FORMAT_8DW);
+   }
 
if (rtc_attr->is_scnd_range) {
MLX5_SET(rtc, attr, ste_format_1, 
MLX5_IFC_RTC_STE_FORMAT_RANGE);
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h 
b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index ee4a61b7eb..9d385fc57f 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -82,6 +82,7 @@ struct mlx5dr_cmd_rtc_create_attr {
uint8_t reparse_mode;
bool is_frst_jumbo;
bool is_scnd_range;
+   bool is_compare;
 };
 
 struct mlx5dr_cmd_alias_obj_create_attr {
diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c 
b/drivers/net/mlx5/hws/mlx5dr_debug.c
index 11557bcab8..a9094cd35b 100644
--- a/drivers/net/mlx5/hws/mlx5dr_debug.c
+++ b/drivers/net/mlx5/hws/mlx5dr_debug.c
@@ -99,6 +99,7 @@ static int
 mlx5dr_debug_dump_matcher_match_template(FILE *f, struct mlx5dr_matcher 
*matcher)
 {
bool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL;
+   bool is_compare = mlx5dr_matcher_is_compare(matcher);
enum mlx5dr_debug_res_type type;
int i, ret;
 
@@ -117,7 +118,8 @@ mlx5dr_debug_dump_matcher_match_template(FILE *f, struct 
mlx5dr_matcher *matcher
return rte_errno;
}
 
-   type = MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER;
+   type = is_compare ? 
MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_COMPARE_MATCH_DEFINER :
+   
MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER;
ret = mlx5dr_debug_dump_matcher_template_definer(f, mt, 
mt->definer, type);
if (ret)
return ret;
diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.h 
b/drivers/net/mlx5/hws/mlx5dr_debug.h
index 5cffdb10b5..a89a6a0b1d 100644
--- a/drivers/net/mlx5/hws/mlx5dr_debug.h
+++ b/drivers/net/mlx5/hws/mlx5dr_debug.h
@@ -24,6 +24,7 @@ enum mlx5dr_debug_res_type {
MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE = 4204,
MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_HASH_DEFINER = 4205,
MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_RANGE_DEFINER = 4206,
+   MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_COMPARE_MATCH_DEFINER = 4207,
 };
 
 static inline uint64_t
diff --git a/drivers

[PATCH v6 2/3] net/mlx5: add support to compare random value

[Michael Baum]

Add support to use "RTE_FLOW_ITEM_TYPE_COMPARE" with
"RTE_FLOW_FIELD_RAMDOM" as an argument.
The random field is supported only when base is an immediate value,
random field cannot be compared with enother field.

Signed-off-by: Michael Baum 
Acked-by: Suanming Mou 
---
 doc/guides/nics/mlx5.rst|  9 -
 drivers/net/mlx5/mlx5_flow_hw.c | 70 -
 2 files changed, 59 insertions(+), 20 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 0d2213497a..c0a5768117 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -431,8 +431,13 @@ Limitations
 
   - Only supported in HW steering(``dv_flow_en`` = 2) mode.
   - Only single flow is supported to the flow table.
-  - Only 32-bit comparison is supported.
-  - Only match with compare result between packet fields is supported.
+  - Only single item is supported per pattern template.
+  - Only 32-bit comparison is supported or 16-bits for random field.
+  - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``,
+``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``.
+  - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field.
+  - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with
+``RTE_FLOW_FIELD_VALUE``.
 
 - No Tx metadata go to the E-Switch steering domain for the Flow group 0.
   The flows within group 0 and set metadata action are rejected by hardware.
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 0d09c220df..b0e93baaf2 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -6721,18 +6721,55 @@ flow_hw_prepend_item(const struct rte_flow_item *items,
return copied_items;
 }
 
-static inline bool
-flow_hw_item_compare_field_supported(enum rte_flow_field_id field)
+static int
+flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,
+   enum rte_flow_field_id base_field,
+   struct rte_flow_error *error)
 {
-   switch (field) {
+   switch (arg_field) {
+   case RTE_FLOW_FIELD_TAG:
+   case RTE_FLOW_FIELD_META:
+   break;
+   case RTE_FLOW_FIELD_RANDOM:
+   if (base_field == RTE_FLOW_FIELD_VALUE)
+   return 0;
+   return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "compare random is supported only 
with immediate value");
+   default:
+   return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "compare item argument field is not 
supported");
+   }
+   switch (base_field) {
case RTE_FLOW_FIELD_TAG:
case RTE_FLOW_FIELD_META:
case RTE_FLOW_FIELD_VALUE:
-   return true;
+   break;
+   default:
+   return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "compare item base field is not 
supported");
+   }
+   return 0;
+}
+
+static inline uint32_t
+flow_hw_item_compare_width_supported(enum rte_flow_field_id field)
+{
+   switch (field) {
+   case RTE_FLOW_FIELD_TAG:
+   case RTE_FLOW_FIELD_META:
+   return 32;
+   case RTE_FLOW_FIELD_RANDOM:
+   return 16;
default:
break;
}
-   return false;
+   return 0;
 }
 
 static int
@@ -6741,6 +6778,7 @@ flow_hw_validate_item_compare(const struct rte_flow_item 
*item,
 {
const struct rte_flow_item_compare *comp_m = item->mask;
const struct rte_flow_item_compare *comp_v = item->spec;
+   int ret;
 
if (unlikely(!comp_m))
return rte_flow_error_set(error, EINVAL,
@@ -6752,19 +6790,13 @@ flow_hw_validate_item_compare(const struct 
rte_flow_item *item,
   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
   NULL,
   "compare item only support full mask");
-   if (!flow_hw_item_compare_field_supported(comp_m->a.field) ||
-   !flow_hw_item_compare_field_supported(comp_m->b.field))
-   return rte_flow_error_set(error, ENOTSUP,
-  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
-  NULL,
-  "compare item field not support");
-   if (comp_m->a.field == RTE_FLOW_FIELD_VALUE &&
-   comp_m->b.field == RTE_FLOW_FIELD_VALUE)
-   return rte_flow_error_set(error, EINVAL,
-  RTE_FLO

[PATCH v6 3/3] net/mlx5/hws: add compare ESP sequence number support

[Michael Baum]

Add support for compare item with "RTE_FLOW_FIELD_ESP_SEQ_NUM" field.

Signed-off-by: Michael Baum 
Acked-by: Suanming Mou 
---
 doc/guides/nics/mlx5.rst  |  1 +
 drivers/net/mlx5/hws/mlx5dr_definer.c | 22 --
 drivers/net/mlx5/mlx5_flow_hw.c   |  3 +++
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index c0a5768117..d7bf81161e 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -434,6 +434,7 @@ Limitations
   - Only single item is supported per pattern template.
   - Only 32-bit comparison is supported or 16-bits for random field.
   - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``,
+``RTE_FLOW_FIELD_ESP_SEQ_NUM``,
 ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``.
   - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field.
   - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c 
b/drivers/net/mlx5/hws/mlx5dr_definer.c
index da50b64fb4..39269b4ede 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -424,10 +424,20 @@ mlx5dr_definer_compare_base_value_set(const void 
*item_spec,
 
value = (const uint32_t *)&b->value[0];
 
-   if (a->field == RTE_FLOW_FIELD_RANDOM)
+   switch (a->field) {
+   case RTE_FLOW_FIELD_RANDOM:
*base = htobe32(*value << 16);
-   else
+   break;
+   case RTE_FLOW_FIELD_TAG:
+   case RTE_FLOW_FIELD_META:
*base = htobe32(*value);
+   break;
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
+   *base = *value;
+   break;
+   default:
+   break;
+   }
 
MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1);
 }
@@ -2930,6 +2940,14 @@ mlx5dr_definer_conv_item_compare_field(const struct 
rte_flow_field_data *f,
fc->compare_idx = dw_offset;
DR_CALC_SET_HDR(fc, random_number, random_number);
break;
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
+   fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER];
+   fc->item_idx = item_idx;
+   fc->tag_set = &mlx5dr_definer_compare_set;
+   fc->tag_mask_set = &mlx5dr_definer_ones_set;
+   fc->compare_idx = dw_offset;
+   DR_CALC_SET_HDR(fc, ipsec, sequence_number);
+   break;
default:
DR_LOG(ERR, "%u field is not supported", f->field);
goto err_notsup;
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index b0e93baaf2..33922bddff 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -6729,6 +6729,7 @@ flow_hw_item_compare_field_validate(enum 
rte_flow_field_id arg_field,
switch (arg_field) {
case RTE_FLOW_FIELD_TAG:
case RTE_FLOW_FIELD_META:
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
break;
case RTE_FLOW_FIELD_RANDOM:
if (base_field == RTE_FLOW_FIELD_VALUE)
@@ -6747,6 +6748,7 @@ flow_hw_item_compare_field_validate(enum 
rte_flow_field_id arg_field,
case RTE_FLOW_FIELD_TAG:
case RTE_FLOW_FIELD_META:
case RTE_FLOW_FIELD_VALUE:
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
break;
default:
return rte_flow_error_set(error, ENOTSUP,
@@ -6763,6 +6765,7 @@ flow_hw_item_compare_width_supported(enum 
rte_flow_field_id field)
switch (field) {
case RTE_FLOW_FIELD_TAG:
case RTE_FLOW_FIELD_META:
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
return 32;
case RTE_FLOW_FIELD_RANDOM:
return 16;
-- 
2.25.1

[PATCH v6 0/3] net/mlx5: add compare item support

[Michael Baum]

Add HWS support for compare item with:
- "RTE_FLOW_FIELD_TAG".
- "RTE_FLOW_FIELD_NETA".
- "RTE_FLOW_FIELD_VALUE".

Add HWS + PMD support for compare item with:
- "RTE_FLOW_FIELD_RANDOM".
- "RTE_FLOW_FIELD_ESP_SEQ_NUM".

v2:
 - Rebase.
 - Add "RTE_FLOW_FIELD_META" compare support.
 - Reduce the "Depends-on" list.

v3:
 - Rebase.
 - Fix typo in function name, r/tranlate/translate.
 - Fix adding a line without newline at end of file.

v4:
 - Rebase.
 - Update documentation.
 - Remove the "Depends-on" label.

v5:
 - Rebase.
 - Add ESP sequence number suppoert and rename the series accordingly.

v6:
 - Rebase.
 - Add "Acked-by" from v5.


Hamdan Igbaria (1):
  net/mlx5/hws: add support for compare matcher

Michael Baum (2):
  net/mlx5: add support to compare random value
  net/mlx5/hws: add compare ESP sequence number support

 doc/guides/nics/mlx5.rst  |  10 +-
 drivers/common/mlx5/mlx5_prm.h|  16 ++
 drivers/net/mlx5/hws/mlx5dr_cmd.c |   9 +-
 drivers/net/mlx5/hws/mlx5dr_cmd.h |   1 +
 drivers/net/mlx5/hws/mlx5dr_debug.c   |   4 +-
 drivers/net/mlx5/hws/mlx5dr_debug.h   |   1 +
 drivers/net/mlx5/hws/mlx5dr_definer.c | 261 +-
 drivers/net/mlx5/hws/mlx5dr_definer.h |  33 
 drivers/net/mlx5/hws/mlx5dr_matcher.c |  53 ++
 drivers/net/mlx5/hws/mlx5dr_matcher.h |  12 +-
 drivers/net/mlx5/mlx5_flow_hw.c   |  73 +--
 11 files changed, 444 insertions(+), 29 deletions(-)

-- 
2.25.1

[PATCH v7 1/3] net/mlx5/hws: add support for compare matcher

[Michael Baum]

From: Hamdan Igbaria 

Add support for compare matcher, this matcher will allow
direct comparison between two packet fields, or a packet
field and a value, with fully masked DW.
For now this matcher hash table is limited to size 1x1,
thus it supports only 1 rule STE.

Signed-off-by: Hamdan Igbaria 
Signed-off-by: Michael Baum 
Acked-by: Suanming Mou 
---
 drivers/common/mlx5/mlx5_prm.h|  16 ++
 drivers/net/mlx5/hws/mlx5dr_cmd.c |   9 +-
 drivers/net/mlx5/hws/mlx5dr_cmd.h |   1 +
 drivers/net/mlx5/hws/mlx5dr_debug.c   |   4 +-
 drivers/net/mlx5/hws/mlx5dr_debug.h   |   1 +
 drivers/net/mlx5/hws/mlx5dr_definer.c | 243 +-
 drivers/net/mlx5/hws/mlx5dr_definer.h |  33 
 drivers/net/mlx5/hws/mlx5dr_matcher.c |  53 ++
 drivers/net/mlx5/hws/mlx5dr_matcher.h |  12 +-
 9 files changed, 363 insertions(+), 9 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 282e59e52c..aceacb04d0 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -3463,6 +3463,7 @@ enum mlx5_ifc_rtc_ste_format {
MLX5_IFC_RTC_STE_FORMAT_8DW = 0x4,
MLX5_IFC_RTC_STE_FORMAT_11DW = 0x5,
MLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7,
+   MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE = 0x8,
 };
 
 enum mlx5_ifc_rtc_reparse_mode {
@@ -3501,6 +3502,21 @@ struct mlx5_ifc_rtc_bits {
u8 reserved_at_1a0[0x260];
 };
 
+struct mlx5_ifc_ste_match_4dw_range_ctrl_dw_bits {
+   u8 match[0x1];
+   u8 reserved_at_1[0x2];
+   u8 base1[0x1];
+   u8 inverse1[0x1];
+   u8 reserved_at_5[0x1];
+   u8 operator1[0x2];
+   u8 reserved_at_8[0x3];
+   u8 base0[0x1];
+   u8 inverse0[0x1];
+   u8 reserved_at_a[0x1];
+   u8 operator0[0x2];
+   u8 compare_delta[0x10];
+};
+
 struct mlx5_ifc_alias_context_bits {
u8 vhca_id_to_be_accessed[0x10];
u8 reserved_at_10[0xd];
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c 
b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index fd07028e5f..0e0cc479a6 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -370,9 +370,12 @@ mlx5dr_cmd_rtc_create(struct ibv_context *ctx,
 attr, obj_type, MLX5_GENERAL_OBJ_TYPE_RTC);
 
attr = MLX5_ADDR_OF(create_rtc_in, in, rtc);
-   MLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ?
-   MLX5_IFC_RTC_STE_FORMAT_11DW :
-   MLX5_IFC_RTC_STE_FORMAT_8DW);
+   if (rtc_attr->is_compare) {
+   MLX5_SET(rtc, attr, ste_format_0, 
MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE);
+   } else {
+   MLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ?
+MLX5_IFC_RTC_STE_FORMAT_11DW : 
MLX5_IFC_RTC_STE_FORMAT_8DW);
+   }
 
if (rtc_attr->is_scnd_range) {
MLX5_SET(rtc, attr, ste_format_1, 
MLX5_IFC_RTC_STE_FORMAT_RANGE);
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h 
b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index ee4a61b7eb..9d385fc57f 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -82,6 +82,7 @@ struct mlx5dr_cmd_rtc_create_attr {
uint8_t reparse_mode;
bool is_frst_jumbo;
bool is_scnd_range;
+   bool is_compare;
 };
 
 struct mlx5dr_cmd_alias_obj_create_attr {
diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c 
b/drivers/net/mlx5/hws/mlx5dr_debug.c
index 11557bcab8..a9094cd35b 100644
--- a/drivers/net/mlx5/hws/mlx5dr_debug.c
+++ b/drivers/net/mlx5/hws/mlx5dr_debug.c
@@ -99,6 +99,7 @@ static int
 mlx5dr_debug_dump_matcher_match_template(FILE *f, struct mlx5dr_matcher 
*matcher)
 {
bool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL;
+   bool is_compare = mlx5dr_matcher_is_compare(matcher);
enum mlx5dr_debug_res_type type;
int i, ret;
 
@@ -117,7 +118,8 @@ mlx5dr_debug_dump_matcher_match_template(FILE *f, struct 
mlx5dr_matcher *matcher
return rte_errno;
}
 
-   type = MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER;
+   type = is_compare ? 
MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_COMPARE_MATCH_DEFINER :
+   
MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER;
ret = mlx5dr_debug_dump_matcher_template_definer(f, mt, 
mt->definer, type);
if (ret)
return ret;
diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.h 
b/drivers/net/mlx5/hws/mlx5dr_debug.h
index 5cffdb10b5..a89a6a0b1d 100644
--- a/drivers/net/mlx5/hws/mlx5dr_debug.h
+++ b/drivers/net/mlx5/hws/mlx5dr_debug.h
@@ -24,6 +24,7 @@ enum mlx5dr_debug_res_type {
MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE = 4204,
MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_HASH_DEFINER = 4205,
MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_RANGE_DEFINER = 4206,
+   MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_COMPARE_MATCH_DEFINER = 4207,
 };
 
 static inline uint64_t
diff --git a/drivers

[PATCH v7 2/3] net/mlx5: add support to compare random value

[Michael Baum]

Add support to use "RTE_FLOW_ITEM_TYPE_COMPARE" with
"RTE_FLOW_FIELD_RAMDOM" as an argument.
The random field is supported only when base is an immediate value,
random field cannot be compared with enother field.

Signed-off-by: Michael Baum 
Acked-by: Suanming Mou 
---
 doc/guides/nics/mlx5.rst|  9 -
 drivers/net/mlx5/mlx5_flow_hw.c | 70 -
 2 files changed, 59 insertions(+), 20 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 0d2213497a..c0a5768117 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -431,8 +431,13 @@ Limitations
 
   - Only supported in HW steering(``dv_flow_en`` = 2) mode.
   - Only single flow is supported to the flow table.
-  - Only 32-bit comparison is supported.
-  - Only match with compare result between packet fields is supported.
+  - Only single item is supported per pattern template.
+  - Only 32-bit comparison is supported or 16-bits for random field.
+  - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``,
+``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``.
+  - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field.
+  - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with
+``RTE_FLOW_FIELD_VALUE``.
 
 - No Tx metadata go to the E-Switch steering domain for the Flow group 0.
   The flows within group 0 and set metadata action are rejected by hardware.
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 3ae1220587..f31ba2df2b 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -6721,18 +6721,55 @@ flow_hw_prepend_item(const struct rte_flow_item *items,
return copied_items;
 }
 
-static inline bool
-flow_hw_item_compare_field_supported(enum rte_flow_field_id field)
+static int
+flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field,
+   enum rte_flow_field_id base_field,
+   struct rte_flow_error *error)
 {
-   switch (field) {
+   switch (arg_field) {
+   case RTE_FLOW_FIELD_TAG:
+   case RTE_FLOW_FIELD_META:
+   break;
+   case RTE_FLOW_FIELD_RANDOM:
+   if (base_field == RTE_FLOW_FIELD_VALUE)
+   return 0;
+   return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "compare random is supported only 
with immediate value");
+   default:
+   return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "compare item argument field is not 
supported");
+   }
+   switch (base_field) {
case RTE_FLOW_FIELD_TAG:
case RTE_FLOW_FIELD_META:
case RTE_FLOW_FIELD_VALUE:
-   return true;
+   break;
+   default:
+   return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "compare item base field is not 
supported");
+   }
+   return 0;
+}
+
+static inline uint32_t
+flow_hw_item_compare_width_supported(enum rte_flow_field_id field)
+{
+   switch (field) {
+   case RTE_FLOW_FIELD_TAG:
+   case RTE_FLOW_FIELD_META:
+   return 32;
+   case RTE_FLOW_FIELD_RANDOM:
+   return 16;
default:
break;
}
-   return false;
+   return 0;
 }
 
 static int
@@ -6741,6 +6778,7 @@ flow_hw_validate_item_compare(const struct rte_flow_item 
*item,
 {
const struct rte_flow_item_compare *comp_m = item->mask;
const struct rte_flow_item_compare *comp_v = item->spec;
+   int ret;
 
if (unlikely(!comp_m))
return rte_flow_error_set(error, EINVAL,
@@ -6752,19 +6790,13 @@ flow_hw_validate_item_compare(const struct 
rte_flow_item *item,
   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
   NULL,
   "compare item only support full mask");
-   if (!flow_hw_item_compare_field_supported(comp_m->a.field) ||
-   !flow_hw_item_compare_field_supported(comp_m->b.field))
-   return rte_flow_error_set(error, ENOTSUP,
-  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
-  NULL,
-  "compare item field not support");
-   if (comp_m->a.field == RTE_FLOW_FIELD_VALUE &&
-   comp_m->b.field == RTE_FLOW_FIELD_VALUE)
-   return rte_flow_error_set(error, EINVAL,
-  RTE_FLO

[PATCH v7 3/3] net/mlx5/hws: add compare ESP sequence number support

[Michael Baum]

Add support for compare item with "RTE_FLOW_FIELD_ESP_SEQ_NUM" field.

Signed-off-by: Michael Baum 
Acked-by: Suanming Mou 
---
 doc/guides/nics/mlx5.rst  |  1 +
 drivers/net/mlx5/hws/mlx5dr_definer.c | 22 --
 drivers/net/mlx5/mlx5_flow_hw.c   |  3 +++
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index c0a5768117..d7bf81161e 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -434,6 +434,7 @@ Limitations
   - Only single item is supported per pattern template.
   - Only 32-bit comparison is supported or 16-bits for random field.
   - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``,
+``RTE_FLOW_FIELD_ESP_SEQ_NUM``,
 ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``.
   - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field.
   - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c 
b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 45e5bc5a61..c1508e6b53 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -424,10 +424,20 @@ mlx5dr_definer_compare_base_value_set(const void 
*item_spec,
 
value = (const uint32_t *)&b->value[0];
 
-   if (a->field == RTE_FLOW_FIELD_RANDOM)
+   switch (a->field) {
+   case RTE_FLOW_FIELD_RANDOM:
*base = htobe32(*value << 16);
-   else
+   break;
+   case RTE_FLOW_FIELD_TAG:
+   case RTE_FLOW_FIELD_META:
*base = htobe32(*value);
+   break;
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
+   *base = *value;
+   break;
+   default:
+   break;
+   }
 
MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1);
 }
@@ -2930,6 +2940,14 @@ mlx5dr_definer_conv_item_compare_field(const struct 
rte_flow_field_data *f,
fc->compare_idx = dw_offset;
DR_CALC_SET_HDR(fc, random_number, random_number);
break;
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
+   fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER];
+   fc->item_idx = item_idx;
+   fc->tag_set = &mlx5dr_definer_compare_set;
+   fc->tag_mask_set = &mlx5dr_definer_ones_set;
+   fc->compare_idx = dw_offset;
+   DR_CALC_SET_HDR(fc, ipsec, sequence_number);
+   break;
default:
DR_LOG(ERR, "%u field is not supported", f->field);
goto err_notsup;
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index f31ba2df2b..531c90e0ee 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -6729,6 +6729,7 @@ flow_hw_item_compare_field_validate(enum 
rte_flow_field_id arg_field,
switch (arg_field) {
case RTE_FLOW_FIELD_TAG:
case RTE_FLOW_FIELD_META:
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
break;
case RTE_FLOW_FIELD_RANDOM:
if (base_field == RTE_FLOW_FIELD_VALUE)
@@ -6747,6 +6748,7 @@ flow_hw_item_compare_field_validate(enum 
rte_flow_field_id arg_field,
case RTE_FLOW_FIELD_TAG:
case RTE_FLOW_FIELD_META:
case RTE_FLOW_FIELD_VALUE:
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
break;
default:
return rte_flow_error_set(error, ENOTSUP,
@@ -6763,6 +6765,7 @@ flow_hw_item_compare_width_supported(enum 
rte_flow_field_id field)
switch (field) {
case RTE_FLOW_FIELD_TAG:
case RTE_FLOW_FIELD_META:
+   case RTE_FLOW_FIELD_ESP_SEQ_NUM:
return 32;
case RTE_FLOW_FIELD_RANDOM:
return 16;
-- 
2.25.1

[PATCH v7 0/3] net/mlx5: add compare item support

[Michael Baum]

Add HWS support for compare item with:
- "RTE_FLOW_FIELD_TAG".
- "RTE_FLOW_FIELD_NETA".
- "RTE_FLOW_FIELD_VALUE".

Add HWS + PMD support for compare item with:
- "RTE_FLOW_FIELD_RANDOM".
- "RTE_FLOW_FIELD_ESP_SEQ_NUM".

v2:
 - Rebase.
 - Add "RTE_FLOW_FIELD_META" compare support.
 - Reduce the "Depends-on" list.

v3:
 - Rebase.
 - Fix typo in function name, r/tranlate/translate.
 - Fix adding a line without newline at end of file.

v4:
 - Rebase.
 - Update documentation.
 - Remove the "Depends-on" label.

v5:
 - Rebase.
 - Add ESP sequence number suppoert and rename the series accordingly.

v6:
 - Rebase.
 - Add "Acked-by" from v5.

v7:
 - Rebase.

Hamdan Igbaria (1):
  net/mlx5/hws: add support for compare matcher

Michael Baum (2):
  net/mlx5: add support to compare random value
  net/mlx5/hws: add compare ESP sequence number support

 doc/guides/nics/mlx5.rst  |  10 +-
 drivers/common/mlx5/mlx5_prm.h|  16 ++
 drivers/net/mlx5/hws/mlx5dr_cmd.c |   9 +-
 drivers/net/mlx5/hws/mlx5dr_cmd.h |   1 +
 drivers/net/mlx5/hws/mlx5dr_debug.c   |   4 +-
 drivers/net/mlx5/hws/mlx5dr_debug.h   |   1 +
 drivers/net/mlx5/hws/mlx5dr_definer.c | 261 +-
 drivers/net/mlx5/hws/mlx5dr_definer.h |  33 
 drivers/net/mlx5/hws/mlx5dr_matcher.c |  53 ++
 drivers/net/mlx5/hws/mlx5dr_matcher.h |  12 +-
 drivers/net/mlx5/mlx5_flow_hw.c   |  73 +--
 11 files changed, 444 insertions(+), 29 deletions(-)

-- 
2.25.1

RE: [PATCH v5 05/39] ring: use C11 alignas

[Konstantin Ananyev]

> 
> The current location used for __rte_aligned(a) for alignment of types
> and variables is not compatible with MSVC. There is only a single
> location accepted by both toolchains.
> 
> For variables standard C11 offers alignas(a) supported by conformant
> compilers i.e. both MSVC and GCC.
> 
> For types the standard offers no alignment facility that compatibly
> interoperates with C and C++ but may be achieved by relocating the
> placement of __rte_aligned(a) to the aforementioned location accepted
> by all currently supported toolchains.
> 
> To allow alignment for both compilers do the following:
> 
> * Move __rte_aligned from the end of {struct,union} definitions to
>   be between {struct,union} and tag.
> 
>   The placement between {struct,union} and the tag allows the desired
>   alignment to be imparted on the type regardless of the toolchain being
>   used for all of GCC, LLVM, MSVC compilers building both C and C++.
> 
> * Replace use of __rte_aligned(a) on variables/fields with alignas(a).
> 
> Signed-off-by: Tyler Retzlaff 
> Acked-by: Morten Brørup 
> ---
>  lib/ring/rte_ring_core.h| 16 +---
>  lib/ring/rte_ring_peek_zc.h |  4 ++--
>  2 files changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/lib/ring/rte_ring_core.h b/lib/ring/rte_ring_core.h
> index b770873..497d535 100644
> --- a/lib/ring/rte_ring_core.h
> +++ b/lib/ring/rte_ring_core.h
> @@ -19,6 +19,8 @@
>   * instead.
>   */
> 
> +#include 
> +
>  #ifdef __cplusplus
>  extern "C" {
>  #endif
> @@ -78,7 +80,7 @@ struct rte_ring_headtail {
> 
>  union __rte_ring_rts_poscnt {
>   /** raw 8B value to read/write *cnt* and *pos* as one atomic op */
> - RTE_ATOMIC(uint64_t) raw __rte_aligned(8);
> + alignas(8) RTE_ATOMIC(uint64_t) raw;

One small question - here and below, would it possible to do 
'alignas(sizeof(uint64_t))' instead of 'alignas(8)?
Or MSVC has some restrictions here?


>   struct {
>   uint32_t cnt; /**< head/tail reference counter */
>   uint32_t pos; /**< head/tail position */
> @@ -94,7 +96,7 @@ struct rte_ring_rts_headtail {
> 

RE: [PATCH v2] app/testpmd: use Tx preparation in txonly engine

[Konstantin Ananyev]

> >>> TSO breaks when MSS spans more than 8 data fragments. Those
> >>> packets will be dropped by Tx preparation API, but it will
> >>> cause
> >>> MDD event if txonly forwarding engine does not call the Tx
> > preparation
> >>> API before transmitting packets.
> >>>
> >>
> >> txonly is used commonly, adding Tx prepare for a specific case
> >>> may
> >> impact performance for users.
> >>
> >> What happens when driver throws MDD (Malicious Driver Detection)
> > event,
> >> can't it be ignored? As you are already OK to drop the packet,
> >>> can
> >> device be configured to drop these packages?
> >>
> >>
> >> Or as Jerin suggested adding a new forwarding engine is a
> >>> solution,
> > but
> >> that will create code duplication, I prefer to not have it if
> >>> this
> > can
> >> be handled in device level.
> >
> > Actually I am agree with the author of the patch - when TX offloads
> > and/or multisegs are enabled,
> > user supposed to invoke eth_tx_prepare().
> > Not doing that seems like a bug to me.
> 
>  I strongly disagree with that statement, Konstantin!
>  It is not documented anywhere that using TX offloads and/or multisegs
> >>> requires calling rte_eth_tx_prepare() before
>  rte_eth_tx_burst(). And none of the examples do it.
> >>>
> >>> In fact, we do use it for test-pmd/csumonly.c.
> >>> About other sample apps:
> >>> AFAIK, not many of other DPDK apps do use L4 offloads.
> >>> Right now special treatment (pseudo-header cksum calculation) is needed
> >>> only for L4 offloads (CKSUM, SEG).
> >>> So, majority of our apps who rely on other TX offloads (multi-seg, ipv4
> >>> cksum, vlan insertion) happily run without
> >>> calling tx_prepare(), even though it is not the safest way.
> >>>
> 
>  In my opinion:
>  If some driver has limitations for a feature, e.g. max 8 fragments,
> >>> it should be documented for that driver, so the application
>  developer can make the appropriate decisions when designing the
> >>> application.
>  Furthermore, we have APIs for the drivers to expose to the
> >>> applications what the driver supports, so the application can configure
>  itself optimally at startup. Perhaps those APIs need to be expanded.
>  And if a feature limitation is common across the majority of drivers,
> >>> that limitation should be mentioned in the documentation of the
>  feature itself.
> >>>
> >>> Many of such limitations *are* documented and in fact we do have an API
> >>> to check max segments that each driver support,
> >>> see struct rte_eth_desc_lim.
> >>
> >> Yes, this is the kind of API we should provide, so the application can 
> >> configure itself appropriately.
> >>
> >>> The problem is:
> >>> - none of our sample app does proper check on these values, so users
> >>> don't have a good example how to do it.
> >>
> >> Agreed.
> >> Adding an example showing how to do it properly would be the best solution.
> >> Calling tx_prepare() in the examples is certainly not the solution.
> >>
> >>> - with current DPDK API not all of HW/PMD requirements could be
> >>> extracted programmatically:
> >>>let say majority of Intel PMDs for TCP offloads expect pseudo-header
> >>> cksum to be pre-calculated by the SW.
> >>
> >> I hope this requirement is documented somewhere.
> >>
> >>>another example, some HW expects pkt_len to be bigger then some
> >>> threshold value, otherwise HW hang may appear.
> >>
> >> I hope this requirement is also documented somewhere.
> >
> > No idea, I found it only in the code.
> 
> IMHO Tx burst must check such limitations. If you made your HW simpler
> (or just lost it on initial testing), pay in your drivers (or your
> HW+driver will be unusable because of such problems).
> 
> >> Generally, if the requirements cannot be extracted programmatically, they 
> >> must be prominently documented, like this note to
> >> rte_eth_rx_burst():
> >
> > Obviously, more detailed documentation is always good, but...
> > Right now we have 50+ different PMDs from different vendors.
> > Even if each and every of them will carefully document all possible 
> > limitations and necessary preparation steps,
> > how DPDK app developer supposed to  deal with all that?
> > Do you expect everyone, to read carefully through all of them, and handle 
> > all of them properly oh his own
> > in each and every DPDK app he is going to write?
> > That seems unrealistic.
> > Again what to do with backward compatibility: when new driver (with new 
> > limitations) will arise
> > *after* your app is already written and tested?
> 
> +1
> 
> >>
> >>   * @note
> >>   *   Some drivers using vector instructions require that *nb_pkts* is
> >>   *   divisible by 4 or 8, depending on the driver implementation.
> 
> I'm wondering what application should do if it needs to send just one
> packet and do it now. IMHO, such limitations are not acceptable.
> 
> >

[PATCH] app/eventdev: support DMA adapter test

[Amit Prakash Shukla]

Added performance test support for DMA adapter.

Signed-off-by: Amit Prakash Shukla 
---
 app/test-eventdev/evt_common.h   |   3 +
 app/test-eventdev/evt_main.c |  15 ++
 app/test-eventdev/evt_options.c  |  28 +++
 app/test-eventdev/evt_options.h  |  12 ++
 app/test-eventdev/evt_test.h |   6 +
 app/test-eventdev/test_perf_atq.c|  32 ++-
 app/test-eventdev/test_perf_common.c | 293 ++-
 app/test-eventdev/test_perf_common.h |  35 +++-
 app/test-eventdev/test_perf_queue.c  |  30 ++-
 doc/guides/tools/testeventdev.rst|  13 ++
 10 files changed, 438 insertions(+), 29 deletions(-)

diff --git a/app/test-eventdev/evt_common.h b/app/test-eventdev/evt_common.h
index fcb3571438..dbe1e5c0c4 100644
--- a/app/test-eventdev/evt_common.h
+++ b/app/test-eventdev/evt_common.h
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -42,6 +43,7 @@ enum evt_prod_type {
EVT_PROD_TYPE_ETH_RX_ADPTR,  /* Producer type Eth Rx Adapter. */
EVT_PROD_TYPE_EVENT_TIMER_ADPTR,  /* Producer type Timer Adapter. */
EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR,  /* Producer type Crypto Adapter. */
+   EVT_PROD_TYPE_EVENT_DMA_ADPTR,  /* Producer type DMA Adapter. */
EVT_PROD_TYPE_MAX,
 };
 
@@ -86,6 +88,7 @@ struct evt_options {
uint64_t timer_tick_nsec;
uint64_t optm_timer_tick_nsec;
enum evt_prod_type prod_type;
+   enum rte_event_dma_adapter_mode dma_adptr_mode;
enum rte_event_crypto_adapter_mode crypto_adptr_mode;
enum rte_crypto_op_type crypto_op_type;
enum rte_crypto_cipher_algorithm crypto_cipher_alg;
diff --git a/app/test-eventdev/evt_main.c b/app/test-eventdev/evt_main.c
index 13a8500ef7..03114020f1 100644
--- a/app/test-eventdev/evt_main.c
+++ b/app/test-eventdev/evt_main.c
@@ -138,6 +138,14 @@ main(int argc, char **argv)
}
}
 
+   /* Test specific dmadev setup */
+   if (test->ops.dmadev_setup) {
+   if (test->ops.dmadev_setup(test, &opt)) {
+   evt_err("%s: dmadev setup failed", opt.test_name);
+   goto dmadev_destroy;
+   }
+   }
+
/* Test specific eventdev setup */
if (test->ops.eventdev_setup) {
if (test->ops.eventdev_setup(test, &opt)) {
@@ -171,6 +179,9 @@ main(int argc, char **argv)
if (test->ops.cryptodev_destroy)
test->ops.cryptodev_destroy(test, &opt);
 
+   if (test->ops.dmadev_destroy)
+   test->ops.dmadev_destroy(test, &opt);
+
if (test->ops.mempool_destroy)
test->ops.mempool_destroy(test, &opt);
 
@@ -196,6 +207,10 @@ main(int argc, char **argv)
if (test->ops.cryptodev_destroy)
test->ops.cryptodev_destroy(test, &opt);
 
+dmadev_destroy:
+   if (test->ops.dmadev_destroy)
+   test->ops.dmadev_destroy(test, &opt);
+
 ethdev_destroy:
if (test->ops.ethdev_destroy)
test->ops.ethdev_destroy(test, &opt);
diff --git a/app/test-eventdev/evt_options.c b/app/test-eventdev/evt_options.c
index 03fb3bfce0..c624433b47 100644
--- a/app/test-eventdev/evt_options.c
+++ b/app/test-eventdev/evt_options.c
@@ -146,6 +146,27 @@ evt_parse_timer_prod_type_burst(struct evt_options *opt,
return 0;
 }
 
+static int
+evt_parse_dma_prod_type(struct evt_options *opt,
+  const char *arg __rte_unused)
+{
+   opt->prod_type = EVT_PROD_TYPE_EVENT_DMA_ADPTR;
+   return 0;
+}
+
+static int
+evt_parse_dma_adptr_mode(struct evt_options *opt, const char *arg)
+{
+   uint8_t mode;
+   int ret;
+
+   ret = parser_read_uint8(&mode, arg);
+   opt->dma_adptr_mode = mode ? RTE_EVENT_DMA_ADAPTER_OP_FORWARD :
+   RTE_EVENT_DMA_ADAPTER_OP_NEW;
+   return ret;
+}
+
+
 static int
 evt_parse_crypto_prod_type(struct evt_options *opt,
   const char *arg __rte_unused)
@@ -446,6 +467,7 @@ usage(char *program)
"\t--queue_priority   : enable queue priority\n"
"\t--deq_tmo_nsec : global dequeue timeout\n"
"\t--prod_type_ethdev : use ethernet device as producer.\n"
+   "\t--prod_type_dmadev : use dma device as producer.\n"
"\t--prod_type_cryptodev : use crypto device as producer.\n"
"\t--prod_type_timerdev : use event timer device as producer.\n"
"\t expiry_nsec would be the timeout\n"
@@ -457,6 +479,8 @@ usage(char *program)
"\t--timer_tick_nsec  : timer tick interval in ns.\n"
"\t--max_tmo_nsec : max timeout interval in ns.\n"
"\t--expiry_nsec  : event timer expiry ns.\n"
+   "\t--dma_adptr_mode   : 0 for OP_NEW mode (default) and\n"
+   "\t 1 for OP_FORWARD mode.\n"
"\t--crypto_adptr_mode : 0 for

Re: [PATCH v2 0/4] add new QAT gen3 and gen5

[Ji, Kai]

Series-acked-by: Kai Ji 


From: Power, Ciara 
Sent: 23 February 2024 15:12
To: dev@dpdk.org 
Cc: gak...@marvell.com ; Ji, Kai ; 
Kusztal, ArkadiuszX ; Power, Ciara 

Subject: [PATCH v2 0/4] add new QAT gen3 and gen5

This patchset adds support for two new QAT devices.
A new GEN3 device, and a GEN5 device, both of which have
wireless slice support for algorithms such as ZUC-256.

Symmetric, asymmetric and compression are all supported
for these devices.

v2:
  - New patch added for gen5 device that reuses gen4 code,
and new gen3 wireless slice changes.
  - Removed patch to disable asymmetric and compression.
  - Documentation updates added.
  - Fixed ZUC-256 IV modification for raw API path.
  - Fixed setting extended protocol flag bit position.
  - Added check for ZUC-256 wireless slice in slice map.

Ciara Power (4):
  common/qat: add new gen3 device
  common/qat: add zuc256 wireless slice for gen3
  common/qat: add new gen3 CMAC macros
  common/qat: add gen5 device

 doc/guides/compressdevs/qat_comp.rst |   1 +
 doc/guides/cryptodevs/qat.rst|   6 +
 doc/guides/rel_notes/release_24_03.rst   |   7 +
 drivers/common/qat/dev/qat_dev_gen4.c|  31 ++-
 drivers/common/qat/dev/qat_dev_gen5.c|  51 
 drivers/common/qat/dev/qat_dev_gens.h|  54 
 drivers/common/qat/meson.build   |   3 +
 drivers/common/qat/qat_adf/icp_qat_fw.h  |   6 +-
 drivers/common/qat/qat_adf/icp_qat_fw_la.h   |  24 ++
 drivers/common/qat/qat_adf/icp_qat_hw.h  |  26 +-
 drivers/common/qat/qat_common.h  |   1 +
 drivers/common/qat/qat_device.c  |  19 ++
 drivers/common/qat/qat_device.h  |   2 +
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c |   8 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen5.c |  73 +
 drivers/compress/qat/dev/qat_comp_pmd_gens.h |  14 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |   7 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c |  63 -
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c |   4 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c | 278 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  40 ++-
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c|  43 +++
 drivers/crypto/qat/qat_sym_session.c | 177 ++--
 drivers/crypto/qat/qat_sym_session.h |   2 +
 24 files changed, 889 insertions(+), 51 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen5.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen5.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c

--
2.25.1

[PATCH v5 01/14] common/cnxk: remove cn9k Inline IPsec FP opcode defines

[Nithin Dabilpuram]

Since now Inline IPsec in cn9k is using same opcode as LA,
remove the definitions of fast path opcode.

Also fix devarg handling for ipsec_out_max_sa to allow 32-bit.

Fixes: fe5846bcc076 ("net/cnxk: add devargs for min-max SPI")
Signed-off-by: Nithin Dabilpuram 
---

v5:
- Fixed commit messages and added fixes

v4:
- Fixed compilation warnings

v3:
- Added mempool debug fixes patch 14/14

v2:
- Fixed commit messages

drivers/common/cnxk/cnxk_security.c| 230 -
 drivers/common/cnxk/cnxk_security.h|  12 --
 drivers/common/cnxk/roc_ie_on.h|  60 ---
 drivers/common/cnxk/roc_nix_inl.h  |  50 +-
 drivers/common/cnxk/version.map|   4 -
 drivers/net/cnxk/cnxk_ethdev_devargs.c |   2 +-
 6 files changed, 3 insertions(+), 355 deletions(-)

diff --git a/drivers/common/cnxk/cnxk_security.c 
b/drivers/common/cnxk/cnxk_security.c
index 64c901a57a..bab015e3b3 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -574,236 +574,6 @@ cnxk_ot_ipsec_outb_sa_valid(struct roc_ot_ipsec_outb_sa 
*sa)
return !!sa->w2.s.valid;
 }
 
-static inline int
-ipsec_xfrm_verify(struct rte_security_ipsec_xform *ipsec_xfrm,
- struct rte_crypto_sym_xform *crypto_xfrm)
-{
-   if (crypto_xfrm->next == NULL)
-   return -EINVAL;
-
-   if (ipsec_xfrm->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {
-   if (crypto_xfrm->type != RTE_CRYPTO_SYM_XFORM_AUTH ||
-   crypto_xfrm->next->type != RTE_CRYPTO_SYM_XFORM_CIPHER)
-   return -EINVAL;
-   } else {
-   if (crypto_xfrm->type != RTE_CRYPTO_SYM_XFORM_CIPHER ||
-   crypto_xfrm->next->type != RTE_CRYPTO_SYM_XFORM_AUTH)
-   return -EINVAL;
-   }
-
-   return 0;
-}
-
-static int
-onf_ipsec_sa_common_param_fill(struct roc_ie_onf_sa_ctl *ctl, uint8_t *salt,
-  uint8_t *cipher_key, uint8_t *hmac_opad_ipad,
-  struct rte_security_ipsec_xform *ipsec_xfrm,
-  struct rte_crypto_sym_xform *crypto_xfrm)
-{
-   struct rte_crypto_sym_xform *auth_xfrm, *cipher_xfrm;
-   int rc, length, auth_key_len;
-   const uint8_t *key = NULL;
-   uint8_t ccm_flag = 0;
-
-   /* Set direction */
-   switch (ipsec_xfrm->direction) {
-   case RTE_SECURITY_IPSEC_SA_DIR_INGRESS:
-   ctl->direction = ROC_IE_SA_DIR_INBOUND;
-   auth_xfrm = crypto_xfrm;
-   cipher_xfrm = crypto_xfrm->next;
-   break;
-   case RTE_SECURITY_IPSEC_SA_DIR_EGRESS:
-   ctl->direction = ROC_IE_SA_DIR_OUTBOUND;
-   cipher_xfrm = crypto_xfrm;
-   auth_xfrm = crypto_xfrm->next;
-   break;
-   default:
-   return -EINVAL;
-   }
-
-   /* Set protocol - ESP vs AH */
-   switch (ipsec_xfrm->proto) {
-   case RTE_SECURITY_IPSEC_SA_PROTO_ESP:
-   ctl->ipsec_proto = ROC_IE_SA_PROTOCOL_ESP;
-   break;
-   case RTE_SECURITY_IPSEC_SA_PROTO_AH:
-   return -ENOTSUP;
-   default:
-   return -EINVAL;
-   }
-
-   /* Set mode - transport vs tunnel */
-   switch (ipsec_xfrm->mode) {
-   case RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT:
-   ctl->ipsec_mode = ROC_IE_SA_MODE_TRANSPORT;
-   break;
-   case RTE_SECURITY_IPSEC_SA_MODE_TUNNEL:
-   ctl->ipsec_mode = ROC_IE_SA_MODE_TUNNEL;
-   break;
-   default:
-   return -EINVAL;
-   }
-
-   /* Set encryption algorithm */
-   if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
-   length = crypto_xfrm->aead.key.length;
-
-   switch (crypto_xfrm->aead.algo) {
-   case RTE_CRYPTO_AEAD_AES_GCM:
-   ctl->enc_type = ROC_IE_ON_SA_ENC_AES_GCM;
-   ctl->auth_type = ROC_IE_ON_SA_AUTH_NULL;
-   memcpy(salt, &ipsec_xfrm->salt, 4);
-   key = crypto_xfrm->aead.key.data;
-   break;
-   case RTE_CRYPTO_AEAD_AES_CCM:
-   ctl->enc_type = ROC_IE_ON_SA_ENC_AES_CCM;
-   ctl->auth_type = ROC_IE_ON_SA_AUTH_NULL;
-   ccm_flag = 0x07 & ~ROC_CPT_AES_CCM_CTR_LEN;
-   *salt = ccm_flag;
-   memcpy(PLT_PTR_ADD(salt, 1), &ipsec_xfrm->salt, 3);
-   key = crypto_xfrm->aead.key.data;
-   break;
-   default:
-   return -ENOTSUP;
-   }
-
-   } else {
-   rc = ipsec_xfrm_verify(ipsec_xfrm, crypto_xfrm);
-   if (rc)
-   return rc;
-
-   switch (cipher_xfrm->cipher.algo) {
-   case RTE_CRYPTO_CIPHER_AES_CBC:
-   ctl->enc_type = R

[PATCH v5 02/14] net/cnxk: add IPsec SA defines for PMD API

[Nithin Dabilpuram]

Define inbound and outbound IPsec data type for PMD API's
rte_pmd_cnxk_hw_sa_read() and rte_pmd_cnxk_hw_sa_write().

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_ethdev_sec.c |  18 +-
 drivers/net/cnxk/rte_pmd_cnxk.h | 397 +++-
 2 files changed, 411 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c 
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 575d0fabd5..05ec49d981 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -14,6 +14,20 @@
 #include 
 #include 
 
+PLT_STATIC_ASSERT(offsetof(struct rte_pmd_cnxk_ipsec_inb_sa, ctx.ar_winbits) ==
+ offsetof(struct roc_ot_ipsec_inb_sa, ctx.ar_winbits));
+
+PLT_STATIC_ASSERT(offsetof(struct rte_pmd_cnxk_ipsec_outb_sa, ctx.mib_pkts) ==
+ offsetof(struct roc_ot_ipsec_outb_sa, ctx.mib_pkts));
+
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_CTX_MAX_CKEY_LEN == ROC_CTX_MAX_CKEY_LEN);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN == 
RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN);
+
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WIN_SIZE_MIN == ROC_AR_WIN_SIZE_MIN);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WIN_SIZE_MAX == ROC_AR_WIN_SIZE_MAX);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 == 
ROC_LOG_MIN_AR_WIN_SIZE_M1);
+PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WINBITS_SZ == ROC_AR_WINBITS_SZ);
+
 static struct rte_cryptodev_capabilities cn10k_eth_sec_crypto_caps[] = {
{   /* AES GCM */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -1143,7 +1157,7 @@ cn10k_eth_sec_session_update(void *device, struct 
rte_security_session *sess,
 
 int
 rte_pmd_cnxk_hw_sa_read(void *device, struct rte_security_session *sess,
-   void *data, uint32_t len)
+   union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len)
 {
struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device;
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
@@ -1166,7 +1180,7 @@ rte_pmd_cnxk_hw_sa_read(void *device, struct 
rte_security_session *sess,
 
 int
 rte_pmd_cnxk_hw_sa_write(void *device, struct rte_security_session *sess,
-void *data, uint32_t len)
+union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len)
 {
struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device;
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
diff --git a/drivers/net/cnxk/rte_pmd_cnxk.h b/drivers/net/cnxk/rte_pmd_cnxk.h
index 7827c33ac9..43f2a7ed9b 100644
--- a/drivers/net/cnxk/rte_pmd_cnxk.h
+++ b/drivers/net/cnxk/rte_pmd_cnxk.h
@@ -60,6 +60,399 @@ struct rte_pmd_cnxk_sec_action {
enum rte_pmd_cnxk_sec_action_alg alg;
 };
 
+#define RTE_PMD_CNXK_CTX_MAX_CKEY_LEN 32
+#define RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN 128
+
+/** Anti reply window size supported */
+#define RTE_PMD_CNXK_AR_WIN_SIZE_MIN   64
+#define RTE_PMD_CNXK_AR_WIN_SIZE_MAX   4096
+#define RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 5
+
+/** u64 array size to fit anti replay window bits */
+#define RTE_PMD_CNXK_AR_WINBITS_SZ 
(RTE_ALIGN_CEIL(RTE_PMD_CNXK_AR_WIN_SIZE_MAX, 64) / 64)
+
+/** Outer header info for Inbound or Outbound */
+union rte_pmd_cnxk_ipsec_outer_ip_hdr {
+   struct {
+   /** IPv4 destination */
+   uint32_t dst_addr;
+   /** IPv4 source */
+   uint32_t src_addr;
+   } ipv4;
+   struct {
+   /** IPv6 source */
+   uint8_t src_addr[16];
+   /** IPv6 destination */
+   uint8_t dst_addr[16];
+   } ipv6;
+};
+
+/** Inbound IPsec context update region */
+struct rte_pmd_cnxk_ipsec_inb_ctx_update_reg {
+   /** Highest sequence number received */
+   uint64_t ar_base;
+   /** Valid bit for 64-bit words of replay window */
+   uint64_t ar_valid_mask;
+   /** Hard life for SA */
+   uint64_t hard_life;
+   /** Soft life for SA */
+   uint64_t soft_life;
+   /** MIB octets */
+   uint64_t mib_octs;
+   /** MIB packets */
+   uint64_t mib_pkts;
+   /** AR window bits */
+   uint64_t ar_winbits[RTE_PMD_CNXK_AR_WINBITS_SZ];
+};
+
+/** Outbound IPsec IV data */
+union rte_pmd_cnxk_ipsec_outb_iv {
+   uint64_t u64[2];
+   /** IV debug - 16B*/
+   uint8_t iv_dbg[16];
+   struct {
+   /** IV debug - 8B */
+   uint8_t iv_dbg1[4];
+   /** Salt */
+   uint8_t salt[4];
+
+   uint32_t rsvd;
+   /** IV debug - 8B */
+   uint8_t iv_dbg2[4];
+   } s;
+};
+
+/** Outbound IPsec context update region */
+struct rte_pmd_cnxk_ipsec_outb_ctx_update_reg {
+   union {
+   struct {
+   uint64_t reserved_0_2 : 3;
+   uint64_t address : 57;
+   uint64_t mode : 4;
+   } s;
+   uint64_t u64;
+   } err_ctl;
+
+   uint64_t esn_val;
+   uint64_t hard_life;
+  

[PATCH v5 03/14] net/cnxk: add transport mode to security capability on cn9k

[Nithin Dabilpuram]

Add transport mode to security capabilities since it
is supported by UCODE.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn9k_ethdev_sec.c | 33 ++
 1 file changed, 33 insertions(+)

diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c 
b/drivers/net/cnxk/cn9k_ethdev_sec.c
index 688b13ae1e..a0e0a73639 100644
--- a/drivers/net/cnxk/cn9k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn9k_ethdev_sec.c
@@ -351,6 +351,39 @@ static const struct rte_security_capability 
cn9k_eth_sec_capabilities[] = {
.crypto_capabilities = cn9k_eth_sec_crypto_caps,
.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA
},
+   {   /* IPsec Inline Protocol ESP Transport Ingress */
+   .action = RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL,
+   .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
+   .ipsec = {
+   .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
+   .mode = RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT,
+   .direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,
+   .replay_win_sz_max = CNXK_ON_AR_WIN_SIZE_MAX,
+   .options = {
+   .udp_encap = 1,
+   .esn = 1,
+   },
+   },
+   .crypto_capabilities = cn9k_eth_sec_crypto_caps,
+   .ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA
+   },
+   {   /* IPsec Inline Protocol ESP Transport Egress */
+   .action = RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL,
+   .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
+   .ipsec = {
+   .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
+   .mode = RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT,
+   .direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,
+   .replay_win_sz_max = CNXK_ON_AR_WIN_SIZE_MAX,
+   .options = {
+   .iv_gen_disable = 1,
+   .udp_encap = 1,
+   .esn = 1,
+   },
+   },
+   .crypto_capabilities = cn9k_eth_sec_crypto_caps,
+   .ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA
+   },
{
.action = RTE_SECURITY_ACTION_TYPE_NONE
}
-- 
2.25.1

[PATCH v5 04/14] common/cnxk: dump selected SQ entries

[Nithin Dabilpuram]

From: Satha Rao 

New API to dump detailed SQ entries.

Signed-off-by: Satha Rao 
---
 drivers/common/cnxk/roc_nix.h   |   2 +
 drivers/common/cnxk/roc_nix_debug.c | 172 
 drivers/common/cnxk/version.map |   1 +
 3 files changed, 175 insertions(+)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 84e6fc3df5..9d57ca0be7 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -553,6 +553,8 @@ void __roc_api roc_nix_cqe_dump(FILE *file, const struct 
nix_cqe_hdr_s *cq);
 void __roc_api roc_nix_rq_dump(struct roc_nix_rq *rq, FILE *file);
 void __roc_api roc_nix_cq_dump(struct roc_nix_cq *cq, FILE *file);
 void __roc_api roc_nix_sq_dump(struct roc_nix_sq *sq, FILE *file);
+int __roc_api roc_nix_sq_desc_dump(struct roc_nix *roc_nix, uint16_t q, 
uint16_t offset,
+  uint16_t num, FILE *file);
 void __roc_api roc_nix_tm_dump(struct roc_nix *roc_nix, FILE *file);
 void __roc_api roc_nix_dump(struct roc_nix *roc_nix, FILE *file);
 
diff --git a/drivers/common/cnxk/roc_nix_debug.c 
b/drivers/common/cnxk/roc_nix_debug.c
index 8962a76097..26546f9297 100644
--- a/drivers/common/cnxk/roc_nix_debug.c
+++ b/drivers/common/cnxk/roc_nix_debug.c
@@ -1362,3 +1362,175 @@ roc_nix_inl_outb_cpt_lfs_dump(struct roc_nix *roc_nix, 
FILE *file)
cpt_lf_print(&lf_base[i]);
}
 }
+
+static void
+nix_tm_sqe_dump(uint64_t *sqe, int head_off, int end_off, int instr_sz, FILE 
*file, int full,
+   uint16_t *num)
+{
+   int i, j, inc = (8 * (0x2 >> instr_sz)), segs;
+   uint64_t *ptr;
+
+   if (!sqe || !(*num))
+   return;
+
+   ptr = sqe + (head_off * inc);
+   for (i = head_off; i < end_off; i++) {
+   if (!(*num))
+   return;
+   ptr = sqe + (i * inc);
+   nix_dump(file, "Entry : %d >\n", i);
+   nix_dump(file, "\t\tSEND_HDR[0]: 0x%016lx SEND_HDR[1]: 
0x%016lx\n", *ptr,
+*(ptr + 1));
+   *num = *num - 1;
+   if (!full)
+   continue;
+   ptr += 2;
+   if (((*ptr >> 60) & 0xF) == NIX_SUBDC_EXT) {
+   nix_dump(file, "\t\tSUBDC_EXT[0]: 0x%016lx 
DUBDC_EXT[1]: 0x%016lx\n", *ptr,
+*(ptr + 1));
+   ptr += 2;
+   }
+   if (((*ptr >> 60) & 0xF) == NIX_SUBDC_AGE_AND_STATS) {
+   nix_dump(file,
+"\t\tSUBDC_AGE_STATS[0]: 0x%016lx 
SUBDC_AGE_STATS[1]: 0x%016lx\n",
+*ptr, *(ptr + 1));
+   ptr += 2;
+   }
+   if (((*ptr >> 60) & 0xF) == NIX_SUBDC_JUMP) {
+   nix_dump(file, "\t\tSUBDC_JUMP: 0x%016lx\n", *ptr);
+   ptr += 1;
+   ptr = (uint64_t *)*ptr;
+   }
+   if (((*ptr >> 60) & 0xF) == NIX_SUBDC_CRC) {
+   nix_dump(file, "\t\tSUBDC_CRC[0]: 0x%016lx 
SUBDC_CRC[1]: 0x%016lx\n", *ptr,
+*(ptr + 1));
+   ptr += 2;
+   }
+   /* We are not parsing immediate send descriptor */
+   if (((*ptr >> 60) & 0xF) == NIX_SUBDC_IMM) {
+   nix_dump(file, "\t\tSUBDC_IMM: 0x%016lx ", *ptr);
+   continue;
+   }
+   while (1) {
+   if (((*ptr >> 60) & 0xF) == NIX_SUBDC_SG) {
+   nix_dump(file, "\t\tSUBDC_SG: 0x%016lx   ", 
*ptr);
+   segs = (*ptr >> 48) & 0x3;
+   ptr += 1;
+   for (j = 0; j < segs; j++) {
+   nix_dump(file, "\t\t\t  0x%016lx   ", 
*ptr);
+   ptr += 1;
+   }
+   if (segs == 2)
+   ptr += 1;
+   } else if (((*ptr >> 60) & 0xF) == NIX_SUBDC_SG2) {
+   nix_dump(file, "\t\tSUBDC_SG2: 0x%016lx   ", 
*ptr);
+   ptr += 1;
+   nix_dump(file, "\t\t\t  0x%016lx   ", *ptr);
+   ptr += 1;
+   } else
+   break;
+   }
+   }
+}
+
+int
+roc_nix_sq_desc_dump(struct roc_nix *roc_nix, uint16_t q, uint16_t offset, 
uint16_t num, FILE *file)
+{
+   int head_off, count, rc = 0, tail_off, full = 0;
+   struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+   struct roc_nix_sq *sq = nix->sqs[q];
+   void *sqb_buf, *dat, *tail_sqb;
+   struct ndc_sync_op *ndc_req;
+   struct dev *dev = &nix->dev;
+   uint16_t sqes_per_sqb;
+   struct mbox *mbox;
+
+ 

[PATCH v5 05/14] net/cnxk: added Tx descriptor dump API

[Nithin Dabilpuram]

From: Satha Rao 

New API to dump selected descriptor entries from SQE list.

Signed-off-by: Satha Rao 
---
 drivers/net/cnxk/cnxk_ethdev.c |  1 +
 drivers/net/cnxk/cnxk_ethdev.h |  2 ++
 drivers/net/cnxk/cnxk_ethdev_ops.c | 10 ++
 3 files changed, 13 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 2372a4e793..7640910782 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -1821,6 +1821,7 @@ struct eth_dev_ops cnxk_eth_dev_ops = {
.cman_config_init = cnxk_nix_cman_config_init,
.cman_config_set = cnxk_nix_cman_config_set,
.cman_config_get = cnxk_nix_cman_config_get,
+   .eth_tx_descriptor_dump = cnxk_nix_tx_descriptor_dump,
 };
 
 void
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 37b6395b93..45b9055234 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -557,6 +557,8 @@ int cnxk_nix_tm_mark_ip_ecn(struct rte_eth_dev *eth_dev, 
int mark_green,
 int cnxk_nix_tm_mark_ip_dscp(struct rte_eth_dev *eth_dev, int mark_green,
 int mark_yellow, int mark_red,
 struct rte_tm_error *error);
+int cnxk_nix_tx_descriptor_dump(const struct rte_eth_dev *eth_dev, uint16_t 
qid, uint16_t offset,
+   uint16_t num, FILE *file);
 
 /* MTR */
 int cnxk_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops);
diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c 
b/drivers/net/cnxk/cnxk_ethdev_ops.c
index 5de2919047..e9ab8da781 100644
--- a/drivers/net/cnxk/cnxk_ethdev_ops.c
+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c
@@ -1313,3 +1313,13 @@ nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev 
*eth_dev, uint16_t qid,
 exit:
return rc;
 }
+
+int
+cnxk_nix_tx_descriptor_dump(const struct rte_eth_dev *eth_dev, uint16_t qid, 
uint16_t offset,
+   uint16_t num, FILE *file)
+{
+   struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+   struct roc_nix *nix = &dev->nix;
+
+   return roc_nix_sq_desc_dump(nix, qid, offset, num, file);
+}
-- 
2.25.1

[PATCH v5 06/14] net/cnxk: fix issue with buff size compute

[Nithin Dabilpuram]

In case where cnxk_nix_mtu_set() is called before
data->min_rx_buf_size is set, use buf size from first RQ's
mempool.

Fixes: 34b46320f446 ("net/cnxk: perform early MTU setup for event mode")
Cc: sta...@dpdk.org

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cnxk_ethdev_ops.c | 25 ++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c 
b/drivers/net/cnxk/cnxk_ethdev_ops.c
index e9ab8da781..e816884d47 100644
--- a/drivers/net/cnxk/cnxk_ethdev_ops.c
+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c
@@ -544,8 +544,9 @@ cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
struct rte_eth_dev_data *data = eth_dev->data;
struct roc_nix *nix = &dev->nix;
+   struct cnxk_eth_rxq_sp *rxq_sp;
+   uint32_t buffsz = 0;
int rc = -EINVAL;
-   uint32_t buffsz;
 
frame_size += CNXK_NIX_TIMESYNC_RX_OFFSET * dev->ptp_en;
 
@@ -561,8 +562,24 @@ cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
goto exit;
}
 
-   buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
-   old_frame_size = data->mtu + CNXK_NIX_L2_OVERHEAD;
+   if (!eth_dev->data->nb_rx_queues)
+   goto skip_buffsz_check;
+
+   /* Perform buff size check */
+   if (data->min_rx_buf_size) {
+   buffsz = data->min_rx_buf_size;
+   } else if (eth_dev->data->rx_queues && eth_dev->data->rx_queues[0]) {
+   rxq_sp = cnxk_eth_rxq_to_sp(data->rx_queues[0]);
+
+   if (rxq_sp->qconf.mp)
+   buffsz = rte_pktmbuf_data_room_size(rxq_sp->qconf.mp);
+   }
+
+   /* Skip validation if RQ's are not yet setup */
+   if (!buffsz)
+   goto skip_buffsz_check;
+
+   buffsz -= RTE_PKTMBUF_HEADROOM;
 
/* Refuse MTU that requires the support of scattered packets
 * when this feature has not been enabled before.
@@ -580,6 +597,8 @@ cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
goto exit;
}
 
+skip_buffsz_check:
+   old_frame_size = data->mtu + CNXK_NIX_L2_OVERHEAD;
/* if new MTU was smaller than old one, then flush all SQs before MTU 
change */
if (old_frame_size > frame_size) {
if (data->dev_started) {
-- 
2.25.1

[PATCH v5 07/14] common/cnxk: fix Tx MTU configuration

[Nithin Dabilpuram]

Skip setting Tx MTU separately as now the Tx credit configuration
is based on max MTU possible for that link.
Also init MTU with max value for that port.

Fixes: 8589ec212e80 ("net/cnxk: support MTU set")

Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/cnxk/roc_nix.c  |  2 +-
 drivers/common/cnxk/roc_nix.h  |  2 --
 drivers/net/cnxk/cnxk_ethdev_ops.c | 12 +---
 3 files changed, 2 insertions(+), 14 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c
index 97c0ae3e25..90ccb260fb 100644
--- a/drivers/common/cnxk/roc_nix.c
+++ b/drivers/common/cnxk/roc_nix.c
@@ -484,7 +484,7 @@ roc_nix_dev_init(struct roc_nix *roc_nix)
sdp_lbk_id_update(pci_dev, nix);
nix->pci_dev = pci_dev;
nix->reta_sz = reta_sz;
-   nix->mtu = ROC_NIX_DEFAULT_HW_FRS;
+   nix->mtu = roc_nix_max_pkt_len(roc_nix);
nix->dmac_flt_idx = -1;
 
/* Register error and ras interrupts */
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 9d57ca0be7..3799b551f2 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -267,8 +267,6 @@ struct roc_nix_eeprom_info {
 #define ROC_NIX_RSS_KEY_LEN 48 /* 352 Bits */
 #define ROC_NIX_RSS_MCAM_IDX_DEFAULT (-1)
 
-#define ROC_NIX_DEFAULT_HW_FRS 1514
-
 #define ROC_NIX_VWQE_MAX_SIZE_LOG2 11
 #define ROC_NIX_VWQE_MIN_SIZE_LOG2 2
 
diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c 
b/drivers/net/cnxk/cnxk_ethdev_ops.c
index e816884d47..4962f3bced 100644
--- a/drivers/net/cnxk/cnxk_ethdev_ops.c
+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c
@@ -610,19 +610,9 @@ cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 
frame_size -= RTE_ETHER_CRC_LEN;
 
-   /* Update mtu on Tx */
-   rc = roc_nix_mac_mtu_set(nix, frame_size);
-   if (rc) {
-   plt_err("Failed to set MTU, rc=%d", rc);
-   goto exit;
-   }
-
-   /* Sync same frame size on Rx */
+   /* Set frame size on Rx */
rc = roc_nix_mac_max_rx_len_set(nix, frame_size);
if (rc) {
-   /* Rollback to older mtu */
-   roc_nix_mac_mtu_set(nix,
-   old_frame_size - RTE_ETHER_CRC_LEN);
plt_err("Failed to max Rx frame length, rc=%d", rc);
goto exit;
}
-- 
2.25.1

[PATCH v5 08/14] net/cnxk: fix max MTU limit

[Nithin Dabilpuram]

From: Sunil Kumar Kori 

Device can support maximum frame size up to 9212 bytes. While configuring
mtu, overhead is considered as ethernet header size, crc and
2 * (vlan tags) which translates to 26 bytes.

Exposed overhead to the user via rte_eth_dev_info() is 18 bytes which were
leading to set wrong Rx frame size.

Fixes: 8589ec212e80 ("net/cnxk: support MTU set")
Cc: sta...@dpdk.org

Signed-off-by: Sunil Kumar Kori 
---
 drivers/net/cnxk/cnxk_ethdev_ops.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c 
b/drivers/net/cnxk/cnxk_ethdev_ops.c
index 4962f3bced..56049c5dd2 100644
--- a/drivers/net/cnxk/cnxk_ethdev_ops.c
+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c
@@ -20,8 +20,7 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct 
rte_eth_dev_info *devinfo)
devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
devinfo->max_mac_addrs = dev->max_mac_entries;
devinfo->max_vfs = pci_dev->max_vfs;
-   devinfo->max_mtu = devinfo->max_rx_pktlen -
-   (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
+   devinfo->max_mtu = devinfo->max_rx_pktlen - CNXK_NIX_L2_OVERHEAD;
devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD;
 
devinfo->rx_offload_capa = dev->rx_offload_capa;
-- 
2.25.1

[PATCH v5 09/14] common/cnxk: fix RETA table config API

[Nithin Dabilpuram]

From: Kommula Shiva Shankar 

This patch updates queue entries copy in reta table
based on data type.

Fixes: 1bf6746e653b ("common/cnxk: support NIX RSS")

Signed-off-by: Kommula Shiva Shankar 
---
 drivers/common/cnxk/roc_nix_rss.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_rss.c 
b/drivers/common/cnxk/roc_nix_rss.c
index 3599eb9bae..2b88e1360d 100644
--- a/drivers/common/cnxk/roc_nix_rss.c
+++ b/drivers/common/cnxk/roc_nix_rss.c
@@ -196,7 +196,7 @@ roc_nix_rss_reta_set(struct roc_nix *roc_nix, uint8_t group,
if (rc)
return rc;
 
-   memcpy(&nix->reta[group], reta, ROC_NIX_RSS_RETA_MAX);
+   memcpy(&nix->reta[group], reta, sizeof(uint16_t) * 
ROC_NIX_RSS_RETA_MAX);
return 0;
 }
 
@@ -209,7 +209,7 @@ roc_nix_rss_reta_get(struct roc_nix *roc_nix, uint8_t group,
if (group >= ROC_NIX_RSS_GRPS)
return NIX_ERR_PARAM;
 
-   memcpy(reta, &nix->reta[group], ROC_NIX_RSS_RETA_MAX);
+   memcpy(reta, &nix->reta[group], sizeof(uint16_t) * 
ROC_NIX_RSS_RETA_MAX);
return 0;
 }
 
-- 
2.25.1

[PATCH v5 10/14] net/cnxk: fix indirect mbuf handling in Tx path

[Nithin Dabilpuram]

Indirect mbuf can be pointing to data from different pool. Use the right
aura in NIX send header in SG2 and SG case.

Fixes: 862e28128707 ("net/cnxk: add vector Tx for CN9K")
Fixes: f71b7dbbf04b ("net/cnxk: add vector Tx for CN10K")
Fixes: 7e95c11df4f1 ("net/cnxk: add multi-segment Tx for CN9K")
Fixes: 3626d5195d49 ("net/cnxk: add multi-segment Tx for CN10K")
Cc: sta...@dpdk.org

Signed-off-by: Nithin Dabilpuram 
Signed-off-by: Rahul Bhansali 
---
 drivers/net/cnxk/cn10k_ethdev.c   |   6 +
 drivers/net/cnxk/cn10k_rxtx.h |   1 +
 drivers/net/cnxk/cn10k_tx.h   | 269 +++
 drivers/net/cnxk/cn9k_ethdev.c|   6 +
 drivers/net/cnxk/cn9k_ethdev.h|   1 +
 drivers/net/cnxk/cn9k_tx.h| 299 +-
 drivers/net/cnxk/cnxk_ethdev_dp.h |  10 +-
 7 files changed, 414 insertions(+), 178 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index a2e943a3d0..a5696c092a 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -389,7 +389,13 @@ cn10k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, 
uint16_t qidx)
struct roc_nix_sq *sq = &dev->sqs[qidx];
do {
handle_tx_completion_pkts(txq, flags & NIX_TX_VWQE_F);
+   /* Check if SQ is empty */
roc_nix_sq_head_tail_get(nix, sq->qid, &head, &tail);
+   if (head != tail)
+   continue;
+
+   /* Check if completion CQ is empty */
+   roc_nix_cq_head_tail_get(nix, sq->cqid, &head, &tail);
} while (head != tail);
}
 
diff --git a/drivers/net/cnxk/cn10k_rxtx.h b/drivers/net/cnxk/cn10k_rxtx.h
index aeffc4ac92..9f33d0192e 100644
--- a/drivers/net/cnxk/cn10k_rxtx.h
+++ b/drivers/net/cnxk/cn10k_rxtx.h
@@ -177,6 +177,7 @@ handle_tx_completion_pkts(struct cn10k_eth_txq *txq, 
uint8_t mt_safe)
m = m_next;
}
rte_pktmbuf_free_seg(m);
+   txq->tx_compl.ptr[tx_compl_s0->sqe_id] = NULL;
 
head++;
head &= qmask;
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 467f0ccc65..025eff2913 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -786,8 +786,9 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, 
uintptr_t *nixtx_addr,
 
 static __rte_always_inline uint64_t
 cn10k_nix_prefree_seg(struct rte_mbuf *m, struct cn10k_eth_txq *txq,
-   struct nix_send_hdr_s *send_hdr)
+ struct nix_send_hdr_s *send_hdr, uint64_t *aura)
 {
+   struct rte_mbuf *prev = NULL;
uint32_t sqe_id;
 
if (RTE_MBUF_HAS_EXTBUF(m)) {
@@ -796,7 +797,10 @@ cn10k_nix_prefree_seg(struct rte_mbuf *m, struct 
cn10k_eth_txq *txq,
return 1;
}
if (send_hdr->w0.pnc) {
-   txq->tx_compl.ptr[send_hdr->w1.sqe_id]->next = m;
+   sqe_id = send_hdr->w1.sqe_id;
+   prev = txq->tx_compl.ptr[sqe_id];
+   m->next = prev;
+   txq->tx_compl.ptr[sqe_id] = m;
} else {
sqe_id = __atomic_fetch_add(&txq->tx_compl.sqe_id, 1, 
__ATOMIC_RELAXED);
send_hdr->w0.pnc = 1;
@@ -806,10 +810,155 @@ cn10k_nix_prefree_seg(struct rte_mbuf *m, struct 
cn10k_eth_txq *txq,
}
return 1;
} else {
-   return cnxk_nix_prefree_seg(m);
+   return cnxk_nix_prefree_seg(m, aura);
}
 }
 
+#if defined(RTE_ARCH_ARM64)
+/* Only called for first segments of single segmented mbufs */
+static __rte_always_inline void
+cn10k_nix_prefree_seg_vec(struct rte_mbuf **mbufs, struct cn10k_eth_txq *txq,
+ uint64x2_t *senddesc01_w0, uint64x2_t *senddesc23_w0,
+ uint64x2_t *senddesc01_w1, uint64x2_t *senddesc23_w1)
+{
+   struct rte_mbuf **tx_compl_ptr = txq->tx_compl.ptr;
+   uint32_t nb_desc_mask = txq->tx_compl.nb_desc_mask;
+   bool tx_compl_ena = txq->tx_compl.ena;
+   struct rte_mbuf *m0, *m1, *m2, *m3;
+   struct rte_mbuf *cookie;
+   uint64_t w0, w1, aura;
+   uint64_t sqe_id;
+
+   m0 = mbufs[0];
+   m1 = mbufs[1];
+   m2 = mbufs[2];
+   m3 = mbufs[3];
+
+   /* mbuf 0 */
+   w0 = vgetq_lane_u64(*senddesc01_w0, 0);
+   if (RTE_MBUF_HAS_EXTBUF(m0)) {
+   w0 |= BIT_ULL(19);
+   w1 = vgetq_lane_u64(*senddesc01_w1, 0);
+   w1 &= ~0xUL;
+   if (unlikely(!tx_compl_ena)) {
+   rte_pktmbuf_free_seg(m0);
+   } else {
+   sqe_id = 
rte_atomic_fetch_add_explicit(&txq->tx_compl.sqe_id, 1,
+  
rte_

[PATCH v5 11/14] net/cnxk: fix check cookies for multi-seg offload

[Nithin Dabilpuram]

From: Rahul Bhansali 

Fix missing check cookies with multi-seg offload case

Fixes: 3626d5195d49 ("net/cnxk: add multi-segment Tx for CN10K")
Cc: sta...@dpdk.org

Signed-off-by: Rahul Bhansali 
---
 drivers/net/cnxk/cn10k_tx.h | 21 -
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 025eff2913..84d71d0818 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -1867,6 +1867,9 @@ cn10k_nix_prepare_mseg_vec_list(struct rte_mbuf *m, 
uint64_t *cmd,
len -= dlen;
sg_u = sg_u | ((uint64_t)dlen);
 
+   /* Mark mempool object as "put" since it is freed by NIX */
+   RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);
+
nb_segs = m->nb_segs - 1;
m_next = m->next;
m->next = NULL;
@@ -1892,6 +1895,9 @@ cn10k_nix_prepare_mseg_vec_list(struct rte_mbuf *m, 
uint64_t *cmd,
slist++;
}
m->next = NULL;
+   /* Mark mempool object as "put" since it is freed by NIX */
+   RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);
+
m = m_next;
} while (nb_segs);
 
@@ -1915,8 +1921,11 @@ cn10k_nix_prepare_mseg_vec(struct rte_mbuf *m, uint64_t 
*cmd, uint64x2_t *cmd0,
union nix_send_hdr_w0_u sh;
union nix_send_sg_s sg;
 
-   if (m->nb_segs == 1)
+   if (m->nb_segs == 1) {
+   /* Mark mempool object as "put" since it is freed by NIX */
+   RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);
return;
+   }
 
sh.u = vgetq_lane_u64(cmd0[0], 0);
sg.u = vgetq_lane_u64(cmd1[0], 0);
@@ -1976,6 +1985,11 @@ cn10k_nix_prep_lmt_mseg_vector(struct cn10k_eth_txq *txq,
*data128 |= ((__uint128_t)7) << *shift;
*shift += 3;
 
+   /* Mark mempool object as "put" since it is freed by 
NIX */
+   RTE_MEMPOOL_CHECK_COOKIES(mbufs[0]->pool, (void 
**)&mbufs[0], 1, 0);
+   RTE_MEMPOOL_CHECK_COOKIES(mbufs[1]->pool, (void 
**)&mbufs[1], 1, 0);
+   RTE_MEMPOOL_CHECK_COOKIES(mbufs[2]->pool, (void 
**)&mbufs[2], 1, 0);
+   RTE_MEMPOOL_CHECK_COOKIES(mbufs[3]->pool, (void 
**)&mbufs[3], 1, 0);
return 1;
}
}
@@ -1994,6 +2008,11 @@ cn10k_nix_prep_lmt_mseg_vector(struct cn10k_eth_txq *txq,
vst1q_u64(lmt_addr + 10, cmd2[j + 1]);
vst1q_u64(lmt_addr + 12, cmd1[j + 1]);
vst1q_u64(lmt_addr + 14, cmd3[j + 1]);
+
+   /* Mark mempool object as "put" since it is 
freed by NIX */
+   RTE_MEMPOOL_CHECK_COOKIES(mbufs[j]->pool, (void 
**)&mbufs[j], 1, 0);
+   RTE_MEMPOOL_CHECK_COOKIES(mbufs[j + 1]->pool,
+ (void **)&mbufs[j + 
1], 1, 0);
} else if (flags & NIX_TX_NEED_EXT_HDR) {
/* EXT header take 3 each, space for 2 segs.*/
cn10k_nix_prepare_mseg_vec(mbufs[j],
-- 
2.25.1

[PATCH v5 12/14] common/cnxk: fix mbox struct attributes

[Nithin Dabilpuram]

IO attribute is needed to mbox structs to avoid unaligned or pair
access causing by compiler optimization. Add them to structs
where it is missing.

Fixes: 503b82de2cbf ("common/cnxk: add mbox request and response definitions")
Fixes: ddf955d3917e ("common/cnxk: support CPT second pass")
Cc: sta...@dpdk.org

Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/cnxk/roc_mbox.h | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 4b4f48e372..d8a8494ac4 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1427,12 +1427,12 @@ struct nix_cn10k_aq_enq_req {
 struct nix_cn10k_aq_enq_rsp {
struct mbox_msghdr hdr;
union {
-   struct nix_cn10k_rq_ctx_s rq;
-   struct nix_cn10k_sq_ctx_s sq;
-   struct nix_cq_ctx_s cq;
-   struct nix_rsse_s rss;
-   struct nix_rx_mce_s mce;
-   struct nix_band_prof_s prof;
+   __io struct nix_cn10k_rq_ctx_s rq;
+   __io struct nix_cn10k_sq_ctx_s sq;
+   __io struct nix_cq_ctx_s cq;
+   __io struct nix_rsse_s rss;
+   __io struct nix_rx_mce_s mce;
+   __io struct nix_band_prof_s prof;
};
 };
 
@@ -1668,11 +1668,11 @@ struct nix_rq_cpt_field_mask_cfg_req {
 #define RQ_CTX_MASK_MAX 6
union {
uint64_t __io rq_ctx_word_set[RQ_CTX_MASK_MAX];
-   struct nix_cn10k_rq_ctx_s rq_set;
+   __io struct nix_cn10k_rq_ctx_s rq_set;
};
union {
uint64_t __io rq_ctx_word_mask[RQ_CTX_MASK_MAX];
-   struct nix_cn10k_rq_ctx_s rq_mask;
+   __io struct nix_cn10k_rq_ctx_s rq_mask;
};
struct nix_lf_rx_ipec_cfg1_req {
uint32_t __io spb_cpt_aura;
-- 
2.25.1

[PATCH v5 13/14] common/cnxk: use SQ enable and disable API

[Nithin Dabilpuram]

Use SQ enable and disable API in TM setup to affect
the state change. This is needed since now SQ state
helps in avoiding multiple SQ enables / SQ disables
if the SQ is already in that state. Otherwise multiple
mbox messages slows down bootup / teardown.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/cnxk/roc_nix_tm_ops.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c 
b/drivers/common/cnxk/roc_nix_tm_ops.c
index 900b182c76..9f3870a311 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -495,7 +495,7 @@ roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix)
if (!sq)
continue;
 
-   rc = roc_nix_tm_sq_aura_fc(sq, false);
+   rc = roc_nix_sq_ena_dis(sq, false);
if (rc) {
plt_err("Failed to disable sqb aura fc, rc=%d", rc);
goto cleanup;
@@ -607,7 +607,7 @@ roc_nix_tm_hierarchy_xmit_enable(struct roc_nix *roc_nix, 
enum roc_nix_tm_tree t
sq_id = node->id;
sq = nix->sqs[sq_id];
 
-   rc = roc_nix_tm_sq_aura_fc(sq, true);
+   rc = roc_nix_sq_ena_dis(sq, true);
if (rc) {
plt_err("TM sw xon failed on SQ %u, rc=%d", node->id,
rc);
-- 
2.25.1

[PATCH v5 14/14] net/cnxk: fix mbuf fields in multi-seg Tx path

[Nithin Dabilpuram]

From: Rahul Bhansali 

Currently in debug mode when a buffer is allocated in SW,
nb_segs will have invalid values as it didn't come from driver
Rx path. Hence reset mbuf next and nb_segs fields in multi-seg Tx path.

Fixes: 3626d5195d49 ("net/cnxk: add multi-segment Tx for CN10K")

Signed-off-by: Rahul Bhansali 
---
 drivers/net/cnxk/cn10k_tx.h |  2 ++
 drivers/net/cnxk/cn9k_tx.h  | 20 
 2 files changed, 22 insertions(+)

diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 84d71d0818..cc480d24e8 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -1328,6 +1328,7 @@ cn10k_nix_prepare_mseg(struct cn10k_eth_txq *txq,
nb_segs = m->nb_segs - 1;
m_next = m->next;
m->next = NULL;
+   m->nb_segs = 1;
slist = &cmd[3 + off + 1];
 
cookie = RTE_MBUF_DIRECT(m) ? m : rte_mbuf_from_indirect(m);
@@ -1873,6 +1874,7 @@ cn10k_nix_prepare_mseg_vec_list(struct rte_mbuf *m, 
uint64_t *cmd,
nb_segs = m->nb_segs - 1;
m_next = m->next;
m->next = NULL;
+   m->nb_segs = 1;
m = m_next;
/* Fill mbuf segments */
do {
diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h
index 3596651cc2..94acbe64fa 100644
--- a/drivers/net/cnxk/cn9k_tx.h
+++ b/drivers/net/cnxk/cn9k_tx.h
@@ -647,6 +647,10 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq,
rte_io_wmb();
 #else
RTE_SET_USED(cookie);
+#endif
+#ifdef RTE_ENABLE_ASSERT
+   m->next = NULL;
+   m->nb_segs = 1;
 #endif
m = m_next;
if (!m)
@@ -683,6 +687,9 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq,
sg_u = sg->u;
slist++;
}
+#ifdef RTE_ENABLE_ASSERT
+   m->next = NULL;
+#endif
m = m_next;
} while (nb_segs);
 
@@ -696,6 +703,9 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq,
segdw += (off >> 1) + 1 + !!(flags & NIX_TX_OFFLOAD_TSTAMP_F);
send_hdr->w0.sizem1 = segdw - 1;
 
+#ifdef RTE_ENABLE_ASSERT
+   rte_io_wmb();
+#endif
return segdw;
 }
 
@@ -912,6 +922,10 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq,
RTE_SET_USED(cookie);
 #endif
 
+#ifdef RTE_ENABLE_ASSERT
+   m->next = NULL;
+   m->nb_segs = 1;
+#endif
m = m_next;
/* Fill mbuf segments */
do {
@@ -942,6 +956,9 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq,
sg_u = sg->u;
slist++;
}
+#ifdef RTE_ENABLE_ASSERT
+   m->next = NULL;
+#endif
m = m_next;
} while (nb_segs);
 
@@ -957,6 +974,9 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq,
 !!(flags & NIX_TX_OFFLOAD_TSTAMP_F);
send_hdr->w0.sizem1 = segdw - 1;
 
+#ifdef RTE_ENABLE_ASSERT
+   rte_io_wmb();
+#endif
return segdw;
 }
 
-- 
2.25.1

[PATCH v3 0/7] net/mlx5: support copy from inner fields

[Michael Baum]

This patch-set adds support of encapsulation level for HWS modify field
in MLX5 PMD.
Outermost is represented by 0,1 and inner is represented by 2.
In addition, modify inner/outer us added for both IPv6 flow label and
IPv6 traffic class.

v2:
- Rebase.
- Add "copy from inner" to release notes.

v3:
 - Rebase.
 - Add "Acked-by" from v2.
 - Remove the "Depends-on" labels.

Michael Baum (7):
  common/mlx5: remove enum value duplication
  common/mlx5: reorder modification field PRM list
  common/mlx5: add inner PRM fields
  common/mlx5: add IPv6 flow label PRM field
  net/mlx5: add support for modify inner fields
  net/mlx5: support modify IPv6 traffic class field
  net/mlx5: support modify IPv6 flow label field

 doc/guides/nics/mlx5.rst   |  28 -
 doc/guides/rel_notes/release_24_03.rst |   3 +
 drivers/common/mlx5/mlx5_prm.h |  49 +
 drivers/net/mlx5/hws/mlx5dr_action.c   |   4 +-
 drivers/net/mlx5/hws/mlx5dr_pat_arg.c  |   2 +-
 drivers/net/mlx5/mlx5_flow.c   |  12 ++-
 drivers/net/mlx5/mlx5_flow_dv.c| 136 +++--
 drivers/net/mlx5/mlx5_flow_hw.c| 134 +++-
 8 files changed, 283 insertions(+), 85 deletions(-)

-- 
2.25.1

[PATCH v3 1/7] common/mlx5: remove enum value duplication

[Michael Baum]

The "mlx5_modification_field" enumeration has 2 different fields
representing the same value 0x4A.
 1. "MLX5_MODI_OUT_IPV6_NEXT_HDR" - specific for IPv6.
 2. "MLX5_MODI_OUT_IP_PROTOCOL" - for both IPv4 and IPv6.

This patch removes "MLX5_MODI_OUT_IPV6_NEXT_HDR" and replaces all its
usages with "MLX5_MODI_OUT_IP_PROTOCOL".

Signed-off-by: Michael Baum 
Acked-by: Dariusz Sosnowski 
---
 drivers/common/mlx5/mlx5_prm.h| 1 -
 drivers/net/mlx5/hws/mlx5dr_action.c  | 4 ++--
 drivers/net/mlx5/hws/mlx5dr_pat_arg.c | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 282e59e52c..6a8cb7a8aa 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -840,7 +840,6 @@ enum mlx5_modification_field {
MLX5_MODI_IN_MPLS_LABEL_3,
MLX5_MODI_IN_MPLS_LABEL_4,
MLX5_MODI_OUT_IP_PROTOCOL = 0x4A,
-   MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A,
MLX5_MODI_META_REG_C_8 = 0x8F,
MLX5_MODI_META_REG_C_9 = 0x90,
MLX5_MODI_META_REG_C_10 = 0x91,
diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c 
b/drivers/net/mlx5/hws/mlx5dr_action.c
index f55069c675..631763dee0 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -2291,7 +2291,7 @@ mlx5dr_action_create_pop_ipv6_route_ext_mhdr3(struct 
mlx5dr_action *action)
MLX5_SET(copy_action_in, cmd, length, 8);
MLX5_SET(copy_action_in, cmd, src_offset, 24);
MLX5_SET(copy_action_in, cmd, src_field, mod_id);
-   MLX5_SET(copy_action_in, cmd, dst_field, MLX5_MODI_OUT_IPV6_NEXT_HDR);
+   MLX5_SET(copy_action_in, cmd, dst_field, MLX5_MODI_OUT_IP_PROTOCOL);
 
pattern.data = (__be64 *)cmd;
pattern.sz = sizeof(cmd);
@@ -2352,7 +2352,7 @@ mlx5dr_action_create_push_ipv6_route_ext_mhdr1(struct 
mlx5dr_action *action)
/* Set ipv6.protocol to IPPROTO_ROUTING */
MLX5_SET(set_action_in, cmd, action_type, MLX5_MODIFICATION_TYPE_SET);
MLX5_SET(set_action_in, cmd, length, 8);
-   MLX5_SET(set_action_in, cmd, field, MLX5_MODI_OUT_IPV6_NEXT_HDR);
+   MLX5_SET(set_action_in, cmd, field, MLX5_MODI_OUT_IP_PROTOCOL);
MLX5_SET(set_action_in, cmd, data, IPPROTO_ROUTING);
 
pattern.data = (__be64 *)cmd;
diff --git a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c 
b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c
index a949844d24..513549ff3c 100644
--- a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c
+++ b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c
@@ -67,7 +67,7 @@ bool mlx5dr_pat_require_reparse(__be64 *actions, uint16_t 
num_of_actions)
 
/* Below fields can change packet structure require a reparse */
if (field == MLX5_MODI_OUT_ETHERTYPE ||
-   field == MLX5_MODI_OUT_IPV6_NEXT_HDR)
+   field == MLX5_MODI_OUT_IP_PROTOCOL)
return true;
}
 
-- 
2.25.1

[PATCH v3 3/7] common/mlx5: add inner PRM fields

[Michael Baum]

This patch adds inner values into PRM modify field list for each
existing outer field.

Signed-off-by: Michael Baum 
Acked-by: Dariusz Sosnowski 
---
 drivers/common/mlx5/mlx5_prm.h | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 6967acbdc3..6124af1857 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -829,14 +829,17 @@ enum mlx5_modification_field {
MLX5_MODI_OUT_TCP_SEQ_NUM,
MLX5_MODI_IN_TCP_SEQ_NUM,
MLX5_MODI_OUT_TCP_ACK_NUM,
-   MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
+   MLX5_MODI_IN_TCP_ACK_NUM,
MLX5_MODI_OUT_ESP_SPI = 0x5E,
+   MLX5_MODI_IN_ESP_SPI,
MLX5_MODI_GTP_TEID = 0x6E,
MLX5_MODI_OUT_IP_ECN = 0x73,
-   MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75,
+   MLX5_MODI_IN_IP_ECN,
+   MLX5_MODI_TUNNEL_HDR_DW_1,
MLX5_MODI_GTPU_FIRST_EXT_DW_0,
MLX5_MODI_HASH_RESULT = 0x81,
MLX5_MODI_OUT_ESP_SEQ_NUM,
+   MLX5_MODI_IN_ESP_SEQ_NUM,
MLX5_MODI_IN_MPLS_LABEL_0 = 0x8a,
MLX5_MODI_IN_MPLS_LABEL_1,
MLX5_MODI_IN_MPLS_LABEL_2,
@@ -855,7 +858,12 @@ enum mlx5_modification_field {
MLX5_MODI_OUT_IPV6_PAYLOAD_LEN,
MLX5_MODI_OUT_IPV4_IHL,
MLX5_MODI_OUT_TCP_DATA_OFFSET,
-   MLX5_MODI_OUT_IPSEC_NEXT_HDR = 0x126,
+   MLX5_MODI_IN_IPV6_TRAFFIC_CLASS,
+   MLX5_MODI_IN_IPV4_TOTAL_LEN,
+   MLX5_MODI_IN_IPV6_PAYLOAD_LEN,
+   MLX5_MODI_IN_IPV4_IHL,
+   MLX5_MODI_IN_TCP_DATA_OFFSET,
+   MLX5_MODI_OUT_IPSEC_NEXT_HDR,
MLX5_MODI_INVALID = INT_MAX,
 };
 
-- 
2.25.1

[PATCH v3 2/7] common/mlx5: reorder modification field PRM list

[Michael Baum]

Reorder modification field PRM list according to values from lowest to
highest.
This patch also removes value specification from all fields which their
value is one more than previous one.

Signed-off-by: Michael Baum 
Acked-by: Dariusz Sosnowski 
---
 drivers/common/mlx5/mlx5_prm.h | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 6a8cb7a8aa..6967acbdc3 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -816,6 +816,7 @@ enum mlx5_modification_field {
MLX5_MODI_OUT_IPV6_HOPLIMIT,
MLX5_MODI_IN_IPV6_HOPLIMIT,
MLX5_MODI_META_DATA_REG_A,
+   MLX5_MODI_OUT_IP_PROTOCOL,
MLX5_MODI_META_DATA_REG_B = 0x50,
MLX5_MODI_META_REG_C_0,
MLX5_MODI_META_REG_C_1,
@@ -829,32 +830,31 @@ enum mlx5_modification_field {
MLX5_MODI_IN_TCP_SEQ_NUM,
MLX5_MODI_OUT_TCP_ACK_NUM,
MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
+   MLX5_MODI_OUT_ESP_SPI = 0x5E,
MLX5_MODI_GTP_TEID = 0x6E,
MLX5_MODI_OUT_IP_ECN = 0x73,
MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75,
-   MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76,
+   MLX5_MODI_GTPU_FIRST_EXT_DW_0,
MLX5_MODI_HASH_RESULT = 0x81,
+   MLX5_MODI_OUT_ESP_SEQ_NUM,
MLX5_MODI_IN_MPLS_LABEL_0 = 0x8a,
MLX5_MODI_IN_MPLS_LABEL_1,
MLX5_MODI_IN_MPLS_LABEL_2,
MLX5_MODI_IN_MPLS_LABEL_3,
MLX5_MODI_IN_MPLS_LABEL_4,
-   MLX5_MODI_OUT_IP_PROTOCOL = 0x4A,
-   MLX5_MODI_META_REG_C_8 = 0x8F,
-   MLX5_MODI_META_REG_C_9 = 0x90,
-   MLX5_MODI_META_REG_C_10 = 0x91,
-   MLX5_MODI_META_REG_C_11 = 0x92,
-   MLX5_MODI_META_REG_C_12 = 0x93,
-   MLX5_MODI_META_REG_C_13 = 0x94,
-   MLX5_MODI_META_REG_C_14 = 0x95,
-   MLX5_MODI_META_REG_C_15 = 0x96,
+   MLX5_MODI_META_REG_C_8,
+   MLX5_MODI_META_REG_C_9,
+   MLX5_MODI_META_REG_C_10,
+   MLX5_MODI_META_REG_C_11,
+   MLX5_MODI_META_REG_C_12,
+   MLX5_MODI_META_REG_C_13,
+   MLX5_MODI_META_REG_C_14,
+   MLX5_MODI_META_REG_C_15,
MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS = 0x11C,
-   MLX5_MODI_OUT_IPV4_TOTAL_LEN = 0x11D,
-   MLX5_MODI_OUT_IPV6_PAYLOAD_LEN = 0x11E,
-   MLX5_MODI_OUT_IPV4_IHL = 0x11F,
-   MLX5_MODI_OUT_TCP_DATA_OFFSET = 0x120,
-   MLX5_MODI_OUT_ESP_SPI = 0x5E,
-   MLX5_MODI_OUT_ESP_SEQ_NUM = 0x82,
+   MLX5_MODI_OUT_IPV4_TOTAL_LEN,
+   MLX5_MODI_OUT_IPV6_PAYLOAD_LEN,
+   MLX5_MODI_OUT_IPV4_IHL,
+   MLX5_MODI_OUT_TCP_DATA_OFFSET,
MLX5_MODI_OUT_IPSEC_NEXT_HDR = 0x126,
MLX5_MODI_INVALID = INT_MAX,
 };
-- 
2.25.1

[PATCH v3 4/7] common/mlx5: add IPv6 flow label PRM field

[Michael Baum]

Add IPv6 flow label field into PRM modify field list.
The new values are "MLX5_MODI_OUT_IPV6_FLOW_LABEL" and
"MLX5_MODI_IN_IPV6_FLOW_LABEL".

Signed-off-by: Michael Baum 
Acked-by: Dariusz Sosnowski 
---
 drivers/common/mlx5/mlx5_prm.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 6124af1857..92309d453b 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -864,6 +864,8 @@ enum mlx5_modification_field {
MLX5_MODI_IN_IPV4_IHL,
MLX5_MODI_IN_TCP_DATA_OFFSET,
MLX5_MODI_OUT_IPSEC_NEXT_HDR,
+   MLX5_MODI_OUT_IPV6_FLOW_LABEL,
+   MLX5_MODI_IN_IPV6_FLOW_LABEL,
MLX5_MODI_INVALID = INT_MAX,
 };
 
-- 
2.25.1

[PATCH v3 5/7] net/mlx5: add support for modify inner fields

[Michael Baum]

This patch adds support for copying from inner fields using "level" 2.

Signed-off-by: Michael Baum 
Acked-by: Dariusz Sosnowski 
---
 doc/guides/nics/mlx5.rst   |  28 +-
 doc/guides/rel_notes/release_24_03.rst |   1 +
 drivers/net/mlx5/mlx5_flow.c   |  12 ++-
 drivers/net/mlx5/mlx5_flow_dv.c| 113 +++--
 drivers/net/mlx5/mlx5_flow_hw.c| 130 -
 5 files changed, 223 insertions(+), 61 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 0d2213497a..dcf58c0a34 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -639,7 +639,6 @@ Limitations
 Only DWs configured in :ref:`parser creation ` can be 
modified,
 'type' and 'class' fields can be modified when ``match_on_class_mode=2``.
   - Modification of GENEVE TLV option data supports one DW per action.
-  - Encapsulation levels are not supported, can modify outermost header fields 
only.
   - Offsets cannot skip past the boundary of a field.
   - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``
 and packet contains one or more VLAN headers,
@@ -653,6 +652,33 @@ Limitations
   - For flow metadata fields (e.g. META or TAG)
 offset specifies the number of bits to skip from field's start,
 starting from LSB in the least significant byte, in the host order.
+  - Modification of the MPLS header is supported with some limitations:
+
+- Only in HW steering.
+- Only in ``src`` field.
+- Only for outermost tunnel header (``level=2``).
+  For ``RTE_FLOW_FIELD_MPLS``,
+  the default encapsulation level ``0`` describes the outermost tunnel 
header.
+
+  .. note::
+
+ the default encapsulation level ``0`` describes the "outermost that 
match is supported",
+ currently it is first tunnel, but it can be changed to outer when it 
is supported.
+
+  - Default encapsulation level ``0`` describes outermost.
+  - Encapsulation level ``1`` is supported.
+  - Encapsulation level ``2`` is supported with some limitations:
+
+- Only in HW steering.
+- Only in ``src`` field.
+- ``RTE_FLOW_FIELD_VLAN_ID`` is not supported.
+- ``RTE_FLOW_FIELD_IPV4_PROTO`` is not supported.
+- ``RTE_FLOW_FIELD_IPV6_PROTO/DSCP/ECN`` are not supported.
+- ``RTE_FLOW_FIELD_ESP_PROTO/SPI/SEQ_NUM`` are not supported.
+- ``RTE_FLOW_FIELD_TCP_SEQ/ACK_NUM`` are not supported.
+- Second tunnel fields are not supported.
+
+  - Encapsulation levels greater than ``2`` are not supported.
 
 - Age action:
 
diff --git a/doc/guides/rel_notes/release_24_03.rst 
b/doc/guides/rel_notes/release_24_03.rst
index 879bb4944c..0473858e19 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -130,6 +130,7 @@ New Features
   * Added support for matching a random value.
   * Added support for comparing result between packet fields or value.
   * Added support for accumulating value of field into another one.
+  * Added support for copy inner fields in HWS flow engine.
 
 * **Updated Marvell cnxk crypto driver.**
 
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 2b2ae62618..3e179110a0 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -2387,10 +2387,14 @@ flow_validate_modify_field_level(const struct 
rte_flow_field_data *data,
if (data->level == 0)
return 0;
if (data->field != RTE_FLOW_FIELD_TAG &&
-   data->field != (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG)
-   return rte_flow_error_set(error, ENOTSUP,
- RTE_FLOW_ERROR_TYPE_ACTION, NULL,
- "inner header fields modification is 
not supported");
+   data->field != (enum 
rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {
+   if (data->level > 1)
+   return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "inner header fields 
modification is not supported");
+   return 0;
+   }
if (data->tag_index != 0)
return rte_flow_error_set(error, EINVAL,
  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 42810e359c..feda003c07 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -82,6 +82,9 @@
} \
} while (0)
 
+#define CALC_MODI_ID(field, level) \
+   (((level) > 1) ? MLX5_MODI_IN_##field : MLX5_MODI_OUT_##field)
+
 union flow_dv_attr {
struct {
uint32_t valid:1;
@@ -1638,8 +1641,8 @@ mlx5_flow_field_id_to_modify_info
MLX5_ASSERT(data->offset + width <= 48);
off_be

[PATCH v3 6/7] net/mlx5: support modify IPv6 traffic class field

[Michael Baum]

Add HW steering support for IPv6 traffic class field modification.
Copy from inner IPv6 traffic class field is also supported using
"level=2".

Signed-off-by: Michael Baum 
Acked-by: Dariusz Sosnowski 
---
 doc/guides/rel_notes/release_24_03.rst |  1 +
 drivers/net/mlx5/mlx5_flow_dv.c| 11 +++
 drivers/net/mlx5/mlx5_flow_hw.c|  3 ++-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/doc/guides/rel_notes/release_24_03.rst 
b/doc/guides/rel_notes/release_24_03.rst
index 0473858e19..c2fc22ed66 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -127,6 +127,7 @@ New Features
   * Added support for GENEVE matching and modifying in HWS flow engine.
   * Added support for modifying IPv4 proto field in HWS flow engine.
   * Added support for modifying IPsec ESP fields in HWS flow engine.
+  * Added support for modifying IPv6 traffic class field in HWS flow engine.
   * Added support for matching a random value.
   * Added support for comparing result between packet fields or value.
   * Added support for accumulating value of field into another one.
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index feda003c07..2c0c8e37f7 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1394,6 +1394,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev,
return 32;
case RTE_FLOW_FIELD_IPV6_DSCP:
return 6;
+   case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
case RTE_FLOW_FIELD_IPV6_PROTO:
return 8;
@@ -1795,6 +1796,16 @@ mlx5_flow_field_id_to_modify_info
else
info[idx].offset = off_be;
break;
+   case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
+   MLX5_ASSERT(data->offset + width <= 8);
+   off_be = 8 - (data->offset + width);
+   modi_id = CALC_MODI_ID(IPV6_TRAFFIC_CLASS, data->level);
+   info[idx] = (struct field_modify_info){1, 0, modi_id};
+   if (mask)
+   mask[idx] = flow_modify_info_mask_8(width, off_be);
+   else
+   info[idx].offset = off_be;
+   break;
case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
MLX5_ASSERT(data->offset + width <= 16);
off_be = 16 - (data->offset + width);
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index fc1bcdd84e..9d4fdb06c1 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -2878,7 +2878,7 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,
 * bits left. Shift the data left for IPv6 DSCP
 */
if (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS &&
-   !(mask & MLX5_IPV6_HDR_ECN_MASK))
+   mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP)
data <<= MLX5_IPV6_HDR_DSCP_SHIFT;
data = (data & mask) >> off_b;
job->mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);
@@ -5067,6 +5067,7 @@ flow_hw_validate_modify_field_level(const struct 
rte_flow_field_data *data,
case RTE_FLOW_FIELD_IPV4_TTL:
case RTE_FLOW_FIELD_IPV4_SRC:
case RTE_FLOW_FIELD_IPV4_DST:
+   case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
case RTE_FLOW_FIELD_IPV6_SRC:
-- 
2.25.1

[PATCH v3 7/7] net/mlx5: support modify IPv6 flow label field

[Michael Baum]

Add HW steering support for IPv6 flow label field modification.
Copy from inner IPv6 flow label field is also supported using "level=2".

Signed-off-by: Michael Baum 
Acked-by: Dariusz Sosnowski 
---
 doc/guides/rel_notes/release_24_03.rst |  1 +
 drivers/net/mlx5/mlx5_flow_dv.c| 12 
 drivers/net/mlx5/mlx5_flow_hw.c|  1 +
 3 files changed, 14 insertions(+)

diff --git a/doc/guides/rel_notes/release_24_03.rst 
b/doc/guides/rel_notes/release_24_03.rst
index c2fc22ed66..ff9c6552e4 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -128,6 +128,7 @@ New Features
   * Added support for modifying IPv4 proto field in HWS flow engine.
   * Added support for modifying IPsec ESP fields in HWS flow engine.
   * Added support for modifying IPv6 traffic class field in HWS flow engine.
+  * Added support for modifying IPv6 flow label field in HWS flow engine.
   * Added support for matching a random value.
   * Added support for comparing result between packet fields or value.
   * Added support for accumulating value of field into another one.
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 2c0c8e37f7..75a8a223ab 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1394,6 +1394,8 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev,
return 32;
case RTE_FLOW_FIELD_IPV6_DSCP:
return 6;
+   case RTE_FLOW_FIELD_IPV6_FLOW_LABEL:
+   return 20;
case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
case RTE_FLOW_FIELD_IPV6_PROTO:
@@ -1806,6 +1808,16 @@ mlx5_flow_field_id_to_modify_info
else
info[idx].offset = off_be;
break;
+   case RTE_FLOW_FIELD_IPV6_FLOW_LABEL:
+   MLX5_ASSERT(data->offset + width <= 20);
+   off_be = 20 - (data->offset + width);
+   modi_id = CALC_MODI_ID(IPV6_FLOW_LABEL, data->level);
+   info[idx] = (struct field_modify_info){4, 0, modi_id};
+   if (mask)
+   mask[idx] = flow_modify_info_mask_32(width, off_be);
+   else
+   info[idx].offset = off_be;
+   break;
case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
MLX5_ASSERT(data->offset + width <= 16);
off_be = 16 - (data->offset + width);
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 9d4fdb06c1..254273e0fb 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -5068,6 +5068,7 @@ flow_hw_validate_modify_field_level(const struct 
rte_flow_field_data *data,
case RTE_FLOW_FIELD_IPV4_SRC:
case RTE_FLOW_FIELD_IPV4_DST:
case RTE_FLOW_FIELD_IPV6_TRAFFIC_CLASS:
+   case RTE_FLOW_FIELD_IPV6_FLOW_LABEL:
case RTE_FLOW_FIELD_IPV6_PAYLOAD_LEN:
case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
case RTE_FLOW_FIELD_IPV6_SRC:
-- 
2.25.1

RE: [PATCH v2] app/testpmd: use Tx preparation in txonly engine

[Morten Brørup]

> > >>> TSO breaks when MSS spans more than 8 data fragments. Those
> > >>> packets will be dropped by Tx preparation API, but it will
> > >>> cause
> > >>> MDD event if txonly forwarding engine does not call the Tx
> > > preparation
> > >>> API before transmitting packets.
> > >>>
> > >>
> > >> txonly is used commonly, adding Tx prepare for a specific case
> > >>> may
> > >> impact performance for users.
> > >>
> > >> What happens when driver throws MDD (Malicious Driver
> Detection)
> > > event,
> > >> can't it be ignored? As you are already OK to drop the packet,
> > >>> can
> > >> device be configured to drop these packages?
> > >>
> > >>
> > >> Or as Jerin suggested adding a new forwarding engine is a
> > >>> solution,
> > > but
> > >> that will create code duplication, I prefer to not have it if
> > >>> this
> > > can
> > >> be handled in device level.
> > >
> > > Actually I am agree with the author of the patch - when TX
> offloads
> > > and/or multisegs are enabled,
> > > user supposed to invoke eth_tx_prepare().
> > > Not doing that seems like a bug to me.
> > 
> >  I strongly disagree with that statement, Konstantin!
> >  It is not documented anywhere that using TX offloads and/or
> multisegs
> > >>> requires calling rte_eth_tx_prepare() before
> >  rte_eth_tx_burst(). And none of the examples do it.
> > >>>
> > >>> In fact, we do use it for test-pmd/csumonly.c.
> > >>> About other sample apps:
> > >>> AFAIK, not many of other DPDK apps do use L4 offloads.
> > >>> Right now special treatment (pseudo-header cksum calculation) is
> needed
> > >>> only for L4 offloads (CKSUM, SEG).
> > >>> So, majority of our apps who rely on other TX offloads (multi-seg,
> ipv4
> > >>> cksum, vlan insertion) happily run without
> > >>> calling tx_prepare(), even though it is not the safest way.
> > >>>
> > 
> >  In my opinion:
> >  If some driver has limitations for a feature, e.g. max 8
> fragments,
> > >>> it should be documented for that driver, so the application
> >  developer can make the appropriate decisions when designing the
> > >>> application.
> >  Furthermore, we have APIs for the drivers to expose to the
> > >>> applications what the driver supports, so the application can
> configure
> >  itself optimally at startup. Perhaps those APIs need to be
> expanded.
> >  And if a feature limitation is common across the majority of
> drivers,
> > >>> that limitation should be mentioned in the documentation of the
> >  feature itself.
> > >>>
> > >>> Many of such limitations *are* documented and in fact we do have
> an API
> > >>> to check max segments that each driver support,
> > >>> see struct rte_eth_desc_lim.
> > >>
> > >> Yes, this is the kind of API we should provide, so the application
> can configure itself appropriately.
> > >>
> > >>> The problem is:
> > >>> - none of our sample app does proper check on these values, so
> users
> > >>> don't have a good example how to do it.
> > >>
> > >> Agreed.
> > >> Adding an example showing how to do it properly would be the best
> solution.
> > >> Calling tx_prepare() in the examples is certainly not the solution.
> > >>
> > >>> - with current DPDK API not all of HW/PMD requirements could be
> > >>> extracted programmatically:
> > >>>let say majority of Intel PMDs for TCP offloads expect pseudo-
> header
> > >>> cksum to be pre-calculated by the SW.
> > >>
> > >> I hope this requirement is documented somewhere.
> > >>
> > >>>another example, some HW expects pkt_len to be bigger then some
> > >>> threshold value, otherwise HW hang may appear.
> > >>
> > >> I hope this requirement is also documented somewhere.
> > >
> > > No idea, I found it only in the code.
> >
> > IMHO Tx burst must check such limitations. If you made your HW simpler
> > (or just lost it on initial testing), pay in your drivers (or your
> > HW+driver will be unusable because of such problems).
> >
> > >> Generally, if the requirements cannot be extracted
> programmatically, they must be prominently documented, like this note to
> > >> rte_eth_rx_burst():
> > >
> > > Obviously, more detailed documentation is always good, but...
> > > Right now we have 50+ different PMDs from different vendors.
> > > Even if each and every of them will carefully document all possible
> limitations and necessary preparation steps,
> > > how DPDK app developer supposed to  deal with all that?
> > > Do you expect everyone, to read carefully through all of them, and
> handle all of them properly oh his own
> > > in each and every DPDK app he is going to write?
> > > That seems unrealistic.
> > > Again what to do with backward compatibility: when new driver (with
> new limitations) will arise
> > > *after* your app is already written and tested?
> >
> > +1
> >
> > >>
> > >>   * @note
> > >>   *   Some drivers using vector instructions require that *nb_pkts*
>

Re: [PATCH v1] dts: fix smoke tests driver regex

[Jeremy Spewock]

Reviewed-by: Jeremy Spewock 

Re: [PATCH v3 1/4] ethdev: add function to check representor port

[Ferruh Yigit]

On 2/26/2024 1:44 AM, Chaoyong He wrote:
> From: Long Wu 
> 
> Add a function to check if a device is representor port, also
> modified the related codes for PMDs.
> 
> Signed-off-by: Long Wu 
> Reviewed-by: Chaoyong He 
> Reviewed-by: Peng Zhang 
>

Reviewed-by: Ferruh Yigit 

Re: [PATCH v3 0/4] add support of MARK and RSS flow action

[Ferruh Yigit]

On 2/26/2024 1:44 AM, Chaoyong He wrote:
> This patch series add the support of MARK and RSS flow action for NFP
> PMD, also add a new function to help check if a device is representor
> port.
> 
> ---
> v2:
> * Modify the title and description of patch series to make it more
>  clear.
> * Add a new function to ethdev library, PMDs can use it to check if a
> * device is representor port.
> v3:
> * Drop the update of release notes.
> * Replace two more instance in 'rte_class_eth.c' with the new add helper
>  function.
> ---
> 
> Long Wu (4):
>   ethdev: add function to check representor port
>   net/nfp: support MARK flow action
>   net/nfp: add representor RSS configuration
>   net/nfp: support RSS flow action
> 

Series applied to dpdk-next-net/main, thanks.

RE: [PATCH v9] net/bnx2x: fix warnings about rte_memcpy lengths

[Morten Brørup]

> From: Jerin Jacob [mailto:jerinjac...@gmail.com]
> Sent: Monday, 26 February 2024 09.34
> 
> On Fri, Feb 23, 2024 at 7:30 PM Morten Brørup 
> wrote:
> >
> > Bugfix: The vlan in the bulletin does not contain a VLAN header, only
> the
> > VLAN ID, so only copy 2 byte, not 4. The target structure has padding
> > after the field, so copying 2 byte too many is effectively harmless.
> > There is no need to backport this patch.
> >
> > Use RTE_PTR_ADD where copying arrays to the offset of a first field in
> a
> > structure holding multiple fields, to avoid compiler warnings with
> > decorated rte_memcpy.
> >
> > Bugzilla ID: 1146
> >
> > Fixes: 540a211084a7695a1c7bc43068934c140d6989be ("bnx2x: driver core")
> > Cc: step...@networkplumber.org
> > Cc: rm...@marvell.com
> > Cc: shsha...@marvell.com
> > Cc: pa...@marvell.com
> >
> > Signed-off-by: Morten Brørup 
> > Acked-by: Devendra Singh Rawat 
> > ---
> > v9:
> > * Fix checkpatch warning about spaces.
> 
> Fixed the following issues[1] and updated the git commit as follows
> and applied to dpdk-next-net-mrvl/for-main. Thanks

Thank you, Jerin.

[...]

> Is it candidate for Cc: sta...@dpdk.org backport?

No, I don't think so:
1. The extra 2 byte copy is effectively harmless due to padding, as mentioned 
in the commit message.
2. The decorated rte_memcpy (if work on that patch series is ever resumed) is 
an improvement, not a bug fix, and will not be backported. So the memcpy parts 
of this patch are irrelevant for the stable versions.

Re: [PATCH v2 5/5] vhost: enhance virtqueue access lock asserts

[David Marchand]

On Mon, Feb 19, 2024 at 11:52 AM Thomas Monjalon  wrote:
>
> 05/12/2023 10:45, David Marchand:
> > +#define VHOST_USER_ASSERT_LOCK(dev, vq, id) do { \
> > + RTE_BUILD_BUG_ON(!vhost_message_handlers[id].lock_all_qps); \
> > + vq_assert_lock(dev, vq); \
> > +} while (0)
>
> Since "eal: enhance compile-time checks using C11 assert",
> it is not allowed to have non-constant check in RTE_BUILD_BUG_ON:
>
> lib/vhost/vhost_user.c:413:25: note: in expansion of macro 
> 'VHOST_USER_ASSERT_LOCK'
> lib/vhost/vhost_user.c: In function 'vhost_user_set_vring_addr':
> lib/eal/include/rte_common.h:518:56: error: expression in static assertion is 
> not constant
>   #define RTE_BUILD_BUG_ON(condition) do { static_assert(!(condition), 
> #condition); } while (0)
>
> I suppose we can make this check at compile-time with few adjustments.
> For -rc1, I am dropping this patch.

Iiuc, an array content is not constant (from a compiler pov) unless
the elements are integers.

I suspect there is some gcc-specific implementation that could work,
since with the previous implementation of RTE_BUILD_BUG_ON, this check
was working with both gcc and clang...
But I could not find how to.

I have an alternate solution using enums with the existing macros..
I'll post a new revision.


-- 
David Marchand

Re: [PATCH] net/hns3: fix Rx packet truncation when KEEP CRC enabled

[Ferruh Yigit]

On 2/26/2024 3:16 AM, Jie Hai wrote:
> On 2024/2/23 21:53, Ferruh Yigit wrote:
>> On 2/20/2024 3:58 AM, Jie Hai wrote:
>>> Hi, Ferruh,
>>>
>>> Thanks for your review.
>>>
>>> On 2024/2/7 22:15, Ferruh Yigit wrote:
 On 2/6/2024 1:10 AM, Jie Hai wrote:
> From: Dengdui Huang 
>
> When KEEP_CRC offload is enabled, some packets will be truncated and
> the CRC is still be stripped in following cases:
> 1. For HIP08 hardware, the packet type is TCP and the length
>  is less than or equal to 60B.
> 2. For other hardwares, the packet type is IP and the length
>  is less than or equal to 60B.
>

 If a device doesn't support the offload by some packets, it can be
 option to disable offload for that device, instead of calculating it in
 software and append it.
>>>
>>> The KEEP CRC feature of hns3 is faulty only in the specific packet
>>> type and small packet(<60B) case.
>>> What's more, the small ethernet packet is not common.
>>>
 Unless you have a specific usecase, or requirement to support the
 offload.
>>>
>>> Yes, some users of hns3 are already using this feature.
>>> So we cannot drop this offload
>>>
 <...>

> @@ -2492,10 +2544,16 @@ hns3_recv_pkts_simple(void *rx_queue,
>    goto pkt_err;
>      rxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info,
> ol_info);
> -
>    if (rxm->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)
>    rxm->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
>    +    if (unlikely(rxq->crc_len > 0)) {
> +    if (hns3_need_recalculate_crc(rxq, rxm))
> +    hns3_recalculate_crc(rxq, rxm);
> +    rxm->pkt_len -= rxq->crc_len;
> +    rxm->data_len -= rxq->crc_len;
>

 Removing 'crc_len' from 'mbuf->pkt_len' & 'mbuf->data_len' is
 practically same as stripping CRC.

 We don't count CRC length in the statistics, but it should be
 accessible
 in the payload by the user.
>>> Our drivers are behaving exactly as you say.
>>>
>>
>> If so I missed why mbuf 'pkt_len' and 'data_len' reduced by
>> 'rxq->crc_len', can you please explain what above lines does?
>>
>>
> @@ -2470,8 +2523,7 @@ hns3_recv_pkts_simple(void *rx_queue,
>  rxdp->rx.bd_base_info = 0;
> 
>  rxm->data_off = RTE_PKTMBUF_HEADROOM;
> -    rxm->pkt_len = (uint16_t)(rte_le_to_cpu_16(rxd.rx.pkt_len)) -
> -    rxq->crc_len;
> +    rxm->pkt_len = rte_le_to_cpu_16(rxd.rx.pkt_len);
> 
> In the previous code above, the 'pkt_len' is set to the length obtained
> from the BD. the length obtained from the BD already contains CRC length.
> But as you said above, the DPDK requires that the length of the mbuf
> does not contain CRC length . So we subtract 'rxq->crc_len' from
> mbuf'pkt_len' and 'data_len'. This patch doesn't change the logic, it
> just moves the code around.
>

Nope, I am not saying mbuf length shouldn't contain CRC length, indeed
it is other way around and this is our confusion.

CRC length shouldn't be in the statistics, I mean in received bytes stats.
Assume that received packet is 128 bytes and we know it has the CRC,
Rx received bytes stat should be 124 (rx_bytes = 128 - CRC = 124)

But mbuf->data_len & mbuf->pkt_len should have full frame length,
including CRC.

As application explicitly requested to KEEP CRC, it will know last 4
bytes are CRC.
Anything after 'mbuf->data_len' in the mbuf buffer is not valid, so if
you reduce 'mbuf->data_len' by CRC size, application can't know if 4
bytes after 'mbuf->data_len' is valid CRC or not.

[PATCH v3] vhost: enhance virtqueue access lock asserts

[David Marchand]

A simple comment in vhost_user_msg_handler() is not that robust.

Add a lock_all_qps property to message handlers so that their
implementation can add a build check and assert a vq is locked.

Signed-off-by: David Marchand 
---
Changes since v2:
- dropped review tags,
- following use of static_assert() in RTE_BUILD_BUG_ON, reworked build
  check by using enums (one enum is now defined per message type),
- as the added enums must be defined early, moved the definitions of
  handlers at the top of the file,

Changes since v1:
- moved this patch as the last of the series,

---
 lib/vhost/vhost_user.c | 128 +
 1 file changed, 66 insertions(+), 62 deletions(-)

diff --git a/lib/vhost/vhost_user.c b/lib/vhost/vhost_user.c
index 3e8a87e517..84dae612c7 100644
--- a/lib/vhost/vhost_user.c
+++ b/lib/vhost/vhost_user.c
@@ -56,14 +56,72 @@
 #define INFLIGHT_ALIGNMENT 64
 #define INFLIGHT_VERSION   0x1
 
-typedef struct vhost_message_handler {
+typedef const struct vhost_message_handler {
const char *description;
int (*callback)(struct virtio_net **pdev, struct vhu_msg_context *ctx,
int main_fd);
bool accepts_fd;
+   bool lock_all_qps;
 } vhost_message_handler_t;
 static vhost_message_handler_t vhost_message_handlers[];
 
+#define VHOST_MESSAGE_HANDLERS \
+VHOST_MESSAGE_HANDLER(VHOST_USER_NONE, NULL, false, false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_GET_FEATURES, vhost_user_get_features, false, 
false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_FEATURES, vhost_user_set_features, false, 
true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_OWNER, vhost_user_set_owner, false, true) 
\
+VHOST_MESSAGE_HANDLER(VHOST_USER_RESET_OWNER, vhost_user_reset_owner, false, 
false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_MEM_TABLE, vhost_user_set_mem_table, 
true, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_LOG_BASE, vhost_user_set_log_base, true, 
true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_LOG_FD, vhost_user_set_log_fd, true, 
true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_VRING_NUM, vhost_user_set_vring_num, 
false, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_VRING_ADDR, vhost_user_set_vring_addr, 
false, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_VRING_BASE, vhost_user_set_vring_base, 
false, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_GET_VRING_BASE, vhost_user_get_vring_base, 
false, false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_VRING_KICK, vhost_user_set_vring_kick, 
true, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_VRING_CALL, vhost_user_set_vring_call, 
true, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_VRING_ERR, vhost_user_set_vring_err, 
true, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_GET_PROTOCOL_FEATURES, 
vhost_user_get_protocol_features, \
+   false, false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_PROTOCOL_FEATURES, 
vhost_user_set_protocol_features, \
+   false, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_GET_QUEUE_NUM, vhost_user_get_queue_num, 
false, false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_VRING_ENABLE, 
vhost_user_set_vring_enable, false, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SEND_RARP, vhost_user_send_rarp, false, true) 
\
+VHOST_MESSAGE_HANDLER(VHOST_USER_NET_SET_MTU, vhost_user_net_set_mtu, false, 
true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_BACKEND_REQ_FD, vhost_user_set_req_fd, 
true, true) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_IOTLB_MSG, vhost_user_iotlb_msg, false, 
false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_GET_CONFIG, vhost_user_get_config, false, 
false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_CONFIG, vhost_user_set_config, false, 
false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_POSTCOPY_ADVISE, 
vhost_user_set_postcopy_advise, false, false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_POSTCOPY_LISTEN, 
vhost_user_set_postcopy_listen, false, false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_POSTCOPY_END, vhost_user_postcopy_end, false, 
false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_GET_INFLIGHT_FD, vhost_user_get_inflight_fd, 
false, false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_INFLIGHT_FD, vhost_user_set_inflight_fd, 
true, false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_SET_STATUS, vhost_user_set_status, false, 
false) \
+VHOST_MESSAGE_HANDLER(VHOST_USER_GET_STATUS, vhost_user_get_status, false, 
false)
+
+#define VHOST_MESSAGE_HANDLER(id, handler, accepts_fd, lock_all_qps) \
+   id ## _LOCK_ALL_QPS = lock_all_qps,
+enum {
+   VHOST_MESSAGE_HANDLERS
+};
+#undef VHOST_MESSAGE_HANDLER
+
+/* vhost_user_msg_handler() locks all qps based on a handler's lock_all_qps.
+ * Later, a handler may need to ensure the vq has been locked (for example,
+ * when calling lock annotated helpers).
+ *
+ * Note: unfortunately, static_assert() does not see an array content as a
+ * constant expression. Because of this, we can't simply check for
+ * vhost_user_msg_handler[].lock_all_qps.
+ * Instead, define an enum for each handler.
+ */
+#define VHOST_USER_ASSERT_LOCK(dev, vq, id) do { \
+   RTE_BUILD_BUG_ON(id ## _LOCK_ALL_QPS == 

[PATCH v3 0/4] add new QAT gen3 and gen5

[Ciara Power]

This patchset adds support for two new QAT devices.
A new GEN3 device, and a GEN5 device, both of which have
wireless slice support for algorithms such as ZUC-256.

Symmetric, asymmetric and compression are all supported
for these devices.

v3:
  - Modified year in licence tag of new gen5 files.
v2:
  - New patch added for gen5 device that reuses gen4 code,
and new gen3 wireless slice changes.
  - Removed patch to disable asymmetric and compression.
  - Documentation updates added.
  - Fixed ZUC-256 IV modification for raw API path.
  - Fixed setting extended protocol flag bit position.
  - Added check for ZUC-256 wireless slice in slice map.

Ciara Power (4):
  common/qat: add new gen3 device
  common/qat: add zuc256 wireless slice for gen3
  common/qat: add new gen3 CMAC macros
  common/qat: add gen5 device

 doc/guides/compressdevs/qat_comp.rst |   1 +
 doc/guides/cryptodevs/qat.rst|   6 +
 doc/guides/rel_notes/release_24_03.rst   |   7 +
 drivers/common/qat/dev/qat_dev_gen4.c|  31 ++-
 drivers/common/qat/dev/qat_dev_gen5.c|  51 
 drivers/common/qat/dev/qat_dev_gens.h|  54 
 drivers/common/qat/meson.build   |   3 +
 drivers/common/qat/qat_adf/icp_qat_fw.h  |   6 +-
 drivers/common/qat/qat_adf/icp_qat_fw_la.h   |  24 ++
 drivers/common/qat/qat_adf/icp_qat_hw.h  |  26 +-
 drivers/common/qat/qat_common.h  |   1 +
 drivers/common/qat/qat_device.c  |  19 ++
 drivers/common/qat/qat_device.h  |   2 +
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c |   8 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen5.c |  73 +
 drivers/compress/qat/dev/qat_comp_pmd_gens.h |  14 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |   7 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c |  63 -
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c |   4 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c | 278 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  40 ++-
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c|  43 +++
 drivers/crypto/qat/qat_sym_session.c | 177 ++--
 drivers/crypto/qat/qat_sym_session.h |   2 +
 24 files changed, 889 insertions(+), 51 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen5.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen5.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c

-- 
2.25.1

[PATCH v3 1/4] common/qat: add new gen3 device

[Ciara Power]

Add new gen3 QAT device ID.
This device has a wireless slice, but other gen3 devices do not, so we
must set a flag to indicate this wireless enabled device.

Capabilities for the device are slightly different from base gen3
capabilities, some are removed from the list for this device.

Symmetric, asymmetric and compression services are enabled.

Signed-off-by: Ciara Power 
Acked-by: Kai Ji 
---
v2: Added documentation updates.
---
 doc/guides/compressdevs/qat_comp.rst |  1 +
 doc/guides/cryptodevs/qat.rst|  2 ++
 doc/guides/rel_notes/release_24_03.rst   |  4 
 drivers/common/qat/qat_device.c  | 13 +
 drivers/common/qat/qat_device.h  |  2 ++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 11 +++
 6 files changed, 33 insertions(+)

diff --git a/doc/guides/compressdevs/qat_comp.rst 
b/doc/guides/compressdevs/qat_comp.rst
index 475c4a9f9f..338b1bf623 100644
--- a/doc/guides/compressdevs/qat_comp.rst
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -10,6 +10,7 @@ support for the following hardware accelerator devices:
 * ``Intel QuickAssist Technology C62x``
 * ``Intel QuickAssist Technology C3xxx``
 * ``Intel QuickAssist Technology DH895x``
+* ``Intel QuickAssist Technology 300xx``
 
 
 Features
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index dc6b95165d..51190e12d6 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -26,6 +26,7 @@ poll mode crypto driver support for the following hardware 
accelerator devices:
 * ``Intel QuickAssist Technology D15xx``
 * ``Intel QuickAssist Technology C4xxx``
 * ``Intel QuickAssist Technology 4xxx``
+* ``Intel QuickAssist Technology 300xx``
 
 
 Features
@@ -177,6 +178,7 @@ poll mode crypto driver support for the following hardware 
accelerator devices:
 * ``Intel QuickAssist Technology C4xxx``
 * ``Intel QuickAssist Technology 4xxx``
 * ``Intel QuickAssist Technology 401xxx``
+* ``Intel QuickAssist Technology 300xx``
 
 The QAT ASYM PMD has support for:
 
diff --git a/doc/guides/rel_notes/release_24_03.rst 
b/doc/guides/rel_notes/release_24_03.rst
index 879bb4944c..55517eabd8 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -131,6 +131,10 @@ New Features
   * Added support for comparing result between packet fields or value.
   * Added support for accumulating value of field into another one.
 
+* **Updated Intel QuickAssist Technology driver.**
+
+  * Enabled support for new QAT GEN3 (578a) devices in QAT crypto driver.
+
 * **Updated Marvell cnxk crypto driver.**
 
   * Added support for Rx inject in crypto_cn10k.
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index f55dc3c6f0..0e7d387d78 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -53,6 +53,9 @@ static const struct rte_pci_id pci_id_qat_map[] = {
{
RTE_PCI_DEVICE(0x8086, 0x18a1),
},
+   {
+   RTE_PCI_DEVICE(0x8086, 0x578b),
+   },
{
RTE_PCI_DEVICE(0x8086, 0x4941),
},
@@ -194,6 +197,7 @@ pick_gen(const struct rte_pci_device *pci_dev)
case 0x18ef:
return QAT_GEN2;
case 0x18a1:
+   case 0x578b:
return QAT_GEN3;
case 0x4941:
case 0x4943:
@@ -205,6 +209,12 @@ pick_gen(const struct rte_pci_device *pci_dev)
}
 }
 
+static int
+wireless_slice_support(uint16_t pci_dev_id)
+{
+   return pci_dev_id == 0x578b;
+}
+
 struct qat_pci_device *
 qat_pci_device_allocate(struct rte_pci_device *pci_dev,
struct qat_dev_cmd_param *qat_dev_cmd_param)
@@ -282,6 +292,9 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev,
qat_dev->qat_dev_id = qat_dev_id;
qat_dev->qat_dev_gen = qat_dev_gen;
 
+   if (wireless_slice_support(pci_dev->id.device_id))
+   qat_dev->has_wireless_slice = 1;
+
ops_hw = qat_dev_hw_spec[qat_dev->qat_dev_gen];
NOT_NULL(ops_hw->qat_dev_get_misc_bar, goto error,
"QAT internal error! qat_dev_get_misc_bar function not set");
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index aa7988bb74..43e4752812 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -135,6 +135,8 @@ struct qat_pci_device {
/**< Per generation specific information */
uint32_t slice_map;
/**< Map of the crypto and compression slices */
+   uint16_t has_wireless_slice;
+   /**< Wireless Slices supported */
 };
 
 struct qat_gen_hw_data {
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c 
b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index 02bcdb06b1..bc53e2e0f1 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -255,6 +255,17 @@ 

[PATCH v3 2/4] common/qat: add zuc256 wireless slice for gen3

[Ciara Power]

The new gen3 device handles wireless algorithms on wireless slices,
based on the device wireless slice support, set the required flags for
these algorithms to move slice.

One of the algorithms supported for the wireless slices is ZUC 256,
support is added for this, along with modifying the capability for the
device.
The device supports 24 bytes iv for ZUC 256, with iv[20]
being ignored in register.
For 25 byte iv, compress this into 23 bytes.

Signed-off-by: Ciara Power 
Acked-by: Kai Ji 
---
v2:
  - Fixed setting extended protocol flag bit position.
  - Added slice map check for ZUC256 wireless slice.
  - Fixed IV modification for ZUC256 in raw datapath.
  - Added increment size for ZUC256 capabiltiies.
  - Added release note.
---
 doc/guides/rel_notes/release_24_03.rst   |   1 +
 drivers/common/qat/qat_adf/icp_qat_fw.h  |   6 +-
 drivers/common/qat/qat_adf/icp_qat_fw_la.h   |  24 
 drivers/common/qat/qat_adf/icp_qat_hw.h  |  24 +++-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |   7 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c |  52 ++-
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  34 -
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c|  43 ++
 drivers/crypto/qat/qat_sym_session.c | 142 +--
 drivers/crypto/qat/qat_sym_session.h |   2 +
 10 files changed, 312 insertions(+), 23 deletions(-)

diff --git a/doc/guides/rel_notes/release_24_03.rst 
b/doc/guides/rel_notes/release_24_03.rst
index 55517eabd8..0dee1ff104 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -134,6 +134,7 @@ New Features
 * **Updated Intel QuickAssist Technology driver.**
 
   * Enabled support for new QAT GEN3 (578a) devices in QAT crypto driver.
+  * Enabled ZUC256 cipher and auth algorithm for wireless slice enabled GEN3 
device.
 
 * **Updated Marvell cnxk crypto driver.**
 
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h 
b/drivers/common/qat/qat_adf/icp_qat_fw.h
index 3aa17ae041..dd7c926140 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -75,7 +75,8 @@ struct icp_qat_fw_comn_req_hdr {
uint8_t service_type;
uint8_t hdr_flags;
uint16_t serv_specif_flags;
-   uint16_t comn_req_flags;
+   uint8_t comn_req_flags;
+   uint8_t ext_flags;
 };
 
 struct icp_qat_fw_comn_req_rqpars {
@@ -176,9 +177,6 @@ struct icp_qat_fw_comn_resp {
 #define QAT_COMN_PTR_TYPE_SGL 0x1
 #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0
 #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1
-#define QAT_COMN_EXT_FLAGS_BITPOS 8
-#define QAT_COMN_EXT_FLAGS_MASK 0x1
-#define QAT_COMN_EXT_FLAGS_USED 0x1
 
 #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h 
b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
index 70f0effa62..134c309355 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
@@ -81,6 +81,15 @@ struct icp_qat_fw_la_bulk_req {
 #define ICP_QAT_FW_LA_PARTIAL_END 2
 #define QAT_LA_PARTIAL_BITPOS 0
 #define QAT_LA_PARTIAL_MASK 0x3
+#define QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_BITPOS 0
+#define QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS 1
+#define QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_MASK 0x1
+#define QAT_LA_USE_WCP_SLICE 1
+#define QAT_LA_USE_WCP_SLICE_BITPOS 2
+#define QAT_LA_USE_WCP_SLICE_MASK 0x1
+#define QAT_LA_USE_WAT_SLICE_BITPOS 3
+#define QAT_LA_USE_WAT_SLICE 1
+#define QAT_LA_USE_WAT_SLICE_MASK 0x1
 #define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \
cmp_auth, ret_auth, update_state, \
ciph_iv, ciphcfg, partial) \
@@ -188,6 +197,21 @@ struct icp_qat_fw_la_bulk_req {
QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
QAT_LA_PARTIAL_MASK)
 
+#define ICP_QAT_FW_USE_EXTENDED_PROTOCOL_FLAGS_SET(flags, val) \
+   QAT_FIELD_SET(flags, val,   \
+   QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_BITPOS,  \
+   QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_MASK)
+
+#define ICP_QAT_FW_USE_WCP_SLICE_SET(flags, val) \
+   QAT_FIELD_SET(flags, val, \
+   QAT_LA_USE_WCP_SLICE_BITPOS, \
+   QAT_LA_USE_WCP_SLICE_MASK)
+
+#define ICP_QAT_FW_USE_WAT_SLICE_SET(flags, val) \
+   QAT_FIELD_SET(flags, val, \
+   QAT_LA_USE_WAT_SLICE_BITPOS, \
+   QAT_LA_USE_WAT_SLICE_MASK)
+
 #define QAT_FW_LA_MODE2 1
 #define QAT_FW_LA_NO_MODE2 0
 #define QAT_FW_LA_MODE2_MASK 0x1
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h 
b/drivers/common/qat/qat_adf/icp_qat_hw.h
index 33756d512d..4651fb90bb 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -21,7 +21,8 @@ enum icp_qat_slice_mask {
ICP_ACCEL_MASK_CRYPTO1_SLICE = 0x100,
ICP_ACCEL_MASK_CRYPTO2_SLICE = 0x200,
ICP_ACCEL_MASK_SM3_SLICE = 0x400,
-   ICP_ACCEL_MASK_SM4_SLICE = 0x800
+   I

[PATCH v3 3/4] common/qat: add new gen3 CMAC macros

[Ciara Power]

The new QAT GEN3 device uses new macros for CMAC values, rather than
using XCBC_MAC ones.

The wireless slice handles CMAC in the new gen3 device, and no key
precomputes are required by SW.

Signed-off-by: Ciara Power 
Acked-by: Kai Ji 
---
 drivers/common/qat/qat_adf/icp_qat_hw.h |  4 +++-
 drivers/crypto/qat/qat_sym_session.c| 28 +
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h 
b/drivers/common/qat/qat_adf/icp_qat_hw.h
index 4651fb90bb..b99dde2176 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -75,7 +75,7 @@ enum icp_qat_hw_auth_algo {
ICP_QAT_HW_AUTH_ALGO_RESERVED = 20,
ICP_QAT_HW_AUTH_ALGO_RESERVED1 = 21,
ICP_QAT_HW_AUTH_ALGO_RESERVED2 = 22,
-   ICP_QAT_HW_AUTH_ALGO_RESERVED3 = 22,
+   ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC = 22,
ICP_QAT_HW_AUTH_ALGO_RESERVED4 = 23,
ICP_QAT_HW_AUTH_ALGO_RESERVED5 = 24,
ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 = 25,
@@ -180,6 +180,7 @@ struct icp_qat_hw_auth_setup {
 #define ICP_QAT_HW_ZUC_256_MAC_32_STATE1_SZ 8
 #define ICP_QAT_HW_ZUC_256_MAC_64_STATE1_SZ 8
 #define ICP_QAT_HW_ZUC_256_MAC_128_STATE1_SZ 16
+#define ICP_QAT_HW_AES_CMAC_STATE1_SZ 16
 
 #define ICP_QAT_HW_NULL_STATE2_SZ 32
 #define ICP_QAT_HW_MD5_STATE2_SZ 16
@@ -208,6 +209,7 @@ struct icp_qat_hw_auth_setup {
 #define ICP_QAT_HW_GALOIS_H_SZ 16
 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
+#define ICP_QAT_HW_AES_128_CMAC_STATE2_SZ 16
 
 struct icp_qat_hw_auth_sha512 {
struct icp_qat_hw_auth_setup inner_setup;
diff --git a/drivers/crypto/qat/qat_sym_session.c 
b/drivers/crypto/qat/qat_sym_session.c
index ebdad0bd67..b1649b8d18 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -922,11 +922,20 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
break;
case RTE_CRYPTO_AUTH_AES_CMAC:
-   session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
session->aes_cmac = 1;
-   if (internals->qat_dev->has_wireless_slice) {
-   is_wireless = 1;
-   session->is_wireless = 1;
+   if (!internals->qat_dev->has_wireless_slice) {
+   session->qat_hash_alg = 
ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
+   break;
+   }
+   is_wireless = 1;
+   session->is_wireless = 1;
+   switch (key_length) {
+   case ICP_QAT_HW_AES_128_KEY_SZ:
+   session->qat_hash_alg = 
ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC;
+   break;
+   default:
+   QAT_LOG(ERR, "Invalid key length: %d", key_length);
+   return -ENOTSUP;
}
break;
case RTE_CRYPTO_AUTH_AES_GMAC:
@@ -1309,6 +1318,9 @@ static int qat_hash_get_state1_size(enum 
icp_qat_hw_auth_algo qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_NULL:
return QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,
QAT_HW_DEFAULT_ALIGNMENT);
+   case ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC:
+   return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_CMAC_STATE1_SZ,
+   QAT_HW_DEFAULT_ALIGNMENT);
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum state1 size in this case */
return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
@@ -1345,6 +1357,7 @@ static int qat_hash_get_digest_size(enum 
icp_qat_hw_auth_algo qat_hash_alg)
case ICP_QAT_HW_AUTH_ALGO_MD5:
return ICP_QAT_HW_MD5_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
+   case ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC:
return ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum digest size in this case */
@@ -2353,6 +2366,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC
+   || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SM3
@@ -2593,6 +2607,12 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
return -EFAULT;
}
break;
+   case ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC:
+   state1_size = ICP_QAT_HW_AES_CMAC

[PATCH v3 4/4] common/qat: add gen5 device

[Ciara Power]

Add new gen5 QAT device ID.
This device has a wireless slice, so we must set a flag to indicate
this wireless enabled device.
Asides from the wireless slices and some extra capabilities for
wireless algorithms, the device is functionally the same as gen4 and can
reuse most functions and macros.

Symmetric, asymmetric and compression services are enabled.

Signed-off-by: Ciara Power 
Acked-by: Kai Ji 
---
v3:
  - Fixed copyright tag in new files to 2024.
  - Removed v2 changes in notes of commit, this patch was new in v2.
---
 doc/guides/cryptodevs/qat.rst|   4 +
 doc/guides/rel_notes/release_24_03.rst   |   6 +-
 drivers/common/qat/dev/qat_dev_gen4.c|  31 ++-
 drivers/common/qat/dev/qat_dev_gen5.c|  51 
 drivers/common/qat/dev/qat_dev_gens.h|  54 
 drivers/common/qat/meson.build   |   3 +
 drivers/common/qat/qat_common.h  |   1 +
 drivers/common/qat/qat_device.c  |   8 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c |   8 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen5.c |  73 +
 drivers/compress/qat/dev/qat_comp_pmd_gens.h |  14 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c |   4 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c | 278 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |   6 +
 drivers/crypto/qat/qat_sym_session.c |  13 +-
 15 files changed, 524 insertions(+), 30 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen5.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen5.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 51190e12d6..28945bb5f3 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -27,6 +27,7 @@ poll mode crypto driver support for the following hardware 
accelerator devices:
 * ``Intel QuickAssist Technology C4xxx``
 * ``Intel QuickAssist Technology 4xxx``
 * ``Intel QuickAssist Technology 300xx``
+* ``Intel QuickAssist Technology 420xx``
 
 
 Features
@@ -179,6 +180,7 @@ poll mode crypto driver support for the following hardware 
accelerator devices:
 * ``Intel QuickAssist Technology 4xxx``
 * ``Intel QuickAssist Technology 401xxx``
 * ``Intel QuickAssist Technology 300xx``
+* ``Intel QuickAssist Technology 420xx``
 
 The QAT ASYM PMD has support for:
 
@@ -472,6 +474,8 @@ to see the full table)

+-+-+-+-+--+---+---+++--+++
| Yes | No  | No  | 4   | 402xx| IDZ/ N/A  | qat_4xxx  | 4xxx   
| 4944   | 2| 4945   | 16 |

+-+-+-+-+--+---+---+++--+++
+   | Yes | Yes | Yes | 5   | 420xx| linux/6.8+| qat_420xx | 420xx  
| 4946   | 2| 4947   | 16 |
+   
+-+-+-+-+--+---+---+++--+++
 
 * Note: Symmetric mixed crypto algorithms feature on Gen 2 works only with IDZ 
driver version 4.9.0+
 
diff --git a/doc/guides/rel_notes/release_24_03.rst 
b/doc/guides/rel_notes/release_24_03.rst
index 0dee1ff104..439d354cd8 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -133,8 +133,10 @@ New Features
 
 * **Updated Intel QuickAssist Technology driver.**
 
-  * Enabled support for new QAT GEN3 (578a) devices in QAT crypto driver.
-  * Enabled ZUC256 cipher and auth algorithm for wireless slice enabled GEN3 
device.
+  * Enabled support for new QAT GEN3 (578a) and QAT GEN5 (4946)
+devices in QAT crypto driver.
+  * Enabled ZUC256 cipher and auth algorithm for wireless slice
+enabled GEN3 and GEN5 devices.
 
 * **Updated Marvell cnxk crypto driver.**
 
diff --git a/drivers/common/qat/dev/qat_dev_gen4.c 
b/drivers/common/qat/dev/qat_dev_gen4.c
index 1ce262f715..2525e1e695 100644
--- a/drivers/common/qat/dev/qat_dev_gen4.c
+++ b/drivers/common/qat/dev/qat_dev_gen4.c
@@ -10,6 +10,7 @@
 #include "adf_transport_access_macros_gen4vf.h"
 #include "adf_pf2vf_msg.h"
 #include "qat_pf2vf.h"
+#include "qat_dev_gens.h"
 
 #include 
 
@@ -60,7 +61,7 @@ qat_select_valid_queue_gen4(struct qat_pci_device *qat_dev, 
int qp_id,
return -1;
 }
 
-static const struct qat_qp_hw_data *
+const struct qat_qp_hw_data *
 qat_qp_get_hw_data_gen4(struct qat_pci_device *qat_dev,
enum qat_service_type service_type, uint16_t qp_id)
 {
@@ -74,7 +75,7 @@ qat_qp_get_hw_data_gen4(struct qat_pci_device *qat_dev,
return &dev_extra->qp_gen4_data[ring_pair][0];
 }
 
-static int
+int
 qat_qp_rings_per_service_gen4(struct qat_pci_device *qat_dev,
enum qat_service_type service)
 {
@@ -103,7 +104,7 @@ gen4_pick_service(uint8_t hw_service)
}
 }
 
-static int
+int
 qat_dev_read_config_gen4(struct qat_pci_device *qat_dev)
 {
int i = 0;
@@ -143,7 +1

Re: [PATCH v5 02/39] eal: redefine macro to be integer literal for MSVC

[Tyler Retzlaff]

On Mon, Feb 26, 2024 at 12:51:38PM +, Konstantin Ananyev wrote:
> 
> 
> > MSVC __declspec(align(#)) is limited and accepts only integer literals
> > as opposed to constant expressions. define XMM_SIZE to be 16 instead of
> > sizeof(xmm_t) and static_assert that sizeof(xmm_t) == 16 for
> > compatibility.
> > 
> > Signed-off-by: Tyler Retzlaff 
> > Acked-by: Morten Brørup 
> > ---
> >  lib/eal/x86/include/rte_vect.h | 5 -
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/lib/eal/x86/include/rte_vect.h b/lib/eal/x86/include/rte_vect.h
> > index a1a537e..441f1a0 100644
> > --- a/lib/eal/x86/include/rte_vect.h
> > +++ b/lib/eal/x86/include/rte_vect.h
> > @@ -11,6 +11,7 @@
> >   * RTE SSE/AVX related header.
> >   */
> > 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -33,9 +34,11 @@
> > 
> >  typedef __m128i xmm_t;
> > 
> > -#defineXMM_SIZE(sizeof(xmm_t))
> > +#defineXMM_SIZE16
> >  #defineXMM_MASK(XMM_SIZE - 1)
> > 
> > +static_assert(sizeof(xmm_t) == 16, "");
> 
> I think it is better be:
> static_assert(sizeof(xmm_t) == XMM_SIZE, "");
> 

ack, will fix

> 
> BTW, is there any chance that in future versions MSVC would accept 
> align()?

it does seem an oversight. i will ask the msvc team if they would like to 
enhance it.

thanks

> 
> > +
> >  typedef union rte_xmm {
> > xmm_tx;
> > uint8_t  u8[XMM_SIZE / sizeof(uint8_t)];
> > --
> > 1.8.3.1
> 

Re: [PATCH v5 05/39] ring: use C11 alignas

[Tyler Retzlaff]

On Mon, Feb 26, 2024 at 01:23:35PM +, Konstantin Ananyev wrote:
> 
> 
> > 
> > The current location used for __rte_aligned(a) for alignment of types
> > and variables is not compatible with MSVC. There is only a single
> > location accepted by both toolchains.
> > 
> > For variables standard C11 offers alignas(a) supported by conformant
> > compilers i.e. both MSVC and GCC.
> > 
> > For types the standard offers no alignment facility that compatibly
> > interoperates with C and C++ but may be achieved by relocating the
> > placement of __rte_aligned(a) to the aforementioned location accepted
> > by all currently supported toolchains.
> > 
> > To allow alignment for both compilers do the following:
> > 
> > * Move __rte_aligned from the end of {struct,union} definitions to
> >   be between {struct,union} and tag.
> > 
> >   The placement between {struct,union} and the tag allows the desired
> >   alignment to be imparted on the type regardless of the toolchain being
> >   used for all of GCC, LLVM, MSVC compilers building both C and C++.
> > 
> > * Replace use of __rte_aligned(a) on variables/fields with alignas(a).
> > 
> > Signed-off-by: Tyler Retzlaff 
> > Acked-by: Morten Brørup 
> > ---
> >  lib/ring/rte_ring_core.h| 16 +---
> >  lib/ring/rte_ring_peek_zc.h |  4 ++--
> >  2 files changed, 11 insertions(+), 9 deletions(-)
> > 
> > diff --git a/lib/ring/rte_ring_core.h b/lib/ring/rte_ring_core.h
> > index b770873..497d535 100644
> > --- a/lib/ring/rte_ring_core.h
> > +++ b/lib/ring/rte_ring_core.h
> > @@ -19,6 +19,8 @@
> >   * instead.
> >   */
> > 
> > +#include 
> > +
> >  #ifdef __cplusplus
> >  extern "C" {
> >  #endif
> > @@ -78,7 +80,7 @@ struct rte_ring_headtail {
> > 
> >  union __rte_ring_rts_poscnt {
> > /** raw 8B value to read/write *cnt* and *pos* as one atomic op */
> > -   RTE_ATOMIC(uint64_t) raw __rte_aligned(8);
> > +   alignas(8) RTE_ATOMIC(uint64_t) raw;
> 
> One small question - here and below, would it possible to do 
> 'alignas(sizeof(uint64_t))' instead of 'alignas(8)?
> Or MSVC has some restrictions here?

it should be okay to use a constant expression with alignas(n) even with
MSVC because it is conformant, if it isn't it would be a bug.  it is one benefit
over using __declspec(align(a)).

i'll update the series to use sizeof.

> 
> 
> > struct {
> > uint32_t cnt; /**< head/tail reference counter */
> > uint32_t pos; /**< head/tail position */
> > @@ -94,7 +96,7 @@ struct rte_ring_rts_headtail {
> > 

Re: RTE_MARKER with MSVC

[Tyler Retzlaff]

On Sat, Feb 24, 2024 at 12:16:58PM +0100, Morten Brørup wrote:
> Hi Tyler,
> 
> Does MSVC permit empty structures, i.e. structures with no fields? Perhaps 
> with some additional decoration, a la [[msvc::no_unique_address]].
> If so, perhaps that would be a possible workaround for RTE_MARKERs.

i had some pretty long conversations with one of the main msvc devs
about this and they couldn't identify anything that they had that could
be used.

we didn't exhaustively dig through new versions of the standards but
even if there was something there we probably couldn't use it while
still baselined to C11.

i know the inline accessors were not going to be a perfect solution
either for the reason you raise on list. at this point i'm trying to
find a happy medium to solve the problem where everyone doesn't end up
too upset.

even anonymous unions turn out to be an imperfect solution because
there's a corner case they can't cover where the union ends up with a
field that is a FAM.

i even asked if they could just support similar as an extension but they
were pretty firm no. at this point unless enhancements are absolute need
i am not likely to get large investments from msvc (for now). i've spent
an enormous amount of their resources in the last couple of years for
dpdk and they want to see some customers using dpdk before they are able
to commit more.

fortunately i think we have enough now to at least get customers using
dpdk without significant compromises (assuming i can ever get all my
changes upstream).

also in case i haven't said it lately, i appreciate all the review and
input you've given it really helps a lot.

ty


> 
> 
> Med venlig hilsen / Kind regards,
> -Morten Brørup
> 

Re: [PATCH v2 01/17] log: add a per line log helper with parameterized prefix

[Thomas Monjalon]

23/02/2024 00:46, Tyler Retzlaff:
> Providing a custom prefix when logging is common for components. Lift
> ISO C99 compliant helper macros from mlx5_common.h and provide
> RTE_LOG_LINE_PREFIX macro that can expand similar to RTE_LOG_LINE with
> a custom prefix and argument list.
[...]
> > +#define _RTE_LOG_COMMA ,

I'm not sure about the underscore at the beginning.
Anyway it is exported in the API.
By the way it should have a Doxygen comment.

> +
> +#define RTE_LOG_LINE_PREFIX(l, t, prefix, args, ...) do { \
> + RTE_LOG_CHECK_NO_NEWLINE(RTE_FMT_HEAD(prefix __VA_ARGS__ ,)); \
> + RTE_LOG(l, t, RTE_FMT(prefix RTE_FMT_HEAD(__VA_ARGS__ ,) "\n", \
> + args _RTE_LOG_COMMA RTE_FMT_TAIL(__VA_ARGS__ ,))); \
> +} while (0)
> +
> +#define RTE_LOG_DP_LINE_PREFIX(l, t, prefix, args, ...) do { \
> + RTE_LOG_CHECK_NO_NEWLINE(RTE_FMT_HEAD(prefix __VA_ARGS__ ,)); \
> + RTE_LOG_DP(l, t, RTE_FMT(prefix RTE_FMT_HEAD(__VA_ARGS__ ,) "\n", \
> + args _RTE_LOG_COMMA RTE_FMT_TAIL(__VA_ARGS__ ,))); \
> +} while (0)

Please could you add a Doxygen comment for each RTE_LOG_LINE variations,
including previous ones?
Would be nice to have an idea of the output what DP is doing.

Re: [PATCH v5 05/22] mbuf: stop using mbuf cacheline marker fields

[Stephen Hemminger]

On Sat, 24 Feb 2024 11:58:59 +0100
Thomas Monjalon  wrote:

> 24/02/2024 09:21, Tyler Retzlaff:
> > Update prefetch inline functions to access rte_mbuf struct fields
> > directly instead of via cacheline{0,1} marker extension fields.
> > 
> > Signed-off-by: Tyler Retzlaff   
> [...]
> >  rte_mbuf_prefetch_part1(struct rte_mbuf *m)
> >  {
> > -   rte_prefetch0(&m->cacheline0);
> > +   rte_prefetch0(&m->buf_addr);  
> 
> Should be simply "m", no need to point to the first field explicitly.
> 
> [...]
> >  rte_mbuf_prefetch_part2(struct rte_mbuf *m)
> >  {
> >  #if RTE_CACHE_LINE_SIZE == 64
> > -   rte_prefetch0(&m->cacheline1);
> > +#if RTE_IOVA_IN_MBUF
> > +   rte_prefetch0(&m->next);
> > +#else
> > +   rte_prefetch0(&m->dynfield2);
> > +#endif  
> 
> I think it is better to calculate m + min cache line size
> instead of relying on fields.
> 
> 

Agree with Thomas, the markers and field dependency are bad idea.

[PATCH v6 02/39] eal: redefine macro to be integer literal for MSVC

[Tyler Retzlaff]

MSVC __declspec(align(#)) is limited and accepts only integer literals
as opposed to constant expressions. define XMM_SIZE to be 16 instead of
sizeof(xmm_t) and static_assert that sizeof(xmm_t) == 16 for
compatibility.

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/eal/x86/include/rte_vect.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/lib/eal/x86/include/rte_vect.h b/lib/eal/x86/include/rte_vect.h
index a1a537e..5ac3ccf 100644
--- a/lib/eal/x86/include/rte_vect.h
+++ b/lib/eal/x86/include/rte_vect.h
@@ -11,6 +11,7 @@
  * RTE SSE/AVX related header.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -33,9 +34,11 @@
 
 typedef __m128i xmm_t;
 
-#defineXMM_SIZE(sizeof(xmm_t))
+#defineXMM_SIZE16
 #defineXMM_MASK(XMM_SIZE - 1)
 
+static_assert(sizeof(xmm_t) == XMM_SIZE, "");
+
 typedef union rte_xmm {
xmm_tx;
uint8_t  u8[XMM_SIZE / sizeof(uint8_t)];
-- 
1.8.3.1

[PATCH v6 01/39] eal: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Expand __rte_aligned(a) to __declspec(align(a)) when building
  with MSVC.

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
Acked-by: Bruce Richardson 
---
 lib/eal/arm/include/rte_vect.h   |  4 ++--
 lib/eal/common/malloc_elem.h |  4 ++--
 lib/eal/common/malloc_heap.h |  4 ++--
 lib/eal/common/rte_keepalive.c   |  3 ++-
 lib/eal/common/rte_random.c  |  4 ++--
 lib/eal/common/rte_service.c |  8 
 lib/eal/include/generic/rte_atomic.h |  4 ++--
 lib/eal/include/rte_common.h | 23 +++
 lib/eal/loongarch/include/rte_vect.h |  8 
 lib/eal/ppc/include/rte_vect.h   |  4 ++--
 lib/eal/riscv/include/rte_vect.h |  4 ++--
 lib/eal/x86/include/rte_vect.h   |  4 ++--
 lib/eal/x86/rte_power_intrinsics.c   | 10 ++
 13 files changed, 47 insertions(+), 37 deletions(-)

diff --git a/lib/eal/arm/include/rte_vect.h b/lib/eal/arm/include/rte_vect.h
index 8cfe4bd..c97d299 100644
--- a/lib/eal/arm/include/rte_vect.h
+++ b/lib/eal/arm/include/rte_vect.h
@@ -24,14 +24,14 @@
 #defineXMM_SIZE(sizeof(xmm_t))
 #defineXMM_MASK(XMM_SIZE - 1)
 
-typedef union rte_xmm {
+typedef union __rte_aligned(16) rte_xmm {
xmm_tx;
uint8_t  u8[XMM_SIZE / sizeof(uint8_t)];
uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
double   pd[XMM_SIZE / sizeof(double)];
-} __rte_aligned(16) rte_xmm_t;
+} rte_xmm_t;
 
 #if defined(RTE_ARCH_ARM) && defined(RTE_ARCH_32)
 /* NEON intrinsic vqtbl1q_u8() is not supported in ARMv7-A(AArch32) */
diff --git a/lib/eal/common/malloc_elem.h b/lib/eal/common/malloc_elem.h
index 952ce73..c7ff671 100644
--- a/lib/eal/common/malloc_elem.h
+++ b/lib/eal/common/malloc_elem.h
@@ -20,7 +20,7 @@ enum elem_state {
ELEM_PAD  /* element is a padding-only header */
 };
 
-struct malloc_elem {
+struct __rte_cache_aligned malloc_elem {
struct malloc_heap *heap;
struct malloc_elem *volatile prev;
/**< points to prev elem in memseg */
@@ -48,7 +48,7 @@ struct malloc_elem {
size_t user_size;
uint64_t asan_cookie[2]; /* must be next to header_cookie */
 #endif
-} __rte_cache_aligned;
+};
 
 static const unsigned int MALLOC_ELEM_HEADER_LEN = sizeof(struct malloc_elem);
 
diff --git a/lib/eal/common/malloc_heap.h b/lib/eal/common/malloc_heap.h
index 8f3ab57..0c49588 100644
--- a/lib/eal/common/malloc_heap.h
+++ b/lib/eal/common/malloc_heap.h
@@ -21,7 +21,7 @@
 /**
  * Structure to hold malloc heap
  */
-struct malloc_heap {
+struct __rte_cache_aligned malloc_heap {
rte_spinlock_t lock;
LIST_HEAD(, malloc_elem) free_head[RTE_HEAP_NUM_FREELISTS];
struct malloc_elem *volatile first;
@@ -31,7 +31,7 @@ struct malloc_heap {
unsigned int socket_id;
size_t total_size;
char name[RTE_HEAP_NAME_MAX_LEN];
-} __rte_cache_aligned;
+};
 
 void *
 malloc_heap_alloc(const char *type, size_t size, int socket, unsigned int 
flags,
diff --git a/lib/eal/common/rte_keepalive.c b/lib/eal/common/rte_keepalive.c
index f6db973..391c1be 100644
--- a/lib/eal/common/rte_keepalive.c
+++ b/lib/eal/common/rte_keepalive.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2015-2016 Intel Corporation
  */
 
+#include 
 #include 
 
 #include 
@@ -19,7 +20,7 @@ struct rte_keepalive {
/*
 * Each element must be cache aligned to prevent false sharing.
 */
-   enum rte_keepalive_state core_state __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) enum rte_keepalive_state 
core_state;
} live_data[RTE_KEEPALIVE_MAXCORES];
 
/** Last-seen-alive timestamps */
diff --git a/lib/eal/common/rte_random.c b/lib/eal/common/rte_random.c
index 7709b8f..90e91b3 100644
--- a/lib/eal/common/rte_random.c
+++ b/lib/eal/common/rte_random.c
@@ -13,14 +13,14 @@
 #include 
 #include 
 
-struct rte_rand_state {
+str

[PATCH v6 00/39] use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

** NOTE **

Finally, In the interest of not creating more API (internal or not) the
series does not introduce a wrapper for C11 alignas. If we don't introduce
a macro an application can't take a dependency.

v6:
  * update static_assert to use XMM_SIZE instead of literal integer 16
  * update 2 explicit alignments of ring struct fields to use
  * alignas(sizeof(uint64_t)) instead of alignas(8)

v5:
  * rebase series.
  * reword all commit messages with why the change is necessary.
  * document guidance for the usage of __rte_aligned macro indicating
that it should be used for type alignment only and advising that for
variable alignment standard C11 alignas(a) should be preferred.

v4:
  * restore explicit alignment of 8-byte integers in mbuf and
ring patches, natural alignment may be 4-bytes on 32-bit
targets.
v3:
  * add missing patches for __rte_cache_aligned and
__rte_cache_min_aligned
v2:
  * add missing #include  for alignas macro.

Tyler Retzlaff (39):
  eal: use C11 alignas
  eal: redefine macro to be integer literal for MSVC
  stack: use C11 alignas
  sched: use C11 alignas
  ring: use C11 alignas
  pipeline: use C11 alignas
  net: use C11 alignas
  mbuf: use C11 alignas
  hash: use C11 alignas
  eventdev: use C11 alignas
  ethdev: use C11 alignas
  dmadev: use C11 alignas
  distributor: use C11 alignas
  acl: use C11 alignas
  vhost: use C11 alignas
  timer: use C11 alignas
  table: use C11 alignas
  reorder: use C11 alignas
  regexdev: use C11 alignas
  rcu: use C11 alignas
  power: use C11 alignas
  rawdev: use C11 alignas
  port: use C11 alignas
  pdcp: use C11 alignas
  node: use C11 alignas
  mldev: use C11 alignas
  mempool: use C11 alignas
  member: use C11 alignas
  lpm: use C11 alignas
  ipsec: use C11 alignas
  jobstats: use C11 alignas
  bpf: use C11 alignas
  compressdev: use C11 alignas
  cryptodev: use C11 alignas
  dispatcher: use C11 alignas
  fib: use C11 alignas
  gpudev: use C11 alignas
  graph: use C11 alignas
  ip_frag: use C11 alignas

 lib/acl/acl_run.h  |  4 ++--
 lib/acl/acl_run_altivec.h  |  6 --
 lib/acl/acl_run_neon.h |  6 --
 lib/bpf/bpf_pkt.c  |  4 ++--
 lib/compressdev/rte_comp.h |  4 ++--
 lib/compressdev/rte_compressdev_internal.h |  8 +++
 lib/cryptodev/cryptodev_pmd.h  |  8 +++
 lib/cryptodev/rte_cryptodev_core.h |  4 ++--
 lib/dispatcher/rte_dispatcher.c|  4 ++--
 lib/distributor/distributor_private.h  | 34 --
 lib/distributor/rte_distributor.c  |  5 +++--
 lib/dmadev/rte_dmadev_core.h   |  4 ++--
 lib/dmadev/rte_dmadev_pmd.h|  8 +++
 lib/eal/arm/include/rte_vect.h |  4 ++--
 lib/eal/common/malloc_elem.h   |  4 ++--
 lib/eal/common/malloc_heap.h   |  4 ++--
 lib/eal/common/rte_keepalive.c |  3 ++-
 lib/eal/common/rte_random.c|  4 ++--
 lib/eal/common/rte_service.c   |  8 +++
 lib/eal/include/generic/rte_atomic.h   |  4 ++--
 lib/eal/include/rte_common.h   | 23 +---
 lib/eal/loongarch/include/rte_vect.h   |  8 +++
 lib/eal/ppc/include/rte_vect.h |  4 ++--
 lib/eal/riscv/include/rte_vect.h   |  4 ++--
 lib/eal/x86/include/rte_vect.h |  9 +---
 lib/eal/x86/rte_power_intrinsics.c | 10 +
 lib/ethdev/ethdev_driver.h |  8 +++
 lib/ethdev/rte_ethdev.h| 16 +++---
 lib/ethdev/rte_ethdev_core.h   |  4 ++--
 lib/ethdev/rte_flow_driver.h   |  4 ++--
 lib/eventdev/event_timer_adapter_pmd.h |  4 ++--
 lib/eventdev/eventdev_pmd.h|  8 +++
 lib/eventdev/rte_event_crypto_adapter.c| 16 +++---
 lib/eventdev/rte_event_dma_adapter.c   | 16 +++---
 lib/eventdev/rte_event_eth_rx_adapter.c|  8 +++
 lib/eventdev/rte_event_eth_tx_adapter.c|  4 ++--
 lib/eventdev/rte_event_timer_adapter.c |  9 
 lib/eventdev/rte_event_timer_adapter.h |  8 +++
 lib/eventdev/rte_eventdev.h|  8 +++
 lib/eventdev/rte_eventdev_core.h   |  4 ++--
 lib/fib/dir24_8.h  |  4 +++-
 lib/fib/trie.h |  4 +++-
 lib/gpudev/gpudev_driver.h |  4 ++--
 lib/graph/gr

[PATCH v6 03/39] stack: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/stack/rte_stack.h | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/lib/stack/rte_stack.h b/lib/stack/rte_stack.h
index a379300..8ff0659 100644
--- a/lib/stack/rte_stack.h
+++ b/lib/stack/rte_stack.h
@@ -15,6 +15,8 @@
 #ifndef _RTE_STACK_H_
 #define _RTE_STACK_H_
 
+#include 
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -42,7 +44,7 @@ struct rte_stack_lf_head {
 
 struct rte_stack_lf_list {
/** List head */
-   struct rte_stack_lf_head head __rte_aligned(16);
+   alignas(16) struct rte_stack_lf_head head;
/** List len */
RTE_ATOMIC(uint64_t) len;
 };
@@ -52,11 +54,11 @@ struct rte_stack_lf_list {
  */
 struct rte_stack_lf {
/** LIFO list of elements */
-   struct rte_stack_lf_list used __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) struct rte_stack_lf_list used;
/** LIFO list of free elements */
-   struct rte_stack_lf_list free __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) struct rte_stack_lf_list free;
/** LIFO elements */
-   struct rte_stack_lf_elem elems[] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) struct rte_stack_lf_elem elems[];
 };
 
 /* Structure containing the LIFO, its current length, and a lock for mutual
@@ -71,9 +73,9 @@ struct rte_stack_std {
 /* The RTE stack structure contains the LIFO structure itself, plus metadata
  * such as its name and memzone pointer.
  */
-struct rte_stack {
+struct __rte_cache_aligned rte_stack {
/** Name of the stack. */
-   char name[RTE_STACK_NAMESIZE] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) char name[RTE_STACK_NAMESIZE];
/** Memzone containing the rte_stack structure. */
const struct rte_memzone *memzone;
uint32_t capacity; /**< Usable size of the stack. */
@@ -82,7 +84,7 @@ struct rte_stack {
struct rte_stack_lf stack_lf; /**< Lock-free LIFO structure. */
struct rte_stack_std stack_std; /**< LIFO structure. */
};
-} __rte_cache_aligned;
+};
 
 /**
  * The stack uses lock-free push and pop functions. This flag is only
-- 
1.8.3.1

[PATCH v6 04/39] sched: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

Replace use of __rte_aligned_16 with C11 alignas(16) and garbage collect
the __rte_aligned_16 macro which was only used once.

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/sched/rte_sched.c| 21 +++--
 lib/sched/rte_sched_common.h |  2 --
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index d90aa53..bbdb5d1 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2010-2014 Intel Corporation
  */
 
+#include 
 #include 
 #include 
 
@@ -57,7 +58,7 @@ struct rte_sched_pipe_profile {
uint8_t  wrr_cost[RTE_SCHED_BE_QUEUES_PER_PIPE];
 };
 
-struct rte_sched_pipe {
+struct __rte_cache_aligned rte_sched_pipe {
/* Token bucket (TB) */
uint64_t tb_time; /* time of last update */
uint64_t tb_credits;
@@ -75,7 +76,7 @@ struct rte_sched_pipe {
/* TC oversubscription */
uint64_t tc_ov_credits;
uint8_t tc_ov_period_id;
-} __rte_cache_aligned;
+};
 
 struct rte_sched_queue {
uint16_t qw;
@@ -145,7 +146,7 @@ struct rte_sched_grinder {
uint8_t wrr_cost[RTE_SCHED_BE_QUEUES_PER_PIPE];
 };
 
-struct rte_sched_subport {
+struct __rte_cache_aligned rte_sched_subport {
/* Token bucket (TB) */
uint64_t tb_time; /* time of last update */
uint64_t tb_credits;
@@ -164,7 +165,7 @@ struct rte_sched_subport {
double tc_ov_rate;
 
/* Statistics */
-   struct rte_sched_subport_stats stats __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) struct rte_sched_subport_stats stats;
 
/* subport profile */
uint32_t profile;
@@ -193,7 +194,7 @@ struct rte_sched_subport {
 
/* Bitmap */
struct rte_bitmap *bmp;
-   uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] 
__rte_aligned_16;
+   alignas(16) uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS];
 
/* Grinders */
struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
@@ -212,10 +213,10 @@ struct rte_sched_subport {
struct rte_sched_pipe_profile *pipe_profiles;
uint8_t *bmp_array;
struct rte_mbuf **queue_array;
-   uint8_t memory[0] __rte_cache_aligned;
-} __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint8_t memory[0];
+};
 
-struct rte_sched_port {
+struct __rte_cache_aligned rte_sched_port {
/* User parameters */
uint32_t n_subports_per_port;
uint32_t n_pipes_per_subport;
@@ -244,8 +245,8 @@ struct rte_sched_port {
 
/* Large data structures */
struct rte_sched_subport_profile *subport_profiles;
-   struct rte_sched_subport *subports[0] __rte_cache_aligned;
-} __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) struct rte_sched_subport *subports[0];
+};
 
 enum rte_sched_subport_array {
e_RTE_SCHED_SUBPORT_ARRAY_PIPE = 0,
diff --git a/lib/sched/rte_sched_common.h b/lib/sched/rte_sched_common.h
index 419700b..573d164 100644
--- a/lib/sched/rte_sched_common.h
+++ b/lib/sched/rte_sched_common.h
@@ -12,8 +12,6 @@
 #include 
 #include 
 
-#define __rte_aligned_16 __rte_aligned(16)
-
 #if 0
 static inline uint32_t
 rte_min_pos_4_u16(uint16_t *x)
-- 
1.8.3.1

[PATCH v6 05/39] ring: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/ring/rte_ring_core.h| 16 +---
 lib/ring/rte_ring_peek_zc.h |  4 ++--
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/lib/ring/rte_ring_core.h b/lib/ring/rte_ring_core.h
index b770873..f958064 100644
--- a/lib/ring/rte_ring_core.h
+++ b/lib/ring/rte_ring_core.h
@@ -19,6 +19,8 @@
  * instead.
  */
 
+#include 
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -78,7 +80,7 @@ struct rte_ring_headtail {
 
 union __rte_ring_rts_poscnt {
/** raw 8B value to read/write *cnt* and *pos* as one atomic op */
-   RTE_ATOMIC(uint64_t) raw __rte_aligned(8);
+   alignas(sizeof(uint64_t)) RTE_ATOMIC(uint64_t) raw;
struct {
uint32_t cnt; /**< head/tail reference counter */
uint32_t pos; /**< head/tail position */
@@ -94,7 +96,7 @@ struct rte_ring_rts_headtail {
 
 union __rte_ring_hts_pos {
/** raw 8B value to read/write *head* and *tail* as one atomic op */
-   RTE_ATOMIC(uint64_t) raw __rte_aligned(8);
+   alignas(sizeof(uint64_t)) RTE_ATOMIC(uint64_t) raw;
struct {
RTE_ATOMIC(uint32_t) head; /**< head position */
RTE_ATOMIC(uint32_t) tail; /**< tail position */
@@ -117,7 +119,7 @@ struct rte_ring_hts_headtail {
  * a problem.
  */
 struct rte_ring {
-   char name[RTE_RING_NAMESIZE] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) char name[RTE_RING_NAMESIZE];
/**< Name of the ring. */
int flags;   /**< Flags supplied at creation. */
const struct rte_memzone *memzone;
@@ -129,20 +131,20 @@ struct rte_ring {
RTE_CACHE_GUARD;
 
/** Ring producer status. */
-   union {
+   union __rte_cache_aligned {
struct rte_ring_headtail prod;
struct rte_ring_hts_headtail hts_prod;
struct rte_ring_rts_headtail rts_prod;
-   }  __rte_cache_aligned;
+   };
 
RTE_CACHE_GUARD;
 
/** Ring consumer status. */
-   union {
+   union __rte_cache_aligned {
struct rte_ring_headtail cons;
struct rte_ring_hts_headtail hts_cons;
struct rte_ring_rts_headtail rts_cons;
-   }  __rte_cache_aligned;
+   };
 
RTE_CACHE_GUARD;
 };
diff --git a/lib/ring/rte_ring_peek_zc.h b/lib/ring/rte_ring_peek_zc.h
index 8fb279c..0b5e34b 100644
--- a/lib/ring/rte_ring_peek_zc.h
+++ b/lib/ring/rte_ring_peek_zc.h
@@ -79,7 +79,7 @@
  * This structure contains the pointers and length of the space
  * reserved on the ring storage.
  */
-struct rte_ring_zc_data {
+struct __rte_cache_aligned rte_ring_zc_data {
/* Pointer to the first space in the ring */
void *ptr1;
/* Pointer to the second space in the ring if there is wrap-around.
@@ -92,7 +92,7 @@ struct rte_ring_zc_data {
 * will give the number of elements available at ptr2.
 */
unsigned int n1;
-} __rte_cache_aligned;
+};
 
 static __rte_always_inline void
 __rte_ring_get_elem_addr(struct rte_ring *r, uint32_t head,
-- 
1.8.3.1

[PATCH v6 06/39] pipeline: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/pipeline/rte_pipeline.c   |  4 ++--
 lib/pipeline/rte_port_in_action.c |  3 ++-
 lib/pipeline/rte_swx_ipsec.c  |  4 +++-
 lib/pipeline/rte_table_action.c   | 24 
 4 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/lib/pipeline/rte_pipeline.c b/lib/pipeline/rte_pipeline.c
index 945bb02..a09a89f 100644
--- a/lib/pipeline/rte_pipeline.c
+++ b/lib/pipeline/rte_pipeline.c
@@ -104,7 +104,7 @@ struct rte_table {
 
 #define RTE_PIPELINE_MAX_NAME_SZ   124
 
-struct rte_pipeline {
+struct __rte_cache_aligned rte_pipeline {
/* Input parameters */
char name[RTE_PIPELINE_MAX_NAME_SZ];
int socket_id;
@@ -132,7 +132,7 @@ struct rte_pipeline {
uint64_t pkts_mask;
uint64_t n_pkts_ah_drop;
uint64_t pkts_drop_mask;
-} __rte_cache_aligned;
+};
 
 static inline uint32_t
 rte_mask_get_next(uint64_t mask, uint32_t pos)
diff --git a/lib/pipeline/rte_port_in_action.c 
b/lib/pipeline/rte_port_in_action.c
index 5818973..bbacaff 100644
--- a/lib/pipeline/rte_port_in_action.c
+++ b/lib/pipeline/rte_port_in_action.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2010-2018 Intel Corporation
  */
 
+#include 
 #include 
 #include 
 
@@ -282,7 +283,7 @@ struct rte_port_in_action_profile *
 struct rte_port_in_action {
struct ap_config cfg;
struct ap_data data;
-   uint8_t memory[0] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint8_t memory[0];
 };
 
 static __rte_always_inline void *
diff --git a/lib/pipeline/rte_swx_ipsec.c b/lib/pipeline/rte_swx_ipsec.c
index 28576c2..76b853f 100644
--- a/lib/pipeline/rte_swx_ipsec.c
+++ b/lib/pipeline/rte_swx_ipsec.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2022 Intel Corporation
  */
+
+#include 
 #include 
 #include 
 #include 
@@ -154,7 +156,7 @@ struct rte_swx_ipsec {
/*
 * Table memory.
 */
-   uint8_t memory[] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint8_t memory[];
 };
 
 static inline struct ipsec_sa *
diff --git a/lib/pipeline/rte_table_action.c b/lib/pipeline/rte_table_action.c
index dfdbc66..87c3e0e 100644
--- a/lib/pipeline/rte_table_action.c
+++ b/lib/pipeline/rte_table_action.c
@@ -465,11 +465,11 @@ struct encap_qinq_data {
uint64_t)(s)) & 0x1LLU) << 8) |\
(((uint64_t)(ttl)) & 0xFFLLU)))
 
-struct encap_mpls_data {
+struct __rte_aligned(2) encap_mpls_data {
struct rte_ether_hdr ether;
uint32_t mpls[RTE_TABLE_ACTION_MPLS_LABELS_MAX];
uint32_t mpls_count;
-} __rte_packed __rte_aligned(2);
+} __rte_packed;
 
 #define PPP_PROTOCOL_IP0x0021
 
@@ -487,42 +487,42 @@ struct encap_pppoe_data {
 
 #define IP_PROTO_UDP   17
 
-struct encap_vxlan_ipv4_data {
+struct __rte_aligned(2) encap_vxlan_ipv4_data {
struct rte_ether_hdr ether;
struct rte_ipv4_hdr ipv4;
struct rte_udp_hdr udp;
struct rte_vxlan_hdr vxlan;
-} __rte_packed __rte_aligned(2);
+} __rte_packed;
 
-struct encap_vxlan_ipv4_vlan_data {
+struct __rte_aligned(2) encap_vxlan_ipv4_vlan_data {
struct rte_ether_hdr ether;
struct rte_vlan_hdr vlan;
struct rte_ipv4_hdr ipv4;
struct rte_udp_hdr udp;
struct rte_vxlan_hdr vxlan;
-} __rte_packed __rte_aligned(2);
+} __rte_packed;
 
-struct encap_vxlan_ipv6_data {
+struct __rte_aligned(2) encap_vxlan_ipv6_data {
struct rte_ether_hdr ether;
struct rte_ipv6_hdr ipv6;
struct rte_udp_hdr udp;
struct rte_vxlan_hdr vxlan;
-} __rte_packed __rte_aligned(2);
+} __rte_packed;
 
-struct encap_vxlan_ipv6_vlan_data {
+struct __rte_aligned(2) encap_vxlan_ipv6_vlan_data {
struct rte_ether_hdr ether;
struct rte_vlan_hdr vlan;
struct rte_ipv6_hdr ipv6;
struct rte_udp_hdr udp;
struct rte_vxlan_hdr vxlan;
-} __rte_pack

[PATCH v6 09/39] hash: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/hash/rte_cuckoo_hash.h | 16 +---
 lib/hash/rte_thash.c   |  4 +++-
 lib/hash/rte_thash.h   |  8 
 3 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/lib/hash/rte_cuckoo_hash.h b/lib/hash/rte_cuckoo_hash.h
index 8ea793c..a528f1d 100644
--- a/lib/hash/rte_cuckoo_hash.h
+++ b/lib/hash/rte_cuckoo_hash.h
@@ -11,6 +11,8 @@
 #ifndef _RTE_CUCKOO_HASH_H_
 #define _RTE_CUCKOO_HASH_H_
 
+#include 
+
 #if defined(RTE_ARCH_X86)
 #include "rte_cmp_x86.h"
 #endif
@@ -117,10 +119,10 @@ enum cmp_jump_table_case {
 
 #define RTE_HASH_TSX_MAX_RETRY  10
 
-struct lcore_cache {
+struct __rte_cache_aligned lcore_cache {
unsigned len; /**< Cache len */
uint32_t objs[LCORE_CACHE_SIZE]; /**< Cache objects */
-} __rte_cache_aligned;
+};
 
 /* Structure that stores key-value pair */
 struct rte_hash_key {
@@ -141,7 +143,7 @@ enum rte_hash_sig_compare_function {
 };
 
 /** Bucket structure */
-struct rte_hash_bucket {
+struct __rte_cache_aligned rte_hash_bucket {
uint16_t sig_current[RTE_HASH_BUCKET_ENTRIES];
 
RTE_ATOMIC(uint32_t) key_idx[RTE_HASH_BUCKET_ENTRIES];
@@ -149,10 +151,10 @@ struct rte_hash_bucket {
uint8_t flag[RTE_HASH_BUCKET_ENTRIES];
 
void *next;
-} __rte_cache_aligned;
+};
 
 /** A hash table structure. */
-struct rte_hash {
+struct __rte_cache_aligned rte_hash {
char name[RTE_HASH_NAMESIZE];   /**< Name of the hash. */
uint32_t entries;   /**< Total table entries. */
uint32_t num_buckets;   /**< Number of buckets in table. */
@@ -170,7 +172,7 @@ struct rte_hash {
 
/* Fields used in lookup */
 
-   uint32_t key_len __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint32_t key_len;
/**< Length of hash key. */
uint8_t hw_trans_mem_support;
/**< If hardware transactional memory is used. */
@@ -220,7 +222,7 @@ struct rte_hash {
uint32_t *ext_bkt_to_free;
RTE_ATOMIC(uint32_t) *tbl_chng_cnt;
/**< Indicates if the hash table changed from last read. */
-} __rte_cache_aligned;
+};
 
 struct queue_node {
struct rte_hash_bucket *bkt; /* Current bucket on the bfs search */
diff --git a/lib/hash/rte_thash.c b/lib/hash/rte_thash.c
index e8de071..6464fd3 100644
--- a/lib/hash/rte_thash.c
+++ b/lib/hash/rte_thash.c
@@ -2,6 +2,8 @@
  * Copyright(c) 2021 Intel Corporation
  */
 
+#include 
+
 #include 
 
 #include 
@@ -80,7 +82,7 @@ struct rte_thash_subtuple_helper {
uint32_ttuple_offset;   /** < Offset in bits of the subtuple */
uint32_ttuple_len;  /** < Length in bits of the subtuple */
uint32_tlsb_msk;/** < (1 << reta_sz_log) - 1 */
-   __extension__ uint32_t  compl_table[0] __rte_cache_aligned;
+   __extension__ alignas(RTE_CACHE_LINE_SIZE) uint32_t compl_table[0];
/** < Complementary table */
 };
 
diff --git a/lib/hash/rte_thash.h b/lib/hash/rte_thash.h
index 2681b1b..30b657e 100644
--- a/lib/hash/rte_thash.h
+++ b/lib/hash/rte_thash.h
@@ -99,14 +99,14 @@ struct rte_ipv6_tuple {
};
 };
 
+#ifdef RTE_ARCH_X86
+union __rte_aligned(XMM_SIZE) rte_thash_tuple {
+#else
 union rte_thash_tuple {
+#endif
struct rte_ipv4_tuple   v4;
struct rte_ipv6_tuple   v6;
-#ifdef RTE_ARCH_X86
-} __rte_aligned(XMM_SIZE);
-#else
 };
-#endif
 
 /**
  * Prepare special converted key to use with rte_softrss_be()
-- 
1.8.3.1

[PATCH v6 10/39] eventdev: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/eventdev/event_timer_adapter_pmd.h  |  4 ++--
 lib/eventdev/eventdev_pmd.h |  8 
 lib/eventdev/rte_event_crypto_adapter.c | 16 
 lib/eventdev/rte_event_dma_adapter.c| 16 
 lib/eventdev/rte_event_eth_rx_adapter.c |  8 
 lib/eventdev/rte_event_eth_tx_adapter.c |  4 ++--
 lib/eventdev/rte_event_timer_adapter.c  |  9 +
 lib/eventdev/rte_event_timer_adapter.h  |  8 
 lib/eventdev/rte_eventdev.h |  8 
 lib/eventdev/rte_eventdev_core.h|  4 ++--
 10 files changed, 43 insertions(+), 42 deletions(-)

diff --git a/lib/eventdev/event_timer_adapter_pmd.h 
b/lib/eventdev/event_timer_adapter_pmd.h
index 65b421b..cd5127f 100644
--- a/lib/eventdev/event_timer_adapter_pmd.h
+++ b/lib/eventdev/event_timer_adapter_pmd.h
@@ -86,7 +86,7 @@ struct event_timer_adapter_ops {
  * @internal Adapter data; structure to be placed in shared memory to be
  * accessible by various processes in a multi-process configuration.
  */
-struct rte_event_timer_adapter_data {
+struct __rte_cache_aligned rte_event_timer_adapter_data {
uint8_t id;
/**< Event timer adapter ID */
uint8_t event_dev_id;
@@ -110,7 +110,7 @@ struct rte_event_timer_adapter_data {
 
uint8_t started : 1;
/**< Flag to indicate adapter started. */
-} __rte_cache_aligned;
+};
 
 #ifdef __cplusplus
 }
diff --git a/lib/eventdev/eventdev_pmd.h b/lib/eventdev/eventdev_pmd.h
index c415624..3934d8e 100644
--- a/lib/eventdev/eventdev_pmd.h
+++ b/lib/eventdev/eventdev_pmd.h
@@ -107,7 +107,7 @@ struct rte_eventdev_global {
  * This structure is safe to place in shared memory to be common among
  * different processes in a multi-process configuration.
  */
-struct rte_eventdev_data {
+struct __rte_cache_aligned rte_eventdev_data {
int socket_id;
/**< Socket ID where memory is allocated */
uint8_t dev_id;
@@ -146,10 +146,10 @@ struct rte_eventdev_data {
 
uint64_t reserved_64s[4]; /**< Reserved for future fields */
void *reserved_ptrs[4];   /**< Reserved for future fields */
-} __rte_cache_aligned;
+};
 
 /** @internal The data structure associated with each event device. */
-struct rte_eventdev {
+struct __rte_cache_aligned rte_eventdev {
struct rte_eventdev_data *data;
/**< Pointer to device data */
struct eventdev_ops *dev_ops;
@@ -189,7 +189,7 @@ struct rte_eventdev {
 
uint64_t reserved_64s[3]; /**< Reserved for future fields */
void *reserved_ptrs[3];   /**< Reserved for future fields */
-} __rte_cache_aligned;
+};
 
 extern struct rte_eventdev *rte_eventdevs;
 /** @internal The pool of rte_eventdev structures. */
diff --git a/lib/eventdev/rte_event_crypto_adapter.c 
b/lib/eventdev/rte_event_crypto_adapter.c
index d46595d..6bc2769 100644
--- a/lib/eventdev/rte_event_crypto_adapter.c
+++ b/lib/eventdev/rte_event_crypto_adapter.c
@@ -42,7 +42,7 @@
 
 #define ECA_ADAPTER_ARRAY "crypto_adapter_array"
 
-struct crypto_ops_circular_buffer {
+struct __rte_cache_aligned crypto_ops_circular_buffer {
/* index of head element in circular buffer */
uint16_t head;
/* index of tail element in circular buffer */
@@ -53,9 +53,9 @@ struct crypto_ops_circular_buffer {
uint16_t size;
/* Pointer to hold rte_crypto_ops for batching */
struct rte_crypto_op **op_buffer;
-} __rte_cache_aligned;
+};
 
-struct event_crypto_adapter {
+struct __rte_cache_aligned event_crypto_adapter {
/* Event device identifier */
uint8_t eventdev_id;
/* Event port identifier */
@@ -98,10 +98,10 @@ struct event_crypto_adapter {
uint16_t nb_qps;
/* Adapter mode */
enum rte_event_crypto_adapter_mode mode;
-} __rte_cache_aligned;
+};
 
 /* Per crypto device information */
-struct crypto_device_info {
+struct __rte_cache_aligned crypto_device_info {
/* Pointer to cryptodev */
struc

[PATCH v6 07/39] net: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/net/net_crc_avx512.c | 14 --
 lib/net/net_crc_neon.c   | 11 ++-
 lib/net/net_crc_sse.c| 17 +
 lib/net/rte_arp.h|  8 
 lib/net/rte_ether.h  |  8 
 5 files changed, 31 insertions(+), 27 deletions(-)

diff --git a/lib/net/net_crc_avx512.c b/lib/net/net_crc_avx512.c
index f6a3ce9..0f48ca0 100644
--- a/lib/net/net_crc_avx512.c
+++ b/lib/net/net_crc_avx512.c
@@ -3,6 +3,8 @@
  */
 
 
+#include 
+
 #include 
 
 #include "net_crc.h"
@@ -20,8 +22,8 @@ struct crc_vpclmulqdq_ctx {
__m128i fold_1x128b;
 };
 
-static struct crc_vpclmulqdq_ctx crc32_eth __rte_aligned(64);
-static struct crc_vpclmulqdq_ctx crc16_ccitt __rte_aligned(64);
+static alignas(64) struct crc_vpclmulqdq_ctx crc32_eth;
+static alignas(64) struct crc_vpclmulqdq_ctx crc16_ccitt;
 
 static uint16_t byte_len_to_mask_table[] = {
0x, 0x0001, 0x0003, 0x0007,
@@ -30,18 +32,18 @@ struct crc_vpclmulqdq_ctx {
0x0fff, 0x1fff, 0x3fff, 0x7fff,
0x};
 
-static const uint8_t shf_table[32] __rte_aligned(16) = {
+static const alignas(16) uint8_t shf_table[32] = {
0x00, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f
 };
 
-static const uint32_t mask[4] __rte_aligned(16) = {
+static const alignas(16) uint32_t mask[4] = {
0x, 0x, 0x, 0x
 };
 
-static const uint32_t mask2[4] __rte_aligned(16) = {
+static const alignas(16) uint32_t mask2[4] = {
0x, 0x, 0x, 0x
 };
 
@@ -93,7 +95,7 @@ struct crc_vpclmulqdq_ctx {
uint32_t offset;
__m128i res2, res3, res4, pshufb_shf;
 
-   const uint32_t mask3[4] __rte_aligned(16) = {
+   const alignas(16) uint32_t mask3[4] = {
   0x80808080, 0x80808080, 0x80808080, 0x80808080
};
 
diff --git a/lib/net/net_crc_neon.c b/lib/net/net_crc_neon.c
index f61d75a..cee75dd 100644
--- a/lib/net/net_crc_neon.c
+++ b/lib/net/net_crc_neon.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2017 Cavium, Inc
  */
 
+#include 
 #include 
 
 #include 
@@ -19,8 +20,8 @@ struct crc_pmull_ctx {
uint64x2_t rk7_rk8;
 };
 
-struct crc_pmull_ctx crc32_eth_pmull __rte_aligned(16);
-struct crc_pmull_ctx crc16_ccitt_pmull __rte_aligned(16);
+alignas(16) struct crc_pmull_ctx crc32_eth_pmull;
+alignas(16) struct crc_pmull_ctx crc16_ccitt_pmull;
 
 /**
  * @brief Performs one folding round
@@ -96,10 +97,10 @@ struct crc_pmull_ctx {
 crcr32_reduce_64_to_32(uint64x2_t data64,
uint64x2_t precomp)
 {
-   static uint32_t mask1[4] __rte_aligned(16) = {
+   static alignas(16) uint32_t mask1[4] = {
0x, 0x, 0x, 0x
};
-   static uint32_t mask2[4] __rte_aligned(16) = {
+   static alignas(16) uint32_t mask2[4] = {
0x, 0x, 0x, 0x
};
uint64x2_t tmp0, tmp1, tmp2;
@@ -148,7 +149,7 @@ struct crc_pmull_ctx {
 
if (unlikely(data_len < 16)) {
/* 0 to 15 bytes */
-   uint8_t buffer[16] __rte_aligned(16);
+   alignas(16) uint8_t buffer[16];
 
memset(buffer, 0, sizeof(buffer));
memcpy(buffer, data, data_len);
diff --git a/lib/net/net_crc_sse.c b/lib/net/net_crc_sse.c
index dd75845..d673ae3 100644
--- a/lib/net/net_crc_sse.c
+++ b/lib/net/net_crc_sse.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2017-2020 Intel Corporation
  */
 
+#include 
 #include 
 
 #include 
@@ -18,8 +19,8 @@ struct crc_pclmulqdq_ctx {
__m128i rk7_rk8;
 };
 
-static struct crc_pclmulqdq_ctx crc32_eth_pclmulqdq __rte_aligned(16);
-static struct crc_pclmulqdq_ctx crc16_ccitt_pclmulqdq __rte_aligned(16);
+static alignas(16) struct crc_pclmulqdq_ctx crc32_e

[PATCH v6 14/39] acl: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/acl/acl_run.h | 4 ++--
 lib/acl/acl_run_altivec.h | 6 --
 lib/acl/acl_run_neon.h| 6 --
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/lib/acl/acl_run.h b/lib/acl/acl_run.h
index 7d215de..7f09241 100644
--- a/lib/acl/acl_run.h
+++ b/lib/acl/acl_run.h
@@ -55,12 +55,12 @@ struct acl_flow_data {
  * Structure to maintain running results for
  * a single packet (up to 4 tries).
  */
-struct completion {
+struct __rte_aligned(XMM_SIZE) completion {
uint32_t *results;  /* running results. */
int32_t   priority[RTE_ACL_MAX_CATEGORIES]; /* running priorities. */
uint32_t  count;/* num of remaining tries */
/* true for allocated struct */
-} __rte_aligned(XMM_SIZE);
+};
 
 /*
  * One parms structure for each slot in the search engine.
diff --git a/lib/acl/acl_run_altivec.h b/lib/acl/acl_run_altivec.h
index 3c30466..2d398ff 100644
--- a/lib/acl/acl_run_altivec.h
+++ b/lib/acl/acl_run_altivec.h
@@ -3,15 +3,17 @@
  * Copyright (C) IBM Corporation 2016.
  */
 
+#include 
+
 #include "acl_run.h"
 #include "acl_vect.h"
 
-struct _altivec_acl_const {
+alignas(RTE_CACHE_LINE_SIZE) struct _altivec_acl_const {
rte_xmm_t xmm_shuffle_input;
rte_xmm_t xmm_index_mask;
rte_xmm_t xmm_ones_16;
rte_xmm_t range_base;
-} altivec_acl_const __rte_cache_aligned = {
+} altivec_acl_const = {
{
.u32 = {0x, 0x04040404, 0x08080808, 0x0c0c0c0c}
},
diff --git a/lib/acl/acl_run_neon.h b/lib/acl/acl_run_neon.h
index 69d1b6d..63074f8 100644
--- a/lib/acl/acl_run_neon.h
+++ b/lib/acl/acl_run_neon.h
@@ -2,14 +2,16 @@
  * Copyright(c) 2015 Cavium, Inc
  */
 
+#include 
+
 #include "acl_run.h"
 #include "acl_vect.h"
 
-struct _neon_acl_const {
+alignas(RTE_CACHE_LINE_SIZE) struct _neon_acl_const {
rte_xmm_t xmm_shuffle_input;
rte_xmm_t xmm_index_mask;
rte_xmm_t range_base;
-} neon_acl_const __rte_cache_aligned = {
+} neon_acl_const = {
{
.u32 = {0x, 0x04040404, 0x08080808, 0x0c0c0c0c}
},
-- 
1.8.3.1

[PATCH v6 11/39] ethdev: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/ethdev/ethdev_driver.h   |  8 
 lib/ethdev/rte_ethdev.h  | 16 
 lib/ethdev/rte_ethdev_core.h |  4 ++--
 lib/ethdev/rte_flow_driver.h |  4 ++--
 4 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h
index 0e4c1f0..bab3a8c 100644
--- a/lib/ethdev/ethdev_driver.h
+++ b/lib/ethdev/ethdev_driver.h
@@ -48,7 +48,7 @@ struct rte_eth_rxtx_callback {
  * memory. This split allows the function pointer and driver data to be per-
  * process, while the actual configuration data for the device is shared.
  */
-struct rte_eth_dev {
+struct __rte_cache_aligned rte_eth_dev {
eth_rx_burst_t rx_pkt_burst; /**< Pointer to PMD receive function */
eth_tx_burst_t tx_pkt_burst; /**< Pointer to PMD transmit function */
 
@@ -93,7 +93,7 @@ struct rte_eth_dev {
 
enum rte_eth_dev_state state; /**< Flag indicating the port state */
void *security_ctx; /**< Context for security ops */
-} __rte_cache_aligned;
+};
 
 struct rte_eth_dev_sriov;
 struct rte_eth_dev_owner;
@@ -104,7 +104,7 @@ struct rte_eth_dev {
  * device. This structure is safe to place in shared memory to be common
  * among different processes in a multi-process configuration.
  */
-struct rte_eth_dev_data {
+struct __rte_cache_aligned rte_eth_dev_data {
char name[RTE_ETH_NAME_MAX_LEN]; /**< Unique identifier name */
 
void **rx_queues; /**< Array of pointers to Rx queues */
@@ -190,7 +190,7 @@ struct rte_eth_dev_data {
uint16_t backer_port_id;
 
pthread_mutex_t flow_ops_mutex; /**< rte_flow ops mutex */
-} __rte_cache_aligned;
+};
 
 /**
  * @internal
diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h
index ed27360..2a92953 100644
--- a/lib/ethdev/rte_ethdev.h
+++ b/lib/ethdev/rte_ethdev.h
@@ -333,12 +333,12 @@ struct rte_eth_stats {
  * A structure used to retrieve link-level information of an Ethernet port.
  */
 __extension__
-struct rte_eth_link {
+struct __rte_aligned(8) rte_eth_link {
uint32_t link_speed;/**< RTE_ETH_SPEED_NUM_ */
uint16_t link_duplex  : 1;  /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */
uint16_t link_autoneg : 1;  /**< RTE_ETH_LINK_[AUTONEG/FIXED] */
uint16_t link_status  : 1;  /**< RTE_ETH_LINK_[DOWN/UP] */
-} __rte_aligned(8);  /**< aligned for atomic64 read/write */
+};  /**< aligned for atomic64 read/write */
 
 /**@{@name Link negotiation
  * Constants used in link management.
@@ -1836,7 +1836,7 @@ struct rte_eth_dev_info {
  * Ethernet device Rx queue information structure.
  * Used to retrieve information about configured queue.
  */
-struct rte_eth_rxq_info {
+struct __rte_cache_min_aligned rte_eth_rxq_info {
struct rte_mempool *mp; /**< mempool used by that queue. */
struct rte_eth_rxconf conf; /**< queue config parameters. */
uint8_t scattered_rx;   /**< scattered packets Rx supported. */
@@ -1850,17 +1850,17 @@ struct rte_eth_rxq_info {
 * Value 0 means that the threshold monitoring is disabled.
 */
uint8_t avail_thresh;
-} __rte_cache_min_aligned;
+};
 
 /**
  * Ethernet device Tx queue information structure.
  * Used to retrieve information about configured queue.
  */
-struct rte_eth_txq_info {
+struct __rte_cache_min_aligned rte_eth_txq_info {
struct rte_eth_txconf conf; /**< queue config parameters. */
uint16_t nb_desc;   /**< configured number of TXDs. */
uint8_t queue_state;/**< one of RTE_ETH_QUEUE_STATE_*. */
-} __rte_cache_min_aligned;
+};
 
 /**
  * @warning
@@ -1870,7 +1870,7 @@ struct rte_eth_txq_info {
  * Used to retrieve Rx queue information when Tx queue reusing mbufs and moving
  * them into Rx mbuf ring.
  */
-struct rte_eth_recycle_rxq_info {
+struct __rte_cache_min_aligned rte_eth_recycle_rxq_info {
struct rte_mbuf **mbuf_ring; /**< mbuf ring of Rx queue. */
struct rte_mempool *m

[PATCH v6 08/39] mbuf: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/mbuf/rte_mbuf_core.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/mbuf/rte_mbuf_core.h b/lib/mbuf/rte_mbuf_core.h
index 5688683..917a811 100644
--- a/lib/mbuf/rte_mbuf_core.h
+++ b/lib/mbuf/rte_mbuf_core.h
@@ -463,7 +463,7 @@ enum {
 /**
  * The generic rte_mbuf, containing a packet mbuf.
  */
-struct rte_mbuf {
+struct __rte_cache_aligned rte_mbuf {
RTE_MARKER cacheline0;
 
void *buf_addr;   /**< Virtual address of segment buffer. */
@@ -476,7 +476,7 @@ struct rte_mbuf {
 * same mbuf cacheline0 layout for 32-bit and 64-bit. This makes
 * working on vector drivers easier.
 */
-   rte_iova_t buf_iova __rte_aligned(sizeof(rte_iova_t));
+   alignas(sizeof(rte_iova_t)) rte_iova_t buf_iova;
 #else
/**
 * Next segment of scattered packet.
@@ -662,7 +662,7 @@ struct rte_mbuf {
uint16_t timesync;
 
uint32_t dynfield1[9]; /**< Reserved for dynamic fields. */
-} __rte_cache_aligned;
+};
 
 /**
  * Function typedef of callback to free externally attached buffer.
-- 
1.8.3.1

[PATCH v6 23/39] port: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/port/rte_port_frag.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/port/rte_port_frag.c b/lib/port/rte_port_frag.c
index 883601a..0940f94 100644
--- a/lib/port/rte_port_frag.c
+++ b/lib/port/rte_port_frag.c
@@ -34,7 +34,7 @@
struct rte_mempool *pool_direct,
struct rte_mempool *pool_indirect);
 
-struct rte_port_ring_reader_frag {
+struct __rte_cache_aligned rte_port_ring_reader_frag {
struct rte_port_in_stats stats;
 
/* Input parameters */
@@ -53,7 +53,7 @@ struct rte_port_ring_reader_frag {
uint32_t pos_frags;
 
frag_op f_frag;
-} __rte_cache_aligned;
+};
 
 static void *
 rte_port_ring_reader_frag_create(void *params, int socket_id, int is_ipv4)
-- 
1.8.3.1

[PATCH v6 12/39] dmadev: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
Acked-by: Chengwen Feng 
---
 lib/dmadev/rte_dmadev_core.h | 4 ++--
 lib/dmadev/rte_dmadev_pmd.h  | 8 
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/lib/dmadev/rte_dmadev_core.h b/lib/dmadev/rte_dmadev_core.h
index e8239c2..29f5251 100644
--- a/lib/dmadev/rte_dmadev_core.h
+++ b/lib/dmadev/rte_dmadev_core.h
@@ -61,7 +61,7 @@ typedef uint16_t (*rte_dma_completed_status_t)(void 
*dev_private,
  * The 'dev_private' field was placed in the first cache line to optimize
  * performance because the PMD mainly depends on this field.
  */
-struct rte_dma_fp_object {
+struct __rte_cache_aligned rte_dma_fp_object {
/** PMD-specific private data. The driver should copy
 * rte_dma_dev.data->dev_private to this field during initialization.
 */
@@ -73,7 +73,7 @@ struct rte_dma_fp_object {
rte_dma_completed_tcompleted;
rte_dma_completed_status_t completed_status;
rte_dma_burst_capacity_t   burst_capacity;
-} __rte_cache_aligned;
+};
 
 extern struct rte_dma_fp_object *rte_dma_fp_objs;
 
diff --git a/lib/dmadev/rte_dmadev_pmd.h b/lib/dmadev/rte_dmadev_pmd.h
index 7f354f6..5872908 100644
--- a/lib/dmadev/rte_dmadev_pmd.h
+++ b/lib/dmadev/rte_dmadev_pmd.h
@@ -94,7 +94,7 @@ struct rte_dma_dev_ops {
  *
  * @see struct rte_dma_dev::data
  */
-struct rte_dma_dev_data {
+struct __rte_cache_aligned rte_dma_dev_data {
char dev_name[RTE_DEV_NAME_MAX_LEN]; /**< Unique identifier name */
int16_t dev_id; /**< Device [external] identifier. */
int16_t numa_node; /**< Local NUMA memory ID. -1 if unknown. */
@@ -103,7 +103,7 @@ struct rte_dma_dev_data {
__extension__
uint8_t dev_started : 1; /**< Device state: STARTED(1)/STOPPED(0). */
uint64_t reserved[2]; /**< Reserved for future fields */
-} __rte_cache_aligned;
+};
 
 /**
  * Possible states of a DMA device.
@@ -122,7 +122,7 @@ enum rte_dma_dev_state {
  * @internal
  * The generic data structure associated with each DMA device.
  */
-struct rte_dma_dev {
+struct __rte_cache_aligned rte_dma_dev {
/** Device info which supplied during device initialization. */
struct rte_device *device;
struct rte_dma_dev_data *data; /**< Pointer to shared device data. */
@@ -132,7 +132,7 @@ struct rte_dma_dev {
const struct rte_dma_dev_ops *dev_ops;
enum rte_dma_dev_state state; /**< Flag indicating the device state. */
uint64_t reserved[2]; /**< Reserved for future fields. */
-} __rte_cache_aligned;
+};
 
 /**
  * @internal
-- 
1.8.3.1

[PATCH v6 13/39] distributor: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/distributor/distributor_private.h | 34 ++
 lib/distributor/rte_distributor.c |  5 +++--
 2 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/lib/distributor/distributor_private.h 
b/lib/distributor/distributor_private.h
index dfeb9b5..07c2c05 100644
--- a/lib/distributor/distributor_private.h
+++ b/lib/distributor/distributor_private.h
@@ -5,6 +5,8 @@
 #ifndef _DIST_PRIV_H_
 #define _DIST_PRIV_H_
 
+#include 
+
 /**
  * @file
  * RTE distributor
@@ -51,10 +53,10 @@
  * the next cache line to worker 0, we pad this out to three cache lines.
  * Only 64-bits of the memory is actually used though.
  */
-union rte_distributor_buffer_single {
+union __rte_cache_aligned rte_distributor_buffer_single {
volatile RTE_ATOMIC(int64_t) bufptr64;
char pad[RTE_CACHE_LINE_SIZE*3];
-} __rte_cache_aligned;
+};
 
 /*
  * Transfer up to 8 mbufs at a time to/from workers, and
@@ -62,12 +64,12 @@
  */
 #define RTE_DIST_BURST_SIZE 8
 
-struct rte_distributor_backlog {
+struct __rte_cache_aligned rte_distributor_backlog {
unsigned int start;
unsigned int count;
-   int64_t pkts[RTE_DIST_BURST_SIZE] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) int64_t pkts[RTE_DIST_BURST_SIZE];
uint16_t *tags; /* will point to second cacheline of inflights */
-} __rte_cache_aligned;
+};
 
 
 struct rte_distributor_returned_pkts {
@@ -113,17 +115,17 @@ enum rte_distributor_match_function {
  * There is a separate cacheline for returns in the burst API.
  */
 struct rte_distributor_buffer {
-   volatile RTE_ATOMIC(int64_t) bufptr64[RTE_DIST_BURST_SIZE]
-   __rte_cache_aligned; /* <= outgoing to worker */
+   volatile alignas(RTE_CACHE_LINE_SIZE) RTE_ATOMIC(int64_t) 
bufptr64[RTE_DIST_BURST_SIZE];
+   /* <= outgoing to worker */
 
-   int64_t pad1 __rte_cache_aligned;/* <= one cache line  */
+   alignas(RTE_CACHE_LINE_SIZE) int64_t pad1;/* <= one cache line  */
 
-   volatile RTE_ATOMIC(int64_t) retptr64[RTE_DIST_BURST_SIZE]
-   __rte_cache_aligned; /* <= incoming from worker */
+   volatile alignas(RTE_CACHE_LINE_SIZE) RTE_ATOMIC(int64_t) 
retptr64[RTE_DIST_BURST_SIZE];
+   /* <= incoming from worker */
 
-   int64_t pad2 __rte_cache_aligned;/* <= one cache line  */
+   alignas(RTE_CACHE_LINE_SIZE) int64_t pad2;/* <= one cache line  */
 
-   int count __rte_cache_aligned;   /* <= number of current mbufs */
+   alignas(RTE_CACHE_LINE_SIZE) int count;   /* <= number of current 
mbufs */
 };
 
 struct rte_distributor {
@@ -138,11 +140,11 @@ struct rte_distributor {
 * on the worker core. Second cache line are the backlog
 * that are going to go to the worker core.
 */
-   uint16_t in_flight_tags[RTE_DISTRIB_MAX_WORKERS][RTE_DIST_BURST_SIZE*2]
-   __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint16_t
+   in_flight_tags[RTE_DISTRIB_MAX_WORKERS][RTE_DIST_BURST_SIZE*2];
 
-   struct rte_distributor_backlog backlog[RTE_DISTRIB_MAX_WORKERS]
-   __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) struct rte_distributor_backlog
+   backlog[RTE_DISTRIB_MAX_WORKERS];
 
struct rte_distributor_buffer bufs[RTE_DISTRIB_MAX_WORKERS];
 
diff --git a/lib/distributor/rte_distributor.c 
b/lib/distributor/rte_distributor.c
index e842dc9..e58727c 100644
--- a/lib/distributor/rte_distributor.c
+++ b/lib/distributor/rte_distributor.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2017 Intel Corporation
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -447,7 +448,7 @@
struct rte_mbuf *next_mb = NULL;
int64_t next_value = 0;
uint16_t new_tag = 0;
-   uint16_t flows[RTE_DIST_BURST_SIZE] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint16_t flows[RTE_DIST_BURST_SIZE];
unsigned int i, j, w,

[PATCH v6 16/39] timer: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/timer/rte_timer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/timer/rte_timer.c b/lib/timer/rte_timer.c
index 53ed221..bb8b6a6 100644
--- a/lib/timer/rte_timer.c
+++ b/lib/timer/rte_timer.c
@@ -24,7 +24,7 @@
 /**
  * Per-lcore info for timers.
  */
-struct priv_timer {
+struct __rte_cache_aligned priv_timer {
struct rte_timer pending_head;  /**< dummy timer instance to head up 
list */
rte_spinlock_t list_lock;   /**< lock to protect list access */
 
@@ -44,7 +44,7 @@ struct priv_timer {
/** per-lcore statistics */
struct rte_timer_debug_stats stats;
 #endif
-} __rte_cache_aligned;
+};
 
 #define FL_ALLOCATED   (1 << 0)
 struct rte_timer_data {
-- 
1.8.3.1

[PATCH v6 17/39] table: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/table/rte_swx_table_learner.c | 4 ++--
 lib/table/rte_table_acl.c | 3 ++-
 lib/table/rte_table_array.c   | 7 ---
 lib/table/rte_table_hash_cuckoo.c | 4 +++-
 lib/table/rte_table_hash_ext.c| 3 ++-
 lib/table/rte_table_hash_key16.c  | 4 +++-
 lib/table/rte_table_hash_key32.c  | 4 +++-
 lib/table/rte_table_hash_key8.c   | 4 +++-
 lib/table/rte_table_hash_lru.c| 3 ++-
 lib/table/rte_table_lpm.c | 3 ++-
 lib/table/rte_table_lpm_ipv6.c| 3 ++-
 11 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/lib/table/rte_swx_table_learner.c 
b/lib/table/rte_swx_table_learner.c
index 2b5e6bd..55a3645 100644
--- a/lib/table/rte_swx_table_learner.c
+++ b/lib/table/rte_swx_table_learner.c
@@ -145,13 +145,13 @@ struct table_params {
size_t total_size;
 };
 
-struct table {
+struct __rte_cache_aligned table {
/* Table parameters. */
struct table_params params;
 
/* Table buckets. */
uint8_t buckets[];
-} __rte_cache_aligned;
+};
 
 /* The timeout (in cycles) is stored in the table as a 32-bit value by 
truncating its least
  * significant 32 bits. Therefore, to make sure the time is always advancing 
when adding the timeout
diff --git a/lib/table/rte_table_acl.c b/lib/table/rte_table_acl.c
index 83411d2..2764cda 100644
--- a/lib/table/rte_table_acl.c
+++ b/lib/table/rte_table_acl.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2010-2014 Intel Corporation
  */
 
+#include 
 #include 
 #include 
 
@@ -47,7 +48,7 @@ struct rte_table_acl {
uint8_t *acl_rule_memory; /* Memory to store the rules */
 
/* Memory to store the action table and stack of free entries */
-   uint8_t memory[0] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint8_t memory[0];
 };
 
 
diff --git a/lib/table/rte_table_array.c b/lib/table/rte_table_array.c
index 80bc2a7..31a17d5 100644
--- a/lib/table/rte_table_array.c
+++ b/lib/table/rte_table_array.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2010-2014 Intel Corporation
  */
 
+#include 
 #include 
 #include 
 
@@ -27,7 +28,7 @@
 
 #endif
 
-struct rte_table_array {
+struct __rte_cache_aligned rte_table_array {
struct rte_table_stats stats;
 
/* Input parameters */
@@ -39,8 +40,8 @@ struct rte_table_array {
uint32_t entry_pos_mask;
 
/* Internal table */
-   uint8_t array[0] __rte_cache_aligned;
-} __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint8_t array[0];
+};
 
 static void *
 rte_table_array_create(void *params, int socket_id, uint32_t entry_size)
diff --git a/lib/table/rte_table_hash_cuckoo.c 
b/lib/table/rte_table_hash_cuckoo.c
index 0f4900c..d3b60f3 100644
--- a/lib/table/rte_table_hash_cuckoo.c
+++ b/lib/table/rte_table_hash_cuckoo.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2010-2017 Intel Corporation
  */
+
+#include 
 #include 
 #include 
 
@@ -42,7 +44,7 @@ struct rte_table_hash {
struct rte_hash *h_table;
 
/* Lookup table */
-   uint8_t memory[0] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint8_t memory[0];
 };
 
 static int
diff --git a/lib/table/rte_table_hash_ext.c b/lib/table/rte_table_hash_ext.c
index 2148d83..61e3c79 100644
--- a/lib/table/rte_table_hash_ext.c
+++ b/lib/table/rte_table_hash_ext.c
@@ -2,6 +2,7 @@
  * Copyright(c) 2010-2017 Intel Corporation
  */
 
+#include 
 #include 
 #include 
 
@@ -99,7 +100,7 @@ struct rte_table_hash {
uint32_t *bkt_ext_stack;
 
/* Table memory */
-   uint8_t memory[0] __rte_cache_aligned;
+   alignas(RTE_CACHE_LINE_SIZE) uint8_t memory[0];
 };
 
 static int
diff --git a/lib/table/rte_table_hash_key16.c b/lib/table/rte_table_hash_key16.c
index 7734aef..2af34a5 100644
--- a/lib/table/rte_table_hash_key16.c
+++ b/lib/table/rte_table_hash_key16.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2010-2017 Intel Corporation
  */
+
+#include 
 #include 
 #include 
 
@@ -83,7 +85,7 @@ 

[PATCH v6 19/39] regexdev: use C11 alignas

[Tyler Retzlaff]

The current location used for __rte_aligned(a) for alignment of types
and variables is not compatible with MSVC. There is only a single
location accepted by both toolchains.

For variables standard C11 offers alignas(a) supported by conformant
compilers i.e. both MSVC and GCC.

For types the standard offers no alignment facility that compatibly
interoperates with C and C++ but may be achieved by relocating the
placement of __rte_aligned(a) to the aforementioned location accepted
by all currently supported toolchains.

To allow alignment for both compilers do the following:

* Move __rte_aligned from the end of {struct,union} definitions to
  be between {struct,union} and tag.

  The placement between {struct,union} and the tag allows the desired
  alignment to be imparted on the type regardless of the toolchain being
  used for all of GCC, LLVM, MSVC compilers building both C and C++.

* Replace use of __rte_aligned(a) on variables/fields with alignas(a).

Signed-off-by: Tyler Retzlaff 
Acked-by: Morten Brørup 
---
 lib/regexdev/rte_regexdev_core.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/lib/regexdev/rte_regexdev_core.h b/lib/regexdev/rte_regexdev_core.h
index 15ba712..32eef6e 100644
--- a/lib/regexdev/rte_regexdev_core.h
+++ b/lib/regexdev/rte_regexdev_core.h
@@ -144,13 +144,13 @@ enum rte_regexdev_state {
  * This structure is safe to place in shared memory to be common among 
different
  * processes in a multi-process configuration.
  */
-struct rte_regexdev_data {
+struct __rte_cache_aligned rte_regexdev_data {
void *dev_private; /**< PMD-specific private data. */
char dev_name[RTE_REGEXDEV_NAME_MAX_LEN]; /**< Unique identifier name */
uint16_t dev_id; /**< Device [external]  identifier. */
struct rte_regexdev_config dev_conf; /**< RegEx configuration. */
uint8_t dev_started : 1; /**< Device started to work. */
-} __rte_cache_aligned;
+};
 
 /**
  * @internal
@@ -162,7 +162,7 @@ struct rte_regexdev_data {
  * memory. This split allows the function pointer and driver data to be per-
  * process, while the actual configuration data for the device is shared.
  */
-struct rte_regexdev {
+struct __rte_cache_aligned rte_regexdev {
regexdev_enqueue_t enqueue;
regexdev_dequeue_t dequeue;
const struct rte_regexdev_ops *dev_ops;
@@ -170,7 +170,7 @@ struct rte_regexdev {
struct rte_device *device; /**< Backing device */
enum rte_regexdev_state state; /**< The device state. */
struct rte_regexdev_data *data;  /**< Pointer to device data. */
-} __rte_cache_aligned;
+};
 
 /**
  * @internal
-- 
1.8.3.1