Re: [PATCH v5 1/3] eal: add basic thread ID and current thread identifier API

[Tyler Retzlaff]

On Wed, May 04, 2022 at 11:55:57PM +0100, Konstantin Ananyev wrote:
> 04/05/2022 16:46, Tyler Retzlaff пишет:
> >Provide a portable type-safe thread identifier.
> >Provide rte_thread_self for obtaining current thread identifier.
> >
> >Signed-off-by: Narcisa Vasile 
> >Signed-off-by: Tyler Retzlaff 
> >Acked-by: Dmitry Kozlyuk 
> >---
> >  lib/eal/include/rte_thread.h | 22 ++
> >  lib/eal/unix/rte_thread.c| 11 +++
> >  lib/eal/version.map  |  3 +++
> >  lib/eal/windows/rte_thread.c | 10 ++
> >  4 files changed, 46 insertions(+)
> >
> >diff --git a/lib/eal/include/rte_thread.h b/lib/eal/include/rte_thread.h
> >index 8be8ed8..14478ba 100644
> >--- a/lib/eal/include/rte_thread.h
> >+++ b/lib/eal/include/rte_thread.h
> >@@ -1,7 +1,10 @@
> >  /* SPDX-License-Identifier: BSD-3-Clause
> >   * Copyright(c) 2021 Mellanox Technologies, Ltd
> >+ * Copyright (C) 2022 Microsoft Corporation
> >   */
> >+#include 
> >+
> >  #include 
> >  #include 
> >@@ -21,10 +24,29 @@
> >  #endif
> >  /**
> >+ * Thread id descriptor.
> >+ */
> >+typedef struct {
> >+uintptr_t opaque_id; /**< thread identifier */
> 
> 
> I know that currently on linux typeof(pthread_id) == unsigned long int.
> Though wouldn't it be safer and cleaner to use pthread_t explicitly
> on posix-like systems?

i believe the previous discussions are.

* preference for reduced or no conditional compilation.
* preference for sizeof(type) to be `the same' on all platforms.
* preference for platform agnostic headers. i.e. don't drag
  platform specific headers into the application namespace when
  including rte_xxx.h headers.

> Something like:
> typedef struct {
> #ifdef WINDOWS
>   uintptr_t opaque_id;
> #else
>   pthread_t opaque_id;
> #endif
> };
> AFAIK POSIX itself doesn't require pthread_t to be an 'arithmetic type'.

yes, this is correct. newer posix introduced this to allow the use of
structs. i assume prior reviewers are aware of the recent posix
standard (or should be).

this type makes no attempt to be usable on platforms that use
a handle > sizeof(uintptr_t). though any platform that does is free
to shove a pointer to struct into the handle at the cost of a
dereference if that is their implementation.

> 
> 
> >+} rte_thread_t;
> >+
> >+/**
> >   * TLS key type, an opaque pointer.
> >   */
> >  typedef struct eal_tls_key *rte_thread_key;
> >+/**
> >+ * @warning
> >+ * @b EXPERIMENTAL: this API may change without prior notice.
> >+ *
> >+ * Get the id of the calling thread.
> >+ *
> >+ * @return
> >+ *   Return the thread id of the calling thread.
> >+ */
> >+__rte_experimental
> >+rte_thread_t rte_thread_self(void);
> >+
> >  #ifdef RTE_HAS_CPUSET
> >  /**
> >diff --git a/lib/eal/unix/rte_thread.c b/lib/eal/unix/rte_thread.c
> >index c34ede9..82e008f 100644
> >--- a/lib/eal/unix/rte_thread.c
> >+++ b/lib/eal/unix/rte_thread.c
> >@@ -1,5 +1,6 @@
> >  /* SPDX-License-Identifier: BSD-3-Clause
> >   * Copyright 2021 Mellanox Technologies, Ltd
> >+ * Copyright (C) 2022 Microsoft Corporation
> >   */
> >  #include 
> >@@ -15,6 +16,16 @@ struct eal_tls_key {
> > pthread_key_t thread_index;
> >  };
> >+rte_thread_t
> >+rte_thread_self(void)
> >+{
> >+rte_thread_t thread_id;
> >+
> >+thread_id.opaque_id = (uintptr_t)pthread_self();
> >+
> >+return thread_id;
> >+}
> >+
> >  int
> >  rte_thread_key_create(rte_thread_key *key, void (*destructor)(void *))
> >  {
> >diff --git a/lib/eal/version.map b/lib/eal/version.map
> >index b53eeb3..05ce8f9 100644
> >--- a/lib/eal/version.map
> >+++ b/lib/eal/version.map
> >@@ -420,6 +420,9 @@ EXPERIMENTAL {
> > rte_intr_instance_free;
> > rte_intr_type_get;
> > rte_intr_type_set;
> >+
> >+# added in 22.07
> >+rte_thread_self;
> >  };
> >  INTERNAL {
> >diff --git a/lib/eal/windows/rte_thread.c b/lib/eal/windows/rte_thread.c
> >index 667287c..59fed3c 100644
> >--- a/lib/eal/windows/rte_thread.c
> >+++ b/lib/eal/windows/rte_thread.c
> >@@ -11,6 +11,16 @@ struct eal_tls_key {
> > DWORD thread_index;
> >  };
> >+rte_thread_t
> >+rte_thread_self(void)
> >+{
> >+rte_thread_t thread_id;
> >+
> >+thread_id.opaque_id = GetCurrentThreadId();
> >+
> >+return thread_id;
> >+}
> >+
> >  int
> >  rte_thread_key_create(rte_thread_key *key,
> > __rte_unused void (*destructor)(void *))

Re: [PATCH] vhost: fix deadlock when handling user messages

[David Marchand]

Hello,

On Thu, May 5, 2022 at 7:42 AM Wenwu Ma  wrote:
>
> In vhost_user_msg_handler(), if vhost message handling
> failed, we should check whether the queue is locked and
> release the lock before returning. Or, it will cause a
> deadlock later.

Fixes: 7f31d4ea05ca ("vhost: fix lock on device readiness notification")
Cc: sta...@dpdk.org

>
> Signed-off-by: Wenwu Ma 
> ---
>  lib/vhost/vhost_user.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/lib/vhost/vhost_user.c b/lib/vhost/vhost_user.c
> index 1d390677fa..80a5df6e9d 100644
> --- a/lib/vhost/vhost_user.c
> +++ b/lib/vhost/vhost_user.c
> @@ -3113,6 +3113,8 @@ vhost_user_msg_handler(int vid, int fd)
> send_vhost_reply(dev, fd, &ctx);
> } else if (ret == RTE_VHOST_MSG_RESULT_ERR) {
> VHOST_LOG_CONFIG(ERR, "(%s) vhost message handling 
> failed.\n", dev->ifname);
> +   if (unlock_required)
> +   vhost_user_unlock_all_queue_pairs(dev);
> return -1;
> }
>

This fixes the issue, but my concern is that changes in the future
might introduce a new return statement (forgetting to unlock).
I suggest having a single return statement, like:

diff --git a/lib/vhost/vhost_user.c b/lib/vhost/vhost_user.c
index 1d390677fa..4baf969ee0 100644
--- a/lib/vhost/vhost_user.c
+++ b/lib/vhost/vhost_user.c
@@ -2976,7 +2976,6 @@ vhost_user_msg_handler(int vid, int fd)
return -1;
}

-   ret = 0;
request = ctx.msg.request.master;
if (request > VHOST_USER_NONE && request < VHOST_USER_MAX &&
vhost_message_str[request]) {
@@ -3113,9 +3112,11 @@ vhost_user_msg_handler(int vid, int fd)
send_vhost_reply(dev, fd, &ctx);
} else if (ret == RTE_VHOST_MSG_RESULT_ERR) {
VHOST_LOG_CONFIG(ERR, "(%s) vhost message handling
failed.\n", dev->ifname);
-   return -1;
+   ret = -1;
+   goto unlock;
}

+   ret = 0;
for (i = 0; i < dev->nr_vring; i++) {
struct vhost_virtqueue *vq = dev->virtqueue[i];
bool cur_ready = vq_is_ready(dev, vq);
@@ -3126,10 +3127,11 @@ vhost_user_msg_handler(int vid, int fd)
}
}

+unlock:
if (unlock_required)
vhost_user_unlock_all_queue_pairs(dev);

-   if (!virtio_is_ready(dev))
+   if (ret != 0 || !virtio_is_ready(dev))
goto out;

/*
@@ -3156,7 +3158,7 @@ vhost_user_msg_handler(int vid, int fd)
}

 out:
-   return 0;
+   return ret;
 }

 static int process_slave_message_reply(struct virtio_net *dev,


-- 
David Marchand

[PATCH v2 0/6] move DPAA2 QDMA driver freom raw to dma

[nipun . gupta]

From: Nipun Gupta 

This change removes the DPAA2 QDMA raw driver and adds the
QDMA driver in dma set of drivers. The underlying I/O
framework remains intact, whereas the configuration part
is done as per the DMA API support.

Changes in v2:
- Fix checkpath errors
- Fix documentation compilation

Nipun Gupta (6):
  raw/dpaa2_qdma: remove dpaa2 QDMA driver from raw
  dma/dpaa2: introduce DPAA2 DMA driver skeleton
  dma/dpaa2: support basic operations
  dma/dpaa2: add PMD apis for additional configuration
  dma/dpaa2: support DMA operations
  dma/dpaa2: support statistics

 MAINTAINERS   |   11 +-
 doc/api/doxy-api.conf.in  |2 +-
 doc/guides/rawdevs/dpaa2_qdma.rst |   74 -
 drivers/bus/fslmc/rte_fslmc.h |1 +
 .../dpaa2_qdma => dma/dpaa2}/dpaa2_qdma.c | 1248 -
 .../dpaa2_qdma => dma/dpaa2}/dpaa2_qdma.h |  195 ++-
 .../dpaa2}/dpaa2_qdma_logs.h  |2 +-
 drivers/dma/dpaa2/meson.build |   18 +
 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h|  173 +++
 drivers/dma/dpaa2/version.map |   11 +
 drivers/dma/meson.build   |1 +
 drivers/raw/dpaa2_qdma/meson.build|7 -
 drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h   |  204 ---
 drivers/raw/dpaa2_qdma/version.map|7 -
 drivers/raw/meson.build   |1 -
 15 files changed, 852 insertions(+), 1103 deletions(-)
 delete mode 100644 doc/guides/rawdevs/dpaa2_qdma.rst
 rename drivers/{raw/dpaa2_qdma => dma/dpaa2}/dpaa2_qdma.c (57%)
 rename drivers/{raw/dpaa2_qdma => dma/dpaa2}/dpaa2_qdma.h (77%)
 rename drivers/{raw/dpaa2_qdma => dma/dpaa2}/dpaa2_qdma_logs.h (97%)
 create mode 100644 drivers/dma/dpaa2/meson.build
 create mode 100644 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h
 create mode 100644 drivers/dma/dpaa2/version.map
 delete mode 100644 drivers/raw/dpaa2_qdma/meson.build
 delete mode 100644 drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h
 delete mode 100644 drivers/raw/dpaa2_qdma/version.map

-- 
2.17.1

[PATCH v2 1/6] raw/dpaa2_qdma: remove dpaa2 QDMA driver from raw

[nipun . gupta]

From: Nipun Gupta 

With DMA devices supported as a separate flavor of devices,
the DPAA2 QDMA driver is moved in the DMA devices.

This change removes the DPAA2 QDMA driver from raw devices.

Signed-off-by: Nipun Gupta 
---
 MAINTAINERS |5 -
 doc/api/doxy-api-index.md   |1 -
 doc/api/doxy-api.conf.in|1 -
 doc/guides/rawdevs/dpaa2_qdma.rst   |   74 -
 drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 1834 ---
 drivers/raw/dpaa2_qdma/dpaa2_qdma.h |  288 ---
 drivers/raw/dpaa2_qdma/dpaa2_qdma_logs.h|   46 -
 drivers/raw/dpaa2_qdma/meson.build  |7 -
 drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h |  204 ---
 drivers/raw/dpaa2_qdma/version.map  |7 -
 drivers/raw/meson.build |1 -
 11 files changed, 2468 deletions(-)
 delete mode 100644 doc/guides/rawdevs/dpaa2_qdma.rst
 delete mode 100644 drivers/raw/dpaa2_qdma/dpaa2_qdma.c
 delete mode 100644 drivers/raw/dpaa2_qdma/dpaa2_qdma.h
 delete mode 100644 drivers/raw/dpaa2_qdma/dpaa2_qdma_logs.h
 delete mode 100644 drivers/raw/dpaa2_qdma/meson.build
 delete mode 100644 drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h
 delete mode 100644 drivers/raw/dpaa2_qdma/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 7c4f541dba..e67215f490 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1379,11 +1379,6 @@ M: Nipun Gupta 
 F: drivers/raw/dpaa2_cmdif/
 F: doc/guides/rawdevs/dpaa2_cmdif.rst
 
-NXP DPAA2 QDMA
-M: Nipun Gupta 
-F: drivers/raw/dpaa2_qdma/
-F: doc/guides/rawdevs/dpaa2_qdma.rst
-
 
 Packet processing
 -
diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md
index 4245b9635c..6c1ca981bc 100644
--- a/doc/api/doxy-api-index.md
+++ b/doc/api/doxy-api-index.md
@@ -53,7 +53,6 @@ The public API headers are grouped by topics:
   [mlx5]   (@ref rte_pmd_mlx5.h),
   [dpaa2_mempool]  (@ref rte_dpaa2_mempool.h),
   [dpaa2_cmdif](@ref rte_pmd_dpaa2_cmdif.h),
-  [dpaa2_qdma] (@ref rte_pmd_dpaa2_qdma.h),
   [crypto_scheduler]   (@ref rte_cryptodev_scheduler.h),
   [dlb2]   (@ref rte_pmd_dlb2.h),
   [ifpga]  (@ref rte_pmd_ifpga.h)
diff --git a/doc/api/doxy-api.conf.in b/doc/api/doxy-api.conf.in
index db2ca9b6ed..a73aac2410 100644
--- a/doc/api/doxy-api.conf.in
+++ b/doc/api/doxy-api.conf.in
@@ -21,7 +21,6 @@ INPUT   = @TOPDIR@/doc/api/doxy-api-index.md \
   @TOPDIR@/drivers/net/mlx5 \
   @TOPDIR@/drivers/net/softnic \
   @TOPDIR@/drivers/raw/dpaa2_cmdif \
-  @TOPDIR@/drivers/raw/dpaa2_qdma \
   @TOPDIR@/drivers/raw/ifpga \
   @TOPDIR@/drivers/raw/ioat \
   @TOPDIR@/lib/eal/include \
diff --git a/doc/guides/rawdevs/dpaa2_qdma.rst 
b/doc/guides/rawdevs/dpaa2_qdma.rst
deleted file mode 100644
index 1b619ea1e1..00
--- a/doc/guides/rawdevs/dpaa2_qdma.rst
+++ /dev/null
@@ -1,74 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-Copyright 2018 NXP
-
-NXP DPAA2 QDMA Driver
-=
-
-The DPAA2 QDMA is an implementation of the rawdev API, that provide means
-to initiate a DMA transaction from CPU. The initiated DMA is performed
-without CPU being involved in the actual DMA transaction. This is achieved
-via using the DPDMAI device exposed by MC.
-
-More information can be found at `NXP Official Website
-`_.
-
-Features
-
-
-The DPAA2 QDMA implements following features in the rawdev API;
-
-- Supports issuing DMA of data within memory without hogging CPU while
-  performing DMA operation.
-- Supports configuring to optionally get status of the DMA translation on
-  per DMA operation basis.
-
-Supported DPAA2 SoCs
-
-
-- LX2160A
-- LS2084A/LS2044A
-- LS2088A/LS2048A
-- LS1088A/LS1048A
-
-Prerequisites
--
-
-See :doc:`../platform/dpaa2` for setup information
-
-- Follow the DPDK :ref:`Getting Started Guide for Linux ` to setup 
the basic DPDK environment.
-
-.. note::
-
-   Some part of fslmc bus code (mc flib - object library) routines are
-   dual licensed (BSD & GPLv2).
-
-
-Enabling logs
--
-
-For enabling logs, use the following EAL parameter:
-
-.. code-block:: console
-
-   ./your_qdma_application  --log-level=pmd.raw.dpaa2.qdma,
-
-Using ``pmd.raw.dpaa2.qdma`` as log matching criteria, all Event PMD logs can 
be
-enabled which are lower than logging ``level``.
-
-
-Initialization
---
-
-The DPAA2 QDMA is exposed as a vdev device which consists of dpdmai devices.
-On EAL initialization, dpdmai devices will be probed and populated into the
-rawdevices. The rawdev ID of the device can be obtained using
-
-* Invoking ``rte_rawdev_get_dev_id("dpdmai.x")`` from the application
-  

[PATCH v2 2/6] dma/dpaa2: introduce DPAA2 DMA driver skeleton

[nipun . gupta]

From: Nipun Gupta 

The DPAA2 DMA driver is an implementation of the dmadev APIs,
that provide means to initiate a DMA transaction from CPU.
Earlier this was part of RAW driver, but with DMA drivers
added as separate flavor of drivers, this driver is being
moved to DMA drivers.

Signed-off-by: Nipun Gupta 
---
 MAINTAINERS |   6 +
 drivers/bus/fslmc/rte_fslmc.h   |   1 +
 drivers/dma/dpaa2/dpaa2_qdma.c  | 275 
 drivers/dma/dpaa2/dpaa2_qdma.h  | 316 
 drivers/dma/dpaa2/dpaa2_qdma_logs.h |  46 
 drivers/dma/dpaa2/meson.build   |  16 ++
 drivers/dma/dpaa2/version.map   |   3 +
 drivers/dma/meson.build |   1 +
 8 files changed, 664 insertions(+)
 create mode 100644 drivers/dma/dpaa2/dpaa2_qdma.c
 create mode 100644 drivers/dma/dpaa2/dpaa2_qdma.h
 create mode 100644 drivers/dma/dpaa2/dpaa2_qdma_logs.h
 create mode 100644 drivers/dma/dpaa2/meson.build
 create mode 100644 drivers/dma/dpaa2/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index e67215f490..432ca49fb3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1198,6 +1198,12 @@ M: Nipun Gupta 
 F: drivers/dma/dpaa/
 F: doc/guides/dmadevs/dpaa.rst
 
+NXP DPAA2 QDMA
+M: Nipun Gupta 
+M: Hemant Agrawal 
+F: drivers/dma/dpaa2_qdma/
+F: doc/guides/dmadevs/dpaa2_qdma.rst
+
 
 RegEx Drivers
 -
diff --git a/drivers/bus/fslmc/rte_fslmc.h b/drivers/bus/fslmc/rte_fslmc.h
index 12b586b13b..8c67bfba55 100644
--- a/drivers/bus/fslmc/rte_fslmc.h
+++ b/drivers/bus/fslmc/rte_fslmc.h
@@ -123,6 +123,7 @@ struct rte_dpaa2_device {
union {
struct rte_eth_dev *eth_dev;/**< ethernet device */
struct rte_cryptodev *cryptodev;/**< Crypto Device */
+   struct rte_dma_dev *dmadev;  /**< DMA Device */
struct rte_rawdev *rawdev;  /**< Raw Device */
};
enum rte_dpaa2_dev_type dev_type;   /**< Device Type */
diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c
new file mode 100644
index 00..9fa48ddfa4
--- /dev/null
+++ b/drivers/dma/dpaa2/dpaa2_qdma.c
@@ -0,0 +1,275 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2018-2022 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "dpaa2_qdma.h"
+#include "dpaa2_qdma_logs.h"
+/* Dynamic log type identifier */
+int dpaa2_qdma_logtype;
+
+uint32_t dpaa2_coherent_no_alloc_cache;
+uint32_t dpaa2_coherent_alloc_cache;
+
+static int
+dpaa2_qdma_reset(struct rte_dma_dev *dev)
+{
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dev->data->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+   int i;
+
+   DPAA2_QDMA_FUNC_TRACE();
+
+   /* In case QDMA device is not in stopped state, return -EBUSY */
+   if (qdma_dev->state == 1) {
+   DPAA2_QDMA_ERR(
+   "Device is in running state. Stop before reset.");
+   return -EBUSY;
+   }
+
+   /* In case there are pending jobs on any VQ, return -EBUSY */
+   for (i = 0; i < qdma_dev->num_vqs; i++) {
+   if (qdma_dev->vqs[i].in_use && (qdma_dev->vqs[i].num_enqueues !=
+   qdma_dev->vqs[i].num_dequeues)) {
+   DPAA2_QDMA_ERR("Jobs are still pending on VQ: %d", i);
+   return -EBUSY;
+   }
+   }
+
+   /* Reset and free virtual queues */
+   for (i = 0; i < qdma_dev->num_vqs; i++) {
+   if (qdma_dev->vqs[i].status_ring)
+   rte_ring_free(qdma_dev->vqs[i].status_ring);
+   }
+   if (qdma_dev->vqs)
+   rte_free(qdma_dev->vqs);
+   qdma_dev->vqs = NULL;
+
+   /* Reset QDMA device structure */
+   qdma_dev->num_vqs = 0;
+
+   return 0;
+}
+
+static struct rte_dma_dev_ops dpaa2_qdma_ops = {
+};
+
+static int
+dpaa2_dpdmai_dev_uninit(struct rte_dma_dev *dev)
+{
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dev->data->dev_private;
+   int ret;
+
+   DPAA2_QDMA_FUNC_TRACE();
+
+   ret = dpdmai_disable(&dpdmai_dev->dpdmai, CMD_PRI_LOW,
+dpdmai_dev->token);
+   if (ret)
+   DPAA2_QDMA_ERR("dmdmai disable failed");
+
+   /* Set up the DQRR storage for Rx */
+   struct dpaa2_queue *rxq = &(dpdmai_dev->rx_queue[0]);
+
+   if (rxq->q_storage) {
+   dpaa2_free_dq_storage(rxq->q_storage);
+   rte_free(rxq->q_storage);
+   }
+
+   /* Close the device at underlying layer*/
+   ret = dpdmai_close(&dpdmai_dev->dpdmai, CMD_PRI_LOW, dpdmai_dev->token);
+   if (ret)
+   DPAA2_QDMA_ERR("Failure closing dpdmai device");
+
+   return 0;
+}
+
+static int
+dpaa2_dpdmai_dev_init(struct rte_dma_dev *dev, int dpdmai_id)
+{
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dev->data->dev_private;
+   struct dpdmai_rx_queue_cfg rx_queue_cfg;
+   struct dpdmai_attr attr;
+  

[PATCH v2 3/6] dma/dpaa2: support basic operations

[nipun . gupta]

From: Nipun Gupta 

This patch support basic DMA operations which includes
device capability and channel setup.

Signed-off-by: Nipun Gupta 
---
 drivers/dma/dpaa2/dpaa2_qdma.c | 182 +
 1 file changed, 182 insertions(+)

diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c
index 9fa48ddfa4..785d8aea7b 100644
--- a/drivers/dma/dpaa2/dpaa2_qdma.c
+++ b/drivers/dma/dpaa2/dpaa2_qdma.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "dpaa2_qdma.h"
 #include "dpaa2_qdma_logs.h"
@@ -15,6 +16,171 @@ int dpaa2_qdma_logtype;
 uint32_t dpaa2_coherent_no_alloc_cache;
 uint32_t dpaa2_coherent_alloc_cache;
 
+static int
+dpaa2_qdma_info_get(const struct rte_dma_dev *dev,
+   struct rte_dma_info *dev_info,
+   uint32_t info_sz)
+{
+   RTE_SET_USED(dev);
+   RTE_SET_USED(info_sz);
+
+   dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
+RTE_DMA_CAPA_MEM_TO_DEV |
+RTE_DMA_CAPA_DEV_TO_DEV |
+RTE_DMA_CAPA_DEV_TO_MEM |
+RTE_DMA_CAPA_SILENT |
+RTE_DMA_CAPA_OPS_COPY;
+   dev_info->max_vchans = DPAA2_QDMA_MAX_VHANS;
+   dev_info->max_desc = DPAA2_QDMA_MAX_DESC;
+   dev_info->min_desc = DPAA2_QDMA_MIN_DESC;
+
+   return 0;
+}
+
+static int
+dpaa2_qdma_configure(struct rte_dma_dev *dev,
+const struct rte_dma_conf *dev_conf,
+uint32_t conf_sz)
+{
+   char name[32]; /* RTE_MEMZONE_NAMESIZE = 32 */
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dev->data->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+
+   DPAA2_QDMA_FUNC_TRACE();
+
+   RTE_SET_USED(conf_sz);
+
+   /* In case QDMA device is not in stopped state, return -EBUSY */
+   if (qdma_dev->state == 1) {
+   DPAA2_QDMA_ERR(
+   "Device is in running state. Stop before config.");
+   return -1;
+   }
+
+   /* Allocate Virtual Queues */
+   sprintf(name, "qdma_%d_vq", dev->data->dev_id);
+   qdma_dev->vqs = rte_malloc(name,
+   (sizeof(struct qdma_virt_queue) * dev_conf->nb_vchans),
+   RTE_CACHE_LINE_SIZE);
+   if (!qdma_dev->vqs) {
+   DPAA2_QDMA_ERR("qdma_virtual_queues allocation failed");
+   return -ENOMEM;
+   }
+   qdma_dev->num_vqs = dev_conf->nb_vchans;
+
+   return 0;
+}
+
+static int
+dpaa2_qdma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
+  const struct rte_dma_vchan_conf *conf,
+  uint32_t conf_sz)
+{
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dev->data->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+   uint32_t pool_size;
+   char ring_name[32];
+   char pool_name[64];
+   int fd_long_format = 1;
+   int sg_enable = 0;
+
+   DPAA2_QDMA_FUNC_TRACE();
+
+   RTE_SET_USED(conf_sz);
+
+   if (qdma_dev->vqs[vchan].flags & DPAA2_QDMA_VQ_FD_SG_FORMAT)
+   sg_enable = 1;
+
+   if (qdma_dev->vqs[vchan].flags & DPAA2_QDMA_VQ_FD_SHORT_FORMAT)
+   fd_long_format = 0;
+
+   if (dev->data->dev_conf.enable_silent)
+   qdma_dev->vqs[vchan].flags |= DPAA2_QDMA_VQ_NO_RESPONSE;
+
+   if (sg_enable) {
+   if (qdma_dev->num_vqs != 1) {
+   DPAA2_QDMA_ERR(
+   "qDMA SG format only supports physical queue!");
+   return -ENODEV;
+   }
+   if (!fd_long_format) {
+   DPAA2_QDMA_ERR(
+   "qDMA SG format only supports long FD format!");
+   return -ENODEV;
+   }
+   pool_size = QDMA_FLE_SG_POOL_SIZE;
+   } else {
+   pool_size = QDMA_FLE_SINGLE_POOL_SIZE;
+   }
+
+   if (qdma_dev->num_vqs == 1)
+   qdma_dev->vqs[vchan].exclusive_hw_queue = 1;
+   else {
+   /* Allocate a Ring for Virtual Queue in VQ mode */
+   snprintf(ring_name, sizeof(ring_name), "status ring %d %d",
+dev->data->dev_id, vchan);
+   qdma_dev->vqs[vchan].status_ring = rte_ring_create(ring_name,
+   conf->nb_desc, rte_socket_id(), 0);
+   if (!qdma_dev->vqs[vchan].status_ring) {
+   DPAA2_QDMA_ERR("Status ring creation failed for vq");
+   return rte_errno;
+   }
+   }
+
+   snprintf(pool_name, sizeof(pool_name),
+   "qdma_fle_pool_dev%d_qid%d", dpdmai_dev->dpdmai_id, vchan);
+   qdma_dev->vqs[vchan].fle_pool = rte_mempool_create(pool_name,
+   conf->nb_desc, pool_size,
+   QDMA_FLE_CACHE_SIZE(conf->nb_desc), 0,
+ 

[PATCH v2 4/6] dma/dpaa2: add PMD apis for additional configuration

[nipun . gupta]

From: Nipun Gupta 

Add additional PMD APIs for DPAA2 QDMA driver for configuring
RBP, Ultra Short format, and Scatter Gather support

Signed-off-by: Nipun Gupta 
---
 doc/api/doxy-api-index.md  |  1 +
 doc/api/doxy-api.conf.in   |  1 +
 drivers/dma/dpaa2/dpaa2_qdma.c | 38 ++
 drivers/dma/dpaa2/meson.build  |  2 +
 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h | 96 ++
 drivers/dma/dpaa2/version.map  |  6 ++
 6 files changed, 144 insertions(+)
 create mode 100644 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h

diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md
index 6c1ca981bc..4245b9635c 100644
--- a/doc/api/doxy-api-index.md
+++ b/doc/api/doxy-api-index.md
@@ -53,6 +53,7 @@ The public API headers are grouped by topics:
   [mlx5]   (@ref rte_pmd_mlx5.h),
   [dpaa2_mempool]  (@ref rte_dpaa2_mempool.h),
   [dpaa2_cmdif](@ref rte_pmd_dpaa2_cmdif.h),
+  [dpaa2_qdma] (@ref rte_pmd_dpaa2_qdma.h),
   [crypto_scheduler]   (@ref rte_cryptodev_scheduler.h),
   [dlb2]   (@ref rte_pmd_dlb2.h),
   [ifpga]  (@ref rte_pmd_ifpga.h)
diff --git a/doc/api/doxy-api.conf.in b/doc/api/doxy-api.conf.in
index a73aac2410..93425e38eb 100644
--- a/doc/api/doxy-api.conf.in
+++ b/doc/api/doxy-api.conf.in
@@ -7,6 +7,7 @@ USE_MDFILE_AS_MAINPAGE  = @TOPDIR@/doc/api/doxy-api-index.md
 INPUT   = @TOPDIR@/doc/api/doxy-api-index.md \
   @TOPDIR@/drivers/bus/vdev \
   @TOPDIR@/drivers/crypto/scheduler \
+  @TOPDIR@/drivers/dma/dpaa2 \
   @TOPDIR@/drivers/event/dlb2 \
   @TOPDIR@/drivers/mempool/dpaa2 \
   @TOPDIR@/drivers/net/ark \
diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c
index 785d8aea7b..54db806736 100644
--- a/drivers/dma/dpaa2/dpaa2_qdma.c
+++ b/drivers/dma/dpaa2/dpaa2_qdma.c
@@ -7,7 +7,10 @@
 #include 
 #include 
 #include 
+
 #include 
+
+#include "rte_pmd_dpaa2_qdma.h"
 #include "dpaa2_qdma.h"
 #include "dpaa2_qdma_logs.h"
 /* Dynamic log type identifier */
@@ -71,6 +74,41 @@ dpaa2_qdma_configure(struct rte_dma_dev *dev,
return 0;
 }
 
+/* Enable FD in Ultra Short format */
+void
+rte_dpaa2_qdma_vchan_fd_us_enable(int16_t dev_id, uint16_t vchan)
+{
+   struct rte_dma_fp_object *obj = &rte_dma_fp_objs[dev_id];
+   struct dpaa2_dpdmai_dev *dpdmai_dev = obj->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+
+   qdma_dev->vqs[vchan].flags |= DPAA2_QDMA_VQ_FD_SHORT_FORMAT;
+}
+
+/* Enable internal SG processing */
+void
+rte_dpaa2_qdma_vchan_internal_sg_enable(int16_t dev_id, uint16_t vchan)
+{
+   struct rte_dma_fp_object *obj = &rte_dma_fp_objs[dev_id];
+   struct dpaa2_dpdmai_dev *dpdmai_dev = obj->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+
+   qdma_dev->vqs[vchan].flags |= DPAA2_QDMA_VQ_FD_SG_FORMAT;
+}
+
+/* Enable RBP */
+void
+rte_dpaa2_qdma_vchan_rbp_enable(int16_t dev_id, uint16_t vchan,
+   struct rte_dpaa2_qdma_rbp *rbp_config)
+{
+   struct rte_dma_fp_object *obj = &rte_dma_fp_objs[dev_id];
+   struct dpaa2_dpdmai_dev *dpdmai_dev = obj->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+
+   memcpy(&qdma_dev->vqs[vchan].rbp, rbp_config,
+   sizeof(struct rte_dpaa2_qdma_rbp));
+}
+
 static int
 dpaa2_qdma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
   const struct rte_dma_vchan_conf *conf,
diff --git a/drivers/dma/dpaa2/meson.build b/drivers/dma/dpaa2/meson.build
index 2b82563e85..a99151e2a5 100644
--- a/drivers/dma/dpaa2/meson.build
+++ b/drivers/dma/dpaa2/meson.build
@@ -14,3 +14,5 @@ sources = files('dpaa2_qdma.c')
 if cc.has_argument('-Wno-pointer-arith')
 cflags += '-Wno-pointer-arith'
 endif
+
+headers = files('rte_pmd_dpaa2_qdma.h')
diff --git a/drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h 
b/drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h
new file mode 100644
index 00..a75cdd7e36
--- /dev/null
+++ b/drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2021-2022 NXP
+ */
+
+#ifndef _RTE_PMD_DPAA2_QDMA_H_
+#define _RTE_PMD_DPAA2_QDMA_H_
+
+/** States if the source addresses is physical. */
+#define RTE_DPAA2_QDMA_JOB_SRC_PHY (1ULL << 30)
+
+/** States if the destination addresses is physical. */
+#define RTE_DPAA2_QDMA_JOB_DEST_PHY(1ULL << 31)
+
+struct rte_dpaa2_qdma_rbp {
+   uint32_t use_ultrashort:1;
+   uint32_t enable:1;
+   /**
+* dportid:
+*  PCI-Express 1
+* 0001 PCI-Express 2
+* 0010 PCI-Express 3
+* 0011 PCI-Express 4
+* 0100 PCI-Express 5
+* 0101 PCI-Express 6
+*/
+   uint32_t dportid:4;
+   uint32_t dpfid:2;
+   uin

[PATCH v2 5/6] dma/dpaa2: support DMA operations

[nipun . gupta]

From: Nipun Gupta 

This patch support copy, submit, completed and
completed status functionality of DMA driver.

Signed-off-by: Nipun Gupta 
---
 drivers/dma/dpaa2/dpaa2_qdma.c | 1173 
 drivers/dma/dpaa2/dpaa2_qdma.h |   71 +-
 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h |   77 ++
 drivers/dma/dpaa2/version.map  |2 +
 4 files changed, 1258 insertions(+), 65 deletions(-)

diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c
index 54db806736..f1f92b5465 100644
--- a/drivers/dma/dpaa2/dpaa2_qdma.c
+++ b/drivers/dma/dpaa2/dpaa2_qdma.c
@@ -13,12 +13,1102 @@
 #include "rte_pmd_dpaa2_qdma.h"
 #include "dpaa2_qdma.h"
 #include "dpaa2_qdma_logs.h"
+
+#define DPAA2_QDMA_PREFETCH "prefetch"
+
 /* Dynamic log type identifier */
 int dpaa2_qdma_logtype;
 
 uint32_t dpaa2_coherent_no_alloc_cache;
 uint32_t dpaa2_coherent_alloc_cache;
 
+static inline int
+qdma_populate_fd_pci(phys_addr_t src, phys_addr_t dest,
+uint32_t len, struct qbman_fd *fd,
+struct rte_dpaa2_qdma_rbp *rbp, int ser)
+{
+   fd->simple_pci.saddr_lo = lower_32_bits((uint64_t) (src));
+   fd->simple_pci.saddr_hi = upper_32_bits((uint64_t) (src));
+
+   fd->simple_pci.len_sl = len;
+
+   fd->simple_pci.bmt = 1;
+   fd->simple_pci.fmt = 3;
+   fd->simple_pci.sl = 1;
+   fd->simple_pci.ser = ser;
+
+   fd->simple_pci.sportid = rbp->sportid;  /*pcie 3 */
+   fd->simple_pci.srbp = rbp->srbp;
+   if (rbp->srbp)
+   fd->simple_pci.rdttype = 0;
+   else
+   fd->simple_pci.rdttype = dpaa2_coherent_alloc_cache;
+
+   /*dest is pcie memory */
+   fd->simple_pci.dportid = rbp->dportid;  /*pcie 3 */
+   fd->simple_pci.drbp = rbp->drbp;
+   if (rbp->drbp)
+   fd->simple_pci.wrttype = 0;
+   else
+   fd->simple_pci.wrttype = dpaa2_coherent_no_alloc_cache;
+
+   fd->simple_pci.daddr_lo = lower_32_bits((uint64_t) (dest));
+   fd->simple_pci.daddr_hi = upper_32_bits((uint64_t) (dest));
+
+   return 0;
+}
+
+static inline int
+qdma_populate_fd_ddr(phys_addr_t src, phys_addr_t dest,
+uint32_t len, struct qbman_fd *fd, int ser)
+{
+   fd->simple_ddr.saddr_lo = lower_32_bits((uint64_t) (src));
+   fd->simple_ddr.saddr_hi = upper_32_bits((uint64_t) (src));
+
+   fd->simple_ddr.len = len;
+
+   fd->simple_ddr.bmt = 1;
+   fd->simple_ddr.fmt = 3;
+   fd->simple_ddr.sl = 1;
+   fd->simple_ddr.ser = ser;
+   /**
+* src If RBP=0 {NS,RDTTYPE[3:0]}: 0_1011
+* Coherent copy of cacheable memory,
+   * lookup in downstream cache, no allocate
+* on miss
+*/
+   fd->simple_ddr.rns = 0;
+   fd->simple_ddr.rdttype = dpaa2_coherent_alloc_cache;
+   /**
+* dest If RBP=0 {NS,WRTTYPE[3:0]}: 0_0111
+* Coherent write of cacheable memory,
+* lookup in downstream cache, no allocate on miss
+*/
+   fd->simple_ddr.wns = 0;
+   fd->simple_ddr.wrttype = dpaa2_coherent_no_alloc_cache;
+
+   fd->simple_ddr.daddr_lo = lower_32_bits((uint64_t) (dest));
+   fd->simple_ddr.daddr_hi = upper_32_bits((uint64_t) (dest));
+
+   return 0;
+}
+
+static void
+dpaa2_qdma_populate_fle(struct qbman_fle *fle,
+   uint64_t fle_iova,
+   struct rte_dpaa2_qdma_rbp *rbp,
+   uint64_t src, uint64_t dest,
+   size_t len, uint32_t flags, uint32_t fmt)
+{
+   struct qdma_sdd *sdd;
+   uint64_t sdd_iova;
+
+   sdd = (struct qdma_sdd *)
+   ((uintptr_t)(uint64_t)fle - QDMA_FLE_FLE_OFFSET +
+   QDMA_FLE_SDD_OFFSET);
+   sdd_iova = fle_iova - QDMA_FLE_FLE_OFFSET + QDMA_FLE_SDD_OFFSET;
+
+   /* first frame list to source descriptor */
+   DPAA2_SET_FLE_ADDR(fle, sdd_iova);
+   DPAA2_SET_FLE_LEN(fle, (2 * (sizeof(struct qdma_sdd;
+
+   /* source and destination descriptor */
+   if (rbp && rbp->enable) {
+   /* source */
+   sdd->read_cmd.portid = rbp->sportid;
+   sdd->rbpcmd_simple.pfid = rbp->spfid;
+   sdd->rbpcmd_simple.vfid = rbp->svfid;
+
+   if (rbp->srbp) {
+   sdd->read_cmd.rbp = rbp->srbp;
+   sdd->read_cmd.rdtype = DPAA2_RBP_MEM_RW;
+   } else {
+   sdd->read_cmd.rdtype = dpaa2_coherent_no_alloc_cache;
+   }
+   sdd++;
+   /* destination */
+   sdd->write_cmd.portid = rbp->dportid;
+   sdd->rbpcmd_simple.pfid = rbp->dpfid;
+   sdd->rbpcmd_simple.vfid = rbp->dvfid;
+
+   if (rbp->drbp) {
+   sdd->write_cmd.rbp = rbp->drbp;
+   sdd->write_cmd.wrttype = DPAA2_RBP_MEM_RW;
+   } else {
+   sdd->write_cmd.w

[PATCH v2 6/6] dma/dpaa2: support statistics

[nipun . gupta]

From: Nipun Gupta 

This patch support DMA read and reset statistics operations.

Signed-off-by: Nipun Gupta 
---
 drivers/dma/dpaa2/dpaa2_qdma.c | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c
index f1f92b5465..a93a60565d 100644
--- a/drivers/dma/dpaa2/dpaa2_qdma.c
+++ b/drivers/dma/dpaa2/dpaa2_qdma.c
@@ -1427,6 +1427,38 @@ dpaa2_qdma_close(__rte_unused struct rte_dma_dev *dev)
return 0;
 }
 
+static int
+dpaa2_qdma_stats_get(const struct rte_dma_dev *dmadev, uint16_t vchan,
+   struct rte_dma_stats *rte_stats, uint32_t size)
+{
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dmadev->data->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+   struct qdma_virt_queue *qdma_vq = &qdma_dev->vqs[vchan];
+   struct rte_dma_stats *stats = &qdma_vq->stats;
+
+   RTE_SET_USED(size);
+
+   /* TODO - directly use stats */
+   stats->submitted = qdma_vq->num_enqueues;
+   stats->completed = qdma_vq->num_dequeues;
+   *rte_stats = *stats;
+
+   return 0;
+}
+
+static int
+dpaa2_qdma_stats_reset(struct rte_dma_dev *dmadev, uint16_t vchan)
+{
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dmadev->data->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+   struct qdma_virt_queue *qdma_vq = &qdma_dev->vqs[vchan];
+
+   qdma_vq->num_enqueues = 0;
+   qdma_vq->num_dequeues = 0;
+
+   return 0;
+}
+
 static uint16_t
 dpaa2_qdma_burst_capacity(const void *dev_private, uint16_t vchan)
 {
@@ -1444,6 +1476,8 @@ static struct rte_dma_dev_ops dpaa2_qdma_ops = {
.dev_stop = dpaa2_qdma_stop,
.dev_close= dpaa2_qdma_close,
.vchan_setup  = dpaa2_qdma_vchan_setup,
+   .stats_get= dpaa2_qdma_stats_get,
+   .stats_reset  = dpaa2_qdma_stats_reset,
 };
 
 static int
-- 
2.17.1

RE: [PATCH v4 1/5] vhost: prepare sync for descriptor to mbuf refactoring

[Yang, YvonneX]

> -Original Message-
> From: xuan.d...@intel.com 
> Sent: 2022年5月5日 14:24
> To: maxime.coque...@redhat.com; Xia, Chenbo 
> Cc: dev@dpdk.org; Hu, Jiayu ; Jiang, Cheng1
> ; Pai G, Sunil ;
> lian...@liangbit.com; Ding, Xuan 
> Subject: [PATCH v4 1/5] vhost: prepare sync for descriptor to mbuf refactoring
> 
> From: Xuan Ding 
> 
> This patch extracts the descriptors to buffers filling from
> copy_desc_to_mbuf() into a dedicated function. Besides, enqueue and dequeue
> path are refactored to use the same function
> sync_fill_seg() for preparing batch elements, which simplifies the code 
> without
> performance degradation.
> 
> Signed-off-by: Xuan Ding 
> Reviewed-by: Maxime Coquelin 
> ---
>  lib/vhost/virtio_net.c | 78 --
>  1 file changed, 38 insertions(+), 40 deletions(-)
> 

Tested-by: Yvonne Yang 

RE: [PATCH v4 2/5] vhost: prepare async for descriptor to mbuf refactoring

[Yang, YvonneX]

> -Original Message-
> From: xuan.d...@intel.com 
> Sent: 2022年5月5日 14:24
> To: maxime.coque...@redhat.com; Xia, Chenbo 
> Cc: dev@dpdk.org; Hu, Jiayu ; Jiang, Cheng1
> ; Pai G, Sunil ;
> lian...@liangbit.com; Ding, Xuan 
> Subject: [PATCH v4 2/5] vhost: prepare async for descriptor to mbuf 
> refactoring
> 
> From: Xuan Ding 
> 
> This patch refactors vhost async enqueue path and dequeue path to use the
> same function async_fill_seg() for preparing batch elements, which simplifies 
> the
> code without performance degradation.
> 
> Signed-off-by: Xuan Ding 
> Reviewed-by: Maxime Coquelin 
> ---
>  lib/vhost/virtio_net.c | 22 ++
>  1 file changed, 14 insertions(+), 8 deletions(-)
> 


Tested-by: Yvonne Yang 

RE: [PATCH v4 3/5] vhost: merge sync and async descriptor to mbuf filling

[Yang, YvonneX]

> -Original Message-
> From: xuan.d...@intel.com 
> Sent: 2022年5月5日 14:24
> To: maxime.coque...@redhat.com; Xia, Chenbo 
> Cc: dev@dpdk.org; Hu, Jiayu ; Jiang, Cheng1
> ; Pai G, Sunil ;
> lian...@liangbit.com; Ding, Xuan 
> Subject: [PATCH v4 3/5] vhost: merge sync and async descriptor to mbuf filling
> 
> From: Xuan Ding 
> 
> This patch refactors copy_desc_to_mbuf() used by the sync path to support both
> sync and async descriptor to mbuf filling.
> 
> Signed-off-by: Xuan Ding 
> Reviewed-by: Maxime Coquelin 
> ---
>  lib/vhost/vhost.h  |  1 +
>  lib/vhost/virtio_net.c | 48 --
>  2 files changed, 38 insertions(+), 11 deletions(-)
> 

Tested-by: Yvonne Yang 

RE: [PATCH v4 5/5] examples/vhost: support async dequeue data path

[Yang, YvonneX]

> -Original Message-
> From: xuan.d...@intel.com 
> Sent: 2022年5月5日 14:24
> To: maxime.coque...@redhat.com; Xia, Chenbo 
> Cc: dev@dpdk.org; Hu, Jiayu ; Jiang, Cheng1
> ; Pai G, Sunil ;
> lian...@liangbit.com; Ding, Xuan ; Ma, WenwuX
> ; Wang, YuanX 
> Subject: [PATCH v4 5/5] examples/vhost: support async dequeue data path
> 
> From: Xuan Ding 
> 
> This patch adds the use case for async dequeue API. Vswitch can leverage DMA
> device to accelerate vhost async dequeue path.
> 
> Signed-off-by: Wenwu Ma 
> Signed-off-by: Yuan Wang 
> Signed-off-by: Xuan Ding 
> ---
>  doc/guides/sample_app_ug/vhost.rst |   9 +-
>  examples/vhost/main.c  | 292 -
>  examples/vhost/main.h  |  35 +++-
>  examples/vhost/virtio_net.c|  16 +-
>  4 files changed, 254 insertions(+), 98 deletions(-)
> 
> diff --git a/doc/guides/sample_app_ug/vhost.rst
> b/doc/guides/sample_app_ug/vhost.rst
> index a6ce4bc8ac..09db965e70 100644
> --- a/doc/guides/sample_app_ug/vhost.rst
> +++ b/doc/guides/sample_app_ug/vhost.rst
> @@ -169,9 +169,12 @@ demonstrates how to use the async vhost APIs. It's
> used in combination with dmas

Tested-by: Yvonne Yang 

RE: [PATCH v4 4/5] vhost: support async dequeue for split ring

[Yang, YvonneX]

> -Original Message-
> From: xuan.d...@intel.com 
> Sent: 2022年5月5日 14:24
> To: maxime.coque...@redhat.com; Xia, Chenbo 
> Cc: dev@dpdk.org; Hu, Jiayu ; Jiang, Cheng1
> ; Pai G, Sunil ;
> lian...@liangbit.com; Ding, Xuan ; Wang, YuanX
> 
> Subject: [PATCH v4 4/5] vhost: support async dequeue for split ring
> 
> From: Xuan Ding 
> 
> This patch implements asynchronous dequeue data path for vhost split ring, a
> new API rte_vhost_async_try_dequeue_burst() is introduced.
> 
> Signed-off-by: Xuan Ding 
> Signed-off-by: Yuan Wang 
> ---
>  doc/guides/prog_guide/vhost_lib.rst|   7 +
>  doc/guides/rel_notes/release_22_07.rst |   4 +
>  lib/vhost/rte_vhost_async.h|  33 +++
>  lib/vhost/version.map  |   3 +
>  lib/vhost/virtio_net.c | 331
> +
>  5 files changed, 378 insertions(+)
> 
> diff --git a/doc/guides/prog_guide/vhost_lib.rst
> b/doc/guides/prog_guide/vhost_lib.rst
> index 886f8f5e72..40cf315170 100644
> --- a/doc/guides/prog_guide/vhost_lib.rst
> +++ b/doc/guides/prog_guide/vhost_lib.rst

Tested-by: Yvonne Yang 

[PATCH] net/ice: Modify DCF state checking mechanism and error code

[peng1x . zhang]

From: Peng Zhang 

Add DCF state checking mechanism which will conduct whether reset is
done.And modify error code to avoid misleading.

Fixes: b71573ec2fc2 ("net/ice: retry getting VF VSI map after failure")
Cc: sta...@dpdk.org

Signed-off-by: Peng Zhang 
---
 drivers/net/ice/ice_dcf.c   | 3 ++-
 drivers/net/ice/ice_switch_filter.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c
index 7f0c074b01..3808272ea3 100644
--- a/drivers/net/ice/ice_dcf.c
+++ b/drivers/net/ice/ice_dcf.c
@@ -544,7 +544,8 @@ ice_dcf_handle_vsi_update_event(struct ice_dcf_hw *hw)
 
for (;;) {
if (ice_dcf_get_vf_resource(hw) == 0 &&
-   ice_dcf_get_vf_vsi_map(hw) >= 0) {
+   ice_dcf_get_vf_vsi_map(hw) >= 0 &&
+   ice_dcf_check_reset_done(hw) == 0) {
err = 0;
break;
}
diff --git a/drivers/net/ice/ice_switch_filter.c 
b/drivers/net/ice/ice_switch_filter.c
index 36c9bffb73..199a981018 100644
--- a/drivers/net/ice/ice_switch_filter.c
+++ b/drivers/net/ice/ice_switch_filter.c
@@ -434,7 +434,7 @@ ice_switch_create(struct ice_adapter *ad,
flow->rule = filter_conf_ptr;
} else {
if (ice_dcf_adminq_need_retry(ad))
-   ret = -EAGAIN;
+   ret = -EBUSY;
else
ret = -EINVAL;
 
-- 
2.25.1

[PATCH v2] vhost: fix deadlock when handling user messages

[Wenwu Ma]

In vhost_user_msg_handler(), if vhost message handling
failed, we should check whether the queue is locked and
release the lock before returning. Or, it will cause a
deadlock later.

Fixes: 7f31d4ea05ca ("vhost: fix lock on device readiness notification")
Cc: sta...@dpdk.org

Signed-off-by: Wenwu Ma 
---
 lib/vhost/vhost_user.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/lib/vhost/vhost_user.c b/lib/vhost/vhost_user.c
index 1d390677fa..4baf969ee0 100644
--- a/lib/vhost/vhost_user.c
+++ b/lib/vhost/vhost_user.c
@@ -2976,7 +2976,6 @@ vhost_user_msg_handler(int vid, int fd)
return -1;
}
 
-   ret = 0;
request = ctx.msg.request.master;
if (request > VHOST_USER_NONE && request < VHOST_USER_MAX &&
vhost_message_str[request]) {
@@ -3113,9 +3112,11 @@ vhost_user_msg_handler(int vid, int fd)
send_vhost_reply(dev, fd, &ctx);
} else if (ret == RTE_VHOST_MSG_RESULT_ERR) {
VHOST_LOG_CONFIG(ERR, "(%s) vhost message handling failed.\n", 
dev->ifname);
-   return -1;
+   ret = -1;
+   goto unlock;
}
 
+   ret = 0;
for (i = 0; i < dev->nr_vring; i++) {
struct vhost_virtqueue *vq = dev->virtqueue[i];
bool cur_ready = vq_is_ready(dev, vq);
@@ -3126,10 +3127,11 @@ vhost_user_msg_handler(int vid, int fd)
}
}
 
+unlock:
if (unlock_required)
vhost_user_unlock_all_queue_pairs(dev);
 
-   if (!virtio_is_ready(dev))
+   if (ret != 0 || !virtio_is_ready(dev))
goto out;
 
/*
@@ -3156,7 +3158,7 @@ vhost_user_msg_handler(int vid, int fd)
}
 
 out:
-   return 0;
+   return ret;
 }
 
 static int process_slave_message_reply(struct virtio_net *dev,
-- 
2.25.1

Re: [PATCH] common/cnxk: fix null pointer dereference

[Jerin Jacob]

On Sun, Apr 24, 2022 at 9:47 PM Gowrishankar Muthukrishnan
 wrote:
>
> Fix null pointer dereference reported in coverity scan.
>
> Coverity issue: 372065

Cc: sta...@dpdk.org

> Fixes: 665b6a7400b ("common/cnxk: add NPC helper API")
>
> Signed-off-by: Gowrishankar Muthukrishnan 

Acked-by: Jerin Jacob 
Applied to dpdk-next-net-mrvl/for-next-net. Thanks

> ---
>  drivers/common/cnxk/roc_npc_utils.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/common/cnxk/roc_npc_utils.c 
> b/drivers/common/cnxk/roc_npc_utils.c
> index f9768ea3cf..dadd8826cb 100644
> --- a/drivers/common/cnxk/roc_npc_utils.c
> +++ b/drivers/common/cnxk/roc_npc_utils.c
> @@ -145,6 +145,9 @@ npc_parse_item_basic(const struct roc_npc_item_info *item,
> info->mask = item->mask;
> }
>
> +   if (info->mask == NULL)
> +   return NPC_ERR_INVALID_MASK;
> +
> /* mask specified must be subset of hw supported mask
>  * mask | hw_mask == hw_mask
>  */
> --
> 2.25.1
>

Re: [PATCH] common/cnxk: fix sizeof not portable

[Jerin Jacob]

On Sun, Apr 24, 2022 at 9:47 PM Gowrishankar Muthukrishnan
 wrote:
>
> Fix size of not portable issue reported in coverity scan.
>
> Coverity issue: 376538
> Fixes: 7e9a94909ee ("common/cnxk: realloc inline device XAQ AURA")
>
> Signed-off-by: Gowrishankar Muthukrishnan 

Acked-by: Jerin Jacob 
Applied to dpdk-next-net-mrvl/for-next-net. Thanks


> ---
>  drivers/common/cnxk/roc_nix_inl_dev.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c 
> b/drivers/common/cnxk/roc_nix_inl_dev.c
> index 5a032aab52..8ef2bc85a3 100644
> --- a/drivers/common/cnxk/roc_nix_inl_dev.c
> +++ b/drivers/common/cnxk/roc_nix_inl_dev.c
> @@ -606,7 +606,7 @@ roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle)
> inl_dev->pkt_pools_cnt++;
> inl_dev->pkt_pools =
> plt_realloc(inl_dev->pkt_pools,
> -   sizeof(uint64_t *) * inl_dev->pkt_pools_cnt, 0);
> +   sizeof(uint64_t) * inl_dev->pkt_pools_cnt, 0);
> if (!inl_dev->pkt_pools)
> inl_dev->pkt_pools_cnt = 0;
> else
> --
> 2.25.1
>

Re: [PATCH 8/8] vmxnet3: Fix merge error in initialization for rxDataRing feature

[Andrew Rybchenko]

Hi Pakai,

On 5/4/22 23:37, Pankaj Gupta wrote:

Hi Andrew,

Changes done in this patch was accidentally removed in commit 
046f1161956777e3afb13504acbe8df2ec3a383c.


This was noticed later and we are trying to address this here.


If so, you should add:

Fixes: 046f11619567 ("net/vmxnet3: support MSI-X interrupt")
Cc: sta...@dpdk.org



Thanks,

Pankaj

*From: *Andrew Rybchenko 
*Date: *Wednesday, May 4, 2022 at 8:09 AM
*To: *Pankaj Gupta , Jochen Behrens 
, Yong Wang 

*Cc: *dev@dpdk.org 
*Subject: *Re: [PATCH 8/8] vmxnet3: Fix merge error in initialization 
for rxDataRing feature


⚠External Email

On 5/3/22 07:22, Pankaj Gupta wrote:

Fix merge error in initialization for rxDataRing feature.


Is it a bug fix? If so, it requires corresponding "Fixes:" tag and Cc to
sta...@dpdk.org in order to be backported to stable releases.



Tested, using testpmd, for different hardware version on ESXi 7.0 Update 2.

Signed-off-by: Pankaj Gupta 
---
   drivers/net/vmxnet3/vmxnet3_ethdev.c | 5 +
   1 file changed, 5 insertions(+)

diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c 
b/drivers/net/vmxnet3/vmxnet3_ethdev.c
index 9955f121f6..6ced76ae2a 100644
--- a/drivers/net/vmxnet3/vmxnet3_ethdev.c
+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c
@@ -876,6 +876,11 @@ vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
   rqd->conf.rxRingSize[1]   = rxq->cmd_ring[1].size;
   rqd->conf.compRingSize    = rxq->comp_ring.size;

+ if (VMXNET3_VERSION_GE_3(hw)) {
+ rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
+ rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
+ }
+
   if (hw->intr.lsc_only)
   rqd->conf.intrIdx = 1;
   else





⚠External Email: This email originated from outside of the organization. 
Do not click links or open attachments unless you recognize the sender.

Re: [PATCH] net/cnxk: fix uninitialized scalar variable

[Jerin Jacob]

On Sun, Apr 24, 2022 at 9:48 PM Gowrishankar Muthukrishnan
 wrote:
>
> Fix uninitialized scalar variable reported in coverity scan.
>
> Coverity issue: 371876, 371877
> Fixes: 39dc567c195 ("net/cnxk: add Tx burst for CN9K")
>
> Signed-off-by: Gowrishankar Muthukrishnan 

Squashed similar patch
https://patchwork.dpdk.org/project/dpdk/patch/20220424162239.1680904-1-gmuthukri...@marvell.com/

Acked-by: Jerin Jacob 
Applied to dpdk-next-net-mrvl/for-next-net. Thanks


> ---
>  drivers/net/cnxk/cn9k_tx.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h
> index f55cd4bdf2..a0611a67c9 100644
> --- a/drivers/net/cnxk/cn9k_tx.h
> +++ b/drivers/net/cnxk/cn9k_tx.h
> @@ -526,7 +526,7 @@ cn9k_nix_xmit_pkts(void *tx_queue, struct rte_mbuf 
> **tx_pkts, uint16_t pkts,
>  {
> struct cn9k_eth_txq *txq = tx_queue;
> const rte_iova_t io_addr = txq->io_addr;
> -   uint64_t lso_tun_fmt, mark_fmt = 0;
> +   uint64_t lso_tun_fmt = 0, mark_fmt = 0;
> void *lmt_addr = txq->lmt_addr;
> uint8_t mark_flag = 0;
> uint16_t i;
> @@ -574,7 +574,7 @@ cn9k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf 
> **tx_pkts,
>  {
> struct cn9k_eth_txq *txq = tx_queue;
> const rte_iova_t io_addr = txq->io_addr;
> -   uint64_t lso_tun_fmt, mark_fmt = 0;
> +   uint64_t lso_tun_fmt = 0, mark_fmt = 0;
> void *lmt_addr = txq->lmt_addr;
> uint8_t mark_flag = 0;
> uint16_t segdw;
> --
> 2.25.1
>

Re: [PATCH] net/cnxk: fix out of bounds access in cmd array

[Jerin Jacob]

On Sun, Apr 24, 2022 at 9:53 PM Gowrishankar Muthukrishnan
 wrote:
>
> Fix out of bounds access in cmd array which was reported in coverity
> scan.
>
> Coverity issue: 375245, 375246, 375260, 375263, 375264, 375271, 375278,
> 375279, 375273, 375274, 375275, 375276, 375280, 375281,
> 375283, 375286
> Fixes: c5b97e98837 ("net/cnxk: add cn10k template Tx functions to build")
> Fixes: dd8c20eee47 ("net/cnxk: add cn9k template Tx functions to build")
>
> Signed-off-by: Gowrishankar Muthukrishnan 

Acked-by: Jerin Jacob 
Applied to dpdk-next-net-mrvl/for-next-net. Thanks


> ---
>  drivers/net/cnxk/cn10k_tx.h | 32 
>  drivers/net/cnxk/cn9k_tx.h  | 32 
>  2 files changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
> index 5d4003c5d4..85eba90334 100644
> --- a/drivers/net/cnxk/cn10k_tx.h
> +++ b/drivers/net/cnxk/cn10k_tx.h
> @@ -2728,18 +2728,18 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t 
> *ws,
>
>  /* [T_SEC_F] [TSP] [TSO] [NOFF] [VLAN] [OL3OL4CSUM] [L3L4CSUM] */
>  #define NIX_TX_FASTPATH_MODES_0_15   
>   \
> -   T(no_offload, 4, NIX_TX_OFFLOAD_NONE) 
>  \
> -   T(l3l4csum, 4, L3L4CSUM_F)
>  \
> -   T(ol3ol4csum, 4, OL3OL4CSUM_F)
>  \
> -   T(ol3ol4csum_l3l4csum, 4, OL3OL4CSUM_F | L3L4CSUM_F)  
>  \
> +   T(no_offload, 6, NIX_TX_OFFLOAD_NONE) 
>  \
> +   T(l3l4csum, 6, L3L4CSUM_F)
>  \
> +   T(ol3ol4csum, 6, OL3OL4CSUM_F)
>  \
> +   T(ol3ol4csum_l3l4csum, 6, OL3OL4CSUM_F | L3L4CSUM_F)  
>  \
> T(vlan, 6, VLAN_F)
>  \
> T(vlan_l3l4csum, 6, VLAN_F | L3L4CSUM_F)  
>  \
> T(vlan_ol3ol4csum, 6, VLAN_F | OL3OL4CSUM_F)  
>  \
> T(vlan_ol3ol4csum_l3l4csum, 6, VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)
>  \
> -   T(noff, 4, NOFF_F)
>  \
> -   T(noff_l3l4csum, 4, NOFF_F | L3L4CSUM_F)  
>  \
> -   T(noff_ol3ol4csum, 4, NOFF_F | OL3OL4CSUM_F)  
>  \
> -   T(noff_ol3ol4csum_l3l4csum, 4, NOFF_F | OL3OL4CSUM_F | L3L4CSUM_F)
>  \
> +   T(noff, 6, NOFF_F)
>  \
> +   T(noff_l3l4csum, 6, NOFF_F | L3L4CSUM_F)  
>  \
> +   T(noff_ol3ol4csum, 6, NOFF_F | OL3OL4CSUM_F)  
>  \
> +   T(noff_ol3ol4csum_l3l4csum, 6, NOFF_F | OL3OL4CSUM_F | L3L4CSUM_F)
>  \
> T(noff_vlan, 6, NOFF_F | VLAN_F)  
>  \
> T(noff_vlan_l3l4csum, 6, NOFF_F | VLAN_F | L3L4CSUM_F)
>  \
> T(noff_vlan_ol3ol4csum, 6, NOFF_F | VLAN_F | OL3OL4CSUM_F)
>  \
> @@ -2813,19 +2813,19 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t 
> *ws,
>   TSP_F | TSO_F | NOFF_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)
>
>  #define NIX_TX_FASTPATH_MODES_64_79  
>   \
> -   T(sec, 4, T_SEC_F)
>  \
> -   T(sec_l3l4csum, 4, T_SEC_F | L3L4CSUM_F)  
>  \
> -   T(sec_ol3ol4csum, 4, T_SEC_F | OL3OL4CSUM_F)  
>  \
> -   T(sec_ol3ol4csum_l3l4csum, 4, T_SEC_F | OL3OL4CSUM_F | L3L4CSUM_F)
>  \
> +   T(sec, 6, T_SEC_F)
>  \
> +   T(sec_l3l4csum, 6, T_SEC_F | L3L4CSUM_F)  
>  \
> +   T(sec_ol3ol4csum, 6, T_SEC_F | OL3OL4CSUM_F)  
>  \
> +   T(sec_ol3ol4csum_l3l4csum, 6, T_SEC_F | OL3OL4CSUM_F | L3L4CSUM_F)
>  \
> T(sec_vlan, 6, T_SEC_F | VLAN_F)  
>  \
> T(sec_vlan_l3l4csum, 6, T_SEC_F | VLAN_F | L3L4CSUM_F)
>  \
> T(sec_vlan_ol3ol4csum, 6, T_SEC_F | VLAN_F | OL3OL4CSUM_F)
>  \
> T(sec_vlan_ol3ol4csum_l3l4csum, 6,
>  \
>   T_SEC_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)   
>  \
> -   T(sec_noff, 4, T_SEC_F | NOFF_F)  
>  \
> -   T(sec_noff_l3l4csum, 4, T_SEC_F | NOFF_F | L3L4CSUM_F)
>  \
> -   T(sec_noff_ol3ol4csum, 4, T_SEC_F | NOFF_F | OL3OL4CSUM_F)
>  \
> -   T(sec_noff_ol3ol4csum_l3l4csum, 4,
>  \
> +   T(sec_noff, 6, T_SEC_F | NOFF_F)

Re: [PATCH 7/8] vmxnet3: Set packet for fragmented packet

[Andrew Rybchenko]

Hi Pankaj,


On 5/4/22 23:40, Pankaj Gupta wrote:


Hi Andrew,

Packet type was not set for fragmented packets so we are trying to set 
it in all possible scenarios.


I believe TCP packets can be fragmented.



Theoretically it is possible, yes. OK, my main goal was to check that
we are really talking about L3 fragmentation, not scattering on Rx
and I've got the answer.

Thanks,
Andrew.


Thanks,

Pankaj

*From: *Andrew Rybchenko 
*Date: *Wednesday, May 4, 2022 at 8:08 AM
*To: *Pankaj Gupta , Jochen Behrens 
, Yong Wang 

*Cc: *dev@dpdk.org 
*Subject: *Re: [PATCH 7/8] vmxnet3: Set packet for fragmented packet

⚠External Email

On 5/3/22 07:22, Pankaj Gupta wrote:
> The packet type is set even if it is a fragmented packet

I'm wondering if is really IPv4/IPv6 fragmented packets or just
scattered on Rx across many Rx buffers.
I'm asking since fragmented sounds weird with TCP, since TCP
spec forbids fragmentation.

>
> Tested, using testpmd, for different hardware versions on
> ESXi 7.0 Update 2.
>
> Signed-off-by: Pankaj Gupta 
> ---
>   drivers/net/vmxnet3/vmxnet3_rxtx.c | 17 +
>   1 file changed, 17 insertions(+)
>
> diff --git a/drivers/net/vmxnet3/vmxnet3_rxtx.c 
b/drivers/net/vmxnet3/vmxnet3_rxtx.c

> index a6665fbf70..5e177400c0 100644
> --- a/drivers/net/vmxnet3/vmxnet3_rxtx.c
> +++ b/drivers/net/vmxnet3/vmxnet3_rxtx.c
> @@ -759,6 +759,23 @@ vmxnet3_rx_offload(struct vmxnet3_hw *hw, const 
Vmxnet3_RxCompDesc *rcd,

>   /* Check packet type, checksum errors, etc. */
>   if (rcd->cnc) {
>   ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
> +
> + if (rcd->v4) {
> + packet_type |= 
RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;

> + if (rcd->tcp)
> + packet_type |= RTE_PTYPE_L4_TCP;
> + else if (rcd->udp)
> + packet_type |= RTE_PTYPE_L4_UDP;
> + } else if (rcd->v6) {
> + packet_type |= 
RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;

> + if (rcd->tcp)
> + packet_type |= RTE_PTYPE_L4_TCP;
> + else if (rcd->udp)
> + packet_type |= RTE_PTYPE_L4_UDP;
> + } else {
> + packet_type |= RTE_PTYPE_UNKNOWN;
> + }
> +
>   } else {
>   if (rcd->v4) {
>   packet_type |= 
RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;





⚠External Email: This email originated from outside of the 
organization. Do not click links or open attachments unless you 
recognize the sender.

Re: [PATCH 0/8] vmxnet3 version V5 and V6

[Andrew Rybchenko]

Please, don't forget to use --in-reply-to to the first version
cover letter and you sent subsequent versions.

Also don't forget about version in cover letter and changes
done in subsequent versions.

Also, I guess entire patch series should have

Reviewed-by: Jochen Behrens 

inherited from the first version.

Andrew.

On 5/5/22 00:22, Pankaj Gupta wrote:

Pankaj Gupta (8):
   net/vmxnet3: add V5 support
   net/vmxnet3: implement reta query and reta update
   net/vmxnet3: add Rx queue usage count utility
   net/vmxnet3: report HW version on FW version get
   net/vmxnet3: version 6
   net/vmxnet3: advertise RETA size in device info
   net/vmxnet3: set packet type for fragmented packet
   net/vmxnet3: fix merge error in initialization for rxDataRing feature

  drivers/net/vmxnet3/base/vmxnet3_defs.h |  73 -
  drivers/net/vmxnet3/vmxnet3_ethdev.c| 343 +++-
  drivers/net/vmxnet3/vmxnet3_ethdev.h|  15 +-
  drivers/net/vmxnet3/vmxnet3_rxtx.c  |  49 +++-
  4 files changed, 392 insertions(+), 88 deletions(-)

Re: [PATCH] rte_dev: allow C-symbol-in-C++ dma operations

[Bruce Richardson]

On Wed, May 04, 2022 at 11:39:35PM -0500, Tianhao Chai wrote:
> Currently the "extern C" section ends right before rte_dev_dma_unmap
> and other DMA function declarations, causing some C++ compilers to
> produce C++ mangled symbols to rte_dev_dma_unmap instead of C symbols.
> This leads to build failures later when linking a final executable
> against this object.
> 
> The issue is observed on DPDK 22.03 and G++ 11.
> 

From the git history I think the first offending commit is a753e53.

Fixes: a753e53d517b ("eal: add device event monitor framework")


> Signed-off-by: Tianhao Chai 

Acked-by: Bruce Richardson 

> ---
>  lib/eal/include/rte_dev.h | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/lib/eal/include/rte_dev.h b/lib/eal/include/rte_dev.h
> index 448a41cb0e..e6ff1218f9 100644
> --- a/lib/eal/include/rte_dev.h
> +++ b/lib/eal/include/rte_dev.h
> @@ -320,10 +320,6 @@ rte_dev_iterator_next(struct rte_dev_iterator *it);
>dev != NULL; \
>dev = rte_dev_iterator_next(it))
>  
> -#ifdef __cplusplus
> -}
> -#endif
> -
>  /**
>   * @warning
>   * @b EXPERIMENTAL: this API may change without prior notice
> @@ -496,4 +492,8 @@ int
>  rte_dev_dma_unmap(struct rte_device *dev, void *addr, uint64_t iova,
> size_t len);
>  
> +#ifdef __cplusplus
> +}
> +#endif
> +
>  #endif /* _RTE_DEV_H_ */
> -- 
> 2.35.1
> 




signature.asc
Description: PGP signature

[PATCH v3 0/6] move DPAA2 QDMA driver freom raw to dma

[nipun . gupta]

From: Nipun Gupta 

This change removes the DPAA2 QDMA raw driver and adds the
QDMA driver in dma set of drivers. The underlying I/O
framework remains intact, whereas the configuration part
is done as per the DMA API support.

Changes in v2:
- Fix checkpath errors
- Fix documentation compilation

Changes in v3:
- Add the missing doc/dmadevs/dpaa2.rst file

Nipun Gupta (6):
  raw/dpaa2_qdma: remove dpaa2 QDMA driver from raw
  dma/dpaa2: introduce DPAA2 DMA driver skeleton
  dma/dpaa2: support basic operations
  dma/dpaa2: add PMD apis for additional configuration
  dma/dpaa2: support DMA operations
  dma/dpaa2: support statistics

 MAINTAINERS   |   11 +-
 doc/api/doxy-api.conf.in  |2 +-
 .../dpaa2_qdma.rst => dmadevs/dpaa2.rst}  |   17 +-
 doc/guides/dmadevs/index.rst  |1 +
 doc/guides/platform/dpaa2.rst |4 +-
 doc/guides/rawdevs/index.rst  |1 -
 drivers/bus/fslmc/rte_fslmc.h |1 +
 .../dpaa2_qdma => dma/dpaa2}/dpaa2_qdma.c | 1248 -
 .../dpaa2_qdma => dma/dpaa2}/dpaa2_qdma.h |  195 ++-
 .../dpaa2}/dpaa2_qdma_logs.h  |2 +-
 drivers/dma/dpaa2/meson.build |   18 +
 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h|  173 +++
 drivers/dma/dpaa2/version.map |   11 +
 drivers/dma/meson.build   |1 +
 drivers/raw/dpaa2_qdma/meson.build|7 -
 drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h   |  204 ---
 drivers/raw/dpaa2_qdma/version.map|7 -
 drivers/raw/meson.build   |1 -
 18 files changed, 864 insertions(+), 1040 deletions(-)
 rename doc/guides/{rawdevs/dpaa2_qdma.rst => dmadevs/dpaa2.rst} (75%)
 rename drivers/{raw/dpaa2_qdma => dma/dpaa2}/dpaa2_qdma.c (57%)
 rename drivers/{raw/dpaa2_qdma => dma/dpaa2}/dpaa2_qdma.h (77%)
 rename drivers/{raw/dpaa2_qdma => dma/dpaa2}/dpaa2_qdma_logs.h (97%)
 create mode 100644 drivers/dma/dpaa2/meson.build
 create mode 100644 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h
 create mode 100644 drivers/dma/dpaa2/version.map
 delete mode 100644 drivers/raw/dpaa2_qdma/meson.build
 delete mode 100644 drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h
 delete mode 100644 drivers/raw/dpaa2_qdma/version.map

-- 
2.17.1

[PATCH v3 2/6] dma/dpaa2: introduce DPAA2 DMA driver skeleton

[nipun . gupta]

From: Nipun Gupta 

The DPAA2 DMA  driver is an implementation of the dmadev APIs,
that provide means to initiate a DMA transaction from CPU.
Earlier this was part of RAW driver, but with DMA drivers
added as separate flavor of drivers, this driver is being
moved to DMA drivers.

Signed-off-by: Nipun Gupta 
---
 MAINTAINERS |   6 +
 doc/guides/dmadevs/dpaa2.rst|  64 ++
 doc/guides/dmadevs/index.rst|   1 +
 doc/guides/platform/dpaa2.rst   |   4 +
 drivers/bus/fslmc/rte_fslmc.h   |   1 +
 drivers/dma/dpaa2/dpaa2_qdma.c  | 275 
 drivers/dma/dpaa2/dpaa2_qdma.h  | 316 
 drivers/dma/dpaa2/dpaa2_qdma_logs.h |  46 
 drivers/dma/dpaa2/meson.build   |  16 ++
 drivers/dma/dpaa2/version.map   |   3 +
 drivers/dma/meson.build |   1 +
 11 files changed, 733 insertions(+)
 create mode 100644 doc/guides/dmadevs/dpaa2.rst
 create mode 100644 drivers/dma/dpaa2/dpaa2_qdma.c
 create mode 100644 drivers/dma/dpaa2/dpaa2_qdma.h
 create mode 100644 drivers/dma/dpaa2/dpaa2_qdma_logs.h
 create mode 100644 drivers/dma/dpaa2/meson.build
 create mode 100644 drivers/dma/dpaa2/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index e67215f490..432ca49fb3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1198,6 +1198,12 @@ M: Nipun Gupta 
 F: drivers/dma/dpaa/
 F: doc/guides/dmadevs/dpaa.rst
 
+NXP DPAA2 QDMA
+M: Nipun Gupta 
+M: Hemant Agrawal 
+F: drivers/dma/dpaa2_qdma/
+F: doc/guides/dmadevs/dpaa2_qdma.rst
+
 
 RegEx Drivers
 -
diff --git a/doc/guides/dmadevs/dpaa2.rst b/doc/guides/dmadevs/dpaa2.rst
new file mode 100644
index 00..84e0db10d6
--- /dev/null
+++ b/doc/guides/dmadevs/dpaa2.rst
@@ -0,0 +1,64 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+Copyright 2018-2022 NXP
+
+NXP DPAA2 QDMA Driver
+=
+
+The DPAA2 QDMA is an implementation of the dmadev API, that provide means
+to initiate a DMA transaction from CPU. The initiated DMA is performed
+without CPU being involved in the actual DMA transaction. This is achieved
+via using the DPDMAI device exposed by MC.
+
+More information can be found at `NXP Official Website
+`_.
+
+Supported DPAA2 SoCs
+
+
+- LX2160A
+- LS2084A/LS2044A
+- LS2088A/LS2048A
+- LS1088A/LS1048A
+
+Prerequisites
+-
+
+See :doc:`../platform/dpaa2` for setup information
+
+- Follow the DPDK :ref:`Getting Started Guide for Linux ` to setup 
the basic DPDK environment.
+
+.. note::
+
+   Some part of fslmc bus code (mc flib - object library) routines are
+   dual licensed (BSD & GPLv2).
+
+
+Enabling logs
+-
+
+For enabling logs, use the following EAL parameter:
+
+.. code-block:: console
+
+   ./your_qdma_application  --log-level=pmd.dma.dpaa2.qdma,
+
+Using ``pmd.dma.dpaa2.qdma`` as log matching criteria, all Event PMD logs can 
be
+enabled which are lower than logging ``level``.
+
+
+Initialization
+--
+
+The DPAA2 QDMA is exposed as a dma device which consists of dpdmai devices.
+On EAL initialization, dpdmai devices will be probed and populated into the
+dmadevices. The dmadev ID of the device can be obtained using
+
+* Invoking ``rte_dma_get_dev_id_by_name("dpdmai.x")`` from the application
+  where x is the object ID of the DPDMAI object created by MC. Use can
+  use this index for further rawdev function calls.
+
+Platform Requirement
+
+
+DPAA2 drivers for DPDK can only work on NXP SoCs as listed in the
+``Supported DPAA2 SoCs``.
diff --git a/doc/guides/dmadevs/index.rst b/doc/guides/dmadevs/index.rst
index 6b6406f590..5bd25b32b9 100644
--- a/doc/guides/dmadevs/index.rst
+++ b/doc/guides/dmadevs/index.rst
@@ -13,6 +13,7 @@ an application through DMA API.
 
cnxk
dpaa
+   dpaa2
hisilicon
idxd
ioat
diff --git a/doc/guides/platform/dpaa2.rst b/doc/guides/platform/dpaa2.rst
index 9c8a1e8b0c..a9fcad6ca2 100644
--- a/doc/guides/platform/dpaa2.rst
+++ b/doc/guides/platform/dpaa2.rst
@@ -40,6 +40,10 @@ Common Offload HW Block Drivers
 
See :doc:`../rawdevs/dpaa2_cmdif` for NXP dpaa2 AIOP command interface 
driver information.
 
+5. **DMA Driver**
+
+   See :doc:`../dmadevs/dpaa2` for NXP dpaa2 QDMA driver information.
+
 
 Steps To Setup Platform
 ---
diff --git a/drivers/bus/fslmc/rte_fslmc.h b/drivers/bus/fslmc/rte_fslmc.h
index 12b586b13b..8c67bfba55 100644
--- a/drivers/bus/fslmc/rte_fslmc.h
+++ b/drivers/bus/fslmc/rte_fslmc.h
@@ -123,6 +123,7 @@ struct rte_dpaa2_device {
union {
struct rte_eth_dev *eth_dev;/**< ethernet device */
struct rte_cryptodev *cryptodev;/**< Crypto Device */
+   struct rte_dma_dev *dmadev;  /**< DMA Device */
struct rte_rawdev *rawdev;  /**< Raw Device */
};
enum rte_dpaa2_dev

[PATCH v3 1/6] raw/dpaa2_qdma: remove dpaa2 QDMA driver from raw

[nipun . gupta]

From: Nipun Gupta 

With DMA devices supported as a separate flavor of devices,
the DPAA2 QDMA driver is moved in the DMA devices.

This change removes the DPAA2 QDMA driver from raw devices.

Signed-off-by: Nipun Gupta 
---
 MAINTAINERS |5 -
 doc/api/doxy-api-index.md   |1 -
 doc/api/doxy-api.conf.in|1 -
 doc/guides/platform/dpaa2.rst   |4 -
 doc/guides/rawdevs/dpaa2_qdma.rst   |   74 -
 doc/guides/rawdevs/index.rst|1 -
 drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 1834 ---
 drivers/raw/dpaa2_qdma/dpaa2_qdma.h |  288 ---
 drivers/raw/dpaa2_qdma/dpaa2_qdma_logs.h|   46 -
 drivers/raw/dpaa2_qdma/meson.build  |7 -
 drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h |  204 ---
 drivers/raw/dpaa2_qdma/version.map  |7 -
 drivers/raw/meson.build |1 -
 13 files changed, 2473 deletions(-)
 delete mode 100644 doc/guides/rawdevs/dpaa2_qdma.rst
 delete mode 100644 drivers/raw/dpaa2_qdma/dpaa2_qdma.c
 delete mode 100644 drivers/raw/dpaa2_qdma/dpaa2_qdma.h
 delete mode 100644 drivers/raw/dpaa2_qdma/dpaa2_qdma_logs.h
 delete mode 100644 drivers/raw/dpaa2_qdma/meson.build
 delete mode 100644 drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h
 delete mode 100644 drivers/raw/dpaa2_qdma/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 7c4f541dba..e67215f490 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1379,11 +1379,6 @@ M: Nipun Gupta 
 F: drivers/raw/dpaa2_cmdif/
 F: doc/guides/rawdevs/dpaa2_cmdif.rst
 
-NXP DPAA2 QDMA
-M: Nipun Gupta 
-F: drivers/raw/dpaa2_qdma/
-F: doc/guides/rawdevs/dpaa2_qdma.rst
-
 
 Packet processing
 -
diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md
index 4245b9635c..6c1ca981bc 100644
--- a/doc/api/doxy-api-index.md
+++ b/doc/api/doxy-api-index.md
@@ -53,7 +53,6 @@ The public API headers are grouped by topics:
   [mlx5]   (@ref rte_pmd_mlx5.h),
   [dpaa2_mempool]  (@ref rte_dpaa2_mempool.h),
   [dpaa2_cmdif](@ref rte_pmd_dpaa2_cmdif.h),
-  [dpaa2_qdma] (@ref rte_pmd_dpaa2_qdma.h),
   [crypto_scheduler]   (@ref rte_cryptodev_scheduler.h),
   [dlb2]   (@ref rte_pmd_dlb2.h),
   [ifpga]  (@ref rte_pmd_ifpga.h)
diff --git a/doc/api/doxy-api.conf.in b/doc/api/doxy-api.conf.in
index db2ca9b6ed..a73aac2410 100644
--- a/doc/api/doxy-api.conf.in
+++ b/doc/api/doxy-api.conf.in
@@ -21,7 +21,6 @@ INPUT   = @TOPDIR@/doc/api/doxy-api-index.md \
   @TOPDIR@/drivers/net/mlx5 \
   @TOPDIR@/drivers/net/softnic \
   @TOPDIR@/drivers/raw/dpaa2_cmdif \
-  @TOPDIR@/drivers/raw/dpaa2_qdma \
   @TOPDIR@/drivers/raw/ifpga \
   @TOPDIR@/drivers/raw/ioat \
   @TOPDIR@/lib/eal/include \
diff --git a/doc/guides/platform/dpaa2.rst b/doc/guides/platform/dpaa2.rst
index f1526bd30e..9c8a1e8b0c 100644
--- a/doc/guides/platform/dpaa2.rst
+++ b/doc/guides/platform/dpaa2.rst
@@ -40,10 +40,6 @@ Common Offload HW Block Drivers
 
See :doc:`../rawdevs/dpaa2_cmdif` for NXP dpaa2 AIOP command interface 
driver information.
 
-5. **Rawdev QDMA Driver**
-
-   See :doc:`../rawdevs/dpaa2_qdma` for NXP dpaa2 QDMA driver information.
-
 
 Steps To Setup Platform
 ---
diff --git a/doc/guides/rawdevs/dpaa2_qdma.rst 
b/doc/guides/rawdevs/dpaa2_qdma.rst
deleted file mode 100644
index 1b619ea1e1..00
--- a/doc/guides/rawdevs/dpaa2_qdma.rst
+++ /dev/null
@@ -1,74 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-Copyright 2018 NXP
-
-NXP DPAA2 QDMA Driver
-=
-
-The DPAA2 QDMA is an implementation of the rawdev API, that provide means
-to initiate a DMA transaction from CPU. The initiated DMA is performed
-without CPU being involved in the actual DMA transaction. This is achieved
-via using the DPDMAI device exposed by MC.
-
-More information can be found at `NXP Official Website
-`_.
-
-Features
-
-
-The DPAA2 QDMA implements following features in the rawdev API;
-
-- Supports issuing DMA of data within memory without hogging CPU while
-  performing DMA operation.
-- Supports configuring to optionally get status of the DMA translation on
-  per DMA operation basis.
-
-Supported DPAA2 SoCs
-
-
-- LX2160A
-- LS2084A/LS2044A
-- LS2088A/LS2048A
-- LS1088A/LS1048A
-
-Prerequisites
--
-
-See :doc:`../platform/dpaa2` for setup information
-
-- Follow the DPDK :ref:`Getting Started Guide for Linux ` to setup 
the basic DPDK environment.
-
-.. note::
-
-   Some part of fslmc bus code (mc flib - object library) routines are
-   dual licensed (BSD & GPLv2).
-
-
-Enabling logs
--
-
-For ena

[PATCH v3 3/6] dma/dpaa2: support basic operations

[nipun . gupta]

From: Nipun Gupta 

This patch support basic DMA operations which includes
device capability and channel setup.

Signed-off-by: Nipun Gupta 
---
 drivers/dma/dpaa2/dpaa2_qdma.c | 182 +
 1 file changed, 182 insertions(+)

diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c
index 9fa48ddfa4..785d8aea7b 100644
--- a/drivers/dma/dpaa2/dpaa2_qdma.c
+++ b/drivers/dma/dpaa2/dpaa2_qdma.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "dpaa2_qdma.h"
 #include "dpaa2_qdma_logs.h"
@@ -15,6 +16,171 @@ int dpaa2_qdma_logtype;
 uint32_t dpaa2_coherent_no_alloc_cache;
 uint32_t dpaa2_coherent_alloc_cache;
 
+static int
+dpaa2_qdma_info_get(const struct rte_dma_dev *dev,
+   struct rte_dma_info *dev_info,
+   uint32_t info_sz)
+{
+   RTE_SET_USED(dev);
+   RTE_SET_USED(info_sz);
+
+   dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
+RTE_DMA_CAPA_MEM_TO_DEV |
+RTE_DMA_CAPA_DEV_TO_DEV |
+RTE_DMA_CAPA_DEV_TO_MEM |
+RTE_DMA_CAPA_SILENT |
+RTE_DMA_CAPA_OPS_COPY;
+   dev_info->max_vchans = DPAA2_QDMA_MAX_VHANS;
+   dev_info->max_desc = DPAA2_QDMA_MAX_DESC;
+   dev_info->min_desc = DPAA2_QDMA_MIN_DESC;
+
+   return 0;
+}
+
+static int
+dpaa2_qdma_configure(struct rte_dma_dev *dev,
+const struct rte_dma_conf *dev_conf,
+uint32_t conf_sz)
+{
+   char name[32]; /* RTE_MEMZONE_NAMESIZE = 32 */
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dev->data->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+
+   DPAA2_QDMA_FUNC_TRACE();
+
+   RTE_SET_USED(conf_sz);
+
+   /* In case QDMA device is not in stopped state, return -EBUSY */
+   if (qdma_dev->state == 1) {
+   DPAA2_QDMA_ERR(
+   "Device is in running state. Stop before config.");
+   return -1;
+   }
+
+   /* Allocate Virtual Queues */
+   sprintf(name, "qdma_%d_vq", dev->data->dev_id);
+   qdma_dev->vqs = rte_malloc(name,
+   (sizeof(struct qdma_virt_queue) * dev_conf->nb_vchans),
+   RTE_CACHE_LINE_SIZE);
+   if (!qdma_dev->vqs) {
+   DPAA2_QDMA_ERR("qdma_virtual_queues allocation failed");
+   return -ENOMEM;
+   }
+   qdma_dev->num_vqs = dev_conf->nb_vchans;
+
+   return 0;
+}
+
+static int
+dpaa2_qdma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
+  const struct rte_dma_vchan_conf *conf,
+  uint32_t conf_sz)
+{
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dev->data->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+   uint32_t pool_size;
+   char ring_name[32];
+   char pool_name[64];
+   int fd_long_format = 1;
+   int sg_enable = 0;
+
+   DPAA2_QDMA_FUNC_TRACE();
+
+   RTE_SET_USED(conf_sz);
+
+   if (qdma_dev->vqs[vchan].flags & DPAA2_QDMA_VQ_FD_SG_FORMAT)
+   sg_enable = 1;
+
+   if (qdma_dev->vqs[vchan].flags & DPAA2_QDMA_VQ_FD_SHORT_FORMAT)
+   fd_long_format = 0;
+
+   if (dev->data->dev_conf.enable_silent)
+   qdma_dev->vqs[vchan].flags |= DPAA2_QDMA_VQ_NO_RESPONSE;
+
+   if (sg_enable) {
+   if (qdma_dev->num_vqs != 1) {
+   DPAA2_QDMA_ERR(
+   "qDMA SG format only supports physical queue!");
+   return -ENODEV;
+   }
+   if (!fd_long_format) {
+   DPAA2_QDMA_ERR(
+   "qDMA SG format only supports long FD format!");
+   return -ENODEV;
+   }
+   pool_size = QDMA_FLE_SG_POOL_SIZE;
+   } else {
+   pool_size = QDMA_FLE_SINGLE_POOL_SIZE;
+   }
+
+   if (qdma_dev->num_vqs == 1)
+   qdma_dev->vqs[vchan].exclusive_hw_queue = 1;
+   else {
+   /* Allocate a Ring for Virtual Queue in VQ mode */
+   snprintf(ring_name, sizeof(ring_name), "status ring %d %d",
+dev->data->dev_id, vchan);
+   qdma_dev->vqs[vchan].status_ring = rte_ring_create(ring_name,
+   conf->nb_desc, rte_socket_id(), 0);
+   if (!qdma_dev->vqs[vchan].status_ring) {
+   DPAA2_QDMA_ERR("Status ring creation failed for vq");
+   return rte_errno;
+   }
+   }
+
+   snprintf(pool_name, sizeof(pool_name),
+   "qdma_fle_pool_dev%d_qid%d", dpdmai_dev->dpdmai_id, vchan);
+   qdma_dev->vqs[vchan].fle_pool = rte_mempool_create(pool_name,
+   conf->nb_desc, pool_size,
+   QDMA_FLE_CACHE_SIZE(conf->nb_desc), 0,
+ 

[PATCH v3 4/6] dma/dpaa2: add PMD apis for additional configuration

[nipun . gupta]

From: Nipun Gupta 

Add additional PMD APIs for DPAA2 QDMA driver for configuring
RBP, Ultra Short format, and Scatter Gather support

Signed-off-by: Nipun Gupta 
---
 doc/api/doxy-api-index.md  |  1 +
 doc/api/doxy-api.conf.in   |  1 +
 drivers/dma/dpaa2/dpaa2_qdma.c | 38 ++
 drivers/dma/dpaa2/meson.build  |  2 +
 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h | 96 ++
 drivers/dma/dpaa2/version.map  |  6 ++
 6 files changed, 144 insertions(+)
 create mode 100644 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h

diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md
index 6c1ca981bc..4245b9635c 100644
--- a/doc/api/doxy-api-index.md
+++ b/doc/api/doxy-api-index.md
@@ -53,6 +53,7 @@ The public API headers are grouped by topics:
   [mlx5]   (@ref rte_pmd_mlx5.h),
   [dpaa2_mempool]  (@ref rte_dpaa2_mempool.h),
   [dpaa2_cmdif](@ref rte_pmd_dpaa2_cmdif.h),
+  [dpaa2_qdma] (@ref rte_pmd_dpaa2_qdma.h),
   [crypto_scheduler]   (@ref rte_cryptodev_scheduler.h),
   [dlb2]   (@ref rte_pmd_dlb2.h),
   [ifpga]  (@ref rte_pmd_ifpga.h)
diff --git a/doc/api/doxy-api.conf.in b/doc/api/doxy-api.conf.in
index a73aac2410..93425e38eb 100644
--- a/doc/api/doxy-api.conf.in
+++ b/doc/api/doxy-api.conf.in
@@ -7,6 +7,7 @@ USE_MDFILE_AS_MAINPAGE  = @TOPDIR@/doc/api/doxy-api-index.md
 INPUT   = @TOPDIR@/doc/api/doxy-api-index.md \
   @TOPDIR@/drivers/bus/vdev \
   @TOPDIR@/drivers/crypto/scheduler \
+  @TOPDIR@/drivers/dma/dpaa2 \
   @TOPDIR@/drivers/event/dlb2 \
   @TOPDIR@/drivers/mempool/dpaa2 \
   @TOPDIR@/drivers/net/ark \
diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c
index 785d8aea7b..54db806736 100644
--- a/drivers/dma/dpaa2/dpaa2_qdma.c
+++ b/drivers/dma/dpaa2/dpaa2_qdma.c
@@ -7,7 +7,10 @@
 #include 
 #include 
 #include 
+
 #include 
+
+#include "rte_pmd_dpaa2_qdma.h"
 #include "dpaa2_qdma.h"
 #include "dpaa2_qdma_logs.h"
 /* Dynamic log type identifier */
@@ -71,6 +74,41 @@ dpaa2_qdma_configure(struct rte_dma_dev *dev,
return 0;
 }
 
+/* Enable FD in Ultra Short format */
+void
+rte_dpaa2_qdma_vchan_fd_us_enable(int16_t dev_id, uint16_t vchan)
+{
+   struct rte_dma_fp_object *obj = &rte_dma_fp_objs[dev_id];
+   struct dpaa2_dpdmai_dev *dpdmai_dev = obj->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+
+   qdma_dev->vqs[vchan].flags |= DPAA2_QDMA_VQ_FD_SHORT_FORMAT;
+}
+
+/* Enable internal SG processing */
+void
+rte_dpaa2_qdma_vchan_internal_sg_enable(int16_t dev_id, uint16_t vchan)
+{
+   struct rte_dma_fp_object *obj = &rte_dma_fp_objs[dev_id];
+   struct dpaa2_dpdmai_dev *dpdmai_dev = obj->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+
+   qdma_dev->vqs[vchan].flags |= DPAA2_QDMA_VQ_FD_SG_FORMAT;
+}
+
+/* Enable RBP */
+void
+rte_dpaa2_qdma_vchan_rbp_enable(int16_t dev_id, uint16_t vchan,
+   struct rte_dpaa2_qdma_rbp *rbp_config)
+{
+   struct rte_dma_fp_object *obj = &rte_dma_fp_objs[dev_id];
+   struct dpaa2_dpdmai_dev *dpdmai_dev = obj->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+
+   memcpy(&qdma_dev->vqs[vchan].rbp, rbp_config,
+   sizeof(struct rte_dpaa2_qdma_rbp));
+}
+
 static int
 dpaa2_qdma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
   const struct rte_dma_vchan_conf *conf,
diff --git a/drivers/dma/dpaa2/meson.build b/drivers/dma/dpaa2/meson.build
index 2b82563e85..a99151e2a5 100644
--- a/drivers/dma/dpaa2/meson.build
+++ b/drivers/dma/dpaa2/meson.build
@@ -14,3 +14,5 @@ sources = files('dpaa2_qdma.c')
 if cc.has_argument('-Wno-pointer-arith')
 cflags += '-Wno-pointer-arith'
 endif
+
+headers = files('rte_pmd_dpaa2_qdma.h')
diff --git a/drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h 
b/drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h
new file mode 100644
index 00..a75cdd7e36
--- /dev/null
+++ b/drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2021-2022 NXP
+ */
+
+#ifndef _RTE_PMD_DPAA2_QDMA_H_
+#define _RTE_PMD_DPAA2_QDMA_H_
+
+/** States if the source addresses is physical. */
+#define RTE_DPAA2_QDMA_JOB_SRC_PHY (1ULL << 30)
+
+/** States if the destination addresses is physical. */
+#define RTE_DPAA2_QDMA_JOB_DEST_PHY(1ULL << 31)
+
+struct rte_dpaa2_qdma_rbp {
+   uint32_t use_ultrashort:1;
+   uint32_t enable:1;
+   /**
+* dportid:
+*  PCI-Express 1
+* 0001 PCI-Express 2
+* 0010 PCI-Express 3
+* 0011 PCI-Express 4
+* 0100 PCI-Express 5
+* 0101 PCI-Express 6
+*/
+   uint32_t dportid:4;
+   uint32_t dpfid:2;
+   uin

[PATCH v3 5/6] dma/dpaa2: support DMA operations

[nipun . gupta]

From: Nipun Gupta 

This patch support copy, submit, completed and
completed status functionality of DMA driver.

Signed-off-by: Nipun Gupta 
---
 doc/guides/dmadevs/dpaa2.rst   |   10 +
 drivers/dma/dpaa2/dpaa2_qdma.c | 1173 
 drivers/dma/dpaa2/dpaa2_qdma.h |   71 +-
 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h |   77 ++
 drivers/dma/dpaa2/version.map  |2 +
 5 files changed, 1268 insertions(+), 65 deletions(-)

diff --git a/doc/guides/dmadevs/dpaa2.rst b/doc/guides/dmadevs/dpaa2.rst
index 84e0db10d6..0fad9fabe0 100644
--- a/doc/guides/dmadevs/dpaa2.rst
+++ b/doc/guides/dmadevs/dpaa2.rst
@@ -12,6 +12,16 @@ via using the DPDMAI device exposed by MC.
 More information can be found at `NXP Official Website
 
`_.
 
+Features
+
+
+The DPAA2 QDMA implements following features in the dmadev API;
+
+- Supports issuing DMA of data within memory without hogging CPU while
+  performing DMA operation.
+- Supports configuring to optionally get status of the DMA translation on
+  per DMA operation basis.
+
 Supported DPAA2 SoCs
 
 
diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c
index 54db806736..f1f92b5465 100644
--- a/drivers/dma/dpaa2/dpaa2_qdma.c
+++ b/drivers/dma/dpaa2/dpaa2_qdma.c
@@ -13,12 +13,1102 @@
 #include "rte_pmd_dpaa2_qdma.h"
 #include "dpaa2_qdma.h"
 #include "dpaa2_qdma_logs.h"
+
+#define DPAA2_QDMA_PREFETCH "prefetch"
+
 /* Dynamic log type identifier */
 int dpaa2_qdma_logtype;
 
 uint32_t dpaa2_coherent_no_alloc_cache;
 uint32_t dpaa2_coherent_alloc_cache;
 
+static inline int
+qdma_populate_fd_pci(phys_addr_t src, phys_addr_t dest,
+uint32_t len, struct qbman_fd *fd,
+struct rte_dpaa2_qdma_rbp *rbp, int ser)
+{
+   fd->simple_pci.saddr_lo = lower_32_bits((uint64_t) (src));
+   fd->simple_pci.saddr_hi = upper_32_bits((uint64_t) (src));
+
+   fd->simple_pci.len_sl = len;
+
+   fd->simple_pci.bmt = 1;
+   fd->simple_pci.fmt = 3;
+   fd->simple_pci.sl = 1;
+   fd->simple_pci.ser = ser;
+
+   fd->simple_pci.sportid = rbp->sportid;  /*pcie 3 */
+   fd->simple_pci.srbp = rbp->srbp;
+   if (rbp->srbp)
+   fd->simple_pci.rdttype = 0;
+   else
+   fd->simple_pci.rdttype = dpaa2_coherent_alloc_cache;
+
+   /*dest is pcie memory */
+   fd->simple_pci.dportid = rbp->dportid;  /*pcie 3 */
+   fd->simple_pci.drbp = rbp->drbp;
+   if (rbp->drbp)
+   fd->simple_pci.wrttype = 0;
+   else
+   fd->simple_pci.wrttype = dpaa2_coherent_no_alloc_cache;
+
+   fd->simple_pci.daddr_lo = lower_32_bits((uint64_t) (dest));
+   fd->simple_pci.daddr_hi = upper_32_bits((uint64_t) (dest));
+
+   return 0;
+}
+
+static inline int
+qdma_populate_fd_ddr(phys_addr_t src, phys_addr_t dest,
+uint32_t len, struct qbman_fd *fd, int ser)
+{
+   fd->simple_ddr.saddr_lo = lower_32_bits((uint64_t) (src));
+   fd->simple_ddr.saddr_hi = upper_32_bits((uint64_t) (src));
+
+   fd->simple_ddr.len = len;
+
+   fd->simple_ddr.bmt = 1;
+   fd->simple_ddr.fmt = 3;
+   fd->simple_ddr.sl = 1;
+   fd->simple_ddr.ser = ser;
+   /**
+* src If RBP=0 {NS,RDTTYPE[3:0]}: 0_1011
+* Coherent copy of cacheable memory,
+   * lookup in downstream cache, no allocate
+* on miss
+*/
+   fd->simple_ddr.rns = 0;
+   fd->simple_ddr.rdttype = dpaa2_coherent_alloc_cache;
+   /**
+* dest If RBP=0 {NS,WRTTYPE[3:0]}: 0_0111
+* Coherent write of cacheable memory,
+* lookup in downstream cache, no allocate on miss
+*/
+   fd->simple_ddr.wns = 0;
+   fd->simple_ddr.wrttype = dpaa2_coherent_no_alloc_cache;
+
+   fd->simple_ddr.daddr_lo = lower_32_bits((uint64_t) (dest));
+   fd->simple_ddr.daddr_hi = upper_32_bits((uint64_t) (dest));
+
+   return 0;
+}
+
+static void
+dpaa2_qdma_populate_fle(struct qbman_fle *fle,
+   uint64_t fle_iova,
+   struct rte_dpaa2_qdma_rbp *rbp,
+   uint64_t src, uint64_t dest,
+   size_t len, uint32_t flags, uint32_t fmt)
+{
+   struct qdma_sdd *sdd;
+   uint64_t sdd_iova;
+
+   sdd = (struct qdma_sdd *)
+   ((uintptr_t)(uint64_t)fle - QDMA_FLE_FLE_OFFSET +
+   QDMA_FLE_SDD_OFFSET);
+   sdd_iova = fle_iova - QDMA_FLE_FLE_OFFSET + QDMA_FLE_SDD_OFFSET;
+
+   /* first frame list to source descriptor */
+   DPAA2_SET_FLE_ADDR(fle, sdd_iova);
+   DPAA2_SET_FLE_LEN(fle, (2 * (sizeof(struct qdma_sdd;
+
+   /* source and destination descriptor */
+   if (rbp && rbp->enable) {
+   /* source */
+   sdd->read_cmd.portid = rbp->sportid;
+   sdd->rbp

[PATCH v3 6/6] dma/dpaa2: support statistics

[nipun . gupta]

From: Nipun Gupta 

This patch support DMA read and reset statistics operations.

Signed-off-by: Nipun Gupta 
---
 doc/guides/dmadevs/dpaa2.rst   |  1 +
 drivers/dma/dpaa2/dpaa2_qdma.c | 34 ++
 2 files changed, 35 insertions(+)

diff --git a/doc/guides/dmadevs/dpaa2.rst b/doc/guides/dmadevs/dpaa2.rst
index 0fad9fabe0..d2c26231e2 100644
--- a/doc/guides/dmadevs/dpaa2.rst
+++ b/doc/guides/dmadevs/dpaa2.rst
@@ -21,6 +21,7 @@ The DPAA2 QDMA implements following features in the dmadev 
API;
   performing DMA operation.
 - Supports configuring to optionally get status of the DMA translation on
   per DMA operation basis.
+- Supports statistics.
 
 Supported DPAA2 SoCs
 
diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c
index f1f92b5465..a93a60565d 100644
--- a/drivers/dma/dpaa2/dpaa2_qdma.c
+++ b/drivers/dma/dpaa2/dpaa2_qdma.c
@@ -1427,6 +1427,38 @@ dpaa2_qdma_close(__rte_unused struct rte_dma_dev *dev)
return 0;
 }
 
+static int
+dpaa2_qdma_stats_get(const struct rte_dma_dev *dmadev, uint16_t vchan,
+   struct rte_dma_stats *rte_stats, uint32_t size)
+{
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dmadev->data->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+   struct qdma_virt_queue *qdma_vq = &qdma_dev->vqs[vchan];
+   struct rte_dma_stats *stats = &qdma_vq->stats;
+
+   RTE_SET_USED(size);
+
+   /* TODO - directly use stats */
+   stats->submitted = qdma_vq->num_enqueues;
+   stats->completed = qdma_vq->num_dequeues;
+   *rte_stats = *stats;
+
+   return 0;
+}
+
+static int
+dpaa2_qdma_stats_reset(struct rte_dma_dev *dmadev, uint16_t vchan)
+{
+   struct dpaa2_dpdmai_dev *dpdmai_dev = dmadev->data->dev_private;
+   struct qdma_device *qdma_dev = dpdmai_dev->qdma_dev;
+   struct qdma_virt_queue *qdma_vq = &qdma_dev->vqs[vchan];
+
+   qdma_vq->num_enqueues = 0;
+   qdma_vq->num_dequeues = 0;
+
+   return 0;
+}
+
 static uint16_t
 dpaa2_qdma_burst_capacity(const void *dev_private, uint16_t vchan)
 {
@@ -1444,6 +1476,8 @@ static struct rte_dma_dev_ops dpaa2_qdma_ops = {
.dev_stop = dpaa2_qdma_stop,
.dev_close= dpaa2_qdma_close,
.vchan_setup  = dpaa2_qdma_vchan_setup,
+   .stats_get= dpaa2_qdma_stats_get,
+   .stats_reset  = dpaa2_qdma_stats_reset,
 };
 
 static int
-- 
2.17.1

Re: [PATCH v2 1/1] malloc: fix ASan handling for unmapped memory

[David Marchand]

On Wed, May 4, 2022 at 4:32 PM Anatoly Burakov
 wrote:
>
> Currently, when we free previously allocated memory, we mark the area as
> "freed" for ASan purposes (flag 0xfd). However, sometimes, freeing a
> malloc element will cause pages to be unmapped from memory and re-backed
> with anonymous memory again. This may cause ASan's "use-after-free"
> error down the line, because the allocator will try to write into
> memory areas recently marked as "freed".
>
> To fix this, we need to mark the unmapped memory area as "available",
> and fixup surrounding malloc element header/trailers to enable later
> malloc routines to safely write into new malloc elements' headers or
> trailers.

Bugzilla ID: 994
> Fixes: 6cc51b1293ce ("mem: instrument allocator for ASan")
> Cc: sta...@dpdk.org
>

Reported-by: David Marchand 
> Signed-off-by: Anatoly Burakov 

It fixes the issues I saw with unit tests.
Applied, thanks for working on this problem.


I'll respin my series that enables ASan in GHA.

-- 
David marchand

[PATCH v2 0/2] Enable ASan in GHA

[David Marchand]

Now that rte_malloc instrumentations are fixed, we can enable ASan in
GHA.
There are still some unit tests (relying on multiprocess) that can't
reliably run with ASan enabled. Those unit tests are skipped.

-- 
David Marchand

Changes since v1:
- dropped patch 2 in favor of Anatoly fix,
- rebased the last patch after other unit tests fixes have been merged,

David Marchand (2):
  test/mem: disable ASan when accessing unallocated mem
  ci: build some job with ASan

 .ci/linux-build.sh   |   8 ++
 .github/workflows/build.yml  |   3 +-
 app/test/meson.build | 208 ++-
 app/test/test_memory.c   |   5 +
 lib/eal/common/malloc_elem.h |  10 +-
 lib/eal/include/rte_common.h |  13 +++
 6 files changed, 138 insertions(+), 109 deletions(-)

-- 
2.23.0

[PATCH v2 2/2] ci: build some job with ASan

[David Marchand]

Enable ASan, this can greatly help identify leaks and buffer overflows.
Running unit tests relying on multiprocess is unreliable with ASan
enabled, so skip them.

Signed-off-by: David Marchand 
---
Changes since v1:
- reinstated table_autotest in "ASan-safe" list of ut,

---
 .ci/linux-build.sh  |   8 ++
 .github/workflows/build.yml |   3 +-
 app/test/meson.build| 208 +++-
 3 files changed, 118 insertions(+), 101 deletions(-)

diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
index 774a1441bf..93706c0131 100755
--- a/.ci/linux-build.sh
+++ b/.ci/linux-build.sh
@@ -95,6 +95,14 @@ if [ "$MINI" = "true" ]; then
 OPTS="$OPTS -Denable_drivers=net/null"
 OPTS="$OPTS -Ddisable_libs=*"
 fi
+
+if [ "$ASAN" = "true" ]; then
+OPTS="$OPTS -Db_sanitize=address"
+if [ "${CC%%clang}" != "$CC" ]; then
+OPTS="$OPTS -Db_lundef=false"
+fi
+fi
+
 meson build --werror $OPTS
 ninja -C build
 
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 22daaabb91..45871e76ed 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -16,6 +16,7 @@ jobs:
 env:
   AARCH64: ${{ matrix.config.cross == 'aarch64' }}
   ABI_CHECKS: ${{ contains(matrix.config.checks, 'abi') }}
+  ASAN: ${{ contains(matrix.config.checks, 'asan') }}
   BUILD_32BIT: ${{ matrix.config.cross == 'i386' }}
   BUILD_DOCS: ${{ contains(matrix.config.checks, 'doc') }}
   CC: ccache ${{ matrix.config.compiler }}
@@ -47,7 +48,7 @@ jobs:
   - os: ubuntu-18.04
 compiler: clang
 library: shared
-checks: doc+tests
+checks: asan+doc+tests
   - os: ubuntu-18.04
 compiler: gcc
 library: static
diff --git a/app/test/meson.build b/app/test/meson.build
index 5fc1dd1b7b..bb4621ed2a 100644
--- a/app/test/meson.build
+++ b/app/test/meson.build
@@ -149,96 +149,97 @@ test_deps = enabled_libs
 # as well as libs, the pci and vdev bus drivers are needed for a lot of tests
 test_deps += ['bus_pci', 'bus_vdev']
 
-# Each test is marked with flag true/false
-# to indicate whether it can run in no-huge mode.
+# Each test is marked with flags:
+# - the first flag indicates whether the test can run in no-huge mode,
+# - the second flag indicates whether the test can run with ASan enabled,
 fast_tests = [
-['acl_autotest', true],
-['atomic_autotest', false],
-['bitmap_autotest', true],
-['bpf_autotest', true],
-['bpf_convert_autotest', true],
-['bitops_autotest', true],
-['byteorder_autotest', true],
-['cksum_autotest', true],
-['cmdline_autotest', true],
-['common_autotest', true],
-['cpuflags_autotest', true],
-['debug_autotest', true],
-['devargs_autotest', true],
-['eal_flags_c_opt_autotest', false],
-['eal_flags_main_opt_autotest', false],
-['eal_flags_n_opt_autotest', false],
-['eal_flags_hpet_autotest', false],
-['eal_flags_no_huge_autotest', false],
-['eal_flags_a_opt_autotest', false],
-['eal_flags_b_opt_autotest', false],
-['eal_flags_vdev_opt_autotest', false],
-['eal_flags_r_opt_autotest', false],
-['eal_flags_mem_autotest', false],
-['eal_flags_file_prefix_autotest', false],
-['eal_flags_misc_autotest', false],
-['eal_fs_autotest', true],
-['errno_autotest', true],
-['ethdev_link_status', true],
-['event_ring_autotest', true],
-['fib_autotest', true],
-['fib6_autotest', true],
-['func_reentrancy_autotest', false],
-['hash_autotest', true],
-['interrupt_autotest', true],
-['ipfrag_autotest', false],
-['lcores_autotest', true],
-['logs_autotest', true],
-['lpm_autotest', true],
-['lpm6_autotest', true],
-['malloc_autotest', false],
-['mbuf_autotest', false],
-['mcslock_autotest', false],
-['memcpy_autotest', true],
-['memory_autotest', false],
-['mempool_autotest', false],
-['memzone_autotest', false],
-['meter_autotest', true],
-['multiprocess_autotest', false],
-['per_lcore_autotest', true],
-['pflock_autotest', true],
-['prefetch_autotest', true],
-['rcu_qsbr_autotest', true],
-['pie_autotest', true],
-['rib_autotest', true],
-['rib6_autotest', true],
-['ring_autotest', true],
-['rwlock_test1_autotest', true],
-['rwlock_rda_autotest', true],
-['rwlock_rds_wrm_autotest', true],
-['rwlock_rde_wro_autotest', true],
-['sched_autotest', true],
-['security_autotest', false],
-['spinlock_autotest', true],
-['stack_autotest', false],
-['stack_lf_autotest', false],
-['string_autotest', true],
-['tailq_autotest', true],
-['ti

[PATCH v2 1/2] test/mem: disable ASan when accessing unallocated mem

[David Marchand]

As described in bugzilla, ASan reports accesses to all memory segment as
invalid, since those parts have not been allocated.
Move __rte_no_asan to rte_common.h and disable ASan on a part of the test.

Bugzilla ID: 880
Fixes: 6cc51b1293ce ("mem: instrument allocator for ASan")
Cc: sta...@dpdk.org

Signed-off-by: David Marchand 
Acked-by: Anatoly Burakov 
---
 app/test/test_memory.c   |  5 +
 lib/eal/common/malloc_elem.h | 10 ++
 lib/eal/include/rte_common.h | 13 +
 3 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/app/test/test_memory.c b/app/test/test_memory.c
index 140ac3f3cf..440e5ef838 100644
--- a/app/test/test_memory.c
+++ b/app/test/test_memory.c
@@ -25,6 +25,11 @@
  * - Try to read all memory; it should not segfault.
  */
 
+/*
+ * ASan complains about accessing unallocated memory.
+ * See: https://bugs.dpdk.org/show_bug.cgi?id=880
+ */
+__rte_no_asan
 static int
 check_mem(const struct rte_memseg_list *msl __rte_unused,
const struct rte_memseg *ms, void *arg __rte_unused)
diff --git a/lib/eal/common/malloc_elem.h b/lib/eal/common/malloc_elem.h
index c5f65895e1..952ce7343b 100644
--- a/lib/eal/common/malloc_elem.h
+++ b/lib/eal/common/malloc_elem.h
@@ -7,6 +7,8 @@
 
 #include 
 
+#include 
+
 #define MIN_DATA_SIZE (RTE_CACHE_LINE_SIZE)
 
 /* dummy definition of struct so we can use pointers to it in malloc_elem 
struct */
@@ -131,12 +133,6 @@ malloc_elem_cookies_ok(const struct malloc_elem *elem)
 #define ASAN_MEM_TO_SHADOW(mem) \
RTE_PTR_ADD(ASAN_MEM_SHIFT(mem), ASAN_SHADOW_OFFSET)
 
-#if defined(__clang__)
-#define __rte_no_asan __attribute__((no_sanitize("address", "hwaddress")))
-#else
-#define __rte_no_asan __attribute__((no_sanitize_address))
-#endif
-
 __rte_no_asan
 static inline void
 asan_set_shadow(void *addr, char val)
@@ -276,8 +272,6 @@ old_malloc_size(struct malloc_elem *elem)
 
 #else /* !RTE_MALLOC_ASAN */
 
-#define __rte_no_asan
-
 static inline void
 asan_set_zone(void *ptr __rte_unused, size_t len __rte_unused,
uint32_t val __rte_unused) { }
diff --git a/lib/eal/include/rte_common.h b/lib/eal/include/rte_common.h
index 67587025ab..d56a7570c0 100644
--- a/lib/eal/include/rte_common.h
+++ b/lib/eal/include/rte_common.h
@@ -267,6 +267,19 @@ static void __attribute__((destructor(RTE_PRIO(prio)), 
used)) func(void)
  */
 #define __rte_cold __attribute__((cold))
 
+/**
+ * Disable AddressSanitizer on some code
+ */
+#ifdef RTE_MALLOC_ASAN
+#ifdef RTE_CC_CLANG
+#define __rte_no_asan __attribute__((no_sanitize("address", "hwaddress")))
+#else
+#define __rte_no_asan __attribute__((no_sanitize_address))
+#endif
+#else /* ! RTE_MALLOC_ASAN */
+#define __rte_no_asan
+#endif
+
 /*** Macros for pointer arithmetic /
 
 /**
-- 
2.23.0

Re: [PATCH] rte_dev: allow C-symbol-in-C++ dma operations

[Tyler Retzlaff]

On Wed, May 04, 2022 at 11:39:35PM -0500, Tianhao Chai wrote:
> Currently the "extern C" section ends right before rte_dev_dma_unmap
> and other DMA function declarations, causing some C++ compilers to
> produce C++ mangled symbols to rte_dev_dma_unmap instead of C symbols.
> This leads to build failures later when linking a final executable
> against this object.
> 
> The issue is observed on DPDK 22.03 and G++ 11.
> 
> Signed-off-by: Tianhao Chai 

Acked-by: Tyler Retzlaff 

Re: [PATCH] rte_dev: allow C-symbol-in-C++ dma operations

[David Marchand]

On Thu, May 5, 2022 at 11:00 AM Bruce Richardson
 wrote:
> On Wed, May 04, 2022 at 11:39:35PM -0500, Tianhao Chai wrote:
> > Currently the "extern C" section ends right before rte_dev_dma_unmap
> > and other DMA function declarations, causing some C++ compilers to
> > produce C++ mangled symbols to rte_dev_dma_unmap instead of C symbols.
> > This leads to build failures later when linking a final executable
> > against this object.
> >
> Fixes: a753e53d517b ("eal: add device event monitor framework")
Cc: sta...@dpdk.org

>
> > Signed-off-by: Tianhao Chai 
> Acked-by: Bruce Richardson 
Acked-by: Tyler Retzlaff 

Applied, thanks.


-- 
David Marchand

[PATCH 0/6] Vhost checksum offload improvements

[Maxime Coquelin]

This series aims at improving Vhost checksum offloading
support.

The first patch reverts overwritting MAC address in
testpmd CSUM forward mode. This is required to be able to
test checksum offloading with real traffic. MAC forwarding
mode should be used if the MAC addresses need to be
changed.

Second patch is a Vhost library fix to be compliant with
the Virtio specification, which requires that the
pseudo-header checksum is being set by the device when
offloading the checksum to the guest.

Third patch enables the compliant offloading mode of Vhost
library in Vhost PMD by default, since the legacy mode
violates the mbuf API by setting Tx flags in the receive
path. A new devarg is introduced for application willing
to use the legacy mode.

Fourth patch is just a small cleanup to represent a boolean
value as a boolean.

The two last patches introduces compatibility layers
that performs checksum in SW when the ethdev and Virtio
features are not aligned.

Note that the two last patches are not tagged as fixes
because they rely on the new compliant offload mode of
Vhost library, and so would casue an ABI breakage if
backported.

With this series, it is now possible to perform IO
forwarding between a vhost-user port and a Vitio-user
with kernel backend port even if the guest has negotiated
VIRTIO_NET_F_CSUM.

With csum forward mode, it now works whathever the
offloading configuration set either on Virtio or Ethdev
sides.

Maxime Coquelin (6):
  Revert "app/testpmd: modify mac in csum forwarding"
  vhost: fix missing enqueue pseudo-header calculation
  net/vhost: enable compliant offloading mode
  net/vhost: make VLAN stripping flag a boolean
  net/vhost: perform SW checksum in Rx path
  net/vhost: perform SW checksum in Tx path

 app/test-pmd/csumonly.c|   4 -
 doc/guides/nics/features/vhost.ini |   1 +
 doc/guides/nics/vhost.rst  |   6 ++
 drivers/net/vhost/rte_eth_vhost.c  | 166 -
 lib/vhost/virtio_net.c |  10 ++
 5 files changed, 179 insertions(+), 8 deletions(-)

-- 
2.35.1

[PATCH 1/6] Revert "app/testpmd: modify mac in csum forwarding"

[Maxime Coquelin]

This patch reverts commit 10f4620f02e1 ("app/testpmd: modify mac in csum 
forwarding"),
as the checksum forwarding is expected to only perform
checksum and not also overwritte the source and destination
MAC addresses.

Doing so, we can test checksum offloading with real traffic
without breaking broadcast packets.

Fixes: 10f4620f02e1 ("app/testpmd: modify mac in csum forwarding")
Cc: sta...@dpdk.org

Signed-off-by: Maxime Coquelin 
---
 app/test-pmd/csumonly.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/app/test-pmd/csumonly.c b/app/test-pmd/csumonly.c
index cdb1920763..8b6665d6f3 100644
--- a/app/test-pmd/csumonly.c
+++ b/app/test-pmd/csumonly.c
@@ -894,10 +894,6 @@ pkt_burst_checksum_forward(struct fwd_stream *fs)
 * and inner headers */
 
eth_hdr = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
-   rte_ether_addr_copy(&peer_eth_addrs[fs->peer_addr],
-   ð_hdr->dst_addr);
-   rte_ether_addr_copy(&ports[fs->tx_port].eth_addr,
-   ð_hdr->src_addr);
parse_ethernet(eth_hdr, &info);
l3_hdr = (char *)eth_hdr + info.l2_len;
 
-- 
2.35.1

[PATCH 2/6] vhost: fix missing enqueue pseudo-header calculation

[Maxime Coquelin]

The Virtio specification requires that in case of checksum
offloading, the pseudo-header checksum must be set in the
L4 header.

When received from another Vhost-user port, the packet
checksum might already contain the pseudo-header checksum
but we have no way to know it. So we have no other choice
than doing the pseudo-header checksum systematically.

This patch handles this using the rte_net_intel_cksum_prepare()
helper.

Fixes: 859b480d5afd ("vhost: add guest offload setting")
Cc: sta...@dpdk.org

Signed-off-by: Maxime Coquelin 
---
 lib/vhost/virtio_net.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/lib/vhost/virtio_net.c b/lib/vhost/virtio_net.c
index 5f432b0d77..c0ff3357a8 100644
--- a/lib/vhost/virtio_net.c
+++ b/lib/vhost/virtio_net.c
@@ -548,6 +548,16 @@ virtio_enqueue_offload(struct rte_mbuf *m_buf, struct 
virtio_net_hdr *net_hdr)
csum_l4 |= RTE_MBUF_F_TX_TCP_CKSUM;
 
if (csum_l4) {
+   /*
+* Pseudo-header checksum must be set as per Virtio spec.
+*
+* Note: We don't propagate rte_net_intel_cksum_prepare()
+* errors, as it would have an impact on performance, and an
+* error would mean the packet is dropped by the guest instead
+* of being dropped here.
+*/
+   rte_net_intel_cksum_prepare(m_buf);
+
net_hdr->flags = VIRTIO_NET_HDR_F_NEEDS_CSUM;
net_hdr->csum_start = m_buf->l2_len + m_buf->l3_len;
 
-- 
2.35.1

[PATCH 3/6] net/vhost: enable compliant offloading mode

[Maxime Coquelin]

This patch enables the compliant offloading flags mode by
default, which prevents the Rx path to set Tx offload flags,
which is illegal. A new legacy-ol-flags devarg is introduced
to enable the legacy behaviour.

Signed-off-by: Maxime Coquelin 
---
 doc/guides/nics/vhost.rst |  6 ++
 drivers/net/vhost/rte_eth_vhost.c | 19 ---
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/doc/guides/nics/vhost.rst b/doc/guides/nics/vhost.rst
index ee802ec4a8..d7c0e2ade8 100644
--- a/doc/guides/nics/vhost.rst
+++ b/doc/guides/nics/vhost.rst
@@ -64,6 +64,12 @@ The user can specify below arguments in `--vdev` option.
 It is used to enable external buffer support in vhost library.
 (Default: 0 (disabled))
 
+#.  ``legacy-ol-flags``:
+
+It is used to restore legacy behavior for offloading that was not
+compliant with offloading API.
+(Default: 0 (disabled))
+
 Vhost PMD event handling
 
 
diff --git a/drivers/net/vhost/rte_eth_vhost.c 
b/drivers/net/vhost/rte_eth_vhost.c
index 070f0e6dfd..0a2e8d9b29 100644
--- a/drivers/net/vhost/rte_eth_vhost.c
+++ b/drivers/net/vhost/rte_eth_vhost.c
@@ -31,9 +31,10 @@ enum {VIRTIO_RXQ, VIRTIO_TXQ, VIRTIO_QNUM};
 #define ETH_VHOST_CLIENT_ARG   "client"
 #define ETH_VHOST_IOMMU_SUPPORT"iommu-support"
 #define ETH_VHOST_POSTCOPY_SUPPORT "postcopy-support"
-#define ETH_VHOST_VIRTIO_NET_F_HOST_TSO "tso"
-#define ETH_VHOST_LINEAR_BUF  "linear-buffer"
-#define ETH_VHOST_EXT_BUF  "ext-buffer"
+#define ETH_VHOST_VIRTIO_NET_F_HOST_TSO"tso"
+#define ETH_VHOST_LINEAR_BUF   "linear-buffer"
+#define ETH_VHOST_EXT_BUF  "ext-buffer"
+#define ETH_VHOST_LEGACY_OL_FLAGS  "legacy-ol-flags"
 #define VHOST_MAX_PKT_BURST 32
 
 static const char *valid_arguments[] = {
@@ -1563,6 +1564,7 @@ rte_pmd_vhost_probe(struct rte_vdev_device *dev)
int tso = 0;
int linear_buf = 0;
int ext_buf = 0;
+   int legacy_ol_flags = 0;
struct rte_eth_dev *eth_dev;
const char *name = rte_vdev_device_name(dev);
 
@@ -1672,6 +1674,17 @@ rte_pmd_vhost_probe(struct rte_vdev_device *dev)
flags |= RTE_VHOST_USER_EXTBUF_SUPPORT;
}
 
+   if (rte_kvargs_count(kvlist, ETH_VHOST_LEGACY_OL_FLAGS) == 1) {
+   ret = rte_kvargs_process(kvlist,
+   ETH_VHOST_LEGACY_OL_FLAGS,
+   &open_int, &legacy_ol_flags);
+   if (ret < 0)
+   goto out_free;
+   }
+
+   if (legacy_ol_flags == 0)
+   flags |= RTE_VHOST_USER_NET_COMPLIANT_OL_FLAGS;
+
if (dev->device.numa_node == SOCKET_ID_ANY)
dev->device.numa_node = rte_socket_id();
 
-- 
2.35.1

[PATCH 5/6] net/vhost: perform SW checksum in Rx path

[Maxime Coquelin]

Virtio specification supports host checksum offloading
for L4, which is enabled with VIRTIO_NET_F_CSUM feature
negotiation. However, the Vhost PMD does not advertise
Rx checksum offload capabilities, so we can end-up with
the VIRTIO_NET_F_CSUM feature being negociated, implying
the Vhost library returns packets with checksum being
offloaded while the application did not request for it.

Advertising these offload capabilities at the ethdev level
is not enough, because we could still end-up with the
application not enabling these offloads while the guest
still negotiate them.

This patch advertizes the Rx checksum offload capabilities,
and introduces a compatibility layer to cover the case
VIRTIO_NET_F_CSUM has been negotiated but the application
does not configure the Rx checksum offloads. This function
performis the L4 Rx checksum in SW for UDP and TCP. Note
that it is not needed to calculate the pseudo-header
checksum, because the Virtio specification requires that
the driver do it.

This patch does not advertize SCTP checksum offloading
capability for now, but it could be handled later if the
need arises.

Reported-by: Jason Wang 
Signed-off-by: Maxime Coquelin 
---
 doc/guides/nics/features/vhost.ini |  1 +
 drivers/net/vhost/rte_eth_vhost.c  | 83 ++
 2 files changed, 84 insertions(+)

diff --git a/doc/guides/nics/features/vhost.ini 
b/doc/guides/nics/features/vhost.ini
index ef81abb439..15f4dfe5e8 100644
--- a/doc/guides/nics/features/vhost.ini
+++ b/doc/guides/nics/features/vhost.ini
@@ -7,6 +7,7 @@
 Link status  = Y
 Free Tx mbuf on demand = Y
 Queue status event   = Y
+L4 checksum offload  = P
 Basic stats  = Y
 Extended stats   = Y
 x86-32   = Y
diff --git a/drivers/net/vhost/rte_eth_vhost.c 
b/drivers/net/vhost/rte_eth_vhost.c
index baa973ad6d..d5303f7368 100644
--- a/drivers/net/vhost/rte_eth_vhost.c
+++ b/drivers/net/vhost/rte_eth_vhost.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -107,10 +108,12 @@ struct pmd_internal {
char *iface_name;
uint64_t flags;
uint64_t disable_flags;
+   uint64_t features;
uint16_t max_queues;
int vid;
rte_atomic32_t started;
bool vlan_strip;
+   bool rx_sw_csum;
 };
 
 struct internal_list {
@@ -362,6 +365,70 @@ vhost_update_single_packet_xstats(struct vhost_queue *vq, 
struct rte_mbuf *buf)
vhost_count_xcast_packets(vq, buf);
 }
 
+static void
+vhost_dev_csum_configure(struct rte_eth_dev *eth_dev)
+{
+   struct pmd_internal *internal = eth_dev->data->dev_private;
+   const struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
+
+   internal->rx_sw_csum = false;
+
+   /* SW checksum is not compatible with legacy mode */
+   if (!(internal->flags & RTE_VHOST_USER_NET_COMPLIANT_OL_FLAGS))
+   return;
+
+   if (internal->features & (1ULL << VIRTIO_NET_F_CSUM)) {
+   if (!(rxmode->offloads &
+   (RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 
RTE_ETH_RX_OFFLOAD_TCP_CKSUM))) {
+   VHOST_LOG(NOTICE, "Rx csum will be done in SW, may 
impact performance.");
+   internal->rx_sw_csum = true;
+   }
+   }
+}
+
+static void
+vhost_dev_rx_sw_csum(struct rte_mbuf *mbuf)
+{
+   struct rte_net_hdr_lens hdr_lens;
+   uint32_t ptype, hdr_len;
+   uint16_t csum = 0, csum_offset;
+
+   /* Return early if the L4 checksum was not offloaded */
+   if ((mbuf->ol_flags & RTE_MBUF_F_RX_L4_CKSUM_MASK) != 
RTE_MBUF_F_RX_L4_CKSUM_NONE)
+   return;
+
+   ptype = rte_net_get_ptype(mbuf, &hdr_lens, RTE_PTYPE_ALL_MASK);
+
+   hdr_len = hdr_lens.l2_len + hdr_lens.l3_len;
+
+   switch (ptype & RTE_PTYPE_L4_MASK) {
+   case RTE_PTYPE_L4_TCP:
+   csum_offset = offsetof(struct rte_tcp_hdr, cksum) + hdr_len;
+   break;
+   case RTE_PTYPE_L4_UDP:
+   csum_offset = offsetof(struct rte_udp_hdr, dgram_cksum) + 
hdr_len;
+   break;
+   default:
+   /* Unsupported packet type */
+   return;
+   }
+
+   /* The pseudo-header checksum is already performed, as per Virtio spec 
*/
+   if (rte_raw_cksum_mbuf(mbuf, hdr_len, rte_pktmbuf_pkt_len(mbuf) - 
hdr_len, &csum) < 0)
+   return;
+
+   csum = ~csum;
+   /* See RFC768 */
+   if (unlikely((ptype & RTE_PTYPE_L4_UDP) && csum == 0))
+   csum = 0x;
+
+   if (rte_pktmbuf_data_len(mbuf) >= csum_offset + 1)
+   *rte_pktmbuf_mtod_offset(mbuf, uint16_t *, csum_offset) = csum;
+
+   mbuf->ol_flags &= ~RTE_MBUF_F_RX_L4_CKSUM_MASK;
+   mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
+}
+
 static uint16_t
 eth_vhost_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
 {
@@ -402,6 +469,9 @@ eth_vhost_rx(void *q, struct rte_mbuf **bufs, uint16_t 
nb_bufs)
if

[PATCH 4/6] net/vhost: make VLAN stripping flag a boolean

[Maxime Coquelin]

This trivial patch makes the vlan_strip field of the
pmd_internal struct a boolean, since it is handled as
such.

Signed-off-by: Maxime Coquelin 
---
 drivers/net/vhost/rte_eth_vhost.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/vhost/rte_eth_vhost.c 
b/drivers/net/vhost/rte_eth_vhost.c
index 0a2e8d9b29..baa973ad6d 100644
--- a/drivers/net/vhost/rte_eth_vhost.c
+++ b/drivers/net/vhost/rte_eth_vhost.c
@@ -110,7 +110,7 @@ struct pmd_internal {
uint16_t max_queues;
int vid;
rte_atomic32_t started;
-   uint8_t vlan_strip;
+   bool vlan_strip;
 };
 
 struct internal_list {
-- 
2.35.1

[PATCH 6/6] net/vhost: perform SW checksum in Tx path

[Maxime Coquelin]

Virtio specification supports guest checksum offloading
for L4, which is enabled with VIRTIO_NET_F_GUEST_CSUM
feature negotiation. However, the Vhost PMD does not
advertise Tx checksum offload capabilities.

Advertising these offload capabilities at the ethdev level
is not enough, because we could still end-up with the
application enabling these offloads while the guest not
negotiating it.

This patch advertizes the Tx checksum offload capabilities,
and introduces a compatibility layer to cover the case
VIRTIO_NET_F_GUEST_CSUM has not been negotiated but the
application does configure the Tx checksum offloads. This
function performs the L4 Tx checksum in SW for UDP and TCP.
Compared to Rx SW checksum, the Tx SW checksum function
needs to compute the pseudo-header checksum, as we cannot
knwo whether it was done before.

This patch does not advertize SCTP checksum offloading
capability for now, but it could be handled later if the
need arises.

Reported-by: Jason Wang 
Signed-off-by: Maxime Coquelin 
---
 drivers/net/vhost/rte_eth_vhost.c | 62 +++
 1 file changed, 62 insertions(+)

diff --git a/drivers/net/vhost/rte_eth_vhost.c 
b/drivers/net/vhost/rte_eth_vhost.c
index d5303f7368..52a802de05 100644
--- a/drivers/net/vhost/rte_eth_vhost.c
+++ b/drivers/net/vhost/rte_eth_vhost.c
@@ -114,6 +114,7 @@ struct pmd_internal {
rte_atomic32_t started;
bool vlan_strip;
bool rx_sw_csum;
+   bool tx_sw_csum;
 };
 
 struct internal_list {
@@ -370,8 +371,10 @@ vhost_dev_csum_configure(struct rte_eth_dev *eth_dev)
 {
struct pmd_internal *internal = eth_dev->data->dev_private;
const struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
+   const struct rte_eth_txmode *txmode = ð_dev->data->dev_conf.txmode;
 
internal->rx_sw_csum = false;
+   internal->tx_sw_csum = false;
 
/* SW checksum is not compatible with legacy mode */
if (!(internal->flags & RTE_VHOST_USER_NET_COMPLIANT_OL_FLAGS))
@@ -384,6 +387,56 @@ vhost_dev_csum_configure(struct rte_eth_dev *eth_dev)
internal->rx_sw_csum = true;
}
}
+
+   if (!(internal->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM))) {
+   if (txmode->offloads &
+   (RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 
RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) {
+   VHOST_LOG(NOTICE, "Tx csum will be done in SW, may 
impact performance.");
+   internal->tx_sw_csum = true;
+   }
+   }
+}
+
+static void
+vhost_dev_tx_sw_csum(struct rte_mbuf *mbuf)
+{
+   uint32_t hdr_len;
+   uint16_t csum = 0, csum_offset;
+
+   switch (mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) {
+   case RTE_MBUF_F_TX_L4_NO_CKSUM:
+   return;
+   case RTE_MBUF_F_TX_TCP_CKSUM:
+   csum_offset = offsetof(struct rte_tcp_hdr, cksum);
+   break;
+   case RTE_MBUF_F_TX_UDP_CKSUM:
+   csum_offset = offsetof(struct rte_udp_hdr, dgram_cksum);
+   break;
+   default:
+   /* Unsupported packet type. */
+   return;
+   }
+
+   hdr_len = mbuf->l2_len + mbuf->l3_len;
+   csum_offset += hdr_len;
+
+   /* Prepare the pseudo-header checksum */
+   if (rte_net_intel_cksum_prepare(mbuf) < 0)
+   return;
+
+   if (rte_raw_cksum_mbuf(mbuf, hdr_len, rte_pktmbuf_pkt_len(mbuf) - 
hdr_len, &csum) < 0)
+   return;
+
+   csum = ~csum;
+   /* See RFC768 */
+   if (unlikely((mbuf->packet_type & RTE_PTYPE_L4_UDP) && csum == 0))
+   csum = 0x;
+
+   if (rte_pktmbuf_data_len(mbuf) >= csum_offset + 1)
+   *rte_pktmbuf_mtod_offset(mbuf, uint16_t *, csum_offset) = csum;
+
+   mbuf->ol_flags &= ~RTE_MBUF_F_TX_L4_MASK;
+   mbuf->ol_flags |= RTE_MBUF_F_TX_L4_NO_CKSUM;
 }
 
 static void
@@ -513,6 +566,10 @@ eth_vhost_tx(void *q, struct rte_mbuf **bufs, uint16_t 
nb_bufs)
}
}
 
+   if (r->internal->tx_sw_csum)
+   vhost_dev_tx_sw_csum(m);
+
+
bufs[nb_send] = m;
++nb_send;
}
@@ -1359,6 +1416,11 @@ eth_dev_info(struct rte_eth_dev *dev,
 
dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
+   if (internal->flags & RTE_VHOST_USER_NET_COMPLIANT_OL_FLAGS) {
+   dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
+   RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
+   }
+
dev_info->rx_offload_capa = RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
if (internal->flags & RTE_VHOST_USER_NET_COMPLIANT_OL_FLAGS) {
dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
-- 
2.35.1

RE: [dpdk-dev] [PATCH v5] ethdev: mtr: support protocol based input color selection

[Dumitrescu, Cristian]

> -Original Message-
> From: jer...@marvell.com 
> Sent: Sunday, May 1, 2022 3:47 PM
> To: dev@dpdk.org; Dumitrescu, Cristian ;
> Thomas Monjalon ; Ferruh Yigit
> ; Andrew Rybchenko
> ; Ray Kinsella 
> Cc: ajit.khapa...@broadcom.com; abo...@pensando.io; Xing, Beilei
> ; Richardson, Bruce ;
> ch...@att.com; Xia, Chenbo ; Loftus, Ciara
> ; dsinghra...@marvell.com;
> ed.cz...@atomicrules.com; evge...@amazon.com; gr...@u256.net;
> g.si...@nxp.com; zhouguoy...@huawei.com; Wang, Haiyue
> ; hka...@marvell.com; heinrich.k...@corigine.com;
> hemant.agra...@nxp.com; hyon...@cisco.com; igo...@amazon.com;
> irussk...@marvell.com; jgraj...@cisco.com; Singh, Jasvinder
> ; jianw...@trustnetic.com;
> jiawe...@trustnetic.com; Wu, Jingjing ; Daley, John
> ; john.mil...@atomicrules.com; linvi...@tuxdriver.com;
> Wiles, Keith ; kirankum...@marvell.com;
> ouli...@huawei.com; lir...@marvell.com; lon...@microsoft.com;
> m...@semihalf.com; spin...@cesnet.cz; ma...@nvidia.com; Peters, Matt
> ; maxime.coque...@redhat.com;
> m...@semihalf.com; humi...@huawei.com; pna...@marvell.com;
> ndabilpu...@marvell.com; Yang, Qiming ; Zhang,
> Qi Z ; rad...@marvell.com;
> rahul.lakkire...@chelsio.com; rm...@marvell.com; Xu, Rosen
> ; sachin.sax...@oss.nxp.com; skotesh...@marvell.com;
> shsha...@marvell.com; shaib...@amazon.com; Shepard Siegel
> ; asoma...@amd.com;
> somnath.ko...@broadcom.com; sthem...@microsoft.com; Webster, Steven
> ; sk...@marvell.com;
> mtetsu...@gmail.com; vbu...@marvell.com; viachesl...@nvidia.com; Wang,
> Xiao W ; cloud.wangxiao...@huawei.com;
> yisen.zhu...@huawei.com; Wang, Yong ;
> xuanziya...@huawei.com; Jerin Jacob 
> Subject: [dpdk-dev] [PATCH v5] ethdev: mtr: support protocol based input color
> selection
> 
> From: Jerin Jacob 
> 
> Currently, meter object supports only DSCP based on input color table,
> The patch enhance that to support VLAN based input color table,
> color table based on inner field for the tunnel use case, and
> support for fallback color per meter if packet based on a different field.
> 
> All of the above features are exposed through capability and added
> additional capability to specify the implementation supports
> more than one input color table per ethdev port.
> 
> Suggested-by: Cristian Dumitrescu 
> Signed-off-by: Jerin Jacob 
> ---
> 

Acked-by: Cristian Dumitrescu 

Thanks very much, Jerin!

[Bug 1004] Compilation error with Vtune profile option enabled

[bugzilla]

https://bugs.dpdk.org/show_bug.cgi?id=1004

Bug ID: 1004
   Summary: Compilation error with Vtune profile option enabled
   Product: DPDK
   Version: 22.03
  Hardware: All
OS: All
Status: UNCONFIRMED
  Severity: minor
  Priority: Normal
 Component: ethdev
  Assignee: dev@dpdk.org
  Reporter: aman.deep.si...@intel.com
  Target Milestone: ---

Compilation steps-
   meson build
   meson configure build -Dc_args=-DRTE_ETHDEV_PROFILE_WITH_VTUNE
   ninja -C build

Build error seen-
../lib/ethdev/ethdev_profile.c: In function ‘__rte_eth_dev_profile_init’:
../lib/ethdev/ethdev_profile.c:58:43: error: dereferencing pointer to
incomplete type ‘struct rte_eth_dev’
   58 |  return vtune_profile_rx_init(port_id, dev->data->nb_rx_queues);


Optional- fix for issue
Need to include "ethdev_driver.h" for ‘struct rte_eth_dev’ definition to be
available.

-- 
You are receiving this mail because:
You are the assignee for the bug.

[PATCH v3 01/28] common/cnxk: add multi channel support for SDP send queues

[Nithin Dabilpuram]

From: Subrahmanyam Nilla 

Currently only base channel number is configured as default
channel for all the SDP send queues. Due to this, packets
sent on different SQ's are landing on the same output queue
on the host. Channel number in the send queue should be
configured according to the number of queues assigned to the
SDP PF or VF device.

Signed-off-by: Subrahmanyam Nilla 
---
v3:
- Addressed comments from Jerin
- Removed patch 26/28 and 27/28 due to functional issues
- Added two more fixes.
v2:
- Fixed compilation issue with some compilers in patch 24/24
- Added few more fixes net/cnxk and related code in common/cnxk

 drivers/common/cnxk/roc_nix_queue.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_queue.c 
b/drivers/common/cnxk/roc_nix_queue.c
index 07dab4b..76c049c 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -706,6 +706,7 @@ static int
 sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,
 uint16_t smq)
 {
+   struct roc_nix *roc_nix = nix_priv_to_roc_nix(nix);
struct mbox *mbox = (&nix->dev)->mbox;
struct nix_aq_enq_req *aq;
 
@@ -721,7 +722,11 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, 
uint32_t rr_quantum,
aq->sq.max_sqe_size = sq->max_sqe_sz;
aq->sq.smq = smq;
aq->sq.smq_rr_quantum = rr_quantum;
-   aq->sq.default_chan = nix->tx_chan_base;
+   if (roc_nix_is_sdp(roc_nix))
+   aq->sq.default_chan =
+   nix->tx_chan_base + (sq->qid % nix->tx_chan_cnt);
+   else
+   aq->sq.default_chan = nix->tx_chan_base;
aq->sq.sqe_stype = NIX_STYPE_STF;
aq->sq.ena = 1;
aq->sq.sso_ena = !!sq->sso_ena;
-- 
2.8.4

[PATCH v3 02/28] net/cnxk: add receive channel backpressure for SDP

[Nithin Dabilpuram]

From: Radha Mohan Chintakuntla 

The SDP interfaces also need to be configured for NIX receive channel
backpressure for packet receive.

Signed-off-by: Radha Mohan Chintakuntla 
---
 drivers/common/cnxk/roc_nix_fc.c | 11 +--
 drivers/net/cnxk/cnxk_ethdev.c   |  3 +++
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c
index 8e31443..a0505bd 100644
--- a/drivers/common/cnxk/roc_nix_fc.c
+++ b/drivers/common/cnxk/roc_nix_fc.c
@@ -38,16 +38,13 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)
struct nix_bp_cfg_rsp *rsp;
int rc = -ENOSPC, i;
 
-   if (roc_nix_is_sdp(roc_nix))
-   return 0;
-
if (enable) {
req = mbox_alloc_msg_nix_bp_enable(mbox);
if (req == NULL)
return rc;
 
req->chan_base = 0;
-   if (roc_nix_is_lbk(roc_nix))
+   if (roc_nix_is_lbk(roc_nix) || roc_nix_is_sdp(roc_nix))
req->chan_cnt = NIX_LBK_MAX_CHAN;
else
req->chan_cnt = NIX_CGX_MAX_CHAN;
@@ -203,7 +200,8 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct 
roc_nix_fc_cfg *fc_cfg)
 int
 roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)
 {
-   if (roc_nix_is_vf_or_sdp(roc_nix) && !roc_nix_is_lbk(roc_nix))
+   if (!roc_nix_is_pf(roc_nix) && !roc_nix_is_lbk(roc_nix) &&
+   !roc_nix_is_sdp(roc_nix))
return 0;
 
if (fc_cfg->type == ROC_NIX_FC_CQ_CFG)
@@ -219,7 +217,8 @@ roc_nix_fc_config_get(struct roc_nix *roc_nix, struct 
roc_nix_fc_cfg *fc_cfg)
 int
 roc_nix_fc_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)
 {
-   if (roc_nix_is_vf_or_sdp(roc_nix) && !roc_nix_is_lbk(roc_nix))
+   if (!roc_nix_is_pf(roc_nix) && !roc_nix_is_lbk(roc_nix) &&
+   !roc_nix_is_sdp(roc_nix))
return 0;
 
if (fc_cfg->type == ROC_NIX_FC_CQ_CFG)
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 1fa4131..bd31a9a 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -310,6 +310,9 @@ nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
struct cnxk_fc_cfg *fc = &dev->fc_cfg;
int rc;
 
+   if (roc_nix_is_sdp(&dev->nix))
+   return 0;
+
/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
if (roc_model_is_cn96_ax() &&
dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG)
-- 
2.8.4

[PATCH v3 03/28] common/cnxk: add new pkind for CPT when ts is enabled

[Nithin Dabilpuram]

From: Vidya Sagar Velumuri 

With Timestamp enabled, time stamp will be added to second pass packets
from CPT. NPC needs different configuration to parse second pass packets
with and without timestamp.
New pkind is defined for CPT when time stamp is enabled on NIX.
CPT should use this PKIND for second pass packets when TS is enabled for
corresponding pktio.

Signed-off-by: Vidya Sagar Velumuri 
---
 drivers/common/cnxk/roc_ie_ot.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index 173cc2c..56a1e9f 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -15,6 +15,7 @@
 #define ROC_IE_OT_CTX_ILEN 2
 /* PKIND to be used for CPT Meta parsing */
 #define ROC_IE_OT_CPT_PKIND  58
+#define ROC_IE_OT_CPT_TS_PKIND   54
 #define ROC_IE_OT_SA_CTX_HDR_SIZE 1
 
 enum roc_ie_ot_ucc_ipsec {
-- 
2.8.4

[PATCH v3 05/28] common/cnxk: fix SQ flush sequence

[Nithin Dabilpuram]

From: Satha Rao 

Fix SQ flush sequence to issue NIX RX SW Sync after SMQ flush.
This sync ensures that all the packets that were inflight are
flushed out of memory.

This patch also fixes NULL return issues reported by
static analysis tool in Traffic Manager and sync's mbox
to that of Kernel version.

Fixes: 05d727e8b14a ("common/cnxk: support NIX traffic management")
Fixes: 0b7e667ee303 ("common/cnxk: enable packet marking")

Signed-off-by: Satha Rao 
---
 drivers/common/cnxk/roc_mbox.h| 35 +--
 drivers/common/cnxk/roc_nix_tm.c  |  7 +++
 drivers/common/cnxk/roc_nix_tm_mark.c |  9 +
 3 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b608f58..2c30f19 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -116,7 +116,7 @@ struct mbox_msghdr {
  msg_rsp) \
M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
  sso_grp_priority)\
-   M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
+   M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, ssow_lf_inv_req, msg_rsp) \
M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg,  \
  msg_rsp) \
M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req,   \
@@ -125,6 +125,9 @@ struct mbox_msghdr {
  sso_hws_stats)   \
M(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura,  \
  sso_hw_xaq_release, msg_rsp) \
+   M(SSO_CONFIG_LSW, 0x612, ssow_config_lsw, ssow_config_lsw, msg_rsp)\
+   M(SSO_HWS_CHNG_MSHIP, 0x613, ssow_chng_mship, ssow_chng_mship, \
+ msg_rsp) \
/* TIM mbox IDs (range 0x800 - 0x9FF) */   \
M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
  tim_lf_alloc_rsp)\
@@ -259,7 +262,8 @@ struct mbox_msghdr {
M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req,\
  nix_bp_cfg_rsp)  \
M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req,  \
- msg_rsp)
+ msg_rsp) \
+   M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp)
 
 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
 #define MBOX_UP_CGX_MESSAGES   
\
@@ -1268,6 +1272,33 @@ struct ssow_lf_free_req {
uint16_t __io hws;
 };
 
+#define SSOW_INVAL_SELECTIVE_VER 0x1000
+struct ssow_lf_inv_req {
+   struct mbox_msghdr hdr;
+   uint16_t nb_hws; /* Number of HWS to invalidate*/
+   uint16_t hws[MAX_RVU_BLKLF_CNT]; /* Array of HWS */
+};
+
+struct ssow_config_lsw {
+   struct mbox_msghdr hdr;
+#define SSOW_LSW_DIS0
+#define SSOW_LSW_GW_WAIT 1
+#define SSOW_LSW_GW_IMM 2
+   uint8_t __io lsw_mode;
+#define SSOW_WQE_REL_LSW_WAIT 0
+#define SSOW_WQE_REL_IMM  1
+   uint8_t __io wqe_release;
+};
+
+struct ssow_chng_mship {
+   struct mbox_msghdr hdr;
+   uint8_t __io set;/* Membership set to modify. */
+   uint8_t __io enable; /* Enable/Disable the hwgrps. */
+   uint8_t __io hws;/* HWS to modify. */
+   uint16_t __io nb_hwgrps; /* Number of hwgrps in the array */
+   uint16_t __io hwgrps[MAX_RVU_BLKLF_CNT]; /* Array of hwgrps. */
+};
+
 struct sso_hw_setconfig {
struct mbox_msghdr hdr;
uint32_t __io npa_aura_id;
diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index 5b70c7b..42d3abd 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -590,6 +590,7 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
struct nix_tm_node *node, *sibling;
struct nix_tm_node_list *list;
enum roc_nix_tm_tree tree;
+   struct msg_req *req;
struct mbox *mbox;
struct nix *nix;
uint16_t qid;
@@ -679,6 +680,12 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
rc);
goto cleanup;
}
+
+   req = mbox_alloc_msg_nix_rx_sw_sync(mbox);
+   if (!req)
+   return -ENOSPC;
+
+   rc = mbox_process(mbox);
 cleanup:
/* Restore cgx state */
if (!roc_nix->io_enabled) {
diff --git a/drivers/common/cnxk/roc_nix_tm_mark.c 
b/drivers/common/cnxk/roc_nix_tm_mark.c
index 64cf679..d37292e 100644
--- a/drivers/common/cnxk/roc_nix_

[PATCH v3 06/28] common/cnxk: skip probing SoC environment for CN9k

[Nithin Dabilpuram]

From: Rakesh Kudurumalla 

SoC run platform file is not present in CN9k so probing
is done for CN10k devices

Signed-off-by: Rakesh Kudurumalla 
---
 drivers/common/cnxk/roc_model.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index 1dd374e..a68baa6 100644
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -2,6 +2,9 @@
  * Copyright(C) 2021 Marvell.
  */
 
+#include 
+#include 
+
 #include "roc_api.h"
 #include "roc_priv.h"
 
@@ -211,6 +214,12 @@ of_env_get(struct roc_model *model)
uint64_t flag;
FILE *fp;
 
+   if (access(path, F_OK) != 0) {
+   strncpy(model->env, "HW_PLATFORM", ROC_MODEL_STR_LEN_MAX - 1);
+   model->flag |= ROC_ENV_HW;
+   return;
+   }
+
fp = fopen(path, "r");
if (!fp) {
plt_err("Failed to open %s", path);
-- 
2.8.4

[PATCH v3 07/28] common/cnxk: fix issues in soft expiry disable path

[Nithin Dabilpuram]

Fix issues in mode where soft expiry is disabled in RoC.
When soft expiry support is not enabled in inline device,
memory is not allocated for the ring base array and should
not be accessed.

Fixes: bea5d990a93b ("net/cnxk: support outbound soft expiry notification")
Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/cnxk/roc_nix_inl.c  | 9 +
 drivers/common/cnxk/roc_nix_inl_dev.c  | 5 +++--
 drivers/common/cnxk/roc_nix_inl_priv.h | 1 +
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c 
b/drivers/common/cnxk/roc_nix_inl.c
index d68615a..4573529 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -210,7 +210,7 @@ roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool 
inl_dev_sa)
 uintptr_t
 roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
 {
-   uint32_t max_spi, min_spi, mask;
+   uint32_t max_spi = 0, min_spi = 0, mask;
uintptr_t sa_base;
uint64_t sz;
 
@@ -463,7 +463,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
nix->outb_se_ring_base =
roc_nix->port_id * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS;
 
-   if (inl_dev == NULL) {
+   if (inl_dev == NULL || !inl_dev->set_soft_exp_poll) {
nix->outb_se_ring_cnt = 0;
return 0;
}
@@ -539,11 +539,12 @@ roc_nix_inl_outb_fini(struct roc_nix *roc_nix)
plt_free(nix->outb_sa_base);
nix->outb_sa_base = NULL;
 
-   if (idev && idev->nix_inl_dev) {
+   if (idev && idev->nix_inl_dev && nix->outb_se_ring_cnt) {
inl_dev = idev->nix_inl_dev;
ring_base = inl_dev->sa_soft_exp_ring;
+   ring_base += nix->outb_se_ring_base;
 
-   for (i = 0; i < ROC_NIX_INL_MAX_SOFT_EXP_RNGS; i++) {
+   for (i = 0; i < nix->outb_se_ring_cnt; i++) {
if (ring_base[i])
plt_free(PLT_PTR_CAST(ring_base[i]));
}
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c 
b/drivers/common/cnxk/roc_nix_inl_dev.c
index 51f1f68..5e61a42 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -814,6 +814,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
inl_dev->wqe_skip = roc_inl_dev->wqe_skip;
inl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT;
inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;
+   inl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll;
 
if (roc_inl_dev->spb_drop_pc)
inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;
@@ -849,7 +850,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
if (rc)
goto sso_release;
 
-   if (roc_inl_dev->set_soft_exp_poll) {
+   if (inl_dev->set_soft_exp_poll) {
rc = nix_inl_outb_poll_thread_setup(inl_dev);
if (rc)
goto cpt_release;
@@ -898,7 +899,7 @@ roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev)
inl_dev = idev->nix_inl_dev;
pci_dev = inl_dev->pci_dev;
 
-   if (roc_inl_dev->set_soft_exp_poll) {
+   if (inl_dev->set_soft_exp_poll) {
soft_exp_poll_thread_exit = true;
pthread_join(inl_dev->soft_exp_poll_thread, NULL);
plt_bitmap_free(inl_dev->soft_exp_ring_bmap);
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h 
b/drivers/common/cnxk/roc_nix_inl_priv.h
index f9646a3..1ab8470 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -59,6 +59,7 @@ struct nix_inl_dev {
pthread_t soft_exp_poll_thread;
uint32_t soft_exp_poll_freq;
uint64_t *sa_soft_exp_ring;
+   bool set_soft_exp_poll;
 
/* Soft expiry ring bitmap */
struct plt_bitmap *soft_exp_ring_bmap;
-- 
2.8.4

[PATCH v3 08/28] common/cnxk: convert warning to debug print

[Nithin Dabilpuram]

From: Akhil Goyal 

Inbound SA SPI if not in min-max range specified in devargs,
was marked as a warning. But this is not converted to debug
print because if the entry is found to be duplicate in the mask,
it will give another error print. Hence, warning print is not needed
and is now converted to debug print.

Signed-off-by: Akhil Goyal 
---
 drivers/common/cnxk/roc_nix_inl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c 
b/drivers/common/cnxk/roc_nix_inl.c
index 4573529..05c663d 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -223,7 +223,7 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool 
inb_inl_dev, uint32_t spi)
mask = roc_nix_inl_inb_spi_range(roc_nix, inb_inl_dev, &min_spi,
 &max_spi);
if (spi > max_spi || spi < min_spi)
-   plt_warn("Inbound SA SPI %u not in range (%u..%u)", spi,
+   plt_nix_dbg("Inbound SA SPI %u not in range (%u..%u)", spi,
 min_spi, max_spi);
 
/* Get SA size */
-- 
2.8.4

[PATCH v3 09/28] common/cnxk: use aggregate level rr prio from mbox

[Nithin Dabilpuram]

Use aggregate level Round Robin Priority from mbox response instead of
fixing it to single macro. This is useful when kernel AF driver
changes the constant.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/cnxk/roc_nix_priv.h | 5 +++--
 drivers/common/cnxk/roc_nix_tm.c   | 3 ++-
 drivers/common/cnxk/roc_nix_tm_utils.c | 8 
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_priv.h 
b/drivers/common/cnxk/roc_nix_priv.h
index 9b9ffae..cc69d71 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -181,6 +181,7 @@ struct nix {
uint16_t tm_root_lvl;
uint16_t tm_flags;
uint16_t tm_link_cfg_lvl;
+   uint8_t tm_aggr_lvl_rr_prio;
uint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];
uint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];
uint64_t tm_markfmt_en;
@@ -284,7 +285,6 @@ void nix_unregister_irqs(struct nix *nix);
 
 /* Default TL1 priority and Quantum from AF */
 #define NIX_TM_TL1_DFLT_RR_QTM ((1 << 24) - 1)
-#define NIX_TM_TL1_DFLT_RR_PRIO 1
 
 struct nix_tm_shaper_data {
uint64_t burst_exponent;
@@ -432,7 +432,8 @@ bool nix_tm_child_res_valid(struct nix_tm_node_list *list,
struct nix_tm_node *parent);
 uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig,
  uint16_t *schq, enum roc_nix_tm_tree tree);
-uint8_t nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,
+uint8_t nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq,
+   volatile uint64_t *reg,
volatile uint64_t *regval);
 uint8_t nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
 volatile uint64_t *reg,
diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index 42d3abd..7fd54ef 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -55,7 +55,7 @@ nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node 
*node)
req = mbox_alloc_msg_nix_txschq_cfg(mbox);
req->lvl = NIX_TXSCH_LVL_TL1;
 
-   k = nix_tm_tl1_default_prep(node->parent_hw_id, req->reg,
+   k = nix_tm_tl1_default_prep(nix, node->parent_hw_id, req->reg,
req->regval);
req->num_regs = k;
rc = mbox_process(mbox);
@@ -1288,6 +1288,7 @@ nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree 
tree)
} while (pend);
 
nix->tm_link_cfg_lvl = rsp->link_cfg_lvl;
+   nix->tm_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio;
return 0;
 alloc_err:
for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {
diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c 
b/drivers/common/cnxk/roc_nix_tm_utils.c
index bcdf990..b9b605f 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -478,7 +478,7 @@ nix_tm_child_res_valid(struct nix_tm_node_list *list,
 }
 
 uint8_t
-nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,
+nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq, volatile uint64_t *reg,
volatile uint64_t *regval)
 {
uint8_t k = 0;
@@ -496,7 +496,7 @@ nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t 
*reg,
k++;
 
reg[k] = NIX_AF_TL1X_TOPOLOGY(schq);
-   regval[k] = (NIX_TM_TL1_DFLT_RR_PRIO << 1);
+   regval[k] = (nix->tm_aggr_lvl_rr_prio << 1);
k++;
 
reg[k] = NIX_AF_TL1X_CIR(schq);
@@ -540,7 +540,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct 
nix_tm_node *node,
 * Static Priority is disabled
 */
if (hw_lvl == NIX_TXSCH_LVL_TL1 && nix->tm_flags & NIX_TM_TL1_NO_SP) {
-   rr_prio = NIX_TM_TL1_DFLT_RR_PRIO;
+   rr_prio = nix->tm_aggr_lvl_rr_prio;
child = 0;
}
 
@@ -662,7 +662,7 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node 
*node,
 */
if (hw_lvl == NIX_TXSCH_LVL_TL2 &&
(!nix_tm_have_tl1_access(nix) || nix->tm_flags & NIX_TM_TL1_NO_SP))
-   strict_prio = NIX_TM_TL1_DFLT_RR_PRIO;
+   strict_prio = nix->tm_aggr_lvl_rr_prio;
 
plt_tm_dbg("Schedule config node %s(%u) lvl %u id %u, "
   "prio 0x%" PRIx64 ", rr_quantum/rr_wt 0x%" PRIx64 " (%p)",
-- 
2.8.4

[PATCH v3 11/28] net/cnxk: update LBK ethdev link info

[Nithin Dabilpuram]

Update link info of LBK ethdev i.e AF's VF's as always up
and 100G. This is because there is no phy for the LBK interfaces
and we won't get a link update notification for the same.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cnxk_link.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c
index f10a502..b1d59e3 100644
--- a/drivers/net/cnxk/cnxk_link.c
+++ b/drivers/net/cnxk/cnxk_link.c
@@ -12,6 +12,17 @@ cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool 
set)
else
dev->flags &= ~CNXK_LINK_CFG_IN_PROGRESS_F;
 
+   /* Update link info for LBK */
+   if (!set && roc_nix_is_lbk(&dev->nix)) {
+   struct rte_eth_link link;
+
+   link.link_status = RTE_ETH_LINK_UP;
+   link.link_speed = RTE_ETH_SPEED_NUM_100G;
+   link.link_autoneg = RTE_ETH_LINK_FIXED;
+   link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+   rte_eth_linkstatus_set(dev->eth_dev, &link);
+   }
+
rte_wmb();
 }
 
-- 
2.8.4

[PATCH v3 10/28] net/cnxk: support loopback mode on AF VF's

[Nithin Dabilpuram]

Support internal loopback mode on AF VF's using RoC by setting
Tx channel same as Rx channel.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cnxk_ethdev.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index bd31a9a..e1b1e16 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -1119,6 +1119,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
nb_txq = RTE_MAX(data->nb_tx_queues, 1);
 
+   if (roc_nix_is_lbk(nix))
+   nix->enable_loop = eth_dev->data->dev_conf.lpbk_mode;
+
/* Alloc a nix lf */
rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
if (rc) {
@@ -1242,6 +1245,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
}
}
 
+   if (roc_nix_is_lbk(nix))
+   goto skip_lbk_setup;
+
/* Configure loop back mode */
rc = roc_nix_mac_loopback_enable(nix,
 eth_dev->data->dev_conf.lpbk_mode);
@@ -1250,6 +1256,7 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
goto cq_fini;
}
 
+skip_lbk_setup:
/* Setup Inline security support */
rc = nix_security_setup(dev);
if (rc)
-- 
2.8.4

[PATCH v3 12/28] net/cnxk: add barrier after meta batch free in scalar

[Nithin Dabilpuram]

Add barrier after meta batch free in scalar routine when
lmt lines are exactly full to make sure that next LMT line user
in Tx only starts writing the lines only when previous stoerl's
are complete.

Fixes: 4382a7ccf781 ("net/cnxk: support Rx security offload on cn10k")
Cc: sta...@dpdk.org

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_rx.h | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index e4f5a55..94c1f1e 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -1007,10 +1007,11 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf 
**rx_pkts, uint16_t pkts,
plt_write64((wdata | nb_pkts), rxq->cq_door);
 
/* Free remaining meta buffers if any */
-   if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
+   if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff)
nix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle);
-   plt_io_wmb();
-   }
+
+   if (flags & NIX_RX_OFFLOAD_SECURITY_F)
+   rte_io_wmb();
 
return nb_pkts;
 }
-- 
2.8.4

[PATCH v3 13/28] net/cnxk: disable default inner chksum for outb inline

[Nithin Dabilpuram]

Disable default inner L3/L4 checksum generation for outbound inline
path and enable based on SA options or RTE_MBUF flags as per
the spec. Though the checksum generation is not impacting much
performance, it is overwriting zero checksum for UDP packets
which is not always good.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_ethdev.h |  4 +++-
 drivers/net/cnxk/cn10k_ethdev_sec.c |  3 +++
 drivers/net/cnxk/cn10k_tx.h | 44 ++---
 3 files changed, 42 insertions(+), 9 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h
index 1e49d65..9642d6a 100644
--- a/drivers/net/cnxk/cn10k_ethdev.h
+++ b/drivers/net/cnxk/cn10k_ethdev.h
@@ -71,7 +71,9 @@ struct cn10k_sec_sess_priv {
uint8_t mode : 1;
uint8_t roundup_byte : 5;
uint8_t roundup_len;
-   uint16_t partial_len;
+   uint16_t partial_len : 10;
+   uint16_t chksum : 2;
+   uint16_t rsvd : 4;
};
 
uint64_t u64;
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c 
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 87bb691..b307215 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -552,6 +552,9 @@ cn10k_eth_sec_session_create(void *device,
sess_priv.partial_len = rlens->partial_len;
sess_priv.mode = outb_sa_dptr->w2.s.ipsec_mode;
sess_priv.outer_ip_ver = outb_sa_dptr->w2.s.outer_ip_ver;
+   /* Propagate inner checksum enable from SA to fast path */
+   sess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 |
+   !ipsec->options.l4_csum_enable);
 
/* Pointer from eth_sec -> outb_sa */
eth_sec->sa = outb_sa;
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index de88a21..981bc9b 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -246,6 +246,7 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t 
*cmd0, uint64x2_t *cmd1,
 {
struct cn10k_sec_sess_priv sess_priv;
uint32_t pkt_len, dlen_adj, rlen;
+   uint8_t l3l4type, chksum;
uint64x2_t cmd01, cmd23;
uintptr_t dptr, nixtx;
uint64_t ucode_cmd[4];
@@ -256,10 +257,23 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t 
*cmd0, uint64x2_t *cmd1,
 
sess_priv.u64 = *rte_security_dynfield(m);
 
-   if (flags & NIX_TX_NEED_SEND_HDR_W1)
+   if (flags & NIX_TX_NEED_SEND_HDR_W1) {
l2_len = vgetq_lane_u8(*cmd0, 8);
-   else
+   /* Extract l3l4type either from il3il4type or ol3ol4type */
+   if (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F &&
+   flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)
+   l3l4type = vgetq_lane_u8(*cmd0, 13);
+   else
+   l3l4type = vgetq_lane_u8(*cmd0, 12);
+
+   chksum = (l3l4type & 0x1) << 1 | !!(l3l4type & 0x30);
+   chksum = ~chksum;
+   sess_priv.chksum = sess_priv.chksum & chksum;
+   /* Clear SEND header flags */
+   *cmd0 = vsetq_lane_u16(0, *cmd0, 6);
+   } else {
l2_len = m->l2_len;
+   }
 
/* Retrieve DPTR */
dptr = vgetq_lane_u64(*cmd1, 1);
@@ -291,8 +305,8 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t 
*cmd0, uint64x2_t *cmd1,
sa_base &= ~0xUL;
sa = (uintptr_t)roc_nix_inl_ot_ipsec_outb_sa(sa_base, sess_priv.sa_idx);
ucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | 1UL << 60 | sa);
-   ucode_cmd[0] =
-   (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 | pkt_len);
+   ucode_cmd[0] = (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 |
+   ((uint64_t)sess_priv.chksum) << 32 | pkt_len);
 
/* CPT Word 0 and Word 1 */
cmd01 = vdupq_n_u64((nixtx + 16) | (cn10k_nix_tx_ext_subs(flags) + 1));
@@ -343,6 +357,7 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, 
uintptr_t *nixtx_addr,
struct cn10k_sec_sess_priv sess_priv;
uint32_t pkt_len, dlen_adj, rlen;
struct nix_send_hdr_s *send_hdr;
+   uint8_t l3l4type, chksum;
uint64x2_t cmd01, cmd23;
union nix_send_sg_s *sg;
uintptr_t dptr, nixtx;
@@ -360,10 +375,23 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, 
uintptr_t *nixtx_addr,
else
sg = (union nix_send_sg_s *)&cmd[2];
 
-   if (flags & NIX_TX_NEED_SEND_HDR_W1)
+   if (flags & NIX_TX_NEED_SEND_HDR_W1) {
l2_len = cmd[1] & 0xFF;
-   else
+   /* Extract l3l4type either from il3il4type or ol3ol4type */
+   if (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F &&
+   flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)
+

[PATCH v3 14/28] net/cnxk: fix roundup size with transport mode

[Nithin Dabilpuram]

For transport mode, roundup needs to be based on L4 data
and shouldn't include L3 length.
By including l3 length, rlen that is calculated and put in
send hdr would cross the final length of the packet in some
scenarios where padding is necessary.
Also when outer and inner checksum offload flags are enabled,
get the l2_len and l3_len from il3ptr and il4ptr.

Fixes: 55bfac717c72 ("net/cnxk: support Tx security offload on cn10k")
Cc: sta...@dpdk.org

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_tx.h | 34 ++
 1 file changed, 26 insertions(+), 8 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 981bc9b..c25825c 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -248,23 +248,29 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t 
*cmd0, uint64x2_t *cmd1,
uint32_t pkt_len, dlen_adj, rlen;
uint8_t l3l4type, chksum;
uint64x2_t cmd01, cmd23;
+   uint8_t l2_len, l3_len;
uintptr_t dptr, nixtx;
uint64_t ucode_cmd[4];
uint64_t *laddr;
-   uint8_t l2_len;
uint16_t tag;
uint64_t sa;
 
sess_priv.u64 = *rte_security_dynfield(m);
 
if (flags & NIX_TX_NEED_SEND_HDR_W1) {
-   l2_len = vgetq_lane_u8(*cmd0, 8);
/* Extract l3l4type either from il3il4type or ol3ol4type */
if (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F &&
-   flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)
+   flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) {
+   l2_len = vgetq_lane_u8(*cmd0, 10);
+   /* L4 ptr from send hdr includes l2 and l3 len */
+   l3_len = vgetq_lane_u8(*cmd0, 11) - l2_len;
l3l4type = vgetq_lane_u8(*cmd0, 13);
-   else
+   } else {
+   l2_len = vgetq_lane_u8(*cmd0, 8);
+   /* L4 ptr from send hdr includes l2 and l3 len */
+   l3_len = vgetq_lane_u8(*cmd0, 9) - l2_len;
l3l4type = vgetq_lane_u8(*cmd0, 12);
+   }
 
chksum = (l3l4type & 0x1) << 1 | !!(l3l4type & 0x30);
chksum = ~chksum;
@@ -273,6 +279,7 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t 
*cmd0, uint64x2_t *cmd1,
*cmd0 = vsetq_lane_u16(0, *cmd0, 6);
} else {
l2_len = m->l2_len;
+   l3_len = m->l3_len;
}
 
/* Retrieve DPTR */
@@ -281,6 +288,8 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t 
*cmd0, uint64x2_t *cmd1,
 
/* Calculate dlen adj */
dlen_adj = pkt_len - l2_len;
+   /* Exclude l3 len from roundup for transport mode */
+   dlen_adj -= sess_priv.mode ? 0 : l3_len;
rlen = (dlen_adj + sess_priv.roundup_len) +
   (sess_priv.roundup_byte - 1);
rlen &= ~(uint64_t)(sess_priv.roundup_byte - 1);
@@ -360,10 +369,10 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, 
uintptr_t *nixtx_addr,
uint8_t l3l4type, chksum;
uint64x2_t cmd01, cmd23;
union nix_send_sg_s *sg;
+   uint8_t l2_len, l3_len;
uintptr_t dptr, nixtx;
uint64_t ucode_cmd[4];
uint64_t *laddr;
-   uint8_t l2_len;
uint16_t tag;
uint64_t sa;
 
@@ -376,13 +385,19 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, 
uintptr_t *nixtx_addr,
sg = (union nix_send_sg_s *)&cmd[2];
 
if (flags & NIX_TX_NEED_SEND_HDR_W1) {
-   l2_len = cmd[1] & 0xFF;
/* Extract l3l4type either from il3il4type or ol3ol4type */
if (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F &&
-   flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)
+   flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) {
+   l2_len = (cmd[1] >> 16) & 0xFF;
+   /* L4 ptr from send hdr includes l2 and l3 len */
+   l3_len = ((cmd[1] >> 24) & 0xFF) - l2_len;
l3l4type = (cmd[1] >> 40) & 0xFF;
-   else
+   } else {
+   l2_len = cmd[1] & 0xFF;
+   /* L4 ptr from send hdr includes l2 and l3 len */
+   l3_len = ((cmd[1] >> 8) & 0xFF) - l2_len;
l3l4type = (cmd[1] >> 32) & 0xFF;
+   }
 
chksum = (l3l4type & 0x1) << 1 | !!(l3l4type & 0x30);
chksum = ~chksum;
@@ -391,6 +406,7 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, 
uintptr_t *nixtx_addr,
cmd[1] &= ~(0xUL << 32);
} else {
l2_len = m->l2_len;
+   l3_len = m->l3_len;
}
 
/* Retrieve DPTR */
@@ -399,6 +415,8 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, 
uintptr_t *nixtx_addr,
 
/* Calculate dlen adj */
dlen_adj = pkt_len - l2_len;
+   

[PATCH v3 15/28] net/cnxk: update inline device in ethdev telemetry

[Nithin Dabilpuram]

From: Rakesh Kudurumalla 

inline pf func is updated in ethdev_tel_handle_info
when inline device is attached to any dpdk process

Signed-off-by: Rakesh Kudurumalla 
---
 drivers/net/cnxk/cnxk_ethdev_telemetry.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev_telemetry.c 
b/drivers/net/cnxk/cnxk_ethdev_telemetry.c
index 83bc658..b76dbdf 100644
--- a/drivers/net/cnxk/cnxk_ethdev_telemetry.c
+++ b/drivers/net/cnxk/cnxk_ethdev_telemetry.c
@@ -23,6 +23,7 @@ ethdev_tel_handle_info(const char *cmd __rte_unused,
struct eth_info_s {
/** PF/VF information */
uint16_t pf_func;
+   uint16_t inl_dev_pf_func;
uint8_t max_mac_entries;
bool dmac_filter_ena;
uint8_t dmac_filter_count;
@@ -62,6 +63,8 @@ ethdev_tel_handle_info(const char *cmd __rte_unused,
info = ð_info.info;
dev = cnxk_eth_pmd_priv(eth_dev);
if (dev) {
+   info->inl_dev_pf_func =
+   roc_nix_inl_dev_pffunc_get();
info->pf_func = roc_nix_get_pf_func(&dev->nix);
info->max_mac_entries = dev->max_mac_entries;
info->dmac_filter_ena = dev->dmac_filter_enable;
-- 
2.8.4

[PATCH v3 16/28] net/cnxk: change env for debug IV

[Nithin Dabilpuram]

From: Akhil Goyal 

Changed environment variable name for specifying
debug IV for unit testing of inline IPsec offload
with known test vectors.

Signed-off-by: Akhil Goyal 
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c 
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index b307215..60b7093 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -522,10 +522,11 @@ cn10k_eth_sec_session_create(void *device,
goto mempool_put;
}
 
-   iv_str = getenv("CN10K_ETH_SEC_IV_OVR");
-   if (iv_str)
-   outb_dbg_iv_update(outb_sa_dptr, iv_str);
-
+   if (conf->ipsec.options.iv_gen_disable == 1) {
+   iv_str = getenv("ETH_SEC_IV_OVR");
+   if (iv_str)
+   outb_dbg_iv_update(outb_sa_dptr, iv_str);
+   }
/* Fill outbound sa misc params */
rc = cn10k_eth_sec_outb_sa_misc_fill(&dev->nix, outb_sa_dptr,
 outb_sa, ipsec, sa_idx);
-- 
2.8.4

[PATCH v3 17/28] net/cnxk: reset offload flag if reassembly is disabled

[Nithin Dabilpuram]

From: Akhil Goyal 

The rx offload flag need to be reset if IP reassembly flag
is not set while calling reassembly_conf_set.

Signed-off-by: Akhil Goyal 
---
 drivers/net/cnxk/cn10k_ethdev.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index b5f3c83..d04b9eb 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -547,6 +547,12 @@ cn10k_nix_reassembly_conf_set(struct rte_eth_dev *eth_dev,
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
int rc = 0;
 
+   if (!conf->flags) {
+   /* Clear offload flags on disable */
+   dev->rx_offload_flags &= ~NIX_RX_REAS_F;
+   return 0;
+   }
+
rc = roc_nix_reassembly_configure(conf->timeout_ms,
conf->max_frags);
if (!rc && dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
-- 
2.8.4

[PATCH v3 18/28] net/cnxk: support decrement TTL for inline IPsec

[Nithin Dabilpuram]

From: Akhil Goyal 

Added support for decrementing TTL(IPv4)/hoplimit(IPv6)
while doing inline IPsec processing if the security session
sa options is enabled with dec_ttl.

Signed-off-by: Akhil Goyal 
---
 drivers/net/cnxk/cn10k_ethdev.h | 3 ++-
 drivers/net/cnxk/cn10k_ethdev_sec.c | 1 +
 drivers/net/cnxk/cn10k_tx.h | 6 --
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h
index 9642d6a..c8666ce 100644
--- a/drivers/net/cnxk/cn10k_ethdev.h
+++ b/drivers/net/cnxk/cn10k_ethdev.h
@@ -73,7 +73,8 @@ struct cn10k_sec_sess_priv {
uint8_t roundup_len;
uint16_t partial_len : 10;
uint16_t chksum : 2;
-   uint16_t rsvd : 4;
+   uint16_t dec_ttl : 1;
+   uint16_t rsvd : 3;
};
 
uint64_t u64;
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c 
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 60b7093..f32e169 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -556,6 +556,7 @@ cn10k_eth_sec_session_create(void *device,
/* Propagate inner checksum enable from SA to fast path */
sess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 |
!ipsec->options.l4_csum_enable);
+   sess_priv.dec_ttl = ipsec->options.dec_ttl;
 
/* Pointer from eth_sec -> outb_sa */
eth_sec->sa = outb_sa;
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index c25825c..c482352 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -315,7 +315,8 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t 
*cmd0, uint64x2_t *cmd1,
sa = (uintptr_t)roc_nix_inl_ot_ipsec_outb_sa(sa_base, sess_priv.sa_idx);
ucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | 1UL << 60 | sa);
ucode_cmd[0] = (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 |
-   ((uint64_t)sess_priv.chksum) << 32 | pkt_len);
+   ((uint64_t)sess_priv.chksum) << 32 |
+   ((uint64_t)sess_priv.dec_ttl) << 34 | pkt_len);
 
/* CPT Word 0 and Word 1 */
cmd01 = vdupq_n_u64((nixtx + 16) | (cn10k_nix_tx_ext_subs(flags) + 1));
@@ -442,7 +443,8 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, 
uintptr_t *nixtx_addr,
sa = (uintptr_t)roc_nix_inl_ot_ipsec_outb_sa(sa_base, sess_priv.sa_idx);
ucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | 1UL << 60 | sa);
ucode_cmd[0] = (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 |
-   ((uint64_t)sess_priv.chksum) << 32 | pkt_len);
+   ((uint64_t)sess_priv.chksum) << 32 |
+   ((uint64_t)sess_priv.dec_ttl) << 34 | pkt_len);
 
/* CPT Word 0 and Word 1. Assume no multi-seg support */
cmd01 = vdupq_n_u64((nixtx + 16) | (cn10k_nix_tx_ext_subs(flags) + 1));
-- 
2.8.4

[PATCH v3 19/28] net/cnxk: optimize Rx fast path for security pkts

[Nithin Dabilpuram]

Optimize Rx fast path for security pkts by preprocessing
most of the operations such as sa pointer compute,
inner wqe pointer fetch and ucode completion translation
before the pkt is characterized as inbound inline pkt.
Preprocessed info will be discarded if pkt is not
found to be security pkt. Also fix fetching of CQ word5
for vector mode. Get ucode completion code from CPT parse
header and RLEN from IP4v/IPv6 decrypted packet as it is
in same 64B cacheline as CPT parse header in most of
the cases. By this method, we avoid accessing an extra
cacheline

Fixes: c062f5726f61 ("net/cnxk: support IP reassembly")

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_rx.h | 488 +++-
 1 file changed, 306 insertions(+), 182 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 94c1f1e..14b634e 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -341,6 +341,9 @@ nix_sec_reassemble_frags(const struct cpt_parse_hdr_s *hdr, 
uint64_t cq_w1,
mbuf->data_len = frag_size;
fragx_sum += frag_size;
 
+   /* Mark frag as get */
+   RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
+
/* Frag-2: */
if (hdr->w0.num_frags > 2) {
frag_ptr = (uint64_t *)(finfo + 1);
@@ -354,6 +357,9 @@ nix_sec_reassemble_frags(const struct cpt_parse_hdr_s *hdr, 
uint64_t cq_w1,
*(uint64_t *)(&mbuf->rearm_data) = mbuf_init | data_off;
mbuf->data_len = frag_size;
fragx_sum += frag_size;
+
+   /* Mark frag as get */
+   RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
}
 
/* Frag-3: */
@@ -368,6 +374,9 @@ nix_sec_reassemble_frags(const struct cpt_parse_hdr_s *hdr, 
uint64_t cq_w1,
*(uint64_t *)(&mbuf->rearm_data) = mbuf_init | data_off;
mbuf->data_len = frag_size;
fragx_sum += frag_size;
+
+   /* Mark frag as get */
+   RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
}
 
if (inner_rx->lctype == NPC_LT_LC_IP) {
@@ -413,10 +422,10 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, 
const uint64_t sa_base,
const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)__p;
struct cn10k_inb_priv_data *inb_priv;
struct rte_mbuf *inner = NULL;
-   uint64_t res_w1;
uint32_t sa_idx;
-   uint16_t uc_cc;
+   uint16_t ucc;
uint32_t len;
+   uintptr_t ip;
void *inb_sa;
uint64_t w0;
 
@@ -438,20 +447,23 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, 
const uint64_t sa_base,
*rte_security_dynfield(inner) =
(uint64_t)inb_priv->userdata;
 
-   /* CPT result(struct cpt_cn10k_res_s) is at
-* after first IOVA in meta
+   /* Get ucc from cpt parse header */
+   ucc = hdr->w3.hw_ccode;
+
+   /* Calculate inner packet length as
+* IP total len + l2 len
 */
-   res_w1 = *((uint64_t *)(&inner[1]) + 10);
-   uc_cc = res_w1 & 0xFF;
+   ip = (uintptr_t)hdr + ((cq_w5 >> 16) & 0xFF);
+   ip += ((cq_w1 >> 40) & 0x6);
+   len = rte_be_to_cpu_16(*(uint16_t *)ip);
+   len += ((cq_w5 >> 16) & 0xFF) - (cq_w5 & 0xFF);
+   len += (cq_w1 & BIT(42)) ? 40 : 0;
 
-   /* Calculate inner packet length */
-   len = ((res_w1 >> 16) & 0x) + hdr->w2.il3_off -
-   sizeof(struct cpt_parse_hdr_s) - (w0 & 0x7);
inner->pkt_len = len;
inner->data_len = len;
*(uint64_t *)(&inner->rearm_data) = mbuf_init;
 
-   inner->ol_flags = ((uc_cc == CPT_COMP_WARN) ?
+   inner->ol_flags = ((ucc == CPT_COMP_WARN) ?
   RTE_MBUF_F_RX_SEC_OFFLOAD :
   (RTE_MBUF_F_RX_SEC_OFFLOAD |
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED));
@@ -477,6 +489,12 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, 
const uint64_t sa_base,
*(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf;
*loff = *loff + 1;
 
+   /* Mark meta mbuf as put */
+   RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 0);
+
+   /* Mark inner mbuf as get */
+   RTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1);
+
return inner;
} else if (cq_w1 & BIT(11)) {
inner = (struct rte_mbuf *)(rte_be_to_cpu_64(hdr->wqe_ptr) -
@@

[PATCH v3 20/28] net/cnxk: update olflags with L3/L4 csum offload

[Nithin Dabilpuram]

From: Akhil Goyal 

When the packet is processed with inline IPsec offload,
the ol_flags were updated only with RTE_MBUF_F_RX_SEC_OFFLOAD.
But the hardware can also update the L3/L4 csum offload flags.
Hence, ol_flags are updated with RTE_MBUF_F_RX_IP_CKSUM_GOOD,
RTE_MBUF_F_RX_L4_CKSUM_GOOD, etc based on the microcode completion
codes.

Signed-off-by: Akhil Goyal 
Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_rx.h | 51 -
 1 file changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 14b634e..00bec01 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -42,6 +42,18 @@
 (uint64_t *)(((uintptr_t)((uint64_t *)(b))[i]) - (o)) :   \
   (uint64_t *)(((uintptr_t)(b)) + CQE_SZ(i) - (o)))
 
+#define NIX_RX_SEC_UCC_CONST   
\
+   ((RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1) << 8 |  \
+((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1)\
+<< 24 |   \
+((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1) \
+<< 32 |   \
+((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1)\
+<< 40 |   \
+((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1)\
+<< 48 |   \
+(RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1) << 56)
+
 #ifdef RTE_LIBRTE_MEMPOOL_DEBUG
 static inline void
 nix_mbuf_validate_next(struct rte_mbuf *m)
@@ -467,6 +479,11 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, 
const uint64_t sa_base,
   RTE_MBUF_F_RX_SEC_OFFLOAD :
   (RTE_MBUF_F_RX_SEC_OFFLOAD |
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED));
+
+   ucc = hdr->w3.uc_ccode;
+   inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?
+   ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))
+& 0xFF) << 1 : 0;
} else if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) {
/* Reassembly success */
inner = nix_sec_reassemble_frags(hdr, cq_w1, cq_w5,
@@ -529,6 +546,11 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, 
const uint64_t sa_base,
   (RTE_MBUF_F_RX_SEC_OFFLOAD |
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED));
 
+   ucc = hdr->w3.uc_ccode;
+   inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?
+   ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))
+& 0xFF) << 1 : 0;
+
/* Store meta in lmtline to free
 * Assume all meta's from same aura.
 */
@@ -1313,7 +1335,26 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf 
**mbufs, uint16_t pkts,
sa23 = vaddq_u64(sa23, vdupq_n_u64(sa_base));
 
const uint8x16_t tbl = {
-   0, 0, 0, 0, 0, 0, 0, 0,
+   /* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST */
+   0,
+   /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM */
+   RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
+   /* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN */
+   0,
+   /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM */
+   (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
+RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
+   /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM */
+   (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
+RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
+   /* ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM */
+   (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
+RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
+   /* ROC_IE_OT_UCC_SUCCESS_PKT_UDP_ZEROCSUM */
+   (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
+RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
+   /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM */
+   RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1,
/* HW_CCODE -> RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED 
*/
1, 0, 1, 1, 1, 1, 0, 1,
};
@@ -1419,6 +1460,8 @@ cn10k_ni

[PATCH v3 21/28] net/cnxk: add capabilities for IPsec crypto algos

[Nithin Dabilpuram]

From: Akhil Goyal 

Added supported crypto algorithms for inline IPsec
offload.

Signed-off-by: Akhil Goyal 
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 166 
 1 file changed, 166 insertions(+)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c 
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index f32e169..6a3e636 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -62,6 +62,46 @@ static struct rte_cryptodev_capabilities 
cn10k_eth_sec_crypto_caps[] = {
}, }
}, }
},
+   {   /* AES CTR */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   {.sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+   {.cipher = {
+   .algo = RTE_CRYPTO_CIPHER_AES_CTR,
+   .block_size = 16,
+   .key_size = {
+   .min = 16,
+   .max = 32,
+   .increment = 8
+   },
+   .iv_size = {
+   .min = 12,
+   .max = 16,
+   .increment = 4
+   }
+   }, }
+   }, }
+   },
+   {   /* AES-XCBC */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   { .sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   {.auth = {
+   .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
+   .block_size = 16,
+   .key_size = {
+   .min = 16,
+   .max = 16,
+   .increment = 0
+   },
+   .digest_size = {
+   .min = 12,
+   .max = 12,
+   .increment = 0,
+   },
+   }, }
+   }, }
+   },
{   /* SHA1 HMAC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
@@ -82,6 +122,132 @@ static struct rte_cryptodev_capabilities 
cn10k_eth_sec_crypto_caps[] = {
}, }
}, }
},
+   {   /* SHA256 HMAC */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   {.sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   {.auth = {
+   .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
+   .block_size = 64,
+   .key_size = {
+   .min = 1,
+   .max = 1024,
+   .increment = 1
+   },
+   .digest_size = {
+   .min = 16,
+   .max = 32,
+   .increment = 16
+   },
+   }, }
+   }, }
+   },
+   {   /* SHA384 HMAC */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   {.sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   {.auth = {
+   .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+   .block_size = 64,
+   .key_size = {
+   .min = 1,
+   .max = 1024,
+   .increment = 1
+   },
+   .digest_size = {
+   .min = 24,
+   .max = 48,
+   .increment = 24
+   },
+   }, }
+   }, }
+   },
+   {   /* SHA512 HMAC */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   {.sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   {.auth = {
+   .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
+   .block_size = 128,
+   .key_size = {
+   .min = 1,
+   .max = 1024,
+   .increment = 1
+   },
+   .digest_size = {
+  

[PATCH v3 22/28] net/cnxk: add capabilities for IPsec options

[Nithin Dabilpuram]

From: Akhil Goyal 

Added supported capabilities for various IPsec SA options.

Signed-off-by: Akhil Goyal 
Signed-off-by: Vamsi Attunuru 
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 57 ++---
 1 file changed, 53 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c 
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 6a3e636..7e4941d 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -259,7 +259,20 @@ static const struct rte_security_capability 
cn10k_eth_sec_capabilities[] = {
.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
.mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,
.direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,
-   .options = { 0 }
+   .replay_win_sz_max = ROC_AR_WIN_SIZE_MAX,
+   .options = {
+   .udp_encap = 1,
+   .udp_ports_verify = 1,
+   .copy_df = 1,
+   .copy_dscp = 1,
+   .copy_flabel = 1,
+   .tunnel_hdr_verify = 
RTE_SECURITY_IPSEC_TUNNEL_VERIFY_SRC_DST_ADDR,
+   .dec_ttl = 1,
+   .ip_csum_enable = 1,
+   .l4_csum_enable = 1,
+   .stats = 0,
+   .esn = 1,
+   },
},
.crypto_capabilities = cn10k_eth_sec_crypto_caps,
.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA
@@ -271,7 +284,20 @@ static const struct rte_security_capability 
cn10k_eth_sec_capabilities[] = {
.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
.mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,
.direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,
-   .options = { 0 }
+   .replay_win_sz_max = ROC_AR_WIN_SIZE_MAX,
+   .options = {
+   .iv_gen_disable = 1,
+   .udp_encap = 1,
+   .udp_ports_verify = 1,
+   .copy_df = 1,
+   .copy_dscp = 1,
+   .copy_flabel = 1,
+   .dec_ttl = 1,
+   .ip_csum_enable = 1,
+   .l4_csum_enable = 1,
+   .stats = 0,
+   .esn = 1,
+   },
},
.crypto_capabilities = cn10k_eth_sec_crypto_caps,
.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA
@@ -283,7 +309,19 @@ static const struct rte_security_capability 
cn10k_eth_sec_capabilities[] = {
.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
.mode = RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT,
.direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,
-   .options = { 0 }
+   .replay_win_sz_max = ROC_AR_WIN_SIZE_MAX,
+   .options = {
+   .iv_gen_disable = 1,
+   .udp_encap = 1,
+   .udp_ports_verify = 1,
+   .copy_df = 1,
+   .copy_dscp = 1,
+   .dec_ttl = 1,
+   .ip_csum_enable = 1,
+   .l4_csum_enable = 1,
+   .stats = 0,
+   .esn = 1,
+   },
},
.crypto_capabilities = cn10k_eth_sec_crypto_caps,
.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA
@@ -295,7 +333,18 @@ static const struct rte_security_capability 
cn10k_eth_sec_capabilities[] = {
.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
.mode = RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT,
.direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,
-   .options = { 0 }
+   .replay_win_sz_max = ROC_AR_WIN_SIZE_MAX,
+   .options = {
+   .udp_encap = 1,
+   .udp_ports_verify = 1,
+   .copy_df = 1,
+   .copy_dscp = 1,
+   .dec_ttl = 1,
+   .ip_csum_enable = 1,
+   .l4_csum_enable = 1,
+   .stats = 0,
+   .esn = 1,
+   },
},
.crypto_capabilities = cn10k_eth_sec_crypto_caps,
.ol_flags = RTE_SECURITY_TX_OLOAD

[PATCH v3 23/28] net/cnxk: support security stats

[Nithin Dabilpuram]

From: Akhil Goyal 

Enabled rte_security stats operation based on the configuration
of SA options set while creating session.

Signed-off-by: Vamsi Attunuru 
Signed-off-by: Akhil Goyal 
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 56 ++---
 1 file changed, 52 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c 
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 7e4941d..7c4988b 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -270,7 +270,7 @@ static const struct rte_security_capability 
cn10k_eth_sec_capabilities[] = {
.dec_ttl = 1,
.ip_csum_enable = 1,
.l4_csum_enable = 1,
-   .stats = 0,
+   .stats = 1,
.esn = 1,
},
},
@@ -295,7 +295,7 @@ static const struct rte_security_capability 
cn10k_eth_sec_capabilities[] = {
.dec_ttl = 1,
.ip_csum_enable = 1,
.l4_csum_enable = 1,
-   .stats = 0,
+   .stats = 1,
.esn = 1,
},
},
@@ -319,7 +319,7 @@ static const struct rte_security_capability 
cn10k_eth_sec_capabilities[] = {
.dec_ttl = 1,
.ip_csum_enable = 1,
.l4_csum_enable = 1,
-   .stats = 0,
+   .stats = 1,
.esn = 1,
},
},
@@ -342,7 +342,7 @@ static const struct rte_security_capability 
cn10k_eth_sec_capabilities[] = {
.dec_ttl = 1,
.ip_csum_enable = 1,
.l4_csum_enable = 1,
-   .stats = 0,
+   .stats = 1,
.esn = 1,
},
},
@@ -679,6 +679,11 @@ cn10k_eth_sec_session_create(void *device,
inb_sa_dptr->w1.s.cookie =
rte_cpu_to_be_32(ipsec->spi & spi_mask);
 
+   if (ipsec->options.stats == 1) {
+   /* Enable mib counters */
+   inb_sa_dptr->w0.s.count_mib_bytes = 1;
+   inb_sa_dptr->w0.s.count_mib_pkts = 1;
+   }
/* Prepare session priv */
sess_priv.inb_sa = 1;
sess_priv.sa_idx = ipsec->spi & spi_mask;
@@ -761,6 +766,12 @@ cn10k_eth_sec_session_create(void *device,
/* Save rlen info */
cnxk_ipsec_outb_rlens_get(rlens, ipsec, crypto);
 
+   if (ipsec->options.stats == 1) {
+   /* Enable mib counters */
+   outb_sa_dptr->w0.s.count_mib_bytes = 1;
+   outb_sa_dptr->w0.s.count_mib_pkts = 1;
+   }
+
/* Prepare session priv */
sess_priv.sa_idx = outb_priv->sa_idx;
sess_priv.roundup_byte = rlens->roundup_byte;
@@ -877,6 +888,42 @@ cn10k_eth_sec_capabilities_get(void *device __rte_unused)
return cn10k_eth_sec_capabilities;
 }
 
+static int
+cn10k_eth_sec_session_stats_get(void *device, struct rte_security_session 
*sess,
+   struct rte_security_stats *stats)
+{
+   struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device;
+   struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+   struct cnxk_eth_sec_sess *eth_sec;
+   int rc;
+
+   eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess);
+   if (eth_sec == NULL)
+   return -EINVAL;
+
+   rc = roc_nix_inl_sa_sync(&dev->nix, eth_sec->sa, eth_sec->inb,
+   ROC_NIX_INL_SA_OP_FLUSH);
+   if (rc)
+   return -EINVAL;
+   rte_delay_ms(1);
+
+   stats->protocol = RTE_SECURITY_PROTOCOL_IPSEC;
+
+   if (eth_sec->inb) {
+   stats->ipsec.ipackets =
+   ((struct roc_ot_ipsec_inb_sa 
*)eth_sec->sa)->ctx.mib_pkts;
+   stats->ipsec.ibytes =
+   ((struct roc_ot_ipsec_inb_sa 
*)eth_sec->sa)->ctx.mib_octs;
+   } else {
+   stats->ipsec.opackets =
+   ((struct roc_ot_ipsec_outb_sa 
*)eth_sec->sa)->ctx.mib_pkts;
+   stats->ipsec.obytes =
+   ((struct roc_ot_ipsec_outb_sa 
*)eth_sec->sa)->ctx.mib_octs;
+   }
+
+   return 0;
+}
+
 void
 cn10k_eth_sec_ops_override(void)
 {
@@ -890,4 +937,5 @@ cn10k_eth_sec_ops_override(void)
cnxk_eth_sec_ops.session_create = cn10k_eth_sec_session_create;
cnxk_eth_sec_ops.session_destroy = 

[PATCH v3 24/28] net/cnxk: add support for flow control for outbound inline

[Nithin Dabilpuram]

Add support for flow control in outbound inline path using
fc updates from CPT.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_ethdev.c |  3 +++
 drivers/net/cnxk/cn10k_ethdev.h |  1 +
 drivers/net/cnxk/cn10k_tx.h | 37 -
 drivers/net/cnxk/cnxk_ethdev.c  | 13 +
 drivers/net/cnxk/cnxk_ethdev.h  |  3 +++
 5 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index d04b9eb..de688f0 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -204,6 +204,9 @@ cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, 
uint16_t qid,
 
txq->cpt_io_addr = inl_lf->io_addr;
txq->cpt_fc = inl_lf->fc_addr;
+   txq->cpt_fc_sw = (int32_t *)((uintptr_t)dev->outb.fc_sw_mem +
+crypto_qid * RTE_CACHE_LINE_SIZE);
+
txq->cpt_desc = inl_lf->nb_desc * 0.7;
txq->sa_base = (uint64_t)dev->outb.sa_base;
txq->sa_base |= eth_dev->data->port_id;
diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h
index c8666ce..acfdbb6 100644
--- a/drivers/net/cnxk/cn10k_ethdev.h
+++ b/drivers/net/cnxk/cn10k_ethdev.h
@@ -19,6 +19,7 @@ struct cn10k_eth_txq {
uint64_t sa_base;
uint64_t *cpt_fc;
uint16_t cpt_desc;
+   int32_t *cpt_fc_sw;
uint64_t lso_tun_fmt;
uint64_t ts_mem;
uint64_t mark_flag : 8;
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index c482352..762586f 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -209,6 +209,37 @@ cn10k_nix_tx_skeleton(struct cn10k_eth_txq *txq, uint64_t 
*cmd,
 }
 
 static __rte_always_inline void
+cn10k_nix_sec_fc_wait(struct cn10k_eth_txq *txq, uint16_t nb_pkts)
+{
+   int32_t nb_desc, val, newval;
+   int32_t *fc_sw;
+   volatile uint64_t *fc;
+
+   /* Check if there is any CPT instruction to submit */
+   if (!nb_pkts)
+   return;
+
+again:
+   fc_sw = txq->cpt_fc_sw;
+   val = __atomic_sub_fetch(fc_sw, nb_pkts, __ATOMIC_RELAXED);
+   if (likely(val >= 0))
+   return;
+
+   nb_desc = txq->cpt_desc;
+   fc = txq->cpt_fc;
+   while (true) {
+   newval = nb_desc - __atomic_load_n(fc, __ATOMIC_RELAXED);
+   newval -= nb_pkts;
+   if (newval >= 0)
+   break;
+   }
+
+   if (!__atomic_compare_exchange_n(fc_sw, &val, newval, false,
+__ATOMIC_RELAXED, __ATOMIC_RELAXED))
+   goto again;
+}
+
+static __rte_always_inline void
 cn10k_nix_sec_steorl(uintptr_t io_addr, uint32_t lmt_id, uint8_t lnum,
 uint8_t loff, uint8_t shft)
 {
@@ -995,6 +1026,7 @@ cn10k_nix_xmit_pkts(void *tx_queue, uint64_t *ws, struct 
rte_mbuf **tx_pkts,
if (flags & NIX_TX_OFFLOAD_SECURITY_F) {
/* Reduce pkts to be sent to CPT */
burst -= ((c_lnum << 1) + c_loff);
+   cn10k_nix_sec_fc_wait(txq, (c_lnum << 1) + c_loff);
cn10k_nix_sec_steorl(c_io_addr, c_lmt_id, c_lnum, c_loff,
 c_shft);
}
@@ -1138,6 +1170,7 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t *ws,
if (flags & NIX_TX_OFFLOAD_SECURITY_F) {
/* Reduce pkts to be sent to CPT */
burst -= ((c_lnum << 1) + c_loff);
+   cn10k_nix_sec_fc_wait(txq, (c_lnum << 1) + c_loff);
cn10k_nix_sec_steorl(c_io_addr, c_lmt_id, c_lnum, c_loff,
 c_shft);
}
@@ -2682,9 +2715,11 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,
left -= burst;
 
/* Submit CPT instructions if any */
-   if (flags & NIX_TX_OFFLOAD_SECURITY_F)
+   if (flags & NIX_TX_OFFLOAD_SECURITY_F) {
+   cn10k_nix_sec_fc_wait(txq, (c_lnum << 1) + c_loff);
cn10k_nix_sec_steorl(c_io_addr, c_lmt_id, c_lnum, c_loff,
 c_shft);
+   }
 
/* Trigger LMTST */
if (lnum > 16) {
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index e1b1e16..12ff30f 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -155,9 +155,19 @@ nix_security_setup(struct cnxk_eth_dev *dev)
dev->outb.sa_base = roc_nix_inl_outb_sa_base_get(nix);
dev->outb.sa_bmap_mem = mem;
dev->outb.sa_bmap = bmap;
+
+   dev->outb.fc_sw_mem = plt_zmalloc(dev->outb.nb_crypto_qs *
+ RTE_CACHE_LINE_SIZE,
+ RTE_CACHE_LINE_SIZE);
+   if (!dev->outb.fc_sw_mem) {
+   plt_err("Outbound fc sw mem alloc fail

[PATCH v3 25/28] net/cnxk: perform early MTU setup for eventmode

[Nithin Dabilpuram]

Perform early MTU setup for event mode path in order
to update the Rx/Tx offload flags before Rx adapter setup
starts.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_ethdev.c | 11 +++
 drivers/net/cnxk/cn9k_ethdev.c  | 11 +++
 2 files changed, 22 insertions(+)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index de688f0..bc9e10f 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -248,6 +248,17 @@ cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, 
uint16_t qid,
if (rc)
return rc;
 
+   /* Do initial mtu setup for RQ0 before device start */
+   if (!qid) {
+   rc = nix_recalc_mtu(eth_dev);
+   if (rc)
+   return rc;
+
+   /* Update offload flags */
+   dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
+   dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
+   }
+
rq = &dev->rqs[qid];
cq = &dev->cqs[qid];
 
diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c
index 18cc27e..de33fa7 100644
--- a/drivers/net/cnxk/cn9k_ethdev.c
+++ b/drivers/net/cnxk/cn9k_ethdev.c
@@ -241,6 +241,17 @@ cn9k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, 
uint16_t qid,
if (rc)
return rc;
 
+   /* Do initial mtu setup for RQ0 before device start */
+   if (!qid) {
+   rc = nix_recalc_mtu(eth_dev);
+   if (rc)
+   return rc;
+
+   /* Update offload flags */
+   dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
+   dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
+   }
+
rq = &dev->rqs[qid];
cq = &dev->cqs[qid];
 
-- 
2.8.4

[PATCH v3 26/28] net/cnxk: fix multi-seg extraction in vwqe path

[Nithin Dabilpuram]

Fix multi-seg extraction in vwqe path to avoid updating mbuf[]
array until it is used via cq0 path.

Fixes: 7fbbc981d54f ("event/cnxk: support vectorized Rx event fast path")
Cc: pbhagavat...@marvell.com
Cc: sta...@dpdk.org

Signed-off-by: Nithin Dabilpuram 
Acked-by: Pavan Nikhilesh 
---
 drivers/net/cnxk/cn10k_rx.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 00bec01..5ecb20f 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -1673,10 +1673,6 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf 
**mbufs, uint16_t pkts,
vst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);
vst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);
 
-   /* Store the mbufs to rx_pkts */
-   vst1q_u64((uint64_t *)&mbufs[packets], mbuf01);
-   vst1q_u64((uint64_t *)&mbufs[packets + 2], mbuf23);
-
if (flags & NIX_RX_MULTI_SEG_F) {
/* Multi segment is enable build mseg list for
 * individual mbufs in scalar mode.
@@ -1695,6 +1691,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf 
**mbufs, uint16_t pkts,
mbuf3, mbuf_initializer, flags);
}
 
+   /* Store the mbufs to rx_pkts */
+   vst1q_u64((uint64_t *)&mbufs[packets], mbuf01);
+   vst1q_u64((uint64_t *)&mbufs[packets + 2], mbuf23);
+
/* Mark mempool obj as "get" as it is alloc'ed by NIX */
RTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1);
RTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1);
-- 
2.8.4

[PATCH v3 27/28] net/cnxk: fix hotplug detach sequence for first device

[Nithin Dabilpuram]

Fix hotplug detach sequence to handle case where first PCI
device that is hosting NPA LF is being destroyed while in use.

Fixes: 5a4341c84979 ("net/cnxk: add platform specific probe and remove")
Cc: sta...@dpdk.org

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_ethdev.c | 6 +-
 drivers/net/cnxk/cn9k_ethdev.c  | 6 +-
 drivers/net/cnxk/cnxk_ethdev.c  | 8 
 3 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index bc9e10f..96eeae4 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -778,8 +778,12 @@ cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct 
rte_pci_device *pci_dev)
 
/* Find eth dev allocated */
eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
-   if (!eth_dev)
+   if (!eth_dev) {
+   /* Ignore if ethdev is in mid of detach state in secondary */
+   if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+   return 0;
return -ENOENT;
+   }
 
if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
/* Setup callbacks for secondary process */
diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c
index de33fa7..b46f5da 100644
--- a/drivers/net/cnxk/cn9k_ethdev.c
+++ b/drivers/net/cnxk/cn9k_ethdev.c
@@ -708,8 +708,12 @@ cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct 
rte_pci_device *pci_dev)
 
/* Find eth dev allocated */
eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
-   if (!eth_dev)
+   if (!eth_dev) {
+   /* Ignore if ethdev is in mid of detach state in secondary */
+   if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+   return 0;
return -ENOENT;
+   }
 
if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
/* Setup callbacks for secondary process */
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 12ff30f..3912c24 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -1781,9 +1781,6 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool 
reset)
struct rte_eth_fc_conf fc_conf;
int rc, i;
 
-   /* Disable switch hdr pkind */
-   roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0);
-
plt_free(eth_dev->security_ctx);
eth_dev->security_ctx = NULL;
 
@@ -1791,6 +1788,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool 
reset)
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
 
+   /* Disable switch hdr pkind */
+   roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0);
+
/* Clear the flag since we are closing down */
dev->configured = 0;
 
@@ -1927,7 +1927,7 @@ cnxk_nix_remove(struct rte_pci_device *pci_dev)
 
/* Check if this device is hosting common resource */
nix = roc_idev_npa_nix_get();
-   if (nix->pci_dev != pci_dev)
+   if (!nix || nix->pci_dev != pci_dev)
return 0;
 
/* Try nix fini now */
-- 
2.8.4

[PATCH v3 04/28] common/cnxk: support to configure the ts pkind in CPT

[Nithin Dabilpuram]

From: Vidya Sagar Velumuri 

Add new API to configure the SA table entries with new CPT PKIND
when timestamp is enabled.

Signed-off-by: Vidya Sagar Velumuri 
Acked-by: Ray Kinsella 
---
 drivers/common/cnxk/roc_nix_inl.c  | 59 ++
 drivers/common/cnxk/roc_nix_inl.h  |  2 ++
 drivers/common/cnxk/roc_nix_inl_priv.h |  1 +
 drivers/common/cnxk/version.map|  1 +
 4 files changed, 63 insertions(+)

diff --git a/drivers/common/cnxk/roc_nix_inl.c 
b/drivers/common/cnxk/roc_nix_inl.c
index 569b7f6..d68615a 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -1013,6 +1013,65 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void 
*sa_dptr, void *sa_cptr,
return -ENOTSUP;
 }
 
+int
+roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool 
inb_inl_dev)
+{
+   struct idev_cfg *idev = idev_get_cfg();
+   struct nix_inl_dev *inl_dev = NULL;
+   void *sa, *sa_base = NULL;
+   struct nix *nix = NULL;
+   uint16_t max_spi = 0;
+   uint8_t pkind = 0;
+   int i;
+
+   if (roc_model_is_cn9k())
+   return 0;
+
+   if (!inb_inl_dev && (roc_nix == NULL))
+   return -EINVAL;
+
+   if (inb_inl_dev) {
+   if ((idev == NULL) || (idev->nix_inl_dev == NULL))
+   return 0;
+   inl_dev = idev->nix_inl_dev;
+   } else {
+   nix = roc_nix_to_nix_priv(roc_nix);
+   if (!nix->inl_inb_ena)
+   return 0;
+   sa_base = nix->inb_sa_base;
+   max_spi = roc_nix->ipsec_in_max_spi;
+   }
+
+   if (inl_dev) {
+   if (inl_dev->rq_refs == 0) {
+   inl_dev->ts_ena = ts_ena;
+   max_spi = inl_dev->ipsec_in_max_spi;
+   sa_base = inl_dev->inb_sa_base;
+   } else if (inl_dev->ts_ena != ts_ena) {
+   if (inl_dev->ts_ena)
+   plt_err("Inline device is already configured 
with TS enable");
+   else
+   plt_err("Inline device is already configured 
with TS disable");
+   return -ENOTSUP;
+   } else {
+   return 0;
+   }
+   }
+
+   pkind = ts_ena ? ROC_IE_OT_CPT_TS_PKIND : ROC_IE_OT_CPT_PKIND;
+
+   sa = (uint8_t *)sa_base;
+   if (pkind == ((struct roc_ot_ipsec_inb_sa *)sa)->w0.s.pkind)
+   return 0;
+
+   for (i = 0; i < max_spi; i++) {
+   sa = ((uint8_t *)sa_base) +
+(i * ROC_NIX_INL_OT_IPSEC_INB_SA_SZ);
+   ((struct roc_ot_ipsec_inb_sa *)sa)->w0.s.pkind = pkind;
+   }
+   return 0;
+}
+
 void
 roc_nix_inl_dev_lock(void)
 {
diff --git a/drivers/common/cnxk/roc_nix_inl.h 
b/drivers/common/cnxk/roc_nix_inl.h
index 2c2a4d7..633f090 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -174,6 +174,8 @@ int __roc_api roc_nix_inl_inb_tag_update(struct roc_nix 
*roc_nix,
 uint64_t __roc_api roc_nix_inl_dev_rq_limit_get(void);
 int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time,
uint16_t max_frags);
+int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena,
+  bool inb_inl_dev);
 
 /* NIX Inline Outbound API */
 int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h 
b/drivers/common/cnxk/roc_nix_inl_priv.h
index 0fa5e09..f9646a3 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -76,6 +76,7 @@ struct nix_inl_dev {
uint32_t inb_spi_mask;
bool attach_cptlf;
bool wqe_skip;
+   bool ts_ena;
 };
 
 int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 2a122e5..53586da 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -159,6 +159,7 @@ INTERNAL {
roc_nix_inl_outb_is_enabled;
roc_nix_inl_outb_soft_exp_poll_switch;
roc_nix_inl_sa_sync;
+   roc_nix_inl_ts_pkind_set;
roc_nix_inl_ctx_write;
roc_nix_inl_dev_pffunc_get;
roc_nix_cpt_ctx_cache_sync;
-- 
2.8.4

[PATCH v3 28/28] common/cnxk: add support for per-port RQ in inline device

[Nithin Dabilpuram]

Add support for per port RQ in inline device thereby using
Aura/Pool attributes from that port specific first RQ.
When inline device is used with channel masking, it will
fallback to single RQ for all ethdev ports.

Also remove clamping up of CQ size for LBK ethdev when
inline inbound is enabled as now backpressure is supported
even on LBK ethdevs.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/cnxk/roc_nix.h |   2 +-
 drivers/common/cnxk/roc_nix_debug.c   |   7 +-
 drivers/common/cnxk/roc_nix_inl.c |  81 
 drivers/common/cnxk/roc_nix_inl.h |   5 +-
 drivers/common/cnxk/roc_nix_inl_dev.c |  42 ++--
 drivers/common/cnxk/roc_nix_inl_dev_irq.c | 155 +++---
 drivers/common/cnxk/roc_nix_inl_priv.h|  12 ++-
 drivers/common/cnxk/roc_npc.c |  13 ++-
 drivers/common/cnxk/version.map   |   1 -
 drivers/net/cnxk/cnxk_ethdev.c|  14 +--
 10 files changed, 202 insertions(+), 130 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 1019e37..1c38af0 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -309,7 +309,7 @@ struct roc_nix_rq {
bool spb_drop_ena;
/* End of Input parameters */
struct roc_nix *roc_nix;
-   bool inl_dev_ref;
+   uint16_t inl_dev_refs;
 };
 
 struct roc_nix_cq {
diff --git a/drivers/common/cnxk/roc_nix_debug.c 
b/drivers/common/cnxk/roc_nix_debug.c
index 1ae0451..e05e60d 100644
--- a/drivers/common/cnxk/roc_nix_debug.c
+++ b/drivers/common/cnxk/roc_nix_debug.c
@@ -826,7 +826,7 @@ roc_nix_rq_dump(struct roc_nix_rq *rq)
nix_dump("  vwqe_wait_tmo = %ld", rq->vwqe_wait_tmo);
nix_dump("  vwqe_aura_handle = %ld", rq->vwqe_aura_handle);
nix_dump("  roc_nix = %p", rq->roc_nix);
-   nix_dump("  inl_dev_ref = %d", rq->inl_dev_ref);
+   nix_dump("  inl_dev_refs = %d", rq->inl_dev_refs);
 }
 
 void
@@ -1243,6 +1243,7 @@ roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev)
struct nix_inl_dev *inl_dev =
(struct nix_inl_dev *)&roc_inl_dev->reserved;
struct dev *dev = &inl_dev->dev;
+   int i;
 
nix_dump("nix_inl_dev@%p", inl_dev);
nix_dump("  pf = %d", dev_get_pf(dev->pf_func));
@@ -1259,7 +1260,6 @@ roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev)
nix_dump("  \tssow_msixoff = %d", inl_dev->ssow_msixoff);
nix_dump("  \tnix_cints = %d", inl_dev->cints);
nix_dump("  \tnix_qints = %d", inl_dev->qints);
-   nix_dump("  \trq_refs = %d", inl_dev->rq_refs);
nix_dump("  \tinb_sa_base = 0x%p", inl_dev->inb_sa_base);
nix_dump("  \tinb_sa_sz = %d", inl_dev->inb_sa_sz);
nix_dump("  \txaq_buf_size = %u", inl_dev->xaq_buf_size);
@@ -1269,5 +1269,6 @@ roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev)
nix_dump("  \txaq_mem = 0x%p", inl_dev->xaq.mem);
 
nix_dump("  \tinl_dev_rq:");
-   roc_nix_rq_dump(&inl_dev->rq);
+   for (i = 0; i < inl_dev->nb_rqs; i++)
+   roc_nix_rq_dump(&inl_dev->rqs[i]);
 }
diff --git a/drivers/common/cnxk/roc_nix_inl.c 
b/drivers/common/cnxk/roc_nix_inl.c
index 05c663d..28d01b0 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -585,8 +585,10 @@ int
 roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
 {
struct idev_cfg *idev = idev_get_cfg();
+   int port_id = rq->roc_nix->port_id;
struct nix_inl_dev *inl_dev;
struct roc_nix_rq *inl_rq;
+   uint16_t inl_rq_id;
struct dev *dev;
int rc;
 
@@ -598,19 +600,24 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
if (!inl_dev)
return 0;
 
+   /* Check if this RQ is already holding reference */
+   if (rq->inl_dev_refs)
+   return 0;
+
+   inl_rq_id = inl_dev->nb_rqs > 1 ? port_id : 0;
+   dev = &inl_dev->dev;
+   inl_rq = &inl_dev->rqs[inl_rq_id];
+
/* Just take reference if already inited */
-   if (inl_dev->rq_refs) {
-   inl_dev->rq_refs++;
-   rq->inl_dev_ref = true;
+   if (inl_rq->inl_dev_refs) {
+   inl_rq->inl_dev_refs++;
+   rq->inl_dev_refs = 1;
return 0;
}
-
-   dev = &inl_dev->dev;
-   inl_rq = &inl_dev->rq;
memset(inl_rq, 0, sizeof(struct roc_nix_rq));
 
/* Take RQ pool attributes from the first ethdev RQ */
-   inl_rq->qid = 0;
+   inl_rq->qid = inl_rq_id;
inl_rq->aura_handle = rq->aura_handle;
inl_rq->first_skip = rq->first_skip;
inl_rq->later_skip = rq->later_skip;
@@ -688,8 +695,8 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
return rc;
}
 
-   inl_dev->rq_refs++;
-   rq->inl_dev_ref = true;
+   inl_rq->inl_dev_refs++;
+   rq->inl_dev_refs = 1;
return 0;
 }
 
@@ -697,15 +704,17 @@ int
 roc_nix_inl_dev_rq_put(

[PATCH] ethdev: fix compilation issue with vtune option

[Aman Singh]

When VTune profile option is enabled, compilation
error is seen.

Bugzilla ID: 1004
Fixes: 2c1bbab7f09d ("ethdev: change vtune profiling approach")
Cc: ilia.kura...@intel.com

Signed-off-by: Aman Singh 
---
 lib/ethdev/ethdev_profile.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/ethdev/ethdev_profile.h b/lib/ethdev/ethdev_profile.h
index e5ee4df824..881aec1273 100644
--- a/lib/ethdev/ethdev_profile.h
+++ b/lib/ethdev/ethdev_profile.h
@@ -6,6 +6,7 @@
 #define _RTE_ETHDEV_PROFILE_H_
 
 #include "rte_ethdev.h"
+#include "ethdev_driver.h"
 
 /**
  * Initialization of the Ethernet device profiling.
-- 
2.25.1

Re: [PATCH] net/virtio: support NAPI when using vhost_net backend

[Maxime Coquelin]

Hi Harold,

On 3/2/22 10:41, Harold Huang wrote:

In patch [1], NAPI has been supported in kernel tun driver to accelerate
packet processing received from vhost_net. This will greatly improve the
throughput of the tap device in the vhost_net backend.

[1]: 
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=fb3f903769e8

Signed-off-by: Harold Huang 
---
  drivers/net/virtio/virtio_user/vhost_kernel.c | 9 +++--
  drivers/net/virtio/virtio_user/vhost_kernel_tap.c | 4 ++--
  drivers/net/virtio/virtio_user/vhost_kernel_tap.h | 3 ++-
  3 files changed, 11 insertions(+), 5 deletions(-)



Reviewed-by: Maxime Coquelin 

Thanks,
Maxime

Re: [PATCH] net/vhost: fix access to freed memory

[Maxime Coquelin]

Hi Yuan,

On 3/11/22 17:35, Yuan Wang wrote:

This patch fixes heap-use-after-free reported by ASan.

It is possible for the rte_vhost_dequeue_burst() to access the vq
is freed when numa_realloc() gets called in the device running state.
The control plane will set the vq->access_lock to protected the vq
from the data plane. Unfortunately the lock will fail at the moment
the vq is freed, allowing the rte_vhost_dequeue_burst() to access
the fields of the vq, which will trigger a heap-use-after-free error.

In the case of multiple queues, the vhost pmd can access other queues
that are not ready when the first queue is ready, which makes no sense
and also allows numa_realloc() and rte_vhost_dequeue_burst() access to
vq to happen at the same time. By controlling vq->allow_queuing we can make
the pmd access only the queues that are ready.

Fixes: 1ce3c7fe149 ("net/vhost: emulate device start/stop behavior")

Signed-off-by: Yuan Wang 
---
  drivers/net/vhost/rte_eth_vhost.c | 15 +--
  1 file changed, 13 insertions(+), 2 deletions(-)


It is indeed better for the Vhost PMD to not access virtqueues that
aren't ready.

Reviewed-by: Maxime Coquelin 

Thanks,
Maxime

Re: [PATCH] net/vhost: get csum offload capabilities of vhost backend

[Maxime Coquelin]

Hi Wenwu,

On 2/17/22 16:16, Wenwu Ma wrote:

The current vhost backend lacks csum offloads information,
which will cause testpmd command such as "csum set tcp hw
" to fail. This patch adds the information according
to the device features.

Signed-off-by: Wenwu Ma 
---
  drivers/net/vhost/rte_eth_vhost.c | 18 ++
  1 file changed, 18 insertions(+)

diff --git a/drivers/net/vhost/rte_eth_vhost.c 
b/drivers/net/vhost/rte_eth_vhost.c
index 070f0e6dfd..7593d5a9ae 100644
--- a/drivers/net/vhost/rte_eth_vhost.c
+++ b/drivers/net/vhost/rte_eth_vhost.c
@@ -1281,6 +1281,24 @@ eth_dev_info(struct rte_eth_dev *dev,
RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
dev_info->rx_offload_capa = RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
  
+	if (internal->vid != -1) {

+   uint64_t features = 0;
+   if (rte_vhost_get_negotiated_features(internal->vid, &features) 
!= 0)
+   return 0;
+
+   if (features & (1ULL << VIRTIO_NET_F_CSUM)) {
+   dev_info->tx_offload_capa |= 
RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
+   RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
+   RTE_ETH_TX_OFFLOAD_IPV4_CKSUM;
+   }
+
+   if (features & (1ULL << VIRTIO_NET_F_GUEST_CSUM)) {
+   dev_info->rx_offload_capa |= 
RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
+   RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
+   RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
+   }
+   }
+
return 0;
  }
  



This patch has lots of gaps, since the negotiated Virtio features can
change if the guest driver decides so, so the exposed ethdev offload
capabilities may not represent what is really supported by the guest
driver.

I have done a series that handles this issue by implementing SW
fallbacks in case of misalignment between host application and guest
application:

http://patches.dpdk.org/project/dpdk/cover/20220505102729.821075-1-maxime.coque...@redhat.com/

Please help reviewing & testing the series if possible.

Thanks,
Maxime

Re: [PATCH 1/2] vhost: remove unneeded max enums

[Maxime Coquelin]

Hi David,

On 4/25/22 14:54, David Marchand wrote:

Move message handler description and callbacks into a single array and
remove unneeded VHOST_USER_MAX and VHOST_SLAVE_MAX enums.

Signed-off-by: David Marchand 
---
  drivers/net/virtio/virtio_user/vhost_user.c |   1 -
  examples/vhost_blk/blk_spec.h   |   1 -
  lib/vhost/vhost_user.c  | 175 +---
  lib/vhost/vhost_user.h  |   2 -
  4 files changed, 76 insertions(+), 103 deletions(-)



The patch does a bit more than what the commit title mentions.
What about: "vhost: refactor messages handlers declaration"?

Other than that, the patch content looks good to me:

Reviewed-by: Maxime Coquelin 

Thanks,
Maxime

[PATCH 1/2] config/arm: add SVE control flag

[Rahul Bhansali]

This add the control flag for SVE to enable or disable
RTE_HAS_SVE_ACLE macro in the build.

Signed-off-by: Rahul Bhansali 
---
 config/arm/meson.build | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 8aead74086..dafb342cc6 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
 compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
 endif
 
-if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
+if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
+soc_config.get('sve', true))
 compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
 if (cc.check_header('arm_sve.h'))
 dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
-- 
2.25.1

[PATCH 2/2] config/arm: disable SVE for cn10k

[Rahul Bhansali]

This disable the SVE flag for cn10k.

Performance impact:-
With l3fwd example, lpm lookup performance increased
by ~21% if Neon is used instead of SVE.

Signed-off-by: Rahul Bhansali 
---
 config/arm/meson.build | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index dafb342cc6..39b7a1270c 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -281,7 +281,8 @@ soc_cn10k = {
 ],
 'part_number': '0xd49',
 'extra_march_features': ['crypto'],
-'numa': false
+'numa': false,
+'sve': false
 }
 
 soc_dpaa = {
-- 
2.25.1

Re: [PATCH 2/2] vhost: validate fds attached to messages

[Maxime Coquelin]

On 4/25/22 14:54, David Marchand wrote:

Some message handlers do not expect any file descriptor attached as
ancillary data.
Provide a common way to enforce this by adding a accepts_fd boolean in
the message handler structure. When a message handler sets accepts_fd to
true, it is responsible for calling validate_msg_fds with a right
expected file descriptor count.
This will avoid leaking some file descriptor by mistake when adding
support for new vhost user message types.

Signed-off-by: David Marchand 
---
  lib/vhost/vhost_user.c | 145 -
  1 file changed, 43 insertions(+), 102 deletions(-)



Reviewed-by: Maxime Coquelin 

Thanks,
Maxime

Re: [PATCH 1/2] config/arm: add SVE control flag

[Bruce Richardson]

On Thu, May 05, 2022 at 07:57:43PM +0530, Rahul Bhansali wrote:
> This add the control flag for SVE to enable or disable
> RTE_HAS_SVE_ACLE macro in the build.
> 
> Signed-off-by: Rahul Bhansali 
> ---
>  config/arm/meson.build | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 8aead74086..dafb342cc6 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args) != '' 
> or
>  compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
>  endif
>  
> -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
> +soc_config.get('sve', true))

Please double-indent this so that it does not line up with the following
lines of the block.

>  compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
>  if (cc.check_header('arm_sve.h'))
>  dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
> -- 
> 2.25.1
> 

RE: [EXT] [PATCH 0/3] add partial SGL support to AESNI_MB

[De Lara Guarch, Pablo]

Hi Akhil,

> -Original Message-
> From: Akhil Goyal 
> Sent: Monday, May 2, 2022 10:48 AM
> To: Power, Ciara ; dev@dpdk.org; De Lara Guarch,
> Pablo 
> Cc: Zhang, Roy Fan ; Ji, Kai 
> Subject: RE: [EXT] [PATCH 0/3] add partial SGL support to AESNI_MB
> 
> Hi Pablo,
> Can you review this series?
> 

Sure, will do between today and tomorrow.

Thanks,
Pablo

> Regards,
> Akhil
> > This patchset adds SGL support for GCM and CHACHA20-POLY1305
> > algorithms, using the IPSec-MB JOB API.
> >
> > Supported SGL types:
> >  - INPLACE SGL
> >  - OOP SGL IN, LB OUT
> >  - OOP SGL IN, SGL OUT
> >
> > The SGL Feature Flags for AESNI_MB PMD are not added, as it does not
> > yet support SGL for all other algorithms.
> >
> > Ciara Power (3):
> >   crypto/ipsec_mb: add GCM sgl support to aesni_mb
> >   crypto/ipsec_mb: add chachapoly SGL support to aesni_mb
> >   crypto/ipsec_mb: check SGL support for algorithm
> >
> >  drivers/crypto/ipsec_mb/pmd_aesni_mb.c  | 160 +++-
> >  drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h |   5 +
> >  2 files changed, 160 insertions(+), 5 deletions(-)
> >
> > --
> > 2.25.1

[PATCH v1 1/5] net/ark: update mpu code to match current hardware version

[Ed Czeck]

new version code
remove device-level global operations
remove ark_mpu_reset_stats function

Signed-off-by: Ed Czeck 
---
 drivers/net/ark/ark_ethdev.c|  2 --
 drivers/net/ark/ark_ethdev_rx.c |  4 
 drivers/net/ark/ark_mpu.c   | 21 -
 drivers/net/ark/ark_mpu.h   | 29 ++---
 4 files changed, 6 insertions(+), 50 deletions(-)

diff --git a/drivers/net/ark/ark_ethdev.c b/drivers/net/ark/ark_ethdev.c
index 76b88c62d0..c0578b85ce 100644
--- a/drivers/net/ark/ark_ethdev.c
+++ b/drivers/net/ark/ark_ethdev.c
@@ -524,7 +524,6 @@ ark_config_device(struct rte_eth_dev *dev)
num_q = ark_api_num_queues(mpu);
ark->rx_queues = num_q;
for (i = 0; i < num_q; i++) {
-   ark_mpu_reset(mpu);
mpu = RTE_PTR_ADD(mpu, ARK_MPU_QOFFSET);
}
 
@@ -536,7 +535,6 @@ ark_config_device(struct rte_eth_dev *dev)
num_q = ark_api_num_queues(mpu);
ark->tx_queues = num_q;
for (i = 0; i < num_q; i++) {
-   ark_mpu_reset(mpu);
mpu = RTE_PTR_ADD(mpu, ARK_MPU_QOFFSET);
}
 
diff --git a/drivers/net/ark/ark_ethdev_rx.c b/drivers/net/ark/ark_ethdev_rx.c
index 0fbb2603db..85e34d0bb8 100644
--- a/drivers/net/ark/ark_ethdev_rx.c
+++ b/drivers/net/ark/ark_ethdev_rx.c
@@ -91,9 +91,6 @@ eth_ark_rx_hw_setup(struct rte_eth_dev *dev,
 
ark_udm_write_addr(queue->udm, phys_addr_prod_index);
 
-   /* advance the valid pointer, but don't start until the queue starts */
-   ark_mpu_reset_stats(queue->mpu);
-
/* The seed is the producer index for the HW */
ark_mpu_set_producer(queue->mpu, queue->seed_index);
dev->data->rx_queue_state[rx_queue_idx] = RTE_ETH_QUEUE_STATE_STOPPED;
@@ -589,7 +586,6 @@ eth_rx_queue_stats_reset(void *vqueue)
if (queue == 0)
return;
 
-   ark_mpu_reset_stats(queue->mpu);
ark_udm_queue_stats_reset(queue->udm);
 }
 
diff --git a/drivers/net/ark/ark_mpu.c b/drivers/net/ark/ark_mpu.c
index b8e94b6ed3..9d5ee7841b 100644
--- a/drivers/net/ark/ark_mpu.c
+++ b/drivers/net/ark/ark_mpu.c
@@ -24,10 +24,10 @@ ark_mpu_verify(struct ark_mpu_t *mpu, uint32_t obj_size)
 {
uint32_t version;
 
-   version = mpu->id.vernum & 0xfF00;
-   if ((mpu->id.idnum != 0x2055504d) ||
-   (mpu->hw.obj_size != obj_size) ||
-   (version != 0x3100)) {
+   version = mpu->id.vernum;
+   if (mpu->id.idnum != ARK_MPU_MODID ||
+   version != ARK_MPU_MODVER ||
+   mpu->hw.obj_size != obj_size) {
ARK_PMD_LOG(ERR,
"   MPU module not found as expected %08x"
" \"%c%c%c%c %c%c%c%c\"\n",
@@ -79,16 +79,9 @@ ark_mpu_reset(struct ark_mpu_t *mpu)
mpu->cfg.command = MPU_CMD_FORCE_RESET;
usleep(10);
}
-   ark_mpu_reset_stats(mpu);
return mpu->cfg.command != MPU_CMD_IDLE;
 }
 
-void
-ark_mpu_reset_stats(struct ark_mpu_t *mpu)
-{
-   mpu->stats.pci_request = 1; /* reset stats */
-}
-
 int
 ark_mpu_configure(struct ark_mpu_t *mpu, rte_iova_t ring, uint32_t ring_size,
  int is_tx)
@@ -118,12 +111,6 @@ ark_mpu_dump(struct ark_mpu_t *mpu, const char *code, 
uint16_t qid)
ARK_PMD_LOG(DEBUG, "MPU: %s Q: %3u sw_prod %u, hw_cons: %u\n",
  code, qid,
  mpu->cfg.sw_prod_index, mpu->cfg.hw_cons_index);
-   ARK_PMD_LOG(DEBUG, "MPU: %s state: %d count %d, reserved %d"
- "\n",
- code,
- mpu->debug.state, mpu->debug.count,
- mpu->debug.reserved
- );
 }
 
 void
diff --git a/drivers/net/ark/ark_mpu.h b/drivers/net/ark/ark_mpu.h
index 92c3e67c86..9d2b70d35f 100644
--- a/drivers/net/ark/ark_mpu.h
+++ b/drivers/net/ark/ark_mpu.h
@@ -15,6 +15,8 @@
  * there is minimal documentation.
  */
 
+#define ARK_MPU_MODID 0x2055504d
+#define ARK_MPU_MODVER 0x37313232
 /*
  * MPU hardware structures
  * These are overlay structures to a memory mapped FPGA device.  These
@@ -64,26 +66,6 @@ enum ARK_MPU_COMMAND {
MPU_COMMAND_LIMIT = 0xfFFF
 };
 
-#define ARK_MPU_STATS 0x080
-struct ark_mpu_stats_t {
-   volatile uint64_t pci_request;
-   volatile uint64_t q_empty;
-   volatile uint64_t q_q1;
-   volatile uint64_t q_q2;
-   volatile uint64_t q_q3;
-   volatile uint64_t q_q4;
-   volatile uint64_t q_full;
-};
-
-#define ARK_MPU_DEBUG 0x0C0
-struct ark_mpu_debug_t {
-   volatile uint32_t state;
-   uint32_t reserved;
-   volatile uint32_t count;
-   volatile uint32_t take;
-   volatile uint32_t peek[4];
-};
-
 /*  Consolidated structure */
 struct ark_mpu_t {
struct ark_mpu_id_t id;
@@ -93,12 +75,6 @@ struct ark_mpu_t {
uint8_t reserved1[(ARK_MPU_CFG - ARK_MPU_HW) -
  sizeof(struct ark_mpu_hw_t)];
struct ark_mpu_cfg_t

[PATCH v1 2/5] net/ark: update ddm code to match current hardware version

[Ed Czeck]

new version code
remove device-level start, stop, and reset operations
add queue-based start, stop and reset as required by hardware

Signed-off-by: Ed Czeck 
---
 drivers/net/ark/ark_ddm.c   | 80 +-
 drivers/net/ark/ark_ddm.h   | 86 +
 drivers/net/ark/ark_ethdev.c| 33 -
 drivers/net/ark/ark_ethdev_tx.c | 35 +++---
 4 files changed, 40 insertions(+), 194 deletions(-)

diff --git a/drivers/net/ark/ark_ddm.c b/drivers/net/ark/ark_ddm.c
index b16c739d50..eb88349b7b 100644
--- a/drivers/net/ark/ark_ddm.c
+++ b/drivers/net/ark/ark_ddm.c
@@ -14,95 +14,45 @@ int
 ark_ddm_verify(struct ark_ddm_t *ddm)
 {
uint32_t hw_const;
+   uint32_t hw_ver;
if (sizeof(struct ark_ddm_t) != ARK_DDM_EXPECTED_SIZE) {
ARK_PMD_LOG(ERR, "DDM structure looks incorrect %d vs %zd\n",
ARK_DDM_EXPECTED_SIZE, sizeof(struct ark_ddm_t));
return -1;
}
 
-   hw_const = ddm->cfg.const0;
-   if (hw_const == ARK_DDM_CONST3)
+   hw_const = ddm->cfg.idnum;
+   hw_ver = ddm->cfg.vernum;
+   if (hw_const == ARK_DDM_MODID && hw_ver == ARK_DDM_MODVER)
return 0;
 
-   if (hw_const == ARK_DDM_CONST1) {
-   ARK_PMD_LOG(ERR,
-   "ARK: DDM module is version 1, "
-   "PMD expects version 2\n");
-   return -1;
-   }
-
-   if (hw_const == ARK_DDM_CONST2) {
-   ARK_PMD_LOG(ERR,
-   "ARK: DDM module is version 2, "
-   "PMD expects version 3\n");
-   return -1;
-   }
ARK_PMD_LOG(ERR,
-   "ARK: DDM module not found as expected 0x%08x\n",
-   ddm->cfg.const0);
+   "ARK: DDM module not found as expected"
+   " id: %08x ver: %08x\n",
+   hw_const, hw_ver);
return -1;
 }
 
 void
-ark_ddm_start(struct ark_ddm_t *ddm)
-{
-   ddm->cfg.command = 1;
-}
-
-int
-ark_ddm_stop(struct ark_ddm_t *ddm, const int wait)
+ark_ddm_queue_enable(struct ark_ddm_t *ddm, int enable)
 {
-   int cnt = 0;
-
-   ddm->cfg.command = 2;
-   rte_wmb();
-   while (wait && (ddm->cfg.stop_flushed & 0x01) == 0) {
-   if (cnt++ > 1000)
-   return 1;
-
-   usleep(10);
-   }
-   return 0;
+   ddm->setup.qcommand = enable ? 1U : 0U;
 }
 
 void
-ark_ddm_reset(struct ark_ddm_t *ddm)
-{
-   int status;
-
-   /* reset only works if ddm has stopped properly. */
-   status = ark_ddm_stop(ddm, 1);
-
-   if (status != 0) {
-   ARK_PMD_LOG(NOTICE, "%s  stop failed  doing forced reset\n",
- __func__);
-   ddm->cfg.command = 4;
-   usleep(10);
-   }
-   ddm->cfg.command = 3;
-}
-
-void
-ark_ddm_setup(struct ark_ddm_t *ddm, rte_iova_t cons_addr, uint32_t interval)
+ark_ddm_queue_setup(struct ark_ddm_t *ddm, rte_iova_t cons_addr)
 {
ddm->setup.cons_write_index_addr = cons_addr;
-   ddm->setup.write_index_interval = interval / 4; /* 4 ns period */
+   ddm->setup.cons_index = 0;
 }
 
+/* Global stats clear */
 void
 ark_ddm_stats_reset(struct ark_ddm_t *ddm)
 {
ddm->cfg.tlp_stats_clear = 1;
 }
 
-void
-ark_ddm_dump(struct ark_ddm_t *ddm, const char *msg)
-{
-   ARK_PMD_LOG(DEBUG, "%s Stopped: %d\n", msg,
-ark_ddm_is_stopped(ddm)
-);
-}
-
 void
 ark_ddm_dump_stats(struct ark_ddm_t *ddm, const char *msg)
 {
@@ -116,12 +66,6 @@ ark_ddm_dump_stats(struct ark_ddm_t *ddm, const char *msg)
  "MBufs", stats->tx_mbuf_count);
 }
 
-int
-ark_ddm_is_stopped(struct ark_ddm_t *ddm)
-{
-   return (ddm->cfg.stop_flushed & 0x01) != 0;
-}
-
 uint64_t
 ark_ddm_queue_byte_count(struct ark_ddm_t *ddm)
 {
diff --git a/drivers/net/ark/ark_ddm.h b/drivers/net/ark/ark_ddm.h
index 687ff2519a..84beeb063a 100644
--- a/drivers/net/ark/ark_ddm.h
+++ b/drivers/net/ark/ark_ddm.h
@@ -40,17 +40,24 @@ union ark_tx_meta {
  */
 #define ARK_DDM_CFG 0x
 /* Set unique HW ID for hardware version */
-#define ARK_DDM_CONST3 (0x334d)
-#define ARK_DDM_CONST2 (0x324d)
-#define ARK_DDM_CONST1 (0xfacecafe)
+#define ARK_DDM_MODID 0x204d
+#define ARK_DDM_MODVER 0x37313232
 
 struct ark_ddm_cfg_t {
+   union {
+   char id[4];
+   uint32_t idnum;
+   };
+   union {
+   char ver[4];
+   uint32_t vernum;
+   volatile uint32_t tlp_stats_clear;
+   };
uint32_t r0;
-   volatile uint32_t tlp_stats_clear;
-   uint32_t const0;
volatile uint32_t tag_max;
volatile uint32_t command;
-   volatile uint32_t stop_flushed;
+   uint32_t write_index_interval;  /* 4ns each */
+   volatile uint64_t qflow;
 };
 
 #define ARK_DDM_STATS 0x0020

[PATCH v1 3/5] net/ark: update udm code to match current hardware version

[Ed Czeck]

new version code
remove device-level start, stop, and reset operations
add queue-based start, stop and reset as required by hardware
remove performance structs as they are not in the hardware module

Signed-off-by: Ed Czeck 
---
 drivers/net/ark/ark_ethdev.c|  34 +--
 drivers/net/ark/ark_ethdev_rx.c |  38 +---
 drivers/net/ark/ark_ethdev_rx.h |   1 -
 drivers/net/ark/ark_udm.c   | 103 +++-
 drivers/net/ark/ark_udm.h   |  73 +-
 5 files changed, 27 insertions(+), 222 deletions(-)

diff --git a/drivers/net/ark/ark_ethdev.c b/drivers/net/ark/ark_ethdev.c
index 07d1d2178d..8b4daa819b 100644
--- a/drivers/net/ark/ark_ethdev.c
+++ b/drivers/net/ark/ark_ethdev.c
@@ -512,13 +512,6 @@ ark_config_device(struct rte_eth_dev *dev)
if (ark_ddm_verify(ark->ddm.v))
return -1;
 
-   /* UDM */
-   if (ark_udm_reset(ark->udm.v)) {
-   ARK_PMD_LOG(ERR, "Unable to stop and reset UDM\n");
-   return -1;
-   }
-   /* Keep in reset until the MPU are cleared */
-
/* MPU reset */
mpu = ark->mpurx.v;
num_q = ark_api_num_queues(mpu);
@@ -577,9 +570,6 @@ eth_ark_dev_start(struct rte_eth_dev *dev)
int i;
 
/* RX Side */
-   /* start UDM */
-   ark_udm_start(ark->udm.v);
-
for (i = 0; i < dev->data->nb_rx_queues; i++)
eth_ark_rx_start_queue(dev, i);
 
@@ -627,7 +617,6 @@ eth_ark_dev_stop(struct rte_eth_dev *dev)
uint16_t i;
int status;
struct ark_adapter *ark = dev->data->dev_private;
-   struct ark_mpu_t *mpu;
 
if (ark->started == 0)
return 0;
@@ -660,27 +649,7 @@ eth_ark_dev_stop(struct rte_eth_dev *dev)
}
}
 
-   /* STOP RX Side */
-   /* Stop UDM  multiple tries attempted */
-   for (i = 0; i < 10; i++) {
-   status = ark_udm_stop(ark->udm.v, 1);
-   if (status == 0)
-   break;
-   }
-   if (status || i != 0) {
-   ARK_PMD_LOG(ERR, "UDM stop anomaly. status %d iter: %u. (%s)\n",
-   status, i, __func__);
-   ark_udm_dump(ark->udm.v, "Stop anomaly");
-
-   mpu = ark->mpurx.v;
-   for (i = 0; i < ark->rx_queues; i++) {
-   ark_mpu_dump(mpu, "UDM Stop anomaly", i);
-   mpu = RTE_PTR_ADD(mpu, ARK_MPU_QOFFSET);
-   }
-   }
-
ark_udm_dump_stats(ark->udm.v, "Post stop");
-   ark_udm_dump_perf(ark->udm.v, "Post stop");
 
for (i = 0; i < dev->data->nb_rx_queues; i++)
eth_ark_rx_dump_queue(dev, i, __func__);
@@ -708,10 +677,9 @@ eth_ark_dev_close(struct rte_eth_dev *dev)
 ark->user_data[dev->data->port_id]);
 
eth_ark_dev_stop(dev);
-   eth_ark_udm_force_close(dev);
 
/*
-* TODO This should only be called once for the device during shutdown
+* This should only be called once for the device during shutdown
 */
if (ark->rqpacing)
ark_rqp_dump(ark->rqpacing);
diff --git a/drivers/net/ark/ark_ethdev_rx.c b/drivers/net/ark/ark_ethdev_rx.c
index 85e34d0bb8..cbc0416bc2 100644
--- a/drivers/net/ark/ark_ethdev_rx.c
+++ b/drivers/net/ark/ark_ethdev_rx.c
@@ -200,13 +200,10 @@ eth_ark_dev_rx_queue_setup(struct rte_eth_dev *dev,
queue->mpu = RTE_PTR_ADD(ark->mpurx.v, qidx * ARK_MPU_QOFFSET);
 
/* Configure UDM per queue */
-   ark_udm_stop(queue->udm, 0);
ark_udm_configure(queue->udm,
  RTE_PKTMBUF_HEADROOM,
- queue->dataroom,
- ARK_RX_WRITE_TIME_NS);
-   ark_udm_stats_reset(queue->udm);
-   ark_udm_stop(queue->udm, 0);
+ queue->dataroom);
+   ark_udm_queue_stats_reset(queue->udm);
 
/* populate mbuf reserve */
status = eth_ark_rx_seed_mbufs(queue);
@@ -589,36 +586,6 @@ eth_rx_queue_stats_reset(void *vqueue)
ark_udm_queue_stats_reset(queue->udm);
 }
 
-void
-eth_ark_udm_force_close(struct rte_eth_dev *dev)
-{
-   struct ark_adapter *ark = dev->data->dev_private;
-   struct ark_rx_queue *queue;
-   uint32_t index;
-   uint16_t i;
-
-   if (!ark_udm_is_flushed(ark->udm.v)) {
-   /* restart the MPUs */
-   ARK_PMD_LOG(NOTICE, "UDM not flushed -- forcing flush\n");
-   for (i = 0; i < dev->data->nb_rx_queues; i++) {
-   queue = (struct ark_rx_queue *)dev->data->rx_queues[i];
-   if (queue == 0)
-   continue;
-
-   ark_mpu_start(queue->mpu);
-   /* Add some buffers */
-   index = ARK_RX_MPU_CHUNK + queue->seed_index;
-   ark_mpu_set_producer(queue->mpu, index);
-   }
-   /* Wait to allow da

[PATCH v1 4/5] net/ark: add new devices to support list

[Ed Czeck]

update device list is doc

Signed-off-by: Ed Czeck 
---
 doc/guides/nics/ark.rst  | 4 +++-
 drivers/net/ark/ark_ethdev.c | 6 ++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/doc/guides/nics/ark.rst b/doc/guides/nics/ark.rst
index c965406a7b..cec6fce2ff 100644
--- a/doc/guides/nics/ark.rst
+++ b/doc/guides/nics/ark.rst
@@ -297,6 +297,9 @@ ARK PMD supports the following Arkville RTL PCIe instances 
including:
 * ``1d6c:1017`` - AR-ARK-FX1 [Arkville 64B Multi-Homed Primary Endpoint]
 * ``1d6c:1018`` - AR-ARK-FX1 [Arkville 64B Multi-Homed Secondary Endpoint]
 * ``1d6c:1019`` - AR-ARK-FX1 [Arkville 64B Multi-Homed Tertiary Endpoint]
+* ``1d6c:101a`` - AR-ARK-SRIOV-FX0 [Arkville 32B Primary Physical Function]
+* ``1d6c:101b`` - AR-ARK-SRIOV-FX1 [Arkville 64B Primary Physical Function]
+* ``1d6c:101c`` - AR-ARK-SRIOV-VF [Arkville Virtual Function]
 * ``1d6c:101e`` - AR-ARKA-FX1 [Arkville 64B DPDK Data Mover for Agilex R-Tile]
 * ``1d6c:101f`` - AR-TK242 [2x100GbE Packet Capture Device]
 
@@ -322,7 +325,6 @@ Unsupported Features
 Features that may be part of, or become part of, the Arkville RTL IP that are
 not currently supported or exposed by the ARK PMD include:
 
-* PCIe SR-IOV Virtual Functions (VFs)
 * Arkville's Packet Generator Control and Status
 * Arkville's Packet Director Control and Status
 * Arkville's Packet Checker Control and Status
diff --git a/drivers/net/ark/ark_ethdev.c b/drivers/net/ark/ark_ethdev.c
index 8b4daa819b..7cf896f6f1 100644
--- a/drivers/net/ark/ark_ethdev.c
+++ b/drivers/net/ark/ark_ethdev.c
@@ -94,6 +94,9 @@ static const struct rte_pci_id pci_id_ark_map[] = {
{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x1017)},
{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x1018)},
{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x1019)},
+   {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101a)},
+   {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101b)},
+   {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101c)},
{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101e)},
{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101f)},
{.vendor_id = 0, /* sentinel */ },
@@ -127,6 +130,9 @@ ark_device_caps[] = {
 SET_DEV_CAPS(0x1017, true),
 SET_DEV_CAPS(0x1018, true),
 SET_DEV_CAPS(0x1019, true),
+SET_DEV_CAPS(0x101a, true),
+SET_DEV_CAPS(0x101b, true),
+SET_DEV_CAPS(0x101c, false),
 SET_DEV_CAPS(0x101e, false),
 SET_DEV_CAPS(0x101f, false),
 {.device_id = 0,}
-- 
2.17.1

[PATCH v1 5/5] net/ark: add PMD support for devices as virtual functions

[Ed Czeck]

Add capabilities field isvf to dev struct
Disable configuration calls as required by vf

Signed-off-by: Ed Czeck 
---
 drivers/net/ark/ark_ethdev.c | 79 
 drivers/net/ark/ark_global.h |  1 +
 2 files changed, 45 insertions(+), 35 deletions(-)

diff --git a/drivers/net/ark/ark_ethdev.c b/drivers/net/ark/ark_ethdev.c
index 7cf896f6f1..fde94ee431 100644
--- a/drivers/net/ark/ark_ethdev.c
+++ b/drivers/net/ark/ark_ethdev.c
@@ -113,28 +113,29 @@ static const struct rte_pci_id pci_id_ark_map[] = {
  */
 struct ark_caps {
bool rqpacing;
+   bool isvf;
 };
 struct ark_dev_caps {
uint32_t  device_id;
struct ark_caps  caps;
 };
-#define SET_DEV_CAPS(id, rqp) \
-   {id, {.rqpacing = rqp} }
+#define SET_DEV_CAPS(id, rqp, vf)  \
+   {id, {.rqpacing = rqp, .isvf = vf} }
 
 static const struct ark_dev_caps
 ark_device_caps[] = {
-SET_DEV_CAPS(0x100d, true),
-SET_DEV_CAPS(0x100e, true),
-SET_DEV_CAPS(0x100f, true),
-SET_DEV_CAPS(0x1010, false),
-SET_DEV_CAPS(0x1017, true),
-SET_DEV_CAPS(0x1018, true),
-SET_DEV_CAPS(0x1019, true),
-SET_DEV_CAPS(0x101a, true),
-SET_DEV_CAPS(0x101b, true),
-SET_DEV_CAPS(0x101c, false),
-SET_DEV_CAPS(0x101e, false),
-SET_DEV_CAPS(0x101f, false),
+SET_DEV_CAPS(0x100d, true, false),
+SET_DEV_CAPS(0x100e, true, false),
+SET_DEV_CAPS(0x100f, true, false),
+SET_DEV_CAPS(0x1010, false, false),
+SET_DEV_CAPS(0x1017, true, false),
+SET_DEV_CAPS(0x1018, true, false),
+SET_DEV_CAPS(0x1019, true, false),
+SET_DEV_CAPS(0x101a, true, false),
+SET_DEV_CAPS(0x101b, true, false),
+SET_DEV_CAPS(0x101c, false, true),
+SET_DEV_CAPS(0x101e, false, false),
+SET_DEV_CAPS(0x101f, false, false),
 {.device_id = 0,}
 };
 
@@ -317,6 +318,7 @@ eth_ark_dev_init(struct rte_eth_dev *dev)
while (ark_device_caps[p].device_id != 0) {
if (pci_dev->id.device_id == ark_device_caps[p].device_id) {
rqpacing = ark_device_caps[p].caps.rqpacing;
+   ark->isvf = ark_device_caps[p].caps.isvf;
break;
}
p++;
@@ -498,20 +500,21 @@ ark_config_device(struct rte_eth_dev *dev)
 * Make sure that the packet director, generator and checker are in a
 * known state
 */
-   ark->start_pg = 0;
-   ark->pg_running = 0;
-   ark->pg = ark_pktgen_init(ark->pktgen.v, 0, 1);
-   if (ark->pg == NULL)
-   return -1;
-   ark_pktgen_reset(ark->pg);
-   ark->pc = ark_pktchkr_init(ark->pktchkr.v, 0, 1);
-   if (ark->pc == NULL)
-   return -1;
-   ark_pktchkr_stop(ark->pc);
-   ark->pd = ark_pktdir_init(ark->pktdir.v);
-   if (ark->pd == NULL)
-   return -1;
-
+   if (!ark->isvf) {
+   ark->start_pg = 0;
+   ark->pg_running = 0;
+   ark->pg = ark_pktgen_init(ark->pktgen.v, 0, 1);
+   if (ark->pg == NULL)
+   return -1;
+   ark_pktgen_reset(ark->pg);
+   ark->pc = ark_pktchkr_init(ark->pktchkr.v, 0, 1);
+   if (ark->pc == NULL)
+   return -1;
+   ark_pktchkr_stop(ark->pc);
+   ark->pd = ark_pktdir_init(ark->pktdir.v);
+   if (ark->pd == NULL)
+   return -1;
+   }
/* Verify HW */
if (ark_udm_verify(ark->udm.v))
return -1;
@@ -533,7 +536,7 @@ ark_config_device(struct rte_eth_dev *dev)
mpu = RTE_PTR_ADD(mpu, ARK_MPU_QOFFSET);
}
 
-   if (ark->rqpacing)
+   if (!ark->isvf && ark->rqpacing)
ark_rqp_stats_reset(ark->rqpacing);
 
return 0;
@@ -551,8 +554,10 @@ eth_ark_dev_uninit(struct rte_eth_dev *dev)
ark->user_ext.dev_uninit(dev,
 ark->user_data[dev->data->port_id]);
 
-   ark_pktgen_uninit(ark->pg);
-   ark_pktchkr_uninit(ark->pc);
+   if (!ark->isvf) {
+   ark_pktgen_uninit(ark->pg);
+   ark_pktchkr_uninit(ark->pc);
+   }
 
return 0;
 }
@@ -588,10 +593,10 @@ eth_ark_dev_start(struct rte_eth_dev *dev)
dev->rx_pkt_burst = ð_ark_recv_pkts;
dev->tx_pkt_burst = ð_ark_xmit_pkts;
 
-   if (ark->start_pg)
+   if (!ark->isvf && ark->start_pg)
ark_pktchkr_run(ark->pc);
 
-   if (ark->start_pg && !ark->pg_running) {
+   if (!ark->isvf && ark->start_pg && !ark->pg_running)

Re: [PATCH 0/5] refactor for device info dump

[Ferruh Yigit]

On 4/14/2022 2:00 PM, Min Hu (Connor) wrote:

This patch set contains three patches for refactor, and two patches
for bugfix.

Min Hu (Connor) (5):
   net/hns3: refactor adapter state dump
   net/hns3: refactor feature capability dump
   net/hns3: refactor queue info dump
   net/hns3: fix dump TM info
   net/hns3: fix dump device info



Series applied to dpdk-next-net/main, thanks.

Re: [Patch v2] net/netvsc: report correct stats values

[Ferruh Yigit]

On 5/4/2022 7:38 PM, Long Li wrote:

Subject: Re: [Patch v2] net/netvsc: report correct stats values

On 5/3/2022 9:48 PM, Long Li wrote:

Subject: Re: [Patch v2] net/netvsc: report correct stats values

On 5/3/2022 8:14 PM, Long Li wrote:

Subject: Re: [Patch v2] net/netvsc: report correct stats values

On 5/3/2022 7:18 PM, Long Li wrote:

Subject: Re: [Patch v2] net/netvsc: report correct stats values

On Tue, 26 Apr 2022 22:56:14 +0100 Ferruh Yigit
 wrote:


if (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) {
-   stats->q_opackets[i] = txq->stats.packets;
-   stats->q_obytes[i] = txq->stats.bytes;
+   stats->q_opackets[i] += txq->stats.packets;
+   stats->q_obytes[i] += txq->stats.bytes;


This is per queue stats, 'stats->q_opackets[i]', in next
iteration of the loop, 'i' will be increased and 'txq' will be
updated, so as far as I can see the above change has no affect.


Agree, that is why it was just assignment originally.


The condition here is a little different. NETVSC is a master
device with

another PMD running as a slave. When reporting stats values, it
needs to add the values from the slave PMD. The original code just
overwrites the values from its slave PMD.

Where the initial values are coming from, 'hn_vf_stats_get()'?

If 'hn_vf_stats_get()' fills the stats, what are the values kept in
'txq-

stats.*'

in above updated loop?


Yes, hn_vf_stats_get() fills in the stats from the slave PMD.
txq->stats

values are from the master PMD. Those values are different and
accounted separated from the values from the slave PMD.

I see, since this is a little different than what most of the PMDs
do, can you please put a little more info to the commit log? Or
perhaps can add some comments to the code.


Ok, will do.



And still 'stats->rx_nombuf' change is not required right? If so can
you remove it in the next version?


It is still needed. NETVSC unconditionally calls the slave PMD to receive

packets, even if it can't allocate a mbuf to receive a synthetic packet itself. 
The
accounting of rx_nombuf is valid because the synthetic packets (to NETVSC) and
VF packets (to slave PMD) are routed separately from Hyper-V.

I am not referring to the "+=" update, my comment was because 'stats-

rx_nombuf' is overwritten in 'rte_eth_stats_get()' [1].

Is it still required?


Yes, it is still needed. NETVSC calls the rte_eth_stats_get() on its slave PMD first, and 
stats->rx_nombuf is updated (overwritten) for its slave PMD. Afte that, it needs to add 
to its own dev->data->rx_mbuf_alloc_failed back to stats->rx_nombuf.



But its own stat also will be overwritten (not in PMD function, but in 
ethdev layer).
'stats->rx_nombuf' assignment in the PMD seems has no effect and can be 
removed.


I can't see how it is needed, can you please put a call stack to describe?



[1]
https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.dpdk
.org%2Fdpdk%2Ftree%2Flib%2Fethdev%2Frte_ethdev.c%3Fh%3Dv22.03%23n25
18&data=05%7C01%7Clongli%40microsoft.com%7Cea473df2344c460d575
d08da2dca3e53%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C63787
2643902917430%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQ
IjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sd
ata=FZO%2B%2BnWtLGstHHIZ2aXsDUKNI%2Fi9tbj6jONhp174qKw%3D&res
erved=0

Re: [PATCH 4/5] net/cxgbe: track packets dropped by TP due to congestion

[Ferruh Yigit]

On 4/18/2022 11:24 PM, Rahul Lakkireddy wrote:

Rx packets can get dropped at TP due to congestion and this info
will not get propagated to MPS. Track these Rx dropped packets
in imissed counter. Also add xstats for these counters.

Signed-off-by: Rahul Lakkireddy


What 'TP' stands for? As far as I understand it is a kind of FW (TP 
Microcode) but I didn't able to find any reference to it.

Re: [PATCH 5/5] net/cxgbe: read firmware configuration file from filesystem

[Ferruh Yigit]

On 4/18/2022 11:24 PM, Rahul Lakkireddy wrote:

Add support to read firmware configuration file from
/lib/firmware/cxgb4/ path in the filesystem.



Hi Rahul,

Can you please document the FW config file in the driver documentation?
Please add:
- Path of the config file
- Content of the config file. As far as I can see from the code the 
config file directly sent to the FW, does this mean config file is binary?

- What happens when config file is not found

Also are these values overlap with the devargs that PMD has? If so what 
happens in that case, which one is used, devargs one or config file one?


Previously there was 'cxgbtool' tool to send the config file, is this 
method replacing it? Why not keep using 'cxgbtool'?


Thanks,
ferruh



Signed-off-by: Rahul Lakkireddy


<...>

Re: [PATCH 0/5] net/cxgbe: updates and bug fixes

[Ferruh Yigit]

On 4/18/2022 11:24 PM, Rahul Lakkireddy wrote:

This series of patches add the following updates and bug fixes to
the cxgbe PMD.

Patch 1 fixes an issue with wrong port id being filled in mbufs
allocated in Rx path.

Patch 2 fixes an issue with Txq getting stuck when trying to coalesce
mbufs with chains.

Patch 3 reworks and simplifies the code for posting mbufs and their
payload buffer sizes to hardware in Rx path.

Patch 4 adds support to track packets in Rx path dropped due to
congestion at Rx queues that may not get propagated to the rest
of the Rx pipeline.

Patch 5 adds support to read firmware configuration file from
/lib/firmware/cxgb4/ to allow changing firmware parameters without
having to flash the configuration file onto the adapter.

Thanks,
Rahul

Rahul Lakkireddy (5):
   net/cxgbe: fill correct port info in mbufs for Rx
   net/cxgbe: fix Tx queue stuck with mbuf chain coalescing
   net/cxgbe: simplify Rx payload buffer size posting
   net/cxgbe: track packets dropped by TP due to congestion
   net/cxgbe: read firmware configuration file from filesystem



Except from 4/5 & 5/5,
Series applied to dpdk-next-net/main, thanks.

Please check comments for 4/5 & 5/5. Since patches are independent, I 
think it would be OK to send a new series for remaining patches.


Thanks,
ferruh

Re: [PATCH 5/5] net/cxgbe: read firmware configuration file from filesystem

[Ferruh Yigit]

On 5/5/2022 5:29 PM, Ferruh Yigit wrote:

On 4/18/2022 11:24 PM, Rahul Lakkireddy wrote:

Add support to read firmware configuration file from
/lib/firmware/cxgb4/ path in the filesystem.



Hi Rahul,

Can you please document the FW config file in the driver documentation?
Please add:
- Path of the config file
- Content of the config file. As far as I can see from the code the 
config file directly sent to the FW, does this mean config file is binary?

- What happens when config file is not found

Also are these values overlap with the devargs that PMD has? If so what 
happens in that case, which one is used, devargs one or config file one?


Previously there was 'cxgbtool' tool to send the config file, is this 
method replacing it? Why not keep using 'cxgbtool'?




cc'ed more folks.

This patch introduces a userspace config file for runtime FW config.

What do you think about this approach?
Should we formalize this method more, like introducing an ethdev level 
config option to hold the config file, which can be used for driver 
and/or FW. And perhaps with a defined syntax (yaml?).

Can this be an alternative to PMD devargs?

Cheers,
ferruh

Re: [Patch v2] net/netvsc: report correct stats values

[Stephen Hemminger]

On Thu, 5 May 2022 17:28:38 +0100
Ferruh Yigit  wrote:

> On 5/4/2022 7:38 PM, Long Li wrote:
> >> Subject: Re: [Patch v2] net/netvsc: report correct stats values
> >>
> >> On 5/3/2022 9:48 PM, Long Li wrote:  
>  Subject: Re: [Patch v2] net/netvsc: report correct stats values
> 
>  On 5/3/2022 8:14 PM, Long Li wrote:  
> >> Subject: Re: [Patch v2] net/netvsc: report correct stats values
> >>
> >> On 5/3/2022 7:18 PM, Long Li wrote:  
>  Subject: Re: [Patch v2] net/netvsc: report correct stats values
> 
>  On Tue, 26 Apr 2022 22:56:14 +0100 Ferruh Yigit
>   wrote:
>   
> >>if (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) {
> >> -  stats->q_opackets[i] = txq->stats.packets;
> >> -  stats->q_obytes[i] = txq->stats.bytes;
> >> +  stats->q_opackets[i] += txq->stats.packets;
> >> +  stats->q_obytes[i] += txq->stats.bytes;  
> >
> > This is per queue stats, 'stats->q_opackets[i]', in next
> > iteration of the loop, 'i' will be increased and 'txq' will be
> > updated, so as far as I can see the above change has no affect.  
> 
>  Agree, that is why it was just assignment originally.  
> >>>
> >>> The condition here is a little different. NETVSC is a master
> >>> device with  
> >> another PMD running as a slave. When reporting stats values, it
> >> needs to add the values from the slave PMD. The original code just
> >> overwrites the values from its slave PMD.
> >>
> >> Where the initial values are coming from, 'hn_vf_stats_get()'?
> >>
> >> If 'hn_vf_stats_get()' fills the stats, what are the values kept in
> >> 'txq-  
> > stats.*'  
> >> in above updated loop?  
> >
> > Yes, hn_vf_stats_get() fills in the stats from the slave PMD.
> > txq->stats  
>  values are from the master PMD. Those values are different and
>  accounted separated from the values from the slave PMD.
> 
>  I see, since this is a little different than what most of the PMDs
>  do, can you please put a little more info to the commit log? Or
>  perhaps can add some comments to the code.  
> >>>
> >>> Ok, will do.
> >>>  
> 
>  And still 'stats->rx_nombuf' change is not required right? If so can
>  you remove it in the next version?  
> >>>
> >>> It is still needed. NETVSC unconditionally calls the slave PMD to receive 
> >>>  
> >> packets, even if it can't allocate a mbuf to receive a synthetic packet 
> >> itself. The
> >> accounting of rx_nombuf is valid because the synthetic packets (to NETVSC) 
> >> and
> >> VF packets (to slave PMD) are routed separately from Hyper-V.
> >>
> >> I am not referring to the "+=" update, my comment was because 'stats-  
> >>> rx_nombuf' is overwritten in 'rte_eth_stats_get()' [1].  
> >> Is it still required?  
> > 
> > Yes, it is still needed. NETVSC calls the rte_eth_stats_get() on its slave 
> > PMD first, and stats->rx_nombuf is updated (overwritten) for its slave PMD. 
> > Afte that, it needs to add to its own dev->data->rx_mbuf_alloc_failed back 
> > to stats->rx_nombuf.
> >   
> 
> But its own stat also will be overwritten (not in PMD function, but in 
> ethdev layer).
> 'stats->rx_nombuf' assignment in the PMD seems has no effect and can be 
> removed.
> 
> I can't see how it is needed, can you please put a call stack to describe?

This here:


int
rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats)
{
struct rte_eth_dev *dev;

RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
dev = &rte_eth_devices[port_id];

if (stats == NULL) {
RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u stats to NULL\n",
port_id);
return -EINVAL;
}

memset(stats, 0, sizeof(*stats));

RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP);
stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;
return eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats));
}

Will fill in rx_nombuf from the current rx_mbuf_alloc_failed.
But it happens before the PMD specific stats function.

For the case of nested device like netvsc PMD that value needs to
be summed.

What happens with VF would be:

Call of rte_eth_stats_get on the netvsc PMD port.
stats->rx_nombuf comes from rx_mbuf_alloc_failed of the vmbus part
Netvsc PMD stats get calls rte_eth_stats_get on the VF
Nested rte_eth_stats_get will set stats->rx_nombuf to the value from VF
   the previous value is overwritten.

At end of Netvsc PMD stats get it should be adding the value of any
allocation failures in the VMBUS part.

Summary:
rte_eth_stats_get:  stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;  // 
original
rte_eth_stats_get(vf):  stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;  // 
VF alloc failed
hn_dev_s

Re: [Patch v2] net/netvsc: report correct stats values

[Ferruh Yigit]

On 5/5/2022 5:40 PM, Stephen Hemminger wrote:

On Thu, 5 May 2022 17:28:38 +0100
Ferruh Yigit  wrote:


On 5/4/2022 7:38 PM, Long Li wrote:

Subject: Re: [Patch v2] net/netvsc: report correct stats values

On 5/3/2022 9:48 PM, Long Li wrote:

Subject: Re: [Patch v2] net/netvsc: report correct stats values

On 5/3/2022 8:14 PM, Long Li wrote:

Subject: Re: [Patch v2] net/netvsc: report correct stats values

On 5/3/2022 7:18 PM, Long Li wrote:

Subject: Re: [Patch v2] net/netvsc: report correct stats values

On Tue, 26 Apr 2022 22:56:14 +0100 Ferruh Yigit
 wrote:
  

if (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) {
-   stats->q_opackets[i] = txq->stats.packets;
-   stats->q_obytes[i] = txq->stats.bytes;
+   stats->q_opackets[i] += txq->stats.packets;
+   stats->q_obytes[i] += txq->stats.bytes;


This is per queue stats, 'stats->q_opackets[i]', in next
iteration of the loop, 'i' will be increased and 'txq' will be
updated, so as far as I can see the above change has no affect.


Agree, that is why it was just assignment originally.


The condition here is a little different. NETVSC is a master
device with

another PMD running as a slave. When reporting stats values, it
needs to add the values from the slave PMD. The original code just
overwrites the values from its slave PMD.

Where the initial values are coming from, 'hn_vf_stats_get()'?

If 'hn_vf_stats_get()' fills the stats, what are the values kept in
'txq-

stats.*'

in above updated loop?


Yes, hn_vf_stats_get() fills in the stats from the slave PMD.
txq->stats

values are from the master PMD. Those values are different and
accounted separated from the values from the slave PMD.

I see, since this is a little different than what most of the PMDs
do, can you please put a little more info to the commit log? Or
perhaps can add some comments to the code.


Ok, will do.
  


And still 'stats->rx_nombuf' change is not required right? If so can
you remove it in the next version?


It is still needed. NETVSC unconditionally calls the slave PMD to receive

packets, even if it can't allocate a mbuf to receive a synthetic packet itself. 
The
accounting of rx_nombuf is valid because the synthetic packets (to NETVSC) and
VF packets (to slave PMD) are routed separately from Hyper-V.

I am not referring to the "+=" update, my comment was because 'stats-

rx_nombuf' is overwritten in 'rte_eth_stats_get()' [1].

Is it still required?


Yes, it is still needed. NETVSC calls the rte_eth_stats_get() on its slave PMD first, and 
stats->rx_nombuf is updated (overwritten) for its slave PMD. Afte that, it needs to add 
to its own dev->data->rx_mbuf_alloc_failed back to stats->rx_nombuf.
   


But its own stat also will be overwritten (not in PMD function, but in
ethdev layer).
'stats->rx_nombuf' assignment in the PMD seems has no effect and can be
removed.

I can't see how it is needed, can you please put a call stack to describe?


This here:


int
rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats)
{
struct rte_eth_dev *dev;

RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
dev = &rte_eth_devices[port_id];

if (stats == NULL) {
RTE_ETHDEV_LOG(ERR, "Cannot get ethdev port %u stats to NULL\n",
port_id);
return -EINVAL;
}

memset(stats, 0, sizeof(*stats));

RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP);
stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;
return eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats));
}

Will fill in rx_nombuf from the current rx_mbuf_alloc_failed.
But it happens before the PMD specific stats function.



I keep seeing the ethdev assignment as *after* the dev_ops, but it is 
not [1], so code is OK as it is.



[1]
It seems assignment was after but it is fixed on the way:
Commit 53ecfa24fbcd ("ethdev: fix overwriting driver-specific stats")

[Bug 1005] Build failure with gcc11 in When Using Environment Modules

[bugzilla]

https://bugs.dpdk.org/show_bug.cgi?id=1005

Bug ID: 1005
   Summary: Build failure with gcc11 in When Using Environment
Modules
   Product: DPDK
   Version: 22.03
  Hardware: POWER
OS: Linux
Status: UNCONFIRMED
  Severity: normal
  Priority: Normal
 Component: meson
  Assignee: dev@dpdk.org
  Reporter: d...@linux.vnet.ibm.com
  Target Milestone: ---

Install and enable IBM Advanced Toolchain 15.0 using environment modules:

$ module load at15.0
$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/opt/at15.0/libexec/gcc/powerpc64le-linux-gnu/11.2.1/lto-wrapper
Target: powerpc64le-linux-gnu
Configured with:
/build/at15.0_RHEL8_ppc64le-ppc64le/114/at15.0-2.redhat-8_ppc64le_ppc64le/sources/gcc/configure
--build=powerpc64le-linux-gnu --host=powerpc64le-linux-gnu
--target=powerpc64le-linux-gnu --with-cpu=default64 --prefix=/opt/at15.0
--with-long-double-128 --enable-secureplt --disable-multilib
--with-advance-toolchain=at15.0 --with-glibc-version=2.34
--with-local-prefix=/opt/at15.0 --enable-threads=posix
--enable-languages=c,c++,fortran,go --enable-__cxa_atexit --enable-shared
--enable-checking=release --enable-lto --enable-gnu-indirect-function
--enable-initfini-array --enable-linker-build-id --with-system-zlib
--with-gmp-include=/opt/at15.0/include --with-gmp-lib=/opt/at15.0/lib64
--with-mpfr-include=/opt/at15.0/include --with-mpfr-lib=/opt/at15.0/lib64
--with-mpc-include=/opt/at15.0/include --with-mpc-lib=/opt/at15.0/lib64
--without-ppl --without-cloog --without-libelf
--with-host-libstdcxx='-L/opt/at15.0/lib64 -lstdc++ -lsupc++ -lgmp -lgmpxx -lm'
--with-cpu=power8 --with-tune=power10
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 11.2.1 20220211 (Advance-Toolchain 15.0-2) [64575dfb22ae] (GCC)

Compile DPDK:

$ meson -v
0.61.2
$ meson build
$ ninja -C build

Observe link errors:

ninja: Entering directory `build'
[3324/3341] Linking target app/dpdk-test-acl
FAILED: app/dpdk-test-acl
cc  -o app/dpdk-test-acl app/dpdk-test-acl.p/test-acl_main.c.o -Wl,--as-needed
-Wl,--no-undefined -Wl,-O1 -Wl,--whole-archive -Wl,--start-group
lib/librte_node.a lib/librte_graph.a lib/librte_flow_classify.a
lib/librte_pipeline.a lib/librte_table.a lib/librte_pdump.a lib/librte_port.a
lib/librte_fib.a lib/librte_ipsec.a lib/librte_vhost.a lib/librte_stack.a
lib/librte_security.a lib/librte_sched.a lib/librte_reorder.a lib/librte_rib.a
lib/librte_dmadev.a lib/librte_regexdev.a lib/librte_rawdev.a
lib/librte_power.a lib/librte_pcapng.a lib/librte_member.a lib/librte_lpm.a
lib/librte_latencystats.a lib/librte_kni.a lib/librte_jobstats.a
lib/librte_ip_frag.a lib/librte_gso.a lib/librte_gro.a lib/librte_gpudev.a
lib/librte_eventdev.a lib/librte_efd.a lib/librte_distributor.a
lib/librte_cryptodev.a lib/librte_compressdev.a lib/librte_cfgfile.a
lib/librte_bpf.a lib/librte_bitratestats.a lib/librte_bbdev.a lib/librte_acl.a
lib/librte_timer.a lib/librte_hash.a lib/librte_metrics.a lib/librte_cmdline.a
lib/librte_pci.a lib/librte_ethdev.a lib/librte_meter.a lib/librte_net.a
lib/librte_mbuf.a lib/librte_mempool.a lib/librte_rcu.a lib/librte_ring.a
lib/librte_eal.a lib/librte_telemetry.a lib/librte_kvargs.a
drivers/librte_common_cpt.a drivers/librte_common_dpaax.a
drivers/librte_common_iavf.a drivers/librte_common_octeontx.a
drivers/librte_bus_auxiliary.a drivers/librte_bus_dpaa.a
drivers/librte_bus_fslmc.a drivers/librte_bus_ifpga.a drivers/librte_bus_pci.a
drivers/librte_bus_vdev.a drivers/librte_bus_vmbus.a
drivers/librte_common_cnxk.a drivers/librte_common_mlx5.a
drivers/librte_common_qat.a drivers/librte_mempool_bucket.a
drivers/librte_mempool_cnxk.a drivers/librte_mempool_dpaa.a
drivers/librte_mempool_dpaa2.a drivers/librte_mempool_octeontx.a
drivers/librte_mempool_ring.a drivers/librte_mempool_stack.a
drivers/librte_dma_cnxk.a drivers/librte_dma_dpaa.a
drivers/librte_dma_skeleton.a drivers/librte_net_af_packet.a
drivers/librte_net_ark.a drivers/librte_net_atlantic.a drivers/librte_net_avp.a
drivers/librte_net_axgbe.a drivers/librte_net_bnx2x.a drivers/librte_net_bnxt.a
drivers/librte_net_bond.a drivers/librte_net_cnxk.a drivers/librte_net_cxgbe.a
drivers/librte_net_dpaa.a drivers/librte_net_dpaa2.a drivers/librte_net_e1000.a
drivers/librte_net_ena.a drivers/librte_net_enetc.a
drivers/librte_net_enetfec.a drivers/librte_net_enic.a
drivers/librte_net_failsafe.a drivers/librte_net_fm10k.a
drivers/librte_net_hinic.a drivers/librte_net_i40e.a drivers/librte_net_iavf.a
drivers/librte_net_ice.a drivers/librte_net_igc.a drivers/librte_net_ionic.a
drivers/librte_net_ipn3ke.a drivers/librte_net_ixgbe.a drivers/librte_net_kni.a
drivers/librte_net_liquidio.a drivers/librte_net_memif.a
drivers/librte_net_mlx4.a drivers/librte_net_mlx5.a drivers/librte_net_netvsc.a
drivers/librte_net_nfp.a drivers/librte_net_ngbe.a drivers/librte_net_null.a
drivers/librte_net_octeontx.a d

[PATCH 00/11] Introduce support for RISC-V architecture

[Stanislaw Kardach]

This patchset adds support for building and running DPDK on 64bit RISC-V
architecture. The initial support targets rv64gc (rv64imafdc) ISA and
was tested on SiFive Unmatched development board with the Freedom U740
SoC running Linux (freedom-u-sdk based kernel).
I have tested this codebase using DPDK unit and perf tests as well as
test-pmd, l2fwd and l3fwd examples.
The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
uio_pci_generic and vfio-pci noiommu drivers.

Commits 1-2 fix small issues which are encountered if a given platform
   does not support any vector operations (which is the case with U740).
Commit 3 introduces EAL and build system support for RISC-V architecture
   as well as documentation updates.
Commits 4-7 add missing defines and stubs to enable RISC-V operation in
   non-EAL parts.
Commit 8 adds RISC-V specific cpuflags test.
Commit 9 works around a bug in the current GCC in test_ring compiled
   with -O0 or -Og.
Commit 10 adds RISC-V testing to test-meson-builds.sh automatically
   iterating over cross-compile config files (currently present for
   generic rv64gc and SiFive U740).
Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM
   measurements. This is an extraneous commit which is not directly
   needed for RISC-V support but was noticed when we have started
   gathering test results. If needed, I can submit it separately.

I appreciate Your comments and feedback.

Best Regards,
Stanislaw Kardach

NOTE: This work was sponsored by StarFive and SiFive which is signified by
   "Sponsored-by:" sign-offs in each commit message. After discussing it
   with Thomas Monjalon it seemed a better choice than "Suggested-by" which
   does not fully convey the nature of involvement. However it makes
   Linux checkpatch unhappy so I'm not sure if I shouldn't change the
   sign-offs.

NOTE2: I have added maintainers for each commit based on MAINTAINERS file.
   However some modules (l3fwd, net/tap and cpuflags unit tests) do not have
   any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as
   if it was a commit adding new files.

Michal Mazurek (3):
  lpm: add a scalar version of lookupx4 function
  eal: add initial support for RISC-V architecture
  test/cpuflags: add test for RISC-V cpu flag

Stanislaw Kardach (8):
  examples/l3fwd: fix scalar LPM compilation
  net/ixgbe: enable vector stubs for RISC-V
  net/memif: set memfd syscall ID on RISC-V
  net/tap: set BPF syscall ID for RISC-V
  examples/l3fwd: enable RISC-V operation
  test/ring: disable problematic tests for RISC-V
  devtools: add RISC-V to test-meson-builds.sh
  test/hash: report non HTM numbers for single r/w

 MAINTAINERS   |   6 +
 app/test/test_cpuflags.c  |  81 ++
 app/test/test_hash_readwrite.c|   8 +-
 app/test/test_ring.c  |   8 +
 app/test/test_xmmt_ops.h  |  16 ++
 config/meson.build|   2 +
 config/riscv/meson.build  | 148 ++
 config/riscv/riscv64_linux_gcc|  17 ++
 config/riscv/riscv64_sifive_u740_linux_gcc|  19 +++
 devtools/test-meson-builds.sh |   6 +
 doc/guides/contributing/design.rst|   2 +-
 .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++
 doc/guides/linux_gsg/index.rst|   1 +
 doc/guides/nics/features.rst  |   5 +
 doc/guides/nics/features/default.ini  |   1 +
 doc/guides/nics/features/ixgbe.ini|   1 +
 doc/guides/rel_notes/release_22_07.rst|  29 
 drivers/net/i40e/meson.build  |   6 +
 drivers/net/ixgbe/ixgbe_rxtx.c|   4 +-
 drivers/net/memif/rte_eth_memif.h |   2 +
 drivers/net/tap/tap_bpf.h |   2 +
 examples/l3fwd/l3fwd_em.c |   8 +
 examples/l3fwd/l3fwd_fib.c|   2 +
 examples/l3fwd/l3fwd_lpm.c|   2 +-
 lib/eal/riscv/include/meson.build |  23 +++
 lib/eal/riscv/include/rte_atomic.h|  52 ++
 lib/eal/riscv/include/rte_byteorder.h |  44 ++
 lib/eal/riscv/include/rte_cpuflags.h  |  55 +++
 lib/eal/riscv/include/rte_cycles.h| 103 
 lib/eal/riscv/include/rte_io.h|  21 +++
 lib/eal/riscv/include/rte_mcslock.h   |  18 +++
 lib/eal/riscv/include/rte_memcpy.h|  63 
 lib/eal/riscv/include/rte_pause.h |  31 
 lib/eal/riscv/include/rte_pflock.h|  17 ++
 lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
 lib/eal/riscv/include/rte_prefetch.h  |  50 ++
 lib/eal/riscv/include/rte_rwlock.h|  44 ++
 lib/eal/riscv/include/rte_spinlock.h  |  67 
 lib/eal/riscv/include/rte_ticketlock.

[PATCH 01/11] lpm: add a scalar version of lookupx4 function

[Stanislaw Kardach]

From: Michal Mazurek 

Add an implementation of the rte_lpm_lookupx4() function for platforms
without support for vector operations.

Signed-off-by: Michal Mazurek 
Signed-off-by: Stanislaw Kardach 
Sponsored-by: Frank Zhao 
Sponsored-by: Sam Grove 
---
 doc/guides/rel_notes/release_22_07.rst |   5 +
 lib/lpm/meson.build|   1 +
 lib/lpm/rte_lpm.h  |   4 +-
 lib/lpm/rte_lpm_scalar.h   | 122 +
 4 files changed, 131 insertions(+), 1 deletion(-)
 create mode 100644 lib/lpm/rte_lpm_scalar.h

diff --git a/doc/guides/rel_notes/release_22_07.rst 
b/doc/guides/rel_notes/release_22_07.rst
index 88d6e96cc1..067118174b 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -65,6 +65,11 @@ New Features
   * Added support for promiscuous mode on Windows.
   * Added support for MTU on Windows.
 
+* **Added scalar version of the LPM library.**
+
+  * Added scalar implementation of ``rte_lpm_lookupx4``. This is a fall-back
+implementation for platforms that don't support vector operations.
+
 
 Removed Items
 -
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index 78d91d3421..6b47361fce 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -14,6 +14,7 @@ headers = files('rte_lpm.h', 'rte_lpm6.h')
 indirect_headers += files(
 'rte_lpm_altivec.h',
 'rte_lpm_neon.h',
+'rte_lpm_scalar.h',
 'rte_lpm_sse.h',
 'rte_lpm_sve.h',
 )
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index eb91960e81..b5db6a353a 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -405,8 +405,10 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, 
uint32_t hop[4],
 #endif
 #elif defined(RTE_ARCH_PPC_64)
 #include "rte_lpm_altivec.h"
-#else
+#elif defined(RTE_ARCH_X86)
 #include "rte_lpm_sse.h"
+#else
+#include "rte_lpm_scalar.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/lib/lpm/rte_lpm_scalar.h b/lib/lpm/rte_lpm_scalar.h
new file mode 100644
index 00..991b94e687
--- /dev/null
+++ b/lib/lpm/rte_lpm_scalar.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef _RTE_LPM_SCALAR_H_
+#define _RTE_LPM_SCALAR_H_
+
+#include 
+#include 
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
+   uint32_t defv)
+{
+   rte_xmm_t i24;
+   rte_xmm_t i8;
+   uint32_t tbl[4];
+   uint64_t pt, pt2;
+   const uint32_t *ptbl;
+
+   const rte_xmm_t mask8 = {
+   .u32 = {UINT8_MAX, UINT8_MAX, UINT8_MAX, UINT8_MAX}};
+
+   /*
+* RTE_LPM_VALID_EXT_ENTRY_BITMASK for 2 LPM entries
+* as one 64-bit value (0x03000300).
+*/
+   const uint64_t mask_xv =
+   ((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK |
+   (uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32);
+
+   /*
+* RTE_LPM_LOOKUP_SUCCESS for 2 LPM entries
+* as one 64-bit value (0x01000100).
+*/
+   const uint64_t mask_v =
+   ((uint64_t)RTE_LPM_LOOKUP_SUCCESS |
+   (uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32);
+
+   /* get 4 indexes for tbl24[]. */
+   i24.x = ip;
+   i24.u32[0] >>= CHAR_BIT;
+   i24.u32[1] >>= CHAR_BIT;
+   i24.u32[2] >>= CHAR_BIT;
+   i24.u32[3] >>= CHAR_BIT;
+
+   /* extract values from tbl24[] */
+   ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[0]];
+   tbl[0] = *ptbl;
+   ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[1]];
+   tbl[1] = *ptbl;
+   ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[2]];
+   tbl[2] = *ptbl;
+   ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[3]];
+   tbl[3] = *ptbl;
+
+   /* get 4 indexes for tbl8[]. */
+   i8.x = ip;
+   i8.u64[0] &= mask8.u64[0];
+   i8.u64[1] &= mask8.u64[1];
+
+   pt = (uint64_t)tbl[0] |
+   (uint64_t)tbl[1] << 32;
+   pt2 = (uint64_t)tbl[2] |
+   (uint64_t)tbl[3] << 32;
+
+   /* search successfully finished for all 4 IP addresses. */
+   if (likely((pt & mask_xv) == mask_v) &&
+   likely((pt2 & mask_xv) == mask_v)) {
+   *(uint64_t *)hop = pt & RTE_LPM_MASKX4_RES;
+   *(uint64_t *)(hop + 2) = pt2 & RTE_LPM_MASKX4_RES;
+   return;
+   }
+
+   if (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+   RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+   i8.u32[0] = i8.u32[0] +
+   (tbl[0] & 0x00FF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
+   ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[0]];
+   tbl[0] = *ptbl;
+   }
+   if (unlikely((pt >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+   RTE_LPM_VALID_EXT_ENTRY_BITMASK