RE: [PATCH] net/mlx5: fix add Tx scheduling check

2021-11-14 Thread Raslan Darawsheh 
Hi,


> -Original Message-
> From: Slava Ovsiienko 
> Sent: Wednesday, November 10, 2021 3:06 PM
> To: dev@dpdk.org
> Cc: Raslan Darawsheh ; Matan Azrad
> ; sta...@dpdk.org
> Subject: [PATCH] net/mlx5: fix add Tx scheduling check
> 
> There was the redundant check for the enabled E-Switch, this
> resulted in device probing failure if the Tx scheduling was
> requested and E-Switch was enabled.
> 
> Fixes: f17e4b4ffef9 ("net/mlx5: add Tx scheduling check on queue creation")
> Cc: sta...@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko 
> ---

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

RE: [PATCH] net/mlx5: fix integrity conversion scheme

2021-11-14 Thread Raslan Darawsheh 
Hi,

> -Original Message-
> From: Gregory Etelson 
> Sent: Thursday, November 11, 2021 6:16 PM
> To: dev@dpdk.org; Gregory Etelson ; Slava Ovsiienko
> 
> Cc: sta...@dpdk.org; Matan Azrad 
> Subject: [PATCH] net/mlx5: fix integrity conversion scheme
> 
> RTE flow integrity API provides top-level packet validations.
> RTE integrity bits are not always translated one-to-one to hardware integrity
> bits.
> For example RTE l3_ok and l4_ok integrity bits require 2 hardware integrity
> bits each.
> 
> The patch fixes RTE l3_ok and l4_ok bits translation to match
> ConnectX-6 hardware.
> 
> Cc: sta...@dpdk.org
> 
> Fixes: 79f8952783d0 ("net/mlx5: support integrity flow item")
> 
> Signed-off-by: Gregory Etelson 

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

RE: [PATCH] net/mlx5: fix flex item macro collision

2021-11-14 Thread Raslan Darawsheh 
Hi,
> -Original Message-
> From: Gregory Etelson 
> Sent: Thursday, November 11, 2021 6:23 PM
> To: dev@dpdk.org; Gregory Etelson ; Slava Ovsiienko
> 
> Cc: Matan Azrad 
> Subject: [PATCH] net/mlx5: fix flex item macro collision
> 
> Flex item macro definition values duplicated existing connection tracking
> values.
> 
> The patch provides new values for flex item macros.
> 
> Fixes: a23e9b6e3ee9 ("net/mlx5: handle flex item in flows")
> 
> Signed-off-by: Gregory Etelson 
> Acked-by: Viacheslav Ovsiienko 

Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh

RE: [PATCH] net/mlx5: fix the delay drop bit set overflow

2021-11-14 Thread Raslan Darawsheh 
Hi,


> -Original Message-
> From: Bing Zhao 
> Sent: Friday, November 12, 2021 4:39 PM
> To: Slava Ovsiienko ; Matan Azrad
> 
> Cc: dev@dpdk.org; Raslan Darawsheh 
> Subject: [PATCH] net/mlx5: fix the delay drop bit set overflow
> 
> The attribute to record the global control of hairpin queues' delay drop was
> defined as a bit-field with one bit, and the intention was to reduce the
> memory overhead. In the meanwhile, the macro was defined as an
> enumerated value 0x2.
> 
> No matter what value inputted via devarg, the lowest bit was always zero
> and the higher bits would be ignored. For hairpin queues, the delay drop
> attribute couldn't be enabled.
> 
> With the commit, the double logical negation is used to fix this.
> 
> Fixes: febcac7b46cd ("net/mlx5: support Rx queue delay drop")
> 
> Signed-off-by: Bing Zhao 
> Acked-by: Viacheslav Ovsiienko 

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

[PATCH 1/5] net/mlx5: fix VXLAN-GPE next protocol translation

2021-11-14 Thread Gregory Etelson 
VXLAN-GPE extends VXLAN protocol and provides the next protocol
field specifying the first inner header type.

The application can assign some explicit value to
VXLAN-GPE::next_protocol field or set it to the default one. In the
latter case, the rdma-core library cannot recognize the matcher
built by PMD correctly, and it results in hardware configuration
missing inner headers match.

The patch forces VXLAN-GPE::next_protocol assignment if the
application did not explicitly assign it to the non-default value

Cc: sta...@dpdk.org

Fixes: 90456726eb80 ("net/mlx5: fix VXLAN-GPE item translation")
Signed-off-by: Gregory Etelson 
---
 drivers/net/mlx5/mlx5_flow_dv.c | 76 ++---
 1 file changed, 42 insertions(+), 34 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 1b4e15dff1..f9acb69cca 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -8962,46 +8962,40 @@ flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
 
 static void
 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
-const struct rte_flow_item *item, int inner)
+const struct rte_flow_item *item,
+const uint64_t pattern_flags)
 {
+   static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
-   void *headers_m;
-   void *headers_v;
+   /* The item was validated to be on the outer side */
+   void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
+   void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
void *misc_m =
MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
void *misc_v =
MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
-   char *vni_m;
-   char *vni_v;
-   uint16_t dport;
-   int size;
-   int i;
+   char *vni_m =
+   MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
+   char *vni_v =
+   MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
+   int i, size = sizeof(vxlan_m->vni);
uint8_t flags_m = 0xff;
uint8_t flags_v = 0xc;
+   uint8_t m_protocol, v_protocol;
 
-   if (inner) {
-   headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
-inner_headers);
-   headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
-   } else {
-   headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
-outer_headers);
-   headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
-   }
-   dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
-   MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0x);
-   MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
+   MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
+MLX5_UDP_PORT_VXLAN_GPE);
+   }
+   if (!vxlan_v) {
+   vxlan_v = &dummy_vxlan_gpe_hdr;
+   vxlan_m = &dummy_vxlan_gpe_hdr;
+   } else {
+   if (!vxlan_m)
+   vxlan_m = &rte_flow_item_vxlan_gpe_mask;
}
-   if (!vxlan_v)
-   return;
-   if (!vxlan_m)
-   vxlan_m = &rte_flow_item_vxlan_gpe_mask;
-   size = sizeof(vxlan_m->vni);
-   vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
-   vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
memcpy(vni_m, vxlan_m->vni, size);
for (i = 0; i < size; ++i)
vni_v[i] = vni_m[i] & vxlan_v->vni[i];
@@ -9011,10 +9005,22 @@ flow_dv_translate_item_vxlan_gpe(void *matcher, void 
*key,
}
MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
-   MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
-vxlan_m->protocol);
-   MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
-vxlan_v->protocol);
+   m_protocol = vxlan_m->protocol;
+   v_protocol = vxlan_v->protocol;
+   if (!m_protocol) {
+   m_protocol = 0xff;
+   /* Force next protocol to ensure next headers parsing. */
+   if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
+   v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
+   else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
+   v_proto

[PATCH 2/5] net/mlx5: add Ethernet header to GENEVE RSS expansion

2021-11-14 Thread Gregory Etelson 
RFC-8926 allows inner Ethernet header after GENEVE
tunnel.

Current GENEVE RSS expansion created IPv4 and IPv6 paths
only.

The patch adds Ethernet to RSS expansion scheme.

Cc: sta...@dpdk.org
Signed-off-by: Gregory Etelson 
---
 drivers/net/mlx5/mlx5_flow.c | 34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index f657980737..205fe19cdd 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -258,6 +258,29 @@ mlx5_flow_expand_rss_item_complete(const struct 
rte_flow_item *item)
else
ret = RTE_FLOW_ITEM_TYPE_END;
break;
+   case RTE_FLOW_ITEM_TYPE_GENEVE:
+   ether_type_m = item->mask ?
+  ((const struct rte_flow_item_geneve *)
+  (item->mask))->protocol :
+  rte_flow_item_geneve_mask.protocol;
+   ether_type = ((const struct rte_flow_item_geneve *)
+(item->spec))->protocol;
+   ether_type_m = rte_be_to_cpu_16(ether_type_m);
+   ether_type = rte_be_to_cpu_16(ether_type);
+   switch (ether_type_m & ether_type) {
+   case RTE_ETHER_TYPE_TEB:
+   ret = RTE_FLOW_ITEM_TYPE_ETH;
+   break;
+   case RTE_ETHER_TYPE_IPV4:
+   ret = RTE_FLOW_ITEM_TYPE_IPV4;
+   break;
+   case RTE_ETHER_TYPE_IPV6:
+   ret = RTE_FLOW_ITEM_TYPE_IPV6;
+   break;
+   default:
+   ret = RTE_FLOW_ITEM_TYPE_END;
+   }
+   break;
default:
ret = RTE_FLOW_ITEM_TYPE_VOID;
break;
@@ -530,7 +553,8 @@ enum mlx5_expansion {
MLX5_EXPANSION_IPV6_UDP,
MLX5_EXPANSION_IPV6_TCP,
MLX5_EXPANSION_IPV6_FRAG_EXT,
-   MLX5_EXPANSION_GTP
+   MLX5_EXPANSION_GTP,
+   MLX5_EXPANSION_GENEVE,
 };
 
 /** Supported expansion of items. */
@@ -574,6 +598,7 @@ static const struct mlx5_flow_expand_node 
mlx5_support_expansion[] = {
.next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN,
  MLX5_EXPANSION_VXLAN_GPE,
  MLX5_EXPANSION_MPLS,
+ MLX5_EXPANSION_GENEVE,
  MLX5_EXPANSION_GTP),
.type = RTE_FLOW_ITEM_TYPE_UDP,
.rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP,
@@ -598,6 +623,7 @@ static const struct mlx5_flow_expand_node 
mlx5_support_expansion[] = {
.next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN,
  MLX5_EXPANSION_VXLAN_GPE,
  MLX5_EXPANSION_MPLS,
+ MLX5_EXPANSION_GENEVE,
  MLX5_EXPANSION_GTP),
.type = RTE_FLOW_ITEM_TYPE_UDP,
.rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP,
@@ -701,6 +727,12 @@ static const struct mlx5_flow_expand_node 
mlx5_support_expansion[] = {
  MLX5_EXPANSION_IPV6),
.type = RTE_FLOW_ITEM_TYPE_GTP,
},
+   [MLX5_EXPANSION_GENEVE] = {
+   .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH,
+ MLX5_EXPANSION_IPV4,
+ MLX5_EXPANSION_IPV6),
+   .type = RTE_FLOW_ITEM_TYPE_GENEVE,
+   },
 };
 
 static struct rte_flow_action_handle *
-- 
2.33.1

[PATCH 3/5] net/mlx5: fix RSS expansion scheme for GRE header

2021-11-14 Thread Gregory Etelson 
RFC-2784 allows any valid Ethernet type in GRE protocol type field.

Add Ethernet to GRE RSS expansion.

Cc: sta...@dpdk.org

Fixes: f4b901a46aec ("net/mlx5: add flow GRE item")
Signed-off-by: Gregory Etelson 
---
 drivers/net/mlx5/mlx5_flow.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 205fe19cdd..43598f92ee 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -654,7 +654,8 @@ static const struct mlx5_flow_expand_node 
mlx5_support_expansion[] = {
.type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE,
},
[MLX5_EXPANSION_GRE] = {
-   .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4,
+   .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH,
+ MLX5_EXPANSION_IPV4,
  MLX5_EXPANSION_IPV6,
  MLX5_EXPANSION_GRE_KEY,
  MLX5_EXPANSION_MPLS),
-- 
2.33.1

[PATCH 4/5] net/mlx5: fix GENEVE protocol type translation

2021-11-14 Thread Gregory Etelson 
When application creates several flows to match on GENEVE tunnel
without explicitly specifying GENEVE protocol type value in
flow rules, PMD will translate that to zero mask.
RDMA-CORE cannot distinguish between different inner flow types and
produces identical matchers for each zero mask.

The patch extracts inner header type from flow rule and forces it
in GENEVE protocol type, if application did not specify
any without explicitly specifying GENEVE protocol type value in
flow rules, protocol type value.

Cc: sta...@dpdk.org

Fixes: e59a5dbcfd07 ("net/mlx5: add flow match on GENEVE item")
Signed-off-by: Gregory Etelson 
---
 drivers/net/mlx5/mlx5_flow_dv.c | 78 -
 1 file changed, 47 insertions(+), 31 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index f9acb69cca..bce504391d 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -93,6 +93,20 @@ static int
 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  uint32_t rix_jump);
 
+static inline uint16_t
+mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
+{
+   if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
+   return RTE_ETHER_TYPE_TEB;
+   else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
+   return RTE_ETHER_TYPE_IPV4;
+   else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
+   return RTE_ETHER_TYPE_IPV6;
+   else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
+   return RTE_ETHER_TYPE_MPLS;
+   return 0;
+}
+
 static int16_t
 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
 {
@@ -9038,49 +9052,39 @@ flow_dv_translate_item_vxlan_gpe(void *matcher, void 
*key,
 
 static void
 flow_dv_translate_item_geneve(void *matcher, void *key,
- const struct rte_flow_item *item, int inner)
+ const struct rte_flow_item *item,
+ uint64_t pattern_flags)
 {
+   static const struct rte_flow_item_geneve empty_geneve = {0,};
const struct rte_flow_item_geneve *geneve_m = item->mask;
const struct rte_flow_item_geneve *geneve_v = item->spec;
-   void *headers_m;
-   void *headers_v;
+   /* GENEVE flow item validation allows single tunnel item */
+   void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
+   void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
-   uint16_t dport;
uint16_t gbhdr_m;
uint16_t gbhdr_v;
-   char *vni_m;
-   char *vni_v;
-   size_t size, i;
+   char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
+   char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
+   size_t size = sizeof(geneve_m->vni), i;
+   uint16_t protocol_m, protocol_v;
 
-   if (inner) {
-   headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
-inner_headers);
-   headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
-   } else {
-   headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
-outer_headers);
-   headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
-   }
-   dport = MLX5_UDP_PORT_GENEVE;
if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0x);
-   MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
+   MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
+MLX5_UDP_PORT_GENEVE);
+   }
+   if (!geneve_v) {
+   geneve_v = &empty_geneve;
+   geneve_m = &empty_geneve;
+   } else {
+   if (!geneve_m)
+   geneve_m = &rte_flow_item_geneve_mask;
}
-   if (!geneve_v)
-   return;
-   if (!geneve_m)
-   geneve_m = &rte_flow_item_geneve_mask;
-   size = sizeof(geneve_m->vni);
-   vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
-   vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
memcpy(vni_m, geneve_m->vni, size);
for (i = 0; i < size; ++i)
vni_v[i] = vni_m[i] & geneve_v->vni[i];
-   MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
-rte_be_to_cpu_16(geneve_m->protocol));
-   MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
-rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
MLX5_SET(f

[PATCH 5/5] net/mlx5: fix GRE protocol type translation

2021-11-14 Thread Gregory Etelson 
When application creates several flows to match on GRE tunnel
without explicitly specifying GRE protocol type value in
flow rules, PMD will translate that to zero mask.
RDMA-CORE cannot distinguish between different inner flow types and
produces identical matchers for each zero mask.

The patch extracts inner header type from flow rule and forces it
in GRE protocol type, if application did not specify
any without explicitly specifying GRE protocol type value in
flow rules, protocol type value.

Cc: sta...@dpdk.org

Fixes: fc2c498ccb94 ("net/mlx5: add Direct Verbs translate items")

Signed-off-by: Gregory Etelson 
---
 drivers/net/mlx5/mlx5_flow_dv.c | 70 +++--
 1 file changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index bce504391d..287a17d956 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -8730,18 +8730,19 @@ flow_dv_translate_item_gre_key(void *matcher, void *key,
  *   Flow matcher value.
  * @param[in] item
  *   Flow pattern to translate.
- * @param[in] inner
- *   Item is inner pattern.
+ * @param[in] pattern_flags
+ *   Accumulated pattern flags.
  */
 static void
 flow_dv_translate_item_gre(void *matcher, void *key,
   const struct rte_flow_item *item,
-  int inner)
+  uint64_t pattern_flags)
 {
+   static const struct rte_flow_item_gre empty_gre = {0,};
const struct rte_flow_item_gre *gre_m = item->mask;
const struct rte_flow_item_gre *gre_v = item->spec;
-   void *headers_m;
-   void *headers_v;
+   void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
+   void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
struct {
@@ -8758,26 +8759,17 @@ flow_dv_translate_item_gre(void *matcher, void *key,
uint16_t value;
};
} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
+   uint16_t protocol_m, protocol_v;
 
-   if (inner) {
-   headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
-inner_headers);
-   headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
-   } else {
-   headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
-outer_headers);
-   headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
-   }
MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
-   if (!gre_v)
-   return;
-   if (!gre_m)
-   gre_m = &rte_flow_item_gre_mask;
-   MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
-rte_be_to_cpu_16(gre_m->protocol));
-   MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
-rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+   if (!gre_v) {
+   gre_v = &empty_gre;
+   gre_m = &empty_gre;
+   } else {
+   if (!gre_m)
+   gre_m = &rte_flow_item_gre_mask;
+   }
gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
@@ -8795,6 +8787,16 @@ flow_dv_translate_item_gre(void *matcher, void *key,
MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
 gre_crks_rsvd0_ver_v.s_present &
 gre_crks_rsvd0_ver_m.s_present);
+   protocol_m = rte_be_to_cpu_16(gre_m->protocol);
+   protocol_v = rte_be_to_cpu_16(gre_v->protocol);
+   if (!protocol_m) {
+   /* Force next protocol to prevent matchers duplication */
+   protocol_m = 0x;
+   protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
+   }
+   MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
+   MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
+protocol_m & protocol_v);
 }
 
 /**
@@ -8806,13 +8808,13 @@ flow_dv_translate_item_gre(void *matcher, void *key,
  *   Flow matcher value.
  * @param[in] item
  *   Flow pattern to translate.
- * @param[in] inner
- *   Item is inner pattern.
+ * @param[in] pattern_flags
+ *   Accumulated pattern flags.
  */
 static void
 flow_dv_translate_item_nvgre(void *matcher, void *key,
 const struct rte_flow_item *item,
-int inner)
+unsigned long pattern_flags)
 {
const struct rte_flow_item_nvgre *nvgre_m = item->mask;
const struct rte_flow_item_nvgre *nvgre_v = item->spec;
@@

Re: [PATCH v2] test/bpf_convert: do not require DNS lookup

2021-11-14 Thread Luca Boccassi 
On Wed, 10 Nov 2021 at 16:18, Stephen Hemminger
 wrote:
>
> These tests were using strings with hostname (dpdk.org) and this makes
> test code do a DNS lookup. In container environment used for OpenSuse
> build, DNS is unavailable.  Replace dpdk.org with an IPv4 address
> reserved for documentation (RFC 5737) and use IPv6 in one example (RFC 3849).
> Actual addresses don't matter for this test whichis validating tke
> classic BPF to eBPF for common cases.
>
> Signed-off-by: Stephen Hemminger 
> ---
> v2 - use RFC reserved address
>
>  app/test/test_bpf.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/app/test/test_bpf.c b/app/test/test_bpf.c
> index ef861d05e755..785f3e689e10 100644
> --- a/app/test/test_bpf.c
> +++ b/app/test/test_bpf.c
> @@ -3359,8 +3359,8 @@ static const char * const sample_filters[] = {
> "dst net 192.168.0.0/24",
> "dst net 192.168.0.0 mask 255.255.255.0",
> "port 53",
> -   "host dpdk.org and not (port 80 or port 25)",
> -   "host dpdk.org and not port 80 and not port 25",
> +   "host 192.0.2.1 and not (port 80 or port 25)",
> +   "host 2001:4b98:db0::8 and not port 80 and not port 25",
> "port not 53 and not arp",
> "(tcp[0:2] > 1500 and tcp[0:2] < 1550) or (tcp[2:2] > 1500 and 
> tcp[2:2] < 1550)",
> "ether proto 0x888e",
> --
> 2.30.2

Acked-by: Luca Boccassi

RE: [PATCH v4 15/18] vhost: fix typo in comment

2021-11-14 Thread Xia, Chenbo 
> -Original Message-
> From: Stephen Hemminger 
> Sent: Friday, November 12, 2021 8:02 AM
> To: dev@dpdk.org
> Cc: Stephen Hemminger ; Maxime Coquelin
> ; Xia, Chenbo 
> Subject: [PATCH v4 15/18] vhost: fix typo in comment
> 
> Yet another spelling error found by codespell.
> 
> Signed-off-by: Stephen Hemminger 
> ---
>  lib/vhost/rte_vhost.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/vhost/rte_vhost.h b/lib/vhost/rte_vhost.h
> index af0afbcf60e0..b454c05868e1 100644
> --- a/lib/vhost/rte_vhost.h
> +++ b/lib/vhost/rte_vhost.h
> @@ -796,7 +796,7 @@ rte_vhost_get_vhost_ring_inflight(int vid, uint16_t
> vring_idx,
>  /**
>   * Set split inflight descriptor.
>   *
> - * This function save descriptors that has been comsumed in available
> + * This function save descriptors that has been consumed in available
>   * ring
>   *
>   * @param vid
> @@ -815,7 +815,7 @@ rte_vhost_set_inflight_desc_split(int vid, uint16_t
> vring_idx,
>  /**
>   * Set packed inflight descriptor and get corresponding inflight entry
>   *
> - * This function save descriptors that has been comsumed
> + * This function save descriptors that has been consumed
>   *
>   * @param vid
>   *  vhost device ID
> --
> 2.30.2

Acked-by: Chenbo Xia

[PATCH v2] net/ice: fix secondary process Rx offload path

2021-11-14 Thread Alvin Zhang 
Secondary process depends on the vector offload flag to select right
Rx offload path. This patch adds a variable in share memory to store
the vector offload flag that can be directly read by secondary process.

Fixes: 808a17b3c1e6 ("net/ice: add Rx AVX512 offload path")
Cc: sta...@dpdk.org

Signed-off-by: Alvin Zhang 
---
 drivers/net/ice/ice_ethdev.h |  1 +
 drivers/net/ice/ice_rxtx.c   | 19 +++
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h
index 3a5bb9b..52daae0 100644
--- a/drivers/net/ice/ice_ethdev.h
+++ b/drivers/net/ice/ice_ethdev.h
@@ -538,6 +538,7 @@ struct ice_adapter {
bool rx_use_avx512;
bool tx_use_avx2;
bool tx_use_avx512;
+   int rx_vec_path;
 #endif
 };
 
diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c
index 2d771ea..981493e 100644
--- a/drivers/net/ice/ice_rxtx.c
+++ b/drivers/net/ice/ice_rxtx.c
@@ -3172,15 +3172,14 @@
 #ifdef RTE_ARCH_X86
struct ice_rx_queue *rxq;
int i;
-   int rx_check_ret = -1;
 
if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
ad->rx_use_avx512 = false;
ad->rx_use_avx2 = false;
-   rx_check_ret = ice_rx_vec_dev_check(dev);
+   ad->rx_vec_path = ice_rx_vec_dev_check(dev);
if (ad->ptp_ena)
-   rx_check_ret = -1;
-   if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
+   ad->rx_vec_path = -1;
+   if (ad->rx_vec_path >= 0 && ad->rx_bulk_alloc_allowed &&
rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
ad->rx_vec_allowed = true;
for (i = 0; i < dev->data->nb_rx_queues; i++) {
@@ -3215,7 +3214,8 @@
if (dev->data->scattered_rx) {
if (ad->rx_use_avx512) {
 #ifdef CC_AVX512_SUPPORT
-   if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
+   if (ad->rx_vec_path ==
+   ICE_VECTOR_OFFLOAD_PATH) {
PMD_DRV_LOG(NOTICE,
"Using AVX512 OFFLOAD Vector 
Scattered Rx (port %d).",
dev->data->port_id);
@@ -3230,7 +3230,8 @@
}
 #endif
} else if (ad->rx_use_avx2) {
-   if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
+   if (ad->rx_vec_path ==
+   ICE_VECTOR_OFFLOAD_PATH) {
PMD_DRV_LOG(NOTICE,
"Using AVX2 OFFLOAD Vector 
Scattered Rx (port %d).",
dev->data->port_id);
@@ -3252,7 +3253,8 @@
} else {
if (ad->rx_use_avx512) {
 #ifdef CC_AVX512_SUPPORT
-   if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
+   if (ad->rx_vec_path ==
+   ICE_VECTOR_OFFLOAD_PATH) {
PMD_DRV_LOG(NOTICE,
"Using AVX512 OFFLOAD Vector Rx 
(port %d).",
dev->data->port_id);
@@ -3267,7 +3269,8 @@
}
 #endif
} else if (ad->rx_use_avx2) {
-   if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
+   if (ad->rx_vec_path ==
+   ICE_VECTOR_OFFLOAD_PATH) {
PMD_DRV_LOG(NOTICE,
"Using AVX2 OFFLOAD Vector 
Rx (port %d).",
dev->data->port_id);
-- 
1.8.3.1

[PATCH v3] app/testpmd: fix DCB in VT configuration

2021-11-14 Thread Jie Wang 
When set port DCB in VT mode enabled, it should remove RSS HASH
offload before reconfiguring the device and queues.

Because port multi-queue mode is changed from RSS to DCB in VT.

Fixes: 2a977b891f99 ("app/testpmd: fix DCB configuration")

Signed-off-by: Jie Wang 
---
v3:
 * update commit log.
 * remove RSS HASh offload from DCB in VT.
v2:
 * update commit log.
 * remove RSS HASH offload from port->rx_conf[i].offloads.
---
 app/test-pmd/testpmd.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c
index a66dfb297c..c18942279a 100644
--- a/app/test-pmd/testpmd.c
+++ b/app/test-pmd/testpmd.c
@@ -3948,6 +3948,13 @@ init_port_dcb_config(portid_t pid,
if (retval < 0)
return retval;
port_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_VLAN_FILTER;
+   /* remove RSS HASH offload for DCB in vt mode */
+   if (port_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB) {
+   port_conf.rxmode.offloads &= ~RTE_ETH_RX_OFFLOAD_RSS_HASH;
+   for (i = 0; i < nb_rxq; i++)
+   rte_port->rx_conf[i].offloads &=
+   ~RTE_ETH_RX_OFFLOAD_RSS_HASH;
+   }
 
/* re-configure the device . */
retval = rte_eth_dev_configure(pid, nb_rxq, nb_rxq, &port_conf);
-- 
2.25.1

Re: [PATCH v2] test/bpf_convert: do not require DNS lookup

2021-11-14 Thread Kalesh Anakkur Purayil 
On Wed, Nov 10, 2021 at 9:48 PM Stephen Hemminger <
step...@networkplumber.org> wrote:

> These tests were using strings with hostname (dpdk.org) and this makes
> test code do a DNS lookup. In container environment used for OpenSuse
> build, DNS is unavailable.  Replace dpdk.org with an IPv4 address
>
extra space character before Replace?

> reserved for documentation (RFC 5737) and use IPv6 in one example (RFC
> 3849).
> Actual addresses don't matter for this test whichis validating tke
>
Missing space between which and is and typo in "the"

> classic BPF to eBPF for common cases.
>
> Signed-off-by: Stephen Hemminger 
> ---
> v2 - use RFC reserved address
>
>  app/test/test_bpf.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/app/test/test_bpf.c b/app/test/test_bpf.c
> index ef861d05e755..785f3e689e10 100644
> --- a/app/test/test_bpf.c
> +++ b/app/test/test_bpf.c
> @@ -3359,8 +3359,8 @@ static const char * const sample_filters[] = {
> "dst net 192.168.0.0/24",
> "dst net 192.168.0.0 mask 255.255.255.0",
> "port 53",
> -   "host dpdk.org and not (port 80 or port 25)",
> -   "host dpdk.org and not port 80 and not port 25",
> +   "host 192.0.2.1 and not (port 80 or port 25)",
> +   "host 2001:4b98:db0::8 and not port 80 and not port 25",
> "port not 53 and not arp",
> "(tcp[0:2] > 1500 and tcp[0:2] < 1550) or (tcp[2:2] > 1500 and
> tcp[2:2] < 1550)",
> "ether proto 0x888e",
> --
> 2.30.2
>
>

-- 
Regards,
Kalesh A P

Re: [dpdk-announce] release candidate 21.11-rc2

2021-11-14 Thread Pei Zhang 
Hello Thomas,

The testing with dpdk 21.11-rc2 from Red Hat looks good. We tested below 18
scenarios and all got PASS on RHEL8:

(1)Guest with device assignment(PF) throughput testing(1G hugepage size):
PASS
(2)Guest with device assignment(PF) throughput testing(2M hugepage size) :
PASS
(3)Guest with device assignment(VF) throughput testing: PASS
(4)PVP (host dpdk testpmd as vswitch) 1Q: throughput testing: PASS
(5)PVP vhost-user 2Q throughput testing: PASS
(6)PVP vhost-user 1Q - cross numa node throughput testing: PASS
(7)Guest with vhost-user 2 queues throughput testing: PASS
(8)vhost-user reconnect with dpdk-client, qemu-server: qemu reconnect: PASS
(9)vhost-user reconnect with dpdk-client, qemu-server: ovs reconnect: PASS
(10)PVP 1Q live migration testing: PASS
(11)PVP 1Q cross numa node live migration testing: PASS
(12)Guest with ovs+dpdk+vhost-user 1Q live migration testing: PASS
(13)Guest with ovs+dpdk+vhost-user 1Q live migration testing (2M): PASS
(14)Guest with ovs+dpdk+vhost-user 2Q live migration testing: PASS
(15)Guest with ovs+dpdk+vhost-user 4Q live migration testing: PASS
(16)Host PF + DPDK testing: PASS
(17)Host VF + DPDK testing: PASS
(18)vDPA + host DPDK basic testing: PASS

Versions:
kernel 4.18
qemu 6.2

dpdk: git://dpdk.org/dpdk
# git log -1
commit f4801fdb7828f45ddc4ada148b1b0a230a226570 (HEAD -> main, tag:
v21.11-rc2)
Author: Thomas Monjalon 
Date:   Tue Nov 9 00:45:12 2021 +0100

version: 21.11-rc2

Signed-off-by: Thomas Monjalon 


NICs: X540-AT2 NIC(ixgbe, 10G)

Best regards,

Pei

On Tue, Nov 9, 2021 at 8:45 AM Thomas Monjalon  wrote:

> A new DPDK release candidate is ready for testing:
> https://git.dpdk.org/dpdk/tag/?id=v21.11-rc2
>
> There are 448 new patches in this snapshot.
>
> Release notes:
> https://doc.dpdk.org/guides/rel_notes/release_21_11.html
>
> Highlights of 21.11-rc2:
> - Toeplitz hash using Galois Fields New Instructions (GFNI)
> - virtio RSS
> - vhost power monitor wakeup
> - Xilinx vDPA driver
> - DMA drivers for HiSilicon and Marvell CNXK
> - GPU device class library
> - AddressSanitizer (ASan) integration for debug
> - more API internals hidden (ip_frag, vDPA)
>
> Please test and report issues on bugs.dpdk.org.
> Some bugs found with ASan are tagged and can be found with this query:
> https://bugs.dpdk.org/buglist.cgi?quicksearch=[asan]
>
> DPDK 21.11-rc3 is expected in one week or less.
>
> Thank you everyone
>
>
>

Re: [dpdk-dev] [dpdk-announce] release candidate 21.11-rc2

2021-11-14 Thread Kalesh Anakkur Purayil 
Hi Thomas,

The testing with dpdk 21.11-rc2 from Broadcom looks good. The following is
a list of tests executed with 21.11-rc2:

- Basic functionality:
  Send and receive multiple types of traffic.
- Stats check tests
- RSS tests
- VLAN Offload Tests
- RX/TX Checksum Offload Tests
- Dynamic queue test
- Transmit Segmentation Offload (TSO) Tests
- DPDK Hotplug API Tests
- MTU and Jumbo frame tests
- Changing/checking link status through testpmd.
- Unicast/multicast MAC filtering tests
- VXLAN/Geneve Rx CSO, TSO, RSS tests
- Port Start Stop Tests

We don't see any critical issues blocking the release.

Regards,
Kalesh

On Tue, Nov 9, 2021 at 6:15 AM Thomas Monjalon  wrote:

> A new DPDK release candidate is ready for testing:
> https://git.dpdk.org/dpdk/tag/?id=v21.11-rc2
>
> There are 448 new patches in this snapshot.
>
> Release notes:
> https://doc.dpdk.org/guides/rel_notes/release_21_11.html
>
> Highlights of 21.11-rc2:
> - Toeplitz hash using Galois Fields New Instructions (GFNI)
> - virtio RSS
> - vhost power monitor wakeup
> - Xilinx vDPA driver
> - DMA drivers for HiSilicon and Marvell CNXK
> - GPU device class library
> - AddressSanitizer (ASan) integration for debug
> - more API internals hidden (ip_frag, vDPA)
>
> Please test and report issues on bugs.dpdk.org.
> Some bugs found with ASan are tagged and can be found with this query:
> https://bugs.dpdk.org/buglist.cgi?quicksearch=[asan]
>
> DPDK 21.11-rc3 is expected in one week or less.
>
> Thank you everyone
>
>
>

-- 
Regards,
Kalesh A P

[PATCH v1] app/testpmd: avoid the process ID out of range

2021-11-14 Thread Haiyue Wang 
The 'proc-id' should be less than 'num-procs', if not, exit the testpmd
and show the error message.

Fixes: a550baf24af9 ("app/testpmd: support multi-process")

Signed-off-by: Haiyue Wang 
---
 app/test-pmd/parameters.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/app/test-pmd/parameters.c b/app/test-pmd/parameters.c
index 0974b0a38f..5251722d0f 100644
--- a/app/test-pmd/parameters.c
+++ b/app/test-pmd/parameters.c
@@ -1527,6 +1527,12 @@ launch_args_parse(int argc, char** argv)
rte_exit(EXIT_FAILURE, "Command line is incorrect\n");
}
 
+   if (proc_id >= (int)num_procs)
+   rte_exit(EXIT_FAILURE,
+"The multi-process option '%s(%d)' should be less than 
'%s(%u)'\n",
+PARAM_PROC_ID, proc_id,
+PARAM_NUM_PROCS, num_procs);
+
/* Set offload configuration from command line parameters. */
rx_mode.offloads = rx_offloads;
tx_mode.offloads = tx_offloads;
-- 
2.33.1

[PATCH v11 0/5] drivers/net: add NXP ENETFEC driver

2021-11-14 Thread Apeksha Gupta 
This patch series introduce the enetfec driver, ENETFEC (Fast Ethernet
Controller) is a network poll mode driver for the inbuilt NIC found in
the NXP i.MX 8M Mini SoC.

An overview of the enetfec driver with probe and remove are in patch 1.
Patch 2 design UIO interface so that user space directly communicate with
a UIO based hardware device. UIO interface mmap the Control and Status
Registers (CSR) & BD memory in DPDK which is allocated in kernel and this
gives access to non-cacheble memory for BD.

Patch 3 adds the RX/TX queue configuration setup operations.
Patch 4 adds enqueue and dequeue support. Also adds some basic features
like promiscuous enable, basic stats.
Patch 5 adds checksum and VLAN features.

Apeksha Gupta (5):
  net/enetfec: introduce NXP ENETFEC driver
  net/enetfec: add UIO support
  net/enetfec: support queue configuration
  net/enetfec: add Rx/Tx support
  net/enetfec: add features

 MAINTAINERS|   7 +
 doc/guides/nics/enetfec.rst| 137 +
 doc/guides/nics/features/enetfec.ini   |  14 +
 doc/guides/nics/index.rst  |   1 +
 doc/guides/rel_notes/release_21_11.rst |   5 +
 drivers/net/enetfec/enet_ethdev.c  | 701 +
 drivers/net/enetfec/enet_ethdev.h  | 153 ++
 drivers/net/enetfec/enet_pmd_logs.h|  31 ++
 drivers/net/enetfec/enet_regs.h| 116 
 drivers/net/enetfec/enet_rxtx.c| 273 ++
 drivers/net/enetfec/enet_uio.c | 284 ++
 drivers/net/enetfec/enet_uio.h |  64 +++
 drivers/net/enetfec/meson.build|  13 +
 drivers/net/enetfec/version.map|   3 +
 drivers/net/meson.build|   1 +
 15 files changed, 1803 insertions(+)
 create mode 100644 doc/guides/nics/enetfec.rst
 create mode 100644 doc/guides/nics/features/enetfec.ini
 create mode 100644 drivers/net/enetfec/enet_ethdev.c
 create mode 100644 drivers/net/enetfec/enet_ethdev.h
 create mode 100644 drivers/net/enetfec/enet_pmd_logs.h
 create mode 100644 drivers/net/enetfec/enet_regs.h
 create mode 100644 drivers/net/enetfec/enet_rxtx.c
 create mode 100644 drivers/net/enetfec/enet_uio.c
 create mode 100644 drivers/net/enetfec/enet_uio.h
 create mode 100644 drivers/net/enetfec/meson.build
 create mode 100644 drivers/net/enetfec/version.map

-- 
2.17.1

[PATCH v11 1/5] net/enetfec: introduce NXP ENETFEC driver

2021-11-14 Thread Apeksha Gupta 
ENETFEC (Fast Ethernet Controller) is a network poll mode driver
for NXP SoC i.MX 8M Mini.

This patch adds skeleton for enetfec driver with probe function.

Signed-off-by: Sachin Saxena 
Signed-off-by: Apeksha Gupta 
Acked-by: Hemant Agrawal 
---
 MAINTAINERS|   7 ++
 doc/guides/nics/enetfec.rst| 133 +
 doc/guides/nics/features/enetfec.ini   |   9 ++
 doc/guides/nics/index.rst  |   1 +
 doc/guides/rel_notes/release_21_11.rst |   5 +
 drivers/net/enetfec/enet_ethdev.c  |  82 +++
 drivers/net/enetfec/enet_ethdev.h  |  18 
 drivers/net/enetfec/enet_pmd_logs.h|  31 ++
 drivers/net/enetfec/meson.build|  10 ++
 drivers/net/enetfec/version.map|   3 +
 drivers/net/meson.build|   1 +
 11 files changed, 300 insertions(+)
 create mode 100644 doc/guides/nics/enetfec.rst
 create mode 100644 doc/guides/nics/features/enetfec.ini
 create mode 100644 drivers/net/enetfec/enet_ethdev.c
 create mode 100644 drivers/net/enetfec/enet_ethdev.h
 create mode 100644 drivers/net/enetfec/enet_pmd_logs.h
 create mode 100644 drivers/net/enetfec/meson.build
 create mode 100644 drivers/net/enetfec/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index e157e12f88..2aa81efe20 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -889,6 +889,13 @@ F: drivers/net/enetc/
 F: doc/guides/nics/enetc.rst
 F: doc/guides/nics/features/enetc.ini
 
+NXP enetfec - EXPERIMENTAL
+M: Apeksha Gupta 
+M: Sachin Saxena 
+F: drivers/net/enetfec/
+F: doc/guides/nics/enetfec.rst
+F: doc/guides/nics/features/enetfec.ini
+
 NXP pfe
 M: Gagandeep Singh 
 F: doc/guides/nics/pfe.rst
diff --git a/doc/guides/nics/enetfec.rst b/doc/guides/nics/enetfec.rst
new file mode 100644
index 00..6a86295e34
--- /dev/null
+++ b/doc/guides/nics/enetfec.rst
@@ -0,0 +1,133 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+   Copyright 2021 NXP
+
+ENETFEC Poll Mode Driver
+
+
+The ENETFEC NIC PMD (**librte_net_enetfec**) provides poll mode driver
+support for the inbuilt NIC found in the ** NXP i.MX 8M Mini** SoC.
+
+More information can be found at NXP Official Website
+
+
+ENETFEC
+---
+
+This section provides an overview of the NXP ENETFEC and how it is
+integrated into the DPDK. Driver is taken as **experimental** as driver
+depends on a Linux kernel module 'enetfec-uio', which is not upstreamed
+yet.
+
+Contents summary
+
+- ENETFEC overview
+- ENETFEC features
+- Supported ENETFEC SoCs
+- Prerequisites
+- Driver compilation and testing
+- Limitations
+
+ENETFEC Overview
+
+The i.MX 8M Mini Media Applications Processor is built to achieve both
+high performance and low power consumption. ENETFEC PMD is a hardware
+programmable packet forwarding engine to provide high performance
+Ethernet interface. It has only 1 GB Ethernet interface with RJ45
+connector.
+
+The diagram below shows a system level overview of ENETFEC:
+
+  .. code-block:: console
+
+   =
+   Userspace
++-+
+| ENETFEC Driver  |
+|+-+  |
+|| virtual ethernet device |  |
++-+
+  ^   |
+  |   |
+  |   |
+ RXQ  |   |TXQ
+  |   |
+  |   v
+   =
+   Kernel Space
+   +-+
+   | fec-uio |
+   +=+==
+   Hardware
++-+
+|   i.MX 8M MINI EVK  |
+|   +-+   |
+|   | MAC |   |
++---+-+---+
+| PHY |
++-+
+
+ENETFEC Ethernet driver is traditional DPDK PMD driver running in the
+userspace.'fec-uio' is the kernel driver. The MAC and PHY are the hardware
+blocks. ENETFEC PMD uses standard UIO interface to access kernel for PHY
+initialisation and for mapping the allocated memory of register & buffer
+descriptor with DPDK which gives access to non-cacheable memory for buffer
+descriptor. net_enetfec is logical Ethernet interface, created by ENETFEC
+driver.
+
+- ENETFEC driver registers the device in virtual device driver.
+- RTE framework scans and will invoke the probe function of ENETFEC driver.
+- The probe function will set the basic device registers and also setups BD 
rings.
+- On packet Rx t

[PATCH v11 2/5] net/enetfec: add UIO support

2021-11-14 Thread Apeksha Gupta 
Implemented the fec-uio driver in kernel. enetfec PMD uses
UIO interface to interact with "fec-uio" driver implemented in
kernel for PHY initialisation and for mapping the allocated memory
of register & BD from kernel to DPDK which gives access to
non-cacheable memory for BD.

Signed-off-by: Sachin Saxena 
Signed-off-by: Apeksha Gupta 
Acked-by: Hemant Agrawal 
---
 drivers/net/enetfec/enet_ethdev.c | 209 ++
 drivers/net/enetfec/enet_ethdev.h |  31 
 drivers/net/enetfec/enet_regs.h   | 106 +++
 drivers/net/enetfec/enet_uio.c| 284 ++
 drivers/net/enetfec/enet_uio.h|  64 +++
 drivers/net/enetfec/meson.build   |   3 +-
 6 files changed, 696 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/enetfec/enet_regs.h
 create mode 100644 drivers/net/enetfec/enet_uio.c
 create mode 100644 drivers/net/enetfec/enet_uio.h

diff --git a/drivers/net/enetfec/enet_ethdev.c 
b/drivers/net/enetfec/enet_ethdev.c
index 56bd199191..8bed091efe 100644
--- a/drivers/net/enetfec/enet_ethdev.c
+++ b/drivers/net/enetfec/enet_ethdev.c
@@ -13,14 +13,192 @@
 #include 
 #include 
 #include 
+#include 
 #include "enet_pmd_logs.h"
 #include "enet_ethdev.h"
+#include "enet_regs.h"
+#include "enet_uio.h"
 
 #define ENETFEC_NAME_PMDnet_enetfec
 
+/* FEC receive acceleration */
+#define ENETFEC_RACC_IPDIS RTE_BIT32(1)
+#define ENETFEC_RACC_PRODISRTE_BIT32(2)
+#define ENETFEC_RACC_SHIFT16   RTE_BIT32(7)
+#define ENETFEC_RACC_OPTIONS   (ENETFEC_RACC_IPDIS | \
+   ENETFEC_RACC_PRODIS)
+
+#define ENETFEC_PAUSE_FLAG_AUTONEG 0x1
+#define ENETFEC_PAUSE_FLAG_ENABLE  0x2
+
+/* Pause frame field and FIFO threshold */
+#define ENETFEC_FCERTE_BIT32(5)
+#define ENETFEC_RSEM_V 0x84
+#define ENETFEC_RSFL_V 16
+#define ENETFEC_RAEM_V 0x8
+#define ENETFEC_RAFL_V 0x8
+#define ENETFEC_OPD_V  0xFFF0
+
+#define NUM_OF_BD_QUEUES   6
+
+/*
+ * This function is called to start or restart the ENETFEC during a link
+ * change, transmit timeout, or to reconfigure the ENETFEC. The network
+ * packet processing for this device must be stopped before this call.
+ */
+static void
+enetfec_restart(struct rte_eth_dev *dev)
+{
+   struct enetfec_private *fep = dev->data->dev_private;
+   uint32_t rcntl = OPT_FRAME_SIZE | 0x04;
+   uint32_t ecntl = ENETFEC_ETHEREN;
+   uint32_t val;
+
+   /* Clear any outstanding interrupt. */
+   writel(0x, (uint8_t *)fep->hw_baseaddr_v + ENETFEC_EIR);
+
+   /* Enable MII mode */
+   if (fep->full_duplex == FULL_DUPLEX) {
+   /* FD enable */
+   rte_write32(rte_cpu_to_le_32(0x04),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_TCR);
+   } else {
+   /* No Rcv on Xmit */
+   rcntl |= 0x02;
+   rte_write32(0, (uint8_t *)fep->hw_baseaddr_v + ENETFEC_TCR);
+   }
+
+   if (fep->quirks & QUIRK_RACC) {
+   val = rte_read32((uint8_t *)fep->hw_baseaddr_v + ENETFEC_RACC);
+   /* align IP header */
+   val |= ENETFEC_RACC_SHIFT16;
+   val &= ~ENETFEC_RACC_OPTIONS;
+   rte_write32(rte_cpu_to_le_32(val),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_RACC);
+   rte_write32(rte_cpu_to_le_32(PKT_MAX_BUF_SIZE),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_FRAME_TRL);
+   }
+
+   /*
+* The phy interface and speed need to get configured
+* differently on enet-mac.
+*/
+   if (fep->quirks & QUIRK_HAS_ENETFEC_MAC) {
+   /* Enable flow control and length check */
+   rcntl |= 0x4000 | 0x0020;
+
+   /* RGMII, RMII or MII */
+   rcntl |= RTE_BIT32(6);
+   ecntl |= RTE_BIT32(5);
+   }
+
+   /* enable pause frame*/
+   if ((fep->flag_pause & ENETFEC_PAUSE_FLAG_ENABLE) ||
+   ((fep->flag_pause & ENETFEC_PAUSE_FLAG_AUTONEG)
+   /*&& ndev->phydev && ndev->phydev->pause*/)) {
+   rcntl |= ENETFEC_FCE;
+
+   /* set FIFO threshold parameter to reduce overrun */
+   rte_write32(rte_cpu_to_le_32(ENETFEC_RSEM_V),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_R_FIFO_SEM);
+   rte_write32(rte_cpu_to_le_32(ENETFEC_RSFL_V),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_R_FIFO_SFL);
+   rte_write32(rte_cpu_to_le_32(ENETFEC_RAEM_V),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_R_FIFO_AEM);
+   rte_write32(rte_cpu_to_le_32(ENETFEC_RAFL_V),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_R_FIFO_AFL);
+
+   /* OPD */
+   rte_write32(rte_cpu_to_le_32(ENETFEC_OPD_V),

[PATCH v11 3/5] net/enetfec: support queue configuration

2021-11-14 Thread Apeksha Gupta 
This patch adds Rx/Tx queue configuration setup operations.
On packet reception the respective BD Ring status bit is set
which is then used for packet processing.

Signed-off-by: Sachin Saxena 
Signed-off-by: Apeksha Gupta 
Acked-by: Hemant Agrawal 
---
 drivers/net/enetfec/enet_ethdev.c | 220 +-
 drivers/net/enetfec/enet_ethdev.h |  77 +++
 2 files changed, 296 insertions(+), 1 deletion(-)

diff --git a/drivers/net/enetfec/enet_ethdev.c 
b/drivers/net/enetfec/enet_ethdev.c
index 8bed091efe..0b8b73615d 100644
--- a/drivers/net/enetfec/enet_ethdev.c
+++ b/drivers/net/enetfec/enet_ethdev.c
@@ -41,6 +41,11 @@
 
 #define NUM_OF_BD_QUEUES   6
 
+/* Supported Rx offloads */
+static uint64_t dev_rx_offloads_sup =
+   RTE_ETH_RX_OFFLOAD_CHECKSUM |
+   RTE_ETH_RX_OFFLOAD_VLAN;
+
 /*
  * This function is called to start or restart the ENETFEC during a link
  * change, transmit timeout, or to reconfigure the ENETFEC. The network
@@ -186,10 +191,223 @@ enetfec_eth_stop(struct rte_eth_dev *dev)
return 0;
 }
 
+static int
+enetfec_eth_info(__rte_unused struct rte_eth_dev *dev,
+   struct rte_eth_dev_info *dev_info)
+{
+   dev_info->max_rx_pktlen = ENETFEC_MAX_RX_PKT_LEN;
+   dev_info->max_rx_queues = ENETFEC_MAX_Q;
+   dev_info->max_tx_queues = ENETFEC_MAX_Q;
+   dev_info->rx_offload_capa = dev_rx_offloads_sup;
+   return 0;
+}
+
+static const unsigned short offset_des_active_rxq[] = {
+   ENETFEC_RDAR_0, ENETFEC_RDAR_1, ENETFEC_RDAR_2
+};
+
+static const unsigned short offset_des_active_txq[] = {
+   ENETFEC_TDAR_0, ENETFEC_TDAR_1, ENETFEC_TDAR_2
+};
+
+static int
+enetfec_tx_queue_setup(struct rte_eth_dev *dev,
+   uint16_t queue_idx,
+   uint16_t nb_desc,
+   unsigned int socket_id __rte_unused,
+   const struct rte_eth_txconf *tx_conf)
+{
+   struct enetfec_private *fep = dev->data->dev_private;
+   unsigned int i;
+   struct bufdesc *bdp, *bd_base;
+   struct enetfec_priv_tx_q *txq;
+   unsigned int size;
+   unsigned int dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
+   sizeof(struct bufdesc);
+   unsigned int dsize_log2 = fls64(dsize);
+
+   /* Tx deferred start is not supported */
+   if (tx_conf->tx_deferred_start) {
+   ENETFEC_PMD_ERR("Tx deferred start not supported");
+   return -EINVAL;
+   }
+
+   /* allocate transmit queue */
+   txq = rte_zmalloc(NULL, sizeof(*txq), RTE_CACHE_LINE_SIZE);
+   if (txq == NULL) {
+   ENETFEC_PMD_ERR("transmit queue allocation failed");
+   return -ENOMEM;
+   }
+
+   if (nb_desc > MAX_TX_BD_RING_SIZE) {
+   nb_desc = MAX_TX_BD_RING_SIZE;
+   ENETFEC_PMD_WARN("modified the nb_desc to MAX_TX_BD_RING_SIZE");
+   }
+   txq->bd.ring_size = nb_desc;
+   fep->total_tx_ring_size += txq->bd.ring_size;
+   fep->tx_queues[queue_idx] = txq;
+
+   rte_write32(rte_cpu_to_le_32(fep->bd_addr_p_t[queue_idx]),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_TD_START(queue_idx));
+
+   /* Set transmit descriptor base. */
+   txq = fep->tx_queues[queue_idx];
+   txq->fep = fep;
+   size = dsize * txq->bd.ring_size;
+   bd_base = (struct bufdesc *)fep->dma_baseaddr_t[queue_idx];
+   txq->bd.queue_id = queue_idx;
+   txq->bd.base = bd_base;
+   txq->bd.cur = bd_base;
+   txq->bd.d_size = dsize;
+   txq->bd.d_size_log2 = dsize_log2;
+   txq->bd.active_reg_desc = (uint8_t *)fep->hw_baseaddr_v +
+   offset_des_active_txq[queue_idx];
+   bd_base = (struct bufdesc *)(((uintptr_t)bd_base) + size);
+   txq->bd.last = (struct bufdesc *)(((uintptr_t)bd_base) - dsize);
+   bdp = txq->bd.base;
+   bdp = txq->bd.cur;
+
+   for (i = 0; i < txq->bd.ring_size; i++) {
+   /* Initialize the BD for every fragment in the page. */
+   rte_write16(rte_cpu_to_le_16(0), &bdp->bd_sc);
+   if (txq->tx_mbuf[i] != NULL) {
+   rte_pktmbuf_free(txq->tx_mbuf[i]);
+   txq->tx_mbuf[i] = NULL;
+   }
+   rte_write32(0, &bdp->bd_bufaddr);
+   bdp = enet_get_nextdesc(bdp, &txq->bd);
+   }
+
+   /* Set the last buffer to wrap */
+   bdp = enet_get_prevdesc(bdp, &txq->bd);
+   rte_write16((rte_cpu_to_le_16(TX_BD_WRAP) |
+   rte_read16(&bdp->bd_sc)), &bdp->bd_sc);
+   txq->dirty_tx = bdp;
+   dev->data->tx_queues[queue_idx] = fep->tx_queues[queue_idx];
+   return 0;
+}
+
+static int
+enetfec_rx_queue_setup(struct rte_eth_dev *dev,
+   uint16_t queue_idx,
+   uint16_t nb_rx_desc,
+   unsigned int socket_id __rte_unused,
+   const struct rte_eth_rxconf *rx_con

[PATCH v11 4/5] net/enetfec: add Rx/Tx support

2021-11-14 Thread Apeksha Gupta 
This patch adds burst enqueue and dequeue operations to the enetfec
PMD. Basic features added like promiscuous enable, basic stats.

Signed-off-by: Sachin Saxena 
Signed-off-by: Apeksha Gupta 
Acked-by: Hemant Agrawal 
---
 doc/guides/nics/enetfec.rst  |   2 +
 doc/guides/nics/features/enetfec.ini |   2 +
 drivers/net/enetfec/enet_ethdev.c| 182 ++
 drivers/net/enetfec/enet_ethdev.h|  25 +++
 drivers/net/enetfec/enet_rxtx.c  | 220 +++
 drivers/net/enetfec/meson.build  |   4 +-
 6 files changed, 434 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/enetfec/enet_rxtx.c

diff --git a/doc/guides/nics/enetfec.rst b/doc/guides/nics/enetfec.rst
index 6a86295e34..209073e77c 100644
--- a/doc/guides/nics/enetfec.rst
+++ b/doc/guides/nics/enetfec.rst
@@ -84,6 +84,8 @@ driver.
 ENETFEC Features
 ~
 
+- Basic stats
+- Promiscuous
 - Linux
 - ARMv8
 
diff --git a/doc/guides/nics/features/enetfec.ini 
b/doc/guides/nics/features/enetfec.ini
index bdfbdbd9d4..3d8aa5b627 100644
--- a/doc/guides/nics/features/enetfec.ini
+++ b/doc/guides/nics/features/enetfec.ini
@@ -4,6 +4,8 @@
 ; Refer to default.ini for the full list of available PMD features.
 ;
 [Features]
+Promiscuous mode = Y
+Basic stats = Y
 Linux   = Y
 ARMv8   = Y
 Usage doc   = Y
diff --git a/drivers/net/enetfec/enet_ethdev.c 
b/drivers/net/enetfec/enet_ethdev.c
index 0b8b73615d..9ac7501043 100644
--- a/drivers/net/enetfec/enet_ethdev.c
+++ b/drivers/net/enetfec/enet_ethdev.c
@@ -39,6 +39,8 @@
 #define ENETFEC_RAFL_V 0x8
 #define ENETFEC_OPD_V  0xFFF0
 
+/* Extended buffer descriptor */
+#define ENETFEC_EXTENDED_BD0
 #define NUM_OF_BD_QUEUES   6
 
 /* Supported Rx offloads */
@@ -152,6 +154,38 @@ enetfec_restart(struct rte_eth_dev *dev)
rte_delay_us(10);
 }
 
+static void
+enet_free_buffers(struct rte_eth_dev *dev)
+{
+   struct enetfec_private *fep = dev->data->dev_private;
+   unsigned int i, q;
+   struct rte_mbuf *mbuf;
+   struct bufdesc  *bdp;
+   struct enetfec_priv_rx_q *rxq;
+   struct enetfec_priv_tx_q *txq;
+
+   for (q = 0; q < dev->data->nb_rx_queues; q++) {
+   rxq = fep->rx_queues[q];
+   bdp = rxq->bd.base;
+   for (i = 0; i < rxq->bd.ring_size; i++) {
+   mbuf = rxq->rx_mbuf[i];
+   rxq->rx_mbuf[i] = NULL;
+   rte_pktmbuf_free(mbuf);
+   bdp = enet_get_nextdesc(bdp, &rxq->bd);
+   }
+   }
+
+   for (q = 0; q < dev->data->nb_tx_queues; q++) {
+   txq = fep->tx_queues[q];
+   bdp = txq->bd.base;
+   for (i = 0; i < txq->bd.ring_size; i++) {
+   mbuf = txq->tx_mbuf[i];
+   txq->tx_mbuf[i] = NULL;
+   rte_pktmbuf_free(mbuf);
+   }
+   }
+}
+
 static int
 enetfec_eth_configure(struct rte_eth_dev *dev)
 {
@@ -165,6 +199,8 @@ static int
 enetfec_eth_start(struct rte_eth_dev *dev)
 {
enetfec_restart(dev);
+   dev->rx_pkt_burst = &enetfec_recv_pkts;
+   dev->tx_pkt_burst = &enetfec_xmit_pkts;
 
return 0;
 }
@@ -191,6 +227,101 @@ enetfec_eth_stop(struct rte_eth_dev *dev)
return 0;
 }
 
+static int
+enetfec_eth_close(struct rte_eth_dev *dev)
+{
+   enet_free_buffers(dev);
+   return 0;
+}
+
+static int
+enetfec_eth_link_update(struct rte_eth_dev *dev,
+   int wait_to_complete __rte_unused)
+{
+   struct rte_eth_link link;
+   unsigned int lstatus = 1;
+
+   memset(&link, 0, sizeof(struct rte_eth_link));
+
+   link.link_status = lstatus;
+   link.link_speed = RTE_ETH_SPEED_NUM_1G;
+
+   ENETFEC_PMD_INFO("Port (%d) link is %s\n", dev->data->port_id,
+"Up");
+
+   return rte_eth_linkstatus_set(dev, &link);
+}
+
+static int
+enetfec_promiscuous_enable(struct rte_eth_dev *dev)
+{
+   struct enetfec_private *fep = dev->data->dev_private;
+   uint32_t tmp;
+
+   tmp = rte_read32((uint8_t *)fep->hw_baseaddr_v + ENETFEC_RCR);
+   tmp |= 0x8;
+   tmp &= ~0x2;
+   rte_write32(rte_cpu_to_le_32(tmp),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_RCR);
+
+   return 0;
+}
+
+static int
+enetfec_multicast_enable(struct rte_eth_dev *dev)
+{
+   struct enetfec_private *fep = dev->data->dev_private;
+
+   rte_write32(rte_cpu_to_le_32(0x),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_GAUR);
+   rte_write32(rte_cpu_to_le_32(0x),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_GALR);
+   dev->data->all_multicast = 1;
+
+   rte_write32(rte_cpu_to_le_32(0x0442),
+   (uint8_t *)fep->hw_baseaddr_v + ENETFEC_GAUR);
+   rte_write32(rte_cpu_to_le_32(0x10800049),
+

[PATCH v11 5/5] net/enetfec: add features

2021-11-14 Thread Apeksha Gupta 
This patch adds checksum and VLAN offloads in enetfec network
poll mode driver.

Signed-off-by: Sachin Saxena 
Signed-off-by: Apeksha Gupta 
Acked-by: Hemant Agrawal 
---
 doc/guides/nics/enetfec.rst  |  2 +
 doc/guides/nics/features/enetfec.ini |  3 ++
 drivers/net/enetfec/enet_ethdev.c| 12 +-
 drivers/net/enetfec/enet_ethdev.h|  2 +
 drivers/net/enetfec/enet_regs.h  | 10 +
 drivers/net/enetfec/enet_rxtx.c  | 55 +++-
 6 files changed, 82 insertions(+), 2 deletions(-)

diff --git a/doc/guides/nics/enetfec.rst b/doc/guides/nics/enetfec.rst
index 209073e77c..4014cffde9 100644
--- a/doc/guides/nics/enetfec.rst
+++ b/doc/guides/nics/enetfec.rst
@@ -86,6 +86,8 @@ ENETFEC Features
 
 - Basic stats
 - Promiscuous
+- VLAN offload
+- L3/L4 checksum offload
 - Linux
 - ARMv8
 
diff --git a/doc/guides/nics/features/enetfec.ini 
b/doc/guides/nics/features/enetfec.ini
index 3d8aa5b627..2a34351b43 100644
--- a/doc/guides/nics/features/enetfec.ini
+++ b/doc/guides/nics/features/enetfec.ini
@@ -5,6 +5,9 @@
 ;
 [Features]
 Promiscuous mode = Y
+VLAN offload= Y
+L3 checksum offload  = Y
+L4 checksum offload  = Y
 Basic stats = Y
 Linux   = Y
 ARMv8   = Y
diff --git a/drivers/net/enetfec/enet_ethdev.c 
b/drivers/net/enetfec/enet_ethdev.c
index 9ac7501043..f23bdcc4f1 100644
--- a/drivers/net/enetfec/enet_ethdev.c
+++ b/drivers/net/enetfec/enet_ethdev.c
@@ -79,7 +79,11 @@ enetfec_restart(struct rte_eth_dev *dev)
val = rte_read32((uint8_t *)fep->hw_baseaddr_v + ENETFEC_RACC);
/* align IP header */
val |= ENETFEC_RACC_SHIFT16;
-   val &= ~ENETFEC_RACC_OPTIONS;
+   if (fep->flag_csum & RX_FLAG_CSUM_EN)
+   /* set RX checksum */
+   val |= ENETFEC_RACC_OPTIONS;
+   else
+   val &= ~ENETFEC_RACC_OPTIONS;
rte_write32(rte_cpu_to_le_32(val),
(uint8_t *)fep->hw_baseaddr_v + ENETFEC_RACC);
rte_write32(rte_cpu_to_le_32(PKT_MAX_BUF_SIZE),
@@ -189,6 +193,11 @@ enet_free_buffers(struct rte_eth_dev *dev)
 static int
 enetfec_eth_configure(struct rte_eth_dev *dev)
 {
+   struct enetfec_private *fep = dev->data->dev_private;
+
+   if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM)
+   fep->flag_csum |= RX_FLAG_CSUM_EN;
+
if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
ENETFEC_PMD_ERR("PMD does not support KEEP_CRC offload");
 
@@ -567,6 +576,7 @@ enetfec_eth_init(struct rte_eth_dev *dev)
fep->full_duplex = FULL_DUPLEX;
dev->dev_ops = &enetfec_ops;
rte_eth_dev_probing_finish(dev);
+
return 0;
 }
 
diff --git a/drivers/net/enetfec/enet_ethdev.h 
b/drivers/net/enetfec/enet_ethdev.h
index 06a6c10600..798b6eee05 100644
--- a/drivers/net/enetfec/enet_ethdev.h
+++ b/drivers/net/enetfec/enet_ethdev.h
@@ -10,6 +10,7 @@
 #define BD_LEN 49152
 #define ENETFEC_TX_FR_SIZE 2048
 #define ETH_HLEN   RTE_ETHER_HDR_LEN
+#define VLAN_HLEN  4
 
 /* full duplex */
 #define FULL_DUPLEX0x00
@@ -93,6 +94,7 @@ struct enetfec_private {
struct rte_eth_statsstats;
int full_duplex;
int flag_pause;
+   int flag_csum;
uint32_tquirks;
uint32_tcbus_size;
uint32_tenetfec_e_cntl;
diff --git a/drivers/net/enetfec/enet_regs.h b/drivers/net/enetfec/enet_regs.h
index 5415ed77ea..a300c6f8bc 100644
--- a/drivers/net/enetfec/enet_regs.h
+++ b/drivers/net/enetfec/enet_regs.h
@@ -27,6 +27,12 @@
 #define RX_BD_EMPTY((ushort)0x8000) /* BD is empty */
 #define RX_BD_STATS((ushort)0x013f) /* All buffer descriptor status bits */
 
+/* Ethernet receive use control and status of enhanced buffer descriptor */
+#define BD_ENETFEC_RX_VLAN 0x0004
+
+#define RX_FLAG_CSUM_EN(RX_BD_ICE | RX_BD_PCR)
+#define RX_FLAG_CSUM_ERR   (RX_BD_ICE | RX_BD_PCR)
+
 /* Ethernet transmit use control and status of buffer descriptor */
 #define TX_BD_TC   ((ushort)0x0400) /* Transmit CRC */
 #define TX_BD_LAST ((ushort)0x0800) /* Last in frame */
@@ -56,6 +62,10 @@
 #define QUIRK_HAS_ENETFEC_MAC  (1 << 0)
 /* GBIT supported in controller */
 #define QUIRK_GBIT (1 << 3)
+/* Controller support hardware checksum */
+#define QUIRK_CSUM (1 << 5)
+/* Controller support hardware vlan */
+#define QUIRK_VLAN (1 << 6)
 /* RACC register supported by controller */
 #define QUIRK_RACC (1 << 12)
 /* i.MX8 ENETFEC IP version added the feature to generate the delayed TXC or
diff --git a/drivers/net/enetfec/enet_rxtx.c b/drivers/net/enetfec/enet_rxtx.c
index e61a217dcb..8066b1ef07 100644
--- a/drivers/net/enetfec/ene

RE: [PATCH v3] vhost: fix physical address mapping

2021-11-14 Thread Xia, Chenbo 
Hi Xuan,

> -Original Message-
> From: Ding, Xuan 
> Sent: Wednesday, November 10, 2021 2:07 PM
> To: maxime.coque...@redhat.com; Xia, Chenbo 
> Cc: dev@dpdk.org; Hu, Jiayu ; Wang, YuanX
> ; He, Xingguang ; Ding, Xuan
> 
> Subject: [PATCH v3] vhost: fix physical address mapping
> 
> When choosing IOVA as PA mode, IOVA is likely to be discontinuous,
> which requires page by page mapping for DMA devices. To be consistent,
> this patch implements page by page mapping instead of mapping at the
> region granularity for both IOVA as VA and PA mode.
> 
> Fixes: 7c61fa08b716 ("vhost: enable IOMMU for async vhost")
> 
> Signed-off-by: Xuan Ding 
> ---
> 
> v3:
> * Fix commit title.
> 
> v2:
> * Fix a format issue.
> ---
>  lib/vhost/vhost.h  |   1 +
>  lib/vhost/vhost_user.c | 105 -
>  2 files changed, 53 insertions(+), 53 deletions(-)
> 
> diff --git a/lib/vhost/vhost.h b/lib/vhost/vhost.h
> index 7085e0885c..d246538ca5 100644
> --- a/lib/vhost/vhost.h
> +++ b/lib/vhost/vhost.h
> @@ -355,6 +355,7 @@ struct vring_packed_desc_event {
>  struct guest_page {
>   uint64_t guest_phys_addr;
>   uint64_t host_phys_addr;
> + uint64_t host_user_addr;
>   uint64_t size;
>  };
> 
> diff --git a/lib/vhost/vhost_user.c b/lib/vhost/vhost_user.c
> index a781346c4d..37cdedda3c 100644
> --- a/lib/vhost/vhost_user.c
> +++ b/lib/vhost/vhost_user.c
> @@ -144,52 +144,55 @@ get_blk_size(int fd)
>  }
> 
>  static int
> -async_dma_map(struct rte_vhost_mem_region *region, bool do_map)
> +async_dma_map(struct virtio_net *dev, bool do_map)
>  {
> - uint64_t host_iova;
>   int ret = 0;
> -
> - host_iova = rte_mem_virt2iova((void 
> *)(uintptr_t)region->host_user_addr);
> + uint32_t i;
> + struct guest_page *page;
>   if (do_map) {
> - /* Add mapped region into the default container of DPDK. */
> - ret = rte_vfio_container_dma_map(RTE_VFIO_DEFAULT_CONTAINER_FD,
> -  region->host_user_addr,
> -  host_iova,
> -  region->size);
> - if (ret) {
> - /*
> -  * DMA device may bind with kernel driver, in this case,
> -  * we don't need to program IOMMU manually. However, if 
> no
> -  * device is bound with vfio/uio in DPDK, and vfio 
> kernel
> -  * module is loaded, the API will still be called and 
> return
> -  * with ENODEV/ENOSUP.
> -  *
> -  * DPDK vfio only returns ENODEV/ENOSUP in very similar
> -  * situations(vfio either unsupported, or supported
> -  * but no devices found). Either way, no mappings could 
> be
> -  * performed. We treat it as normal case in async path.
> -  */
> - if (rte_errno == ENODEV || rte_errno == ENOTSUP)
> + for (i = 0; i < dev->nr_guest_pages; i++) {
> + page = &dev->guest_pages[i];
> + ret =
> rte_vfio_container_dma_map(RTE_VFIO_DEFAULT_CONTAINER_FD,
> +  page->host_user_addr,
> +  page->host_phys_addr,
> +  page->size);
> + if (ret) {
> + /*
> +  * DMA device may bind with kernel driver, in 
> this
> case,
> +  * we don't need to program IOMMU manually. 
> However,
> if no
> +  * device is bound with vfio/uio in DPDK, and 
> vfio
> kernel
> +  * module is loaded, the API will still be 
> called and
> return
> +  * with ENODEV/ENOSUP.
> +  *
> +  * DPDK vfio only returns ENODEV/ENOSUP in very
> similar
> +  * situations(vfio either unsupported, or 
> supported
> +  * but no devices found). Either way, no 
> mappings
> could be
> +  * performed. We treat it as normal case in 
> async path.
> +  */
> + if (rte_errno == ENODEV || rte_errno == ENOTSUP)
> + return 0;

I don't think this logic is good enough to only include the case of kernel 
driver +
unneeded mapping. Could also be vfio driver + incorrect mapping. It's not good 
to
assume ENODEV and ENOTSUP only comes from DPDK, it could be from kernel.

> +
> + VHOST_LOG_CONFIG(ERR, "DMA engine map 
> failed\n");
> + /* DMA mapping errors won't stop
> VHST_USER_SET_MEM_TABLE. */
>

RE: [PATCH 1/5] net/mlx5: fix VXLAN-GPE next protocol translation

2021-11-14 Thread Slava Ovsiienko 
> -Original Message-
> From: Gregory Etelson 
> Sent: Sunday, November 14, 2021 17:36
> To: dev@dpdk.org; Gregory Etelson 
> Cc: Matan Azrad ; Raslan Darawsheh
> ; sta...@dpdk.org; Slava Ovsiienko
> ; Raslan Darawsheh 
> Subject: [PATCH 1/5] net/mlx5: fix VXLAN-GPE next protocol translation
> 
> VXLAN-GPE extends VXLAN protocol and provides the next protocol field
> specifying the first inner header type.
> 
> The application can assign some explicit value to VXLAN-GPE::next_protocol
> field or set it to the default one. In the latter case, the rdma-core library
> cannot recognize the matcher built by PMD correctly, and it results in
> hardware configuration missing inner headers match.
> 
> The patch forces VXLAN-GPE::next_protocol assignment if the application did
> not explicitly assign it to the non-default value
> 
> Cc: sta...@dpdk.org
> 
> Fixes: 90456726eb80 ("net/mlx5: fix VXLAN-GPE item translation")
> Signed-off-by: Gregory Etelson 
Acked-by: Viacheslav Ovsiienko

RE: [PATCH 2/5] net/mlx5: add Ethernet header to GENEVE RSS expansion

2021-11-14 Thread Slava Ovsiienko 
> -Original Message-
> From: Gregory Etelson 
> Sent: Sunday, November 14, 2021 17:36
> To: dev@dpdk.org; Gregory Etelson 
> Cc: Matan Azrad ; Raslan Darawsheh
> ; sta...@dpdk.org; Slava Ovsiienko
> 
> Subject: [PATCH 2/5] net/mlx5: add Ethernet header to GENEVE RSS
> expansion
> 
> RFC-8926 allows inner Ethernet header after GENEVE tunnel.
> 
> Current GENEVE RSS expansion created IPv4 and IPv6 paths only.
> 
> The patch adds Ethernet to RSS expansion scheme.
> 
> Cc: sta...@dpdk.org
> Signed-off-by: Gregory Etelson 
Acked-by: Viacheslav Ovsiienko

RE: [PATCH 3/5] net/mlx5: fix RSS expansion scheme for GRE header

2021-11-14 Thread Slava Ovsiienko 
> -Original Message-
> From: Gregory Etelson 
> Sent: Sunday, November 14, 2021 17:36
> To: dev@dpdk.org; Gregory Etelson 
> Cc: Matan Azrad ; Raslan Darawsheh
> ; sta...@dpdk.org; Slava Ovsiienko
> ; Yongseok Koh ; NBU-
> Contact-N?lio Laranjeiro 
> Subject: [PATCH 3/5] net/mlx5: fix RSS expansion scheme for GRE header
> 
> RFC-2784 allows any valid Ethernet type in GRE protocol type field.
> 
> Add Ethernet to GRE RSS expansion.
> 
> Cc: sta...@dpdk.org
> 
> Fixes: f4b901a46aec ("net/mlx5: add flow GRE item")
> Signed-off-by: Gregory Etelson 
Acked-by: Viacheslav Ovsiienko

RE: [PATCH 5/5] net/mlx5: fix GRE protocol type translation

2021-11-14 Thread Slava Ovsiienko 
> -Original Message-
> From: Gregory Etelson 
> Sent: Sunday, November 14, 2021 17:36
> To: dev@dpdk.org; Gregory Etelson 
> Cc: Matan Azrad ; Raslan Darawsheh
> ; sta...@dpdk.org; Slava Ovsiienko
> ; Yongseok Koh ; Ori Kam
> 
> Subject: [PATCH 5/5] net/mlx5: fix GRE protocol type translation
> 
> When application creates several flows to match on GRE tunnel without
> explicitly specifying GRE protocol type value in flow rules, PMD will 
> translate
> that to zero mask.
> RDMA-CORE cannot distinguish between different inner flow types and
> produces identical matchers for each zero mask.
> 
> The patch extracts inner header type from flow rule and forces it in GRE
> protocol type, if application did not specify any without explicitly 
> specifying
> GRE protocol type value in flow rules, protocol type value.
> 
> Cc: sta...@dpdk.org
> 
> Fixes: fc2c498ccb94 ("net/mlx5: add Direct Verbs translate items")
> 
> Signed-off-by: Gregory Etelson 
Acked-by: Viacheslav Ovsiienko

RE: [PATCH 4/5] net/mlx5: fix GENEVE protocol type translation

2021-11-14 Thread Slava Ovsiienko 
> -Original Message-
> From: Gregory Etelson 
> Sent: Sunday, November 14, 2021 17:36
> To: dev@dpdk.org; Gregory Etelson 
> Cc: Matan Azrad ; Raslan Darawsheh
> ; sta...@dpdk.org; Slava Ovsiienko
> ; Moti Haimovsky 
> Subject: [PATCH 4/5] net/mlx5: fix GENEVE protocol type translation
> 
> When application creates several flows to match on GENEVE tunnel without
> explicitly specifying GENEVE protocol type value in flow rules, PMD will
> translate that to zero mask.
> RDMA-CORE cannot distinguish between different inner flow types and
> produces identical matchers for each zero mask.
> 
> The patch extracts inner header type from flow rule and forces it in GENEVE
> protocol type, if application did not specify any without explicitly 
> specifying
> GENEVE protocol type value in flow rules, protocol type value.
> 
> Cc: sta...@dpdk.org
> 
> Fixes: e59a5dbcfd07 ("net/mlx5: add flow match on GENEVE item")
> Signed-off-by: Gregory Etelson 
Acked-by: Viacheslav Ovsiienko