Re: [dpdk-dev] [PATCH] net/ixgbe: enable jumbo frame for VF

[Ye Xiaolong]

On 12/02, Junyu Jiang wrote:
>Enable jumbo frame for VF by configuring DPDK PF.
>
>Signed-off-by: Junyu Jiang 
>---
> drivers/net/ixgbe/ixgbe_pf.c | 13 +
> 1 file changed, 13 insertions(+)
>
>diff --git a/drivers/net/ixgbe/ixgbe_pf.c b/drivers/net/ixgbe/ixgbe_pf.c
>index d0d85e138..66b856e11 100644
>--- a/drivers/net/ixgbe/ixgbe_pf.c
>+++ b/drivers/net/ixgbe/ixgbe_pf.c
>@@ -544,6 +544,7 @@ ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused 
>uint32_t vf, uint32_t *ms
>   struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
>   uint32_t new_mtu = msgbuf[1];
>   uint32_t max_frs;
>+  uint32_t hlreg0;
>   int max_frame = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
> 
>   /* X540 and X550 support jumbo frames in IOV mode */
>@@ -560,6 +561,18 @@ ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused 
>uint32_t vf, uint32_t *ms
>   max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
>  IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
>   if (max_frs < new_mtu) {
>+  hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
>+  if (new_mtu > RTE_ETHER_MAX_LEN) {
>+  dev->data->dev_conf.rxmode.offloads |=
>+  DEV_RX_OFFLOAD_JUMBO_FRAME;
>+  hlreg0 |= IXGBE_HLREG0_JUMBOEN;
>+  } else {
>+  dev->data->dev_conf.rxmode.offloads &=
>+  ~DEV_RX_OFFLOAD_JUMBO_FRAME;
>+  hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
>+  }
>+  IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
>+
>   max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
>   IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
>   }
>-- 
>2.17.1
>


Applied to dpdk-next-net-intel with wei's ack, Thanks.

[dpdk-dev] [PATCH v4] vhost: add config change slave msg support

[Li Feng]

This msg is used to notify qemu that should get the config of backend.

For example, vhost-user-blk uses this msg to notify guest os the
capacity of backend has changed.

The need_reply flag is not mandatory because it will block the sender
thread and master process will send get_config message to fetch the
configuration, this need an extra thread to process the vhost message.

Signed-off-by: Li Feng 
---
v4:
* Fix type and code style.
* Add need_reply support.

v3:
* Move the declare to rte_vhost.h
* Add the symbol in rte_vhost_version.map

v2:
* Fix a little log typo.

 lib/librte_vhost/rte_vhost.h   | 15 +++
 lib/librte_vhost/rte_vhost_version.map |  1 +
 lib/librte_vhost/vhost_user.c  | 35 ++
 lib/librte_vhost/vhost_user.h  |  1 +
 4 files changed, 52 insertions(+)

diff --git a/lib/librte_vhost/rte_vhost.h b/lib/librte_vhost/rte_vhost.h
index 7b5dc87c2..c7b619ae0 100644
--- a/lib/librte_vhost/rte_vhost.h
+++ b/lib/librte_vhost/rte_vhost.h
@@ -10,6 +10,7 @@
  * Interface to vhost-user
  */
 
+#include 
 #include 
 #include 
 
@@ -977,6 +978,20 @@ __rte_experimental
 int
 rte_vhost_get_vdpa_device_id(int vid);
 
+/**
+ * Notify the guest that should get virtio configuration space from backend.
+ *
+ * @param vid
+ *  vhost device ID
+ * @param need_reply
+ *  wait for the master response the status of this operation
+ * @return
+ *  0 on success, < 0 on failure
+ */
+__rte_experimental
+int
+rte_vhost_slave_config_change(int vid, bool need_reply);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/lib/librte_vhost/rte_vhost_version.map 
b/lib/librte_vhost/rte_vhost_version.map
index c512377fe..051d08c12 100644
--- a/lib/librte_vhost/rte_vhost_version.map
+++ b/lib/librte_vhost/rte_vhost_version.map
@@ -65,4 +65,5 @@ EXPERIMENTAL {
rte_vhost_clr_inflight_desc_packed;
rte_vhost_get_vhost_ring_inflight;
rte_vhost_get_vring_base_from_inflight;
+   rte_vhost_slave_config_change;
 };
diff --git a/lib/librte_vhost/vhost_user.c b/lib/librte_vhost/vhost_user.c
index 0cfb8b792..aed1210b1 100644
--- a/lib/librte_vhost/vhost_user.c
+++ b/lib/librte_vhost/vhost_user.c
@@ -2840,6 +2840,41 @@ vhost_user_iotlb_miss(struct virtio_net *dev, uint64_t 
iova, uint8_t perm)
return 0;
 }
 
+static int
+vhost_user_slave_config_change(struct virtio_net *dev, bool need_reply)
+{
+   int ret;
+   uint32_t flags = VHOST_USER_VERSION;
+   if (need_reply)
+   flags |= VHOST_USER_NEED_REPLY;
+   struct VhostUserMsg msg = {
+   .request.slave = VHOST_USER_SLAVE_CONFIG_CHANGE_MSG,
+   .flags = flags,
+   .size = 0,
+   };
+
+   ret = send_vhost_slave_message(dev, &msg);
+   if (ret < 0) {
+   RTE_LOG(ERR, VHOST_CONFIG,
+   "Failed to send config change (%d)\n",
+   ret);
+   return ret;
+   }
+   if (need_reply)
+   return process_slave_message_reply(dev, &msg);
+   return 0;
+}
+
+int
+rte_vhost_slave_config_change(int vid, bool need_reply)
+{
+   struct virtio_net *dev;
+   dev = get_device(vid);
+   if (!dev)
+   return -ENODEV;
+   return vhost_user_slave_config_change(dev, need_reply);
+}
+
 static int vhost_user_slave_set_vring_host_notifier(struct virtio_net *dev,
int index, int fd,
uint64_t offset,
diff --git a/lib/librte_vhost/vhost_user.h b/lib/librte_vhost/vhost_user.h
index 6563f7315..86c364a93 100644
--- a/lib/librte_vhost/vhost_user.h
+++ b/lib/librte_vhost/vhost_user.h
@@ -62,6 +62,7 @@ typedef enum VhostUserRequest {
 typedef enum VhostUserSlaveRequest {
VHOST_USER_SLAVE_NONE = 0,
VHOST_USER_SLAVE_IOTLB_MSG = 1,
+   VHOST_USER_SLAVE_CONFIG_CHANGE_MSG = 2,
VHOST_USER_SLAVE_VRING_HOST_NOTIFIER_MSG = 3,
VHOST_USER_SLAVE_MAX
 } VhostUserSlaveRequest;
-- 
2.11.0


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Re: [dpdk-dev] [PATCH] net/mlx5: allow install more meter actions

[Tonghao Zhang]

ping

On Tue, Dec 17, 2019 at 3:29 PM  wrote:
>
> From: Tonghao Zhang 
>
> When creating the dr rule of meter, the matcher which
> struct is "struct mlx5dv_dr_matcher" should not be
> shared, if shared, mlx5dv_dr_rule_create will return
> NULL. We can't install more metering offload actions.
>
> The call tree (rdma-core-47mlnx1 OFED 4.7-3.2.9):
> * dr_rule_handle_ste_branch
> * dr_rule_create_rule_nic
> * dr_rule_create_rule_fdb
> * dr_rule_create_rule
> * mlx5dv_dr_rule_create
>
> In the dr_rule_handle_ste_branch, if ste is not used,
> mlx5dv_dr_rule_create will return rule, if the ste is
> used, and the ste is the last in the rule, mlx5dv_dr_rule_create
> will return NULL.
>
> dr_rule_handle_ste_branch:
> if dr_ste_not_used_ste
> dr_rule_handle_empty_entry
> else
> dr_rule_find_ste_in_miss_list
> dr_ste_is_last_in_rule: if so return NULL and set errno = EINVAL;
>
> Fixes: 9ea9b049a960 ("net/mlx5: split meter flow")
> Cc: Suanming Mou 
> Cc: sta...@dpdk.org
>
> Signed-off-by: Tonghao Zhang 
> ---
>  drivers/net/mlx5/mlx5_flow.c| 20 +---
>  drivers/net/mlx5/mlx5_flow.h|  2 ++
>  drivers/net/mlx5/mlx5_flow_dv.c |  5 +
>  3 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
> index 0087163..f8cdc25 100644
> --- a/drivers/net/mlx5/mlx5_flow.c
> +++ b/drivers/net/mlx5/mlx5_flow.c
> @@ -3421,7 +3421,9 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev 
> *dev, int32_t priority,
> const struct rte_flow_attr *attr,
> const struct rte_flow_item items[],
> const struct rte_flow_action actions[],
> -   bool external, struct rte_flow_error *error)
> +   bool external,
> +   bool shared,
> +   struct rte_flow_error *error)
>  {
> struct mlx5_flow *dev_flow;
>
> @@ -3434,6 +3436,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev 
> *dev, int32_t priority,
> LIST_INSERT_HEAD(&flow->dev_flows, dev_flow, next);
> if (sub_flow)
> *sub_flow = dev_flow;
> +   dev_flow->matcher_shared = shared;
> return flow_drv_translate(dev, dev_flow, attr, items, actions, error);
>  }
>
> @@ -3741,7 +3744,9 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev 
> *dev, int32_t priority,
>const struct rte_flow_attr *attr,
>const struct rte_flow_item items[],
>const struct rte_flow_action actions[],
> -  bool external, struct rte_flow_error *error)
> +  bool external,
> +  bool shared,
> +  struct rte_flow_error *error)
>  {
> struct mlx5_priv *priv = dev->data->dev_private;
> struct mlx5_dev_config *config = &priv->config;
> @@ -3759,7 +3764,8 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev 
> *dev, int32_t priority,
> config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
> !mlx5_flow_ext_mreg_supported(dev))
> return flow_create_split_inner(dev, flow, NULL, attr, items,
> -  actions, external, error);
> +  actions, external,
> +  shared, error);
> actions_n = flow_parse_qrss_action(actions, &qrss);
> if (qrss) {
> /* Exclude hairpin flows from splitting. */
> @@ -3842,7 +3848,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev 
> *dev, int32_t priority,
> /* Add the unmodified original or prefix subflow. */
> ret = flow_create_split_inner(dev, flow, &dev_flow, attr, items,
>   ext_actions ? ext_actions : actions,
> - external, error);
> + external, shared, error);
> if (ret < 0)
> goto exit;
> assert(dev_flow);
> @@ -3906,7 +3912,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev 
> *dev, int32_t priority,
> ret = flow_create_split_inner(dev, flow, &dev_flow,
>   &q_attr, mtr_sfx ? items :
>   q_items, q_actions,
> - external, error);
> + external, shared, error);
> if (ret < 0)
> goto exit;
> assert(dev_flow);
> @@ -3999,7 +4005,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev 
> *dev, int32_t priority,
> }
> /* Add the prefix subflow. */
> ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 
> items,
> -

[dpdk-dev] [PATCH v2] net/ixgbe: fix flow ctrl mode setting

[Guinan Sun]

When the port starts, the hw register is reset first,
and then the required parameters are set again.
If the parameters to be used are not set after resetting the register,
a read register error will occur. This patch is used to fix the problem.

Fixes: af75078fece3 ("first public release")
Cc: sta...@dpdk.org

Signed-off-by: Guinan Sun 
---
v2: changes
* Modify the initial value of requested_mode and current_mode
---
 drivers/net/ixgbe/ixgbe_ethdev.c | 24 ++--
 drivers/net/ixgbe/ixgbe_ethdev.h |  1 +
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 2c6fd0f13..573117e3a 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -1170,8 +1170,8 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void 
*init_params __rte_unused)
memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
ixgbe_dcb_init(hw, dcb_config);
/* Get Hardware Flow Control setting */
-   hw->fc.requested_mode = ixgbe_fc_full;
-   hw->fc.current_mode = ixgbe_fc_full;
+   hw->fc.requested_mode = ixgbe_fc_none;
+   hw->fc.current_mode = ixgbe_fc_none;
hw->fc.pause_time = IXGBE_FC_PAUSE;
for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
hw->fc.low_water[i] = IXGBE_FC_LO;
@@ -2539,6 +2539,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
 {
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+   struct ixgbe_adapter *adapter = dev->data->dev_private;
struct ixgbe_vf_info *vfinfo =
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
@@ -2555,6 +2556,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
struct ixgbe_macsec_setting *macsec_setting =
IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
+   uint32_t mflcn;
 
PMD_INIT_FUNC_TRACE();
 
@@ -2665,6 +2667,20 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
}
 
ixgbe_restore_statistics_mapping(dev);
+   err = ixgbe_fc_enable(hw);
+   if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
+
+   mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
+
+   /* set or clear MFLCN.PMCF bit depending on configuration */
+   if (adapter->mac_ctrl_frame_fwd != 0)
+   mflcn |= IXGBE_MFLCN_PMCF;
+   else
+   mflcn &= ~IXGBE_MFLCN_PMCF;
+
+   IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
+   IXGBE_WRITE_FLUSH(hw);
+   }
 
err = ixgbe_dev_rxtx_start(dev);
if (err < 0) {
@@ -2893,6 +2909,8 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
 
adapter->rss_reta_updated = 0;
 
+   adapter->mac_ctrl_frame_fwd = 0;
+
hw->adapter_stopped = true;
 }
 
@@ -4646,6 +4664,7 @@ static int
 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 {
struct ixgbe_hw *hw;
+   struct ixgbe_adapter *adapter = dev->data->dev_private;
int err;
uint32_t rx_buf_size;
uint32_t max_high_water;
@@ -4682,6 +4701,7 @@ ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct 
rte_eth_fc_conf *fc_conf)
hw->fc.low_water[0]   = fc_conf->low_water;
hw->fc.send_xon   = fc_conf->send_xon;
hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
+   adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 
err = ixgbe_fc_enable(hw);
 
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h
index 76a1b9d18..5af584f9e 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.h
+++ b/drivers/net/ixgbe/ixgbe_ethdev.h
@@ -510,6 +510,7 @@ struct ixgbe_adapter {
 * mailbox status) link status.
 */
uint8_t pflink_fullchk;
+   uint8_t mac_ctrl_frame_fwd;
 };
 
 struct ixgbe_vf_representor {
-- 
2.17.1

Re: [dpdk-dev] [PATCH 1/3] eal: introduce structure marker typedefs

[Jerin Jacob]

On Wed, Dec 11, 2019 at 4:16 AM Thomas Monjalon  wrote:
>
> 08/12/2019 12:34, jer...@marvell.com:
> > From: Jerin Jacob 
> >
> > Introduce EAL typedef for structure 1B, 2B, 4B, 8B alignment marking and
> > a generic marker for a point in a structure.
> >
> > Signed-off-by: Jerin Jacob 
> > ---
> >  lib/librte_eal/common/include/rte_common.h | 12 
>
> Good idea, thanks.
>
> > +/** Generic marker for a point in a structure. */
>
> I think "a point" may be replaced with "any place" or something else?

Will fix it v2.

>
> > +__extension__ typedef void*RTE_MARKER[0];
>
> Why do we need an extension?
> If it is part of C11, we should use RTE_STD_C11 instead.

Will fix it v2.

> If it is another reason, we could create another meaningful EAL macro.
>
>
>

[dpdk-dev] [PATCH] mempool/octeontx: fix error handling in initialization

[kkanas]

From: Krzysztof Kanas 

When octeontx_get_fpavf fails fpa pointer is used to get
pool_stack_base, which is then freed.

Coverity issue: 351263

Fixes: 9bc692f83baa ("mempool/octeontx: add application domain validation")
Cc: pbhagavat...@marvell.com

Signed-off-by: Krzysztof Kanas 
---
 drivers/mempool/octeontx/octeontx_fpavf.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mempool/octeontx/octeontx_fpavf.c 
b/drivers/mempool/octeontx/octeontx_fpavf.c
index c97267db3cc3..63f8fb3b500a 100644
--- a/drivers/mempool/octeontx/octeontx_fpavf.c
+++ b/drivers/mempool/octeontx/octeontx_fpavf.c
@@ -305,10 +305,8 @@ octeontx_fpapf_pool_destroy(unsigned int gpool_index)
int ret = -1;
 
fpa = octeontx_get_fpavf(gpool_index);
-   if (fpa == NULL) {
-   ret = -EINVAL;
-   goto err;
-   }
+   if (fpa == NULL)
+   return -EINVAL;
 
hdr.coproc = FPA_COPROC;
hdr.msg = FPA_CONFIGSET;
-- 
2.21.0

[dpdk-dev] [PATCH v2 2/3] drivers: use structure marker typedef in eal

[jerinj]

From: Jerin Jacob 

Use new marker typedef available in EAL.

Signed-off-by: Jerin Jacob 
---
 drivers/net/ark/ark_ethdev_rx.c | 2 +-
 drivers/net/ark/ark_ethdev_tx.c | 2 +-
 drivers/net/octeontx2/otx2_ethdev.h | 6 +++---
 drivers/net/thunderx/nicvf_struct.h | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ark/ark_ethdev_rx.c b/drivers/net/ark/ark_ethdev_rx.c
index 6156730bb..4d518d558 100644
--- a/drivers/net/ark/ark_ethdev_rx.c
+++ b/drivers/net/ark/ark_ethdev_rx.c
@@ -57,7 +57,7 @@ struct ark_rx_queue {
 
/* separate cache line */
/* second cache line - fields only used in slow path */
-   MARKER cacheline1 __rte_cache_min_aligned;
+   RTE_MARKER cacheline1 __rte_cache_min_aligned;
 
volatile uint32_t prod_index;   /* step 2 filled by FPGA */
 } __rte_cache_aligned;
diff --git a/drivers/net/ark/ark_ethdev_tx.c b/drivers/net/ark/ark_ethdev_tx.c
index 08bcf431a..289668774 100644
--- a/drivers/net/ark/ark_ethdev_tx.c
+++ b/drivers/net/ark/ark_ethdev_tx.c
@@ -42,7 +42,7 @@ struct ark_tx_queue {
uint32_t pad[1];
 
/* second cache line - fields only used in slow path */
-   MARKER cacheline1 __rte_cache_min_aligned;
+   RTE_MARKER cacheline1 __rte_cache_min_aligned;
uint32_t cons_index;/* hw is done, can be freed */
 } __rte_cache_aligned;
 
diff --git a/drivers/net/octeontx2/otx2_ethdev.h 
b/drivers/net/octeontx2/otx2_ethdev.h
index 987e7607c..a6e8483a0 100644
--- a/drivers/net/octeontx2/otx2_ethdev.h
+++ b/drivers/net/octeontx2/otx2_ethdev.h
@@ -254,7 +254,7 @@ struct otx2_vlan_info {
 
 struct otx2_eth_dev {
OTX2_DEV; /* Base class */
-   MARKER otx2_eth_dev_data_start;
+   RTE_MARKER otx2_eth_dev_data_start;
uint16_t sqb_size;
uint16_t rx_chan_base;
uint16_t tx_chan_base;
@@ -335,7 +335,7 @@ struct otx2_eth_txq {
rte_iova_t fc_iova;
uint16_t sqes_per_sqb_log2;
int16_t nb_sqb_bufs_adj;
-   MARKER slow_path_start;
+   RTE_MARKER slow_path_start;
uint16_t nb_sqb_bufs;
uint16_t sq;
uint64_t offloads;
@@ -357,7 +357,7 @@ struct otx2_eth_rxq {
uint32_t available;
uint16_t rq;
struct otx2_timesync_info *tstamp;
-   MARKER slow_path_start;
+   RTE_MARKER slow_path_start;
uint64_t aura;
uint64_t offloads;
uint32_t qlen;
diff --git a/drivers/net/thunderx/nicvf_struct.h 
b/drivers/net/thunderx/nicvf_struct.h
index 5d1379803..cf1c281a0 100644
--- a/drivers/net/thunderx/nicvf_struct.h
+++ b/drivers/net/thunderx/nicvf_struct.h
@@ -55,7 +55,7 @@ union mbuf_initializer {
 };
 
 struct nicvf_rxq {
-   MARKER rxq_fastpath_data_start;
+   RTE_MARKER rxq_fastpath_data_start;
uint8_t  rbptr_offset;
uint16_t rx_free_thresh;
uint32_t head;
@@ -69,7 +69,7 @@ struct nicvf_rxq {
struct rte_mempool *pool;
union cq_entry_t *desc;
union mbuf_initializer mbuf_initializer;
-   MARKER rxq_fastpath_data_end;
+   RTE_MARKER rxq_fastpath_data_end;
uint8_t rx_drop_en;
uint16_t precharge_cnt;
uint16_t port_id;
-- 
2.24.1

[dpdk-dev] [PATCH v2 1/3] eal: introduce structure marker typedefs

[jerinj]

From: Jerin Jacob 

Introduce EAL typedef for structure 1B, 2B, 4B, 8B alignment marking and
a generic marker for a point in a structure.

Signed-off-by: Jerin Jacob 
---

v2:
- Changed __extension__  to  RTE_STD_C11 (Thomas)
- Change "a point" to "any place" of RTE_MARKER comment(Thomas)

 lib/librte_eal/common/include/rte_common.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/lib/librte_eal/common/include/rte_common.h 
b/lib/librte_eal/common/include/rte_common.h
index 459d082d1..00c8b8434 100644
--- a/lib/librte_eal/common/include/rte_common.h
+++ b/lib/librte_eal/common/include/rte_common.h
@@ -335,6 +335,18 @@ typedef uint64_t phys_addr_t;
 typedef uint64_t rte_iova_t;
 #define RTE_BAD_IOVA ((rte_iova_t)-1)
 
+/*** Structure alignment markers /
+
+/** Generic marker for any place in a structure. */
+RTE_STD_C11 typedef void*RTE_MARKER[0];
+/** Marker for 1B alignment in a structure. */
+RTE_STD_C11 typedef uint8_t  RTE_MARKER8[0];
+/** Marker for 2B alignment in a structure. */
+RTE_STD_C11 typedef uint16_t RTE_MARKER16[0];
+/** Marker for 4B alignment in a structure. */
+RTE_STD_C11 typedef uint16_t RTE_MARKER32[0];
+/** Marker for 8B alignment in a structure. */
+RTE_STD_C11 typedef uint64_t RTE_MARKER64[0];
 
 /**
  * Combines 32b inputs most significant set bits into the least
-- 
2.24.1

[dpdk-dev] [PATCH v2 3/3] mbuf: use structure marker typedef in eal

[jerinj]

From: Jerin Jacob 

Use new marker typedef available in EAL and remove private marker
typedef.

Signed-off-by: Jerin Jacob 
---
 lib/librte_mbuf/rte_mbuf_core.h | 21 -
 1 file changed, 4 insertions(+), 17 deletions(-)

diff --git a/lib/librte_mbuf/rte_mbuf_core.h b/lib/librte_mbuf/rte_mbuf_core.h
index 9a8557d1c..b9a59c879 100644
--- a/lib/librte_mbuf/rte_mbuf_core.h
+++ b/lib/librte_mbuf/rte_mbuf_core.h
@@ -406,19 +406,6 @@ extern "C" {
 #defineRTE_MBUF_DEFAULT_BUF_SIZE   \
(RTE_MBUF_DEFAULT_DATAROOM + RTE_PKTMBUF_HEADROOM)
 
-/*
- * define a set of marker types that can be used to refer to set points in the
- * mbuf.
- */
-__extension__
-typedef void*MARKER[0];   /**< generic marker for a point in a structure */
-__extension__
-typedef uint8_t  MARKER8[0];  /**< generic marker with 1B alignment */
-
- /** marker that allows us to overwrite 8 bytes with a single assignment */
-__extension__
-typedef uint64_t MARKER64[0];
-
 struct rte_mbuf_sched {
uint32_t queue_id;   /**< Queue ID. */
uint8_t traffic_class;
@@ -478,7 +465,7 @@ enum {
  * The generic rte_mbuf, containing a packet mbuf.
  */
 struct rte_mbuf {
-   MARKER cacheline0;
+   RTE_MARKER cacheline0;
 
void *buf_addr;   /**< Virtual address of segment buffer. */
/**
@@ -494,7 +481,7 @@ struct rte_mbuf {
} __rte_aligned(sizeof(rte_iova_t));
 
/* next 8 bytes are initialised on RX descriptor rearm */
-   MARKER64 rearm_data;
+   RTE_MARKER64 rearm_data;
uint16_t data_off;
 
/**
@@ -522,7 +509,7 @@ struct rte_mbuf {
uint64_t ol_flags;/**< Offload features. */
 
/* remaining bytes are set on RX when pulling packet from descriptor */
-   MARKER rx_descriptor_fields1;
+   RTE_MARKER rx_descriptor_fields1;
 
/*
 * The packet type, which is the combination of outer/inner L2, L3, L4
@@ -610,7 +597,7 @@ struct rte_mbuf {
uint64_t timestamp;
 
/* second cache line - fields only used in slow path or on TX */
-   MARKER cacheline1 __rte_cache_min_aligned;
+   RTE_MARKER cacheline1 __rte_cache_min_aligned;
 
RTE_STD_C11
union {
-- 
2.24.1

Re: [dpdk-dev] [PATCH] net/mlx5: fix item flag on GENEVE item validation

[Raslan Darawsheh]

Hi,

> -Original Message-
> From: dev  On Behalf Of Dekel Peled
> Sent: Wednesday, December 18, 2019 5:10 PM
> To: Matan Azrad ; Slava Ovsiienko
> ; Shahaf Shuler 
> Cc: Ori Kam ; dev@dpdk.org; sta...@dpdk.org
> Subject: [dpdk-dev] [PATCH] net/mlx5: fix item flag on GENEVE item
> validation
> 
> On validation of GENEVE item, the wrong flag is used.
> This patch sets the correct bit in item_flags bitmap.
> 
> Fixes: e59a5dbcfd07 ("net/mlx5: add flow match on GENEVE item")
> Cc: sta...@dpdk.org
> 
> Signed-off-by: Dekel Peled 
> ---
>  drivers/net/mlx5/mlx5_flow_dv.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> b/drivers/net/mlx5/mlx5_flow_dv.c index 1a1b6ec..6f35fe1 100644
> --- a/drivers/net/mlx5/mlx5_flow_dv.c
> +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> @@ -4489,7 +4489,7 @@ struct field_modify_info modify_tcp[] = {
>error);
>   if (ret < 0)
>   return ret;
> - last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
> + last_item = MLX5_FLOW_LAYER_GENEVE;
>   break;
>   case RTE_FLOW_ITEM_TYPE_MPLS:
>   ret = mlx5_flow_validate_item_mpls(dev, items,
> --
> 1.8.3.1

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

Re: [dpdk-dev] [PATCH] net/mlx5: add define of LRO segment chunk size

[Raslan Darawsheh]

Hi,

> -Original Message-
> From: dev  On Behalf Of Dekel Peled
> Sent: Wednesday, December 18, 2019 9:52 AM
> To: Matan Azrad ; Slava Ovsiienko
> ; Shahaf Shuler 
> Cc: Ori Kam ; dev@dpdk.org
> Subject: [dpdk-dev] [PATCH] net/mlx5: add define of LRO segment chunk
> size
> 
> Maximal size of coalesced LRO segment is set in TIR attributes as
> number of chunks of size 256 bytes each.
> Current implementation uses the hardcoded value 256 in several places.
> 
> This patch adds a definition for this value, and uses this definition
> in all relevant places.
> A debug message is added to clearly notify the actual configured size.
> 
> Signed-off-by: Dekel Peled 
> Acked-by: Matan Azrad 
> 
> ---
>  drivers/net/mlx5/mlx5.h |  5 -
>  drivers/net/mlx5/mlx5_rxq.c | 15 +++
>  2 files changed, 15 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
> index 0c3a90e..c3df825 100644
> --- a/drivers/net/mlx5/mlx5.h
> +++ b/drivers/net/mlx5/mlx5.h
> @@ -218,8 +218,11 @@ struct mlx5_hca_attr {
>  #define MLX5_LRO_SUPPORTED(dev) \
>   (((struct mlx5_priv *)((dev)->data->dev_private))-
> >config.lro.supported)
> 
> +/* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes.
> */
> +#define MLX5_LRO_SEG_CHUNK_SIZE  256u
> +
>  /* Maximal size of aggregated LRO packet. */
> -#define MLX5_MAX_LRO_SIZE (UINT8_MAX * 256u)
> +#define MLX5_MAX_LRO_SIZE (UINT8_MAX *
> MLX5_LRO_SEG_CHUNK_SIZE)
> 
>  /* LRO configurations structure. */
>  struct mlx5_lro_config {
> diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
> index 986ec01..bbc07db 100644
> --- a/drivers/net/mlx5/mlx5_rxq.c
> +++ b/drivers/net/mlx5/mlx5_rxq.c
> @@ -1717,11 +1717,14 @@ struct mlx5_rxq_obj *
>   *
>   * @param dev
>   *   Pointer to Ethernet device.
> + * @param idx
> + *   RX queue index.
>   * @param max_lro_size
>   *   The maximum size for LRO packet.
>   */
>  static void
> -mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint32_t
> max_lro_size)
> +mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
> +  uint32_t max_lro_size)
>  {
>   struct mlx5_priv *priv = dev->data->dev_private;
> 
> @@ -1730,13 +1733,17 @@ struct mlx5_rxq_obj *
>   MLX5_MAX_TCP_HDR_OFFSET)
>   max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
>   max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
> - assert(max_lro_size >= 256u);
> - max_lro_size /= 256u;
> + assert(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
> + max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
>   if (priv->max_lro_msg_size)
>   priv->max_lro_msg_size =
>   RTE_MIN((uint32_t)priv->max_lro_msg_size,
> max_lro_size);
>   else
>   priv->max_lro_msg_size = max_lro_size;
> + DRV_LOG(DEBUG,
> + "port %u Rx Queue %u max LRO message size adjusted to %u
> bytes",
> + dev->data->port_id, idx,
> + priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
>  }
> 
>  /**
> @@ -1909,7 +1916,7 @@ struct mlx5_rxq_ctrl *
>   rte_errno = EINVAL;
>   goto error;
>   }
> - mlx5_max_lro_msg_size_adjust(dev, max_lro_size);
> + mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
>   /* Toggle RX checksum offload if hardware supports it. */
>   tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
>   tmpl->rxq.hw_timestamp = !!(offloads &
> DEV_RX_OFFLOAD_TIMESTAMP);
> --
> 1.8.3.1

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

Re: [dpdk-dev] [PATCH] net/mlx5: remove redundant define of LRO masks

[Raslan Darawsheh]

Hi,

> -Original Message-
> From: dev  On Behalf Of Dekel Peled
> Sent: Wednesday, December 18, 2019 9:50 AM
> To: Matan Azrad ; Slava Ovsiienko
> ; Shahaf Shuler 
> Cc: Ori Kam ; dev@dpdk.org
> Subject: [dpdk-dev] [PATCH] net/mlx5: remove redundant define of LRO
> masks
> 
> Bit-masks MLX5_FLOW_LAYER_IPV4_LRO and
> MLX5_FLOW_LAYER_IPV6_LRO were
> added during work on LRO.
> They are not used anywhere in current code.
> 
> This patch removes these redundant definitions.
> 
> Signed-off-by: Dekel Peled 
> Acked-by: Matan Azrad 
> 
> ---
>  drivers/net/mlx5/mlx5_flow.h | 6 --
>  1 file changed, 6 deletions(-)
> 
> diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
> index 3fff5dd..08e223e 100644
> --- a/drivers/net/mlx5/mlx5_flow.h
> +++ b/drivers/net/mlx5/mlx5_flow.h
> @@ -131,12 +131,6 @@ enum mlx5_feature_name {
>   (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 |
> \
>MLX5_FLOW_LAYER_OUTER_L4)
> 
> -/* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
> -#define MLX5_FLOW_LAYER_IPV4_LRO \
> - (MLX5_FLOW_LAYER_OUTER_L3_IPV4 |
> MLX5_FLOW_LAYER_OUTER_L4_TCP)
> -#define MLX5_FLOW_LAYER_IPV6_LRO \
> - (MLX5_FLOW_LAYER_OUTER_L3_IPV6 |
> MLX5_FLOW_LAYER_OUTER_L4_TCP)
> -
>  /* Tunnel Masks. */
>  #define MLX5_FLOW_LAYER_TUNNEL \
>   (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
> --
> 1.8.3.1


Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

Re: [dpdk-dev] [PATCH 0/2] net/mlx5: update RSS action handling

[Raslan Darawsheh]

Hi,
> -Original Message-
> From: dev  On Behalf Of Dekel Peled
> Sent: Wednesday, December 18, 2019 12:06 PM
> To: Matan Azrad ; Slava Ovsiienko
> ; Shahaf Shuler 
> Cc: Ori Kam ; dev@dpdk.org
> Subject: [dpdk-dev] [PATCH 0/2] net/mlx5: update RSS action handling
> 
> This series includes 2 patches updating the RSS action handling.
> The first patch fixes an error in existing code.
> The second patch implements additional functionality.
> 
> Dekel Peled (2):
>   net/mlx5: fix setting of Rx hash fields
>   net/mlx5: support RSS on SRC or DST fields only
> 
>  doc/guides/nics/mlx5.rst   |  2 +
>  doc/guides/rel_notes/release_20_02.rst |  6 +++
>  drivers/net/mlx5/mlx5_defs.h   |  7 ++-
>  drivers/net/mlx5/mlx5_flow.c   | 12 +
>  drivers/net/mlx5/mlx5_flow.h   | 21 
>  drivers/net/mlx5/mlx5_flow_dv.c| 91
> ++
>  drivers/net/mlx5/mlx5_rxq.c| 29 ++-
>  7 files changed, 145 insertions(+), 23 deletions(-)
> 
> --
> 1.8.3.1

Series applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

[dpdk-dev] DPDK Release Status Meeting 19/12/2019

[Ferruh Yigit]

Minutes 19 December 2019


Agenda:
* Release Dates
* Subtrees
* OvS

Participants:
* Intel
* Marvell
* Mellanox
* Red Hat


The next two meetings have been cancelled because of coming holidays, see you
next year.
2019 was an amazing year for DPDK, thanks everyone who contributed, it wouldn't
be without you and hopefully 2020 will be even better.
Happy holidays, happy Christmas and a happy new year.


Release Dates
-

* v20.02 dates:
  * Integration/Merge/RC1:  Wednesday 15 January 2020
  * Release:Friday 14 February 2020

  * Reminder for 20.02 roadmaps from contributors,
Marvell, arm & Intel already sent, waiting from other contributors.

* v20.05 proposal:
  * Proposal/V1:Friday 6 March 2020
  * Integration/Merge/RC1:  Friday 10 April 2020
  * Release:Friday 1 May || Wed 13 May
* 1-5 May holiday on PRC, we need to do the release before or after that
  Please comment on between 1 May or 13 May.


Subtrees


* main
  * Not much activity
  * Working on ABI fix patch and ABI tooling

* next-net
  * Nothing much in both backlog and the repo
  * Started getting some patches from subtrees

* next-net-crypto
* next-net-eventdev
  * no update

* next-net-virtio
  * Working on virtio vdpa driver
* vdpa will a new class type and will moved into common folder, this work
  will be done by mlx. virtio patch will have new version on top of this.

* next-net-intel
  * There are three big base code update patchsets will be merged next weeks
  * Some small patches merged, more to merge

* LTS

  * 18.11.6-rc1 released and waiting for testing,
* Target release date is through end of January to give enough testing time


OvS
---

* OvS conference videos are online now:
  http://www.openvswitch.org/support/ovscon2019/



DPDK Release Status Meetings


The DPDK Release Status Meeting is intended for DPDK Committers to discuss
the status of the master tree and sub-trees, and for project managers to
track progress or milestone dates.

The meeting occurs on Thursdays at 8:30 UTC. If you wish to attend just
send an email to "John McNamara " for the invite.

Re: [dpdk-dev] [dpdk-stable] [PATCH] devtools: fix debug build test

[Thomas Monjalon]

16/12/2019 16:29, Thomas Monjalon:
> When testing build with +debug options, the statistics are enabled.
> It was wrongly matching CONFIG_RTE_IBVERBS_LINK_STATIC.
> The pattern is fixed to match only statistics config options.
> 
> Fixes: 2c0dd7b69fb0 ("config: add static linkage of mlx dependency")
> Cc: sta...@dpdk.org
> 
> Reported-by: Ali Alnubani 
> Signed-off-by: Thomas Monjalon 

Applied

Re: [dpdk-dev] [PATCH v1] net/ice: add new device IDs

[Ferruh Yigit]

On 12/19/2019 2:43 AM, Ye Xiaolong wrote:
> On 12/18, Ting Xu wrote:
>> This patch added new device IDs for C822N.
>>
>> Signed-off-by: Ting Xu 
>> ---
>> drivers/net/ice/ice_ethdev.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
>> index de189daba..2cbd82c94 100644
>> --- a/drivers/net/ice/ice_ethdev.c
>> +++ b/drivers/net/ice/ice_ethdev.c
>> @@ -163,6 +163,9 @@ static const struct rte_pci_id pci_id_ice_map[] = {
>>  { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
>>  { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
>>  { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
>> +{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_BACKPLANE) },
>> +{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_QSFP) },
>> +{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SFP) },
>>  { .vendor_id = 0, /* sentinel */ },
>> };
>>
>> -- 
>> 2.17.1
>>
> 
> Acked-by: Xiaolong Ye 
> 
> Applied to dpdk-next-net-intel, Thanks.
> 

Just to double check, if this requires any update in the NIC documentation?

Re: [dpdk-dev] [PATCH v3] build: fix soname info for 19.11 compatiblity

[David Marchand]

On Thu, Dec 12, 2019 at 12:59 PM Bruce Richardson
 wrote:
>
> The soname for each stable ABI version should be just the ABI version major
> number without the minor number. Unfortunately both major and minor were
> used causing version 20.1 to be incompatible with 20.0.
>
> This patch fixes the issue by switching from 2-part to 3-part ABI version
> numbers so that we can keep 20.0 as soname and using the final digits to
> identify the 20.x releases which are ABI compatible. This requires changes
> to both make and meson builds to handle the three-digit version and shrink
> it to 2-digit for soname.
>
> The final fix needed in this patch is to adjust the library version number
> for the ethtool example library, which needs to be upped to 2-digits, as
> external libraries using the DPDK build system also use the logic in this
> file.
>
> Fixes: cba806e07d6f ("build: change ABI versioning to global")
>
> Signed-off-by: Thomas Monjalon 
> Signed-off-by: Bruce Richardson 

Tested-by: David Marchand 


-- 
David Marchand

[dpdk-dev] [PATCH] ethdev: fix switching domain allocation

[Viacheslav Ovsiienko]

The maximum amount of unique switching domain is supposed
to be equal to RTE_MAX_ETHPORTS. The current implementation
allows to allocate only RTE_MAX_ETHPORTS-1 domains.

Fixes: ce9250406323 ("ethdev: add switch domain allocator")
Cc: sta...@dpdk.org

Signed-off-by: Viacheslav Ovsiienko 
---
 lib/librte_ethdev/rte_ethdev.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethdev.c
index 6e9cb24..4c2312c 100644
--- a/lib/librte_ethdev/rte_ethdev.c
+++ b/lib/librte_ethdev/rte_ethdev.c
@@ -5065,10 +5065,10 @@ enum rte_eth_switch_domain_state {
*domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
 
for (i = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID + 1;
-   i < RTE_MAX_ETHPORTS; i++) {
-   if (rte_eth_switch_domains[i].state ==
+   i <= RTE_MAX_ETHPORTS; i++) {
+   if (rte_eth_switch_domains[i - 1].state ==
RTE_ETH_SWITCH_DOMAIN_UNUSED) {
-   rte_eth_switch_domains[i].state =
+   rte_eth_switch_domains[i - 1].state =
RTE_ETH_SWITCH_DOMAIN_ALLOCATED;
*domain_id = i;
return 0;
@@ -5082,14 +5082,15 @@ enum rte_eth_switch_domain_state {
 rte_eth_switch_domain_free(uint16_t domain_id)
 {
if (domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID ||
-   domain_id >= RTE_MAX_ETHPORTS)
+   domain_id > RTE_MAX_ETHPORTS)
return -EINVAL;
 
-   if (rte_eth_switch_domains[domain_id].state !=
+   if (rte_eth_switch_domains[domain_id - 1].state !=
RTE_ETH_SWITCH_DOMAIN_ALLOCATED)
return -EINVAL;
 
-   rte_eth_switch_domains[domain_id].state = RTE_ETH_SWITCH_DOMAIN_UNUSED;
+   rte_eth_switch_domains[domain_id - 1].state =
+   RTE_ETH_SWITCH_DOMAIN_UNUSED;
 
return 0;
 }
-- 
1.8.3.1

[dpdk-dev] [PATCH] mempool: fix mempool obj alignment for non x86

[jerinj]

From: Jerin Jacob 

The exiting optimize_object_size() function address the memory object
alignment constraint on x86 for better performance.

Different (Mirco) architecture may have different
memory alignment constraint for better performance and it not
same as the existing optimize_object_size() function. Some use,
XOR(kind of CRC) scheme to enable DRAM channel distribution
based on the address and some may have a different formula.

Introducing arch_mem_object_align() function to abstract
the differences in different (mirco) architectures and avoid
wasting memory for mempool object alignment for the architecture
the existing optimize_object_size() is not valid.

Additional details:
https://www.mail-archive.com/dev@dpdk.org/msg149157.html

Fixes: af75078fece3 ("first public release")
Cc: sta...@dpdk.org

Signed-off-by: Jerin Jacob 
---
 doc/guides/prog_guide/mempool_lib.rst |  6 +++---
 lib/librte_mempool/rte_mempool.c  | 17 +
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/doc/guides/prog_guide/mempool_lib.rst 
b/doc/guides/prog_guide/mempool_lib.rst
index 3bb84b0a6..eea7a2906 100644
--- a/doc/guides/prog_guide/mempool_lib.rst
+++ b/doc/guides/prog_guide/mempool_lib.rst
@@ -27,10 +27,10 @@ In debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled),
 statistics about get from/put in the pool are stored in the mempool structure.
 Statistics are per-lcore to avoid concurrent access to statistics counters.
 
-Memory Alignment Constraints
-
+Memory Alignment Constraints on X86 architecture
+
 
-Depending on hardware memory configuration, performance can be greatly 
improved by adding a specific padding between objects.
+Depending on hardware memory configuration on X86 architecture, performance 
can be greatly improved by adding a specific padding between objects.
 The objective is to ensure that the beginning of each object starts on a 
different channel and rank in memory so that all channels are equally loaded.
 
 This is particularly true for packet buffers when doing L3 forwarding or flow 
classification.
diff --git a/lib/librte_mempool/rte_mempool.c b/lib/librte_mempool/rte_mempool.c
index 78d8eb941..871894525 100644
--- a/lib/librte_mempool/rte_mempool.c
+++ b/lib/librte_mempool/rte_mempool.c
@@ -45,6 +45,7 @@ EAL_REGISTER_TAILQ(rte_mempool_tailq)
 #define CALC_CACHE_FLUSHTHRESH(c)  \
((typeof(c))((c) * CACHE_FLUSHTHRESH_MULTIPLIER))
 
+#if defined(RTE_ARCH_X86)
 /*
  * return the greatest common divisor between a and b (fast algorithm)
  *
@@ -74,12 +75,13 @@ static unsigned get_gcd(unsigned a, unsigned b)
 }
 
 /*
- * Depending on memory configuration, objects addresses are spread
+ * Depending on memory configuration on x86 arch, objects addresses are spread
  * between channels and ranks in RAM: the pool allocator will add
  * padding between objects. This function return the new size of the
  * object.
  */
-static unsigned optimize_object_size(unsigned obj_size)
+static unsigned
+arch_mem_object_align(unsigned obj_size)
 {
unsigned nrank, nchan;
unsigned new_obj_size;
@@ -99,6 +101,13 @@ static unsigned optimize_object_size(unsigned obj_size)
new_obj_size++;
return new_obj_size * RTE_MEMPOOL_ALIGN;
 }
+#else
+static unsigned
+arch_mem_object_align(unsigned obj_size)
+{
+   return obj_size;
+}
+#endif
 
 struct pagesz_walk_arg {
int socket_id;
@@ -234,8 +243,8 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags,
 */
if ((flags & MEMPOOL_F_NO_SPREAD) == 0) {
unsigned new_size;
-   new_size = optimize_object_size(sz->header_size + sz->elt_size +
-   sz->trailer_size);
+   new_size = arch_mem_object_align
+   (sz->header_size + sz->elt_size + sz->trailer_size);
sz->trailer_size = new_size - sz->header_size - sz->elt_size;
}
 
-- 
2.24.1

Re: [dpdk-dev] [PATCH v3] build: fix soname info for 19.11 compatiblity

[Thomas Monjalon]

19/12/2019 13:42, David Marchand:
> On Thu, Dec 12, 2019 at 12:59 PM Bruce Richardson
>  wrote:
> >
> > The soname for each stable ABI version should be just the ABI version major
> > number without the minor number. Unfortunately both major and minor were
> > used causing version 20.1 to be incompatible with 20.0.
> >
> > This patch fixes the issue by switching from 2-part to 3-part ABI version
> > numbers so that we can keep 20.0 as soname and using the final digits to
> > identify the 20.x releases which are ABI compatible. This requires changes
> > to both make and meson builds to handle the three-digit version and shrink
> > it to 2-digit for soname.
> >
> > The final fix needed in this patch is to adjust the library version number
> > for the ethtool example library, which needs to be upped to 2-digits, as
> > external libraries using the DPDK build system also use the logic in this
> > file.
> >
> > Fixes: cba806e07d6f ("build: change ABI versioning to global")
> >
> > Signed-off-by: Thomas Monjalon 
> > Signed-off-by: Bruce Richardson 

Acked-by: Neil Horman 
Tested-by: Ray Kinsella 
Tested-by: Ferruh Yigit 
Tested-by: Kevin Laatz 

> Tested-by: David Marchand 

Applied, thanks

Re: [dpdk-dev] [dpdk-stable] [PATCH] rte_flow: fix docbook comment

[Ferruh Yigit]

On 12/18/2019 6:44 AM, Slava Ovsiienko wrote:

<...>

> 
>> -Original Message-
>> From: Stephen Hemminger 
>> Sent: Wednesday, December 18, 2019 3:13
>> To: dev@dpdk.org
>> Cc: Stephen Hemminger ; Slava Ovsiienko
>> ; sta...@dpdk.org
>> Subject: [PATCH] rte_flow: fix docbook comment
>>
>> Missing asterisk so that comment is not seen by doxygen.
>>
>> Fixes: 9a2f44c76207 ("ethdev: add flow tag")
>> Cc: viachesl...@mellanox.com
>> Cc: sta...@dpdk.org
>> Signed-off-by: Stephen Hemminger 
>
> Acked-by: Viacheslav Ovsiienko 
>

Applied to dpdk-next-net/master, thanks.

Re: [dpdk-dev] [PATCH] ci: update travis to use bionic

[Laatz, Kevin]

On 17/12/2019 18:03, Aaron Conole wrote:

"Laatz, Kevin"  writes:


On 17/12/2019 14:44, Aaron Conole wrote:

Kevin Laatz  writes:


Currently, the Travis CI is using Ubuntu 16.04 LTS (Xenial) which is
becoming increasingly outdated. This patch updates Travis to use Ubuntu
18.04 LTS (Bionic) which will give us the benefit of more up-to-date
packages being availble and the newer features that come with them.

Signed-off-by: Kevin Laatz 
---
   .travis.yml | 4 ++--
   1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 8f90d06f2..6e0626353 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -4,7 +4,7 @@ compiler:
 - gcc
 - clang
   -dist: xenial
+dist: bionic

This LGTM.


   os:
 - linux
@@ -21,7 +21,7 @@ aarch64_packages: &aarch64_packages
 extra_packages: &extra_packages
 - *required_packages
-  - [libbsd-dev, libpcap-dev, libcrypto++-dev, libjansson4]
+  - [libbsd-dev, libpcap-dev, libcrypto++-dev, libjansson4, abigail-tools]

Will adding the abigail-tools automatically invoke the ABI checks?
Otherwise, maybe it's best to save this for a future commit.

I'll look for the robot build when it comes by.  Thanks!

Yes, the meson option that will be introduced with the "Add ABI
compatibility checks to the meson build" [1] patch set will be set to
"auto" meaning the checks will run if abidiff is found.

Okay.  I'm fine with that change.


[1] http://patches.dpdk.org/project/dpdk/list/?series=7830

I noticed the shared builds are failing:
   https://travis-ci.com/ovsrobot/dpdk/jobs/268042693

But not sure what the issue is with librte_mempool_ring

Can you see why it would fail under bionic?


Between Xenial and Bionic, there has been a slight change (RPATH 
related) in how shared objects are linked causing librte_mempool_ring to 
not be found.


Ruifeng has submitted a patch [1] that addresses this issue.

[1] http://patches.dpdk.org/patch/63978/


   build_32b_packages: &build_32b_packages
 - *required_packages

Re: [dpdk-dev] [EXT] Re: [PATCH] ethdev: allow multiple security sessions to use one rte flow

[Medvedkin, Vladimir]

Hi Anoob,

On 19/12/2019 04:37, Anoob Joseph wrote:

Hi Vladimir,

Please see inline.

Thanks,
Anoob


-Original Message-
From: dev  On Behalf Of Medvedkin, Vladimir
Sent: Wednesday, December 18, 2019 7:22 PM
To: Anoob Joseph ; Ananyev, Konstantin
; Akhil Goyal ;
Adrien Mazarguil ; Doherty, Declan
; Yigit, Ferruh ; Jerin
Jacob Kollanukkaran ; Thomas Monjalon

Cc: Ankur Dwivedi ; Hemant Agrawal
; Matan Azrad ;
Nicolau, Radu ; Shahaf Shuler
; Narayana Prasad Raju Athreya
; dev@dpdk.org
Subject: Re: [dpdk-dev] [EXT] Re: [PATCH] ethdev: allow multiple security
sessions to use one rte flow

Hi Anoob,

On 18/12/2019 03:54, Anoob Joseph wrote:

Hi Vladimir,

Please see inline.

Thanks,
Anoob


-Original Message-
From: Medvedkin, Vladimir 
Sent: Tuesday, December 17, 2019 11:14 PM
To: Anoob Joseph ; Ananyev, Konstantin
; Akhil Goyal ;
Adrien Mazarguil ; Doherty, Declan
; Yigit, Ferruh ;
Jerin Jacob Kollanukkaran ; Thomas Monjalon

Cc: Ankur Dwivedi ; Hemant Agrawal
; Matan Azrad ;

Nicolau,

Radu ; Shahaf Shuler

;

Narayana Prasad Raju Athreya ; dev@dpdk.org
Subject: Re: [EXT] Re: [dpdk-dev] [PATCH] ethdev: allow multiple
security sessions to use one rte flow

Hi Anoob,

On 17/12/2019 14:24, Anoob Joseph wrote:

Hi Vladimir,

Please see inline.

Thanks,
Anoob


-Original Message-
From: Medvedkin, Vladimir 
Sent: Tuesday, December 17, 2019 4:51 PM
To: Anoob Joseph ; Ananyev, Konstantin
; Akhil Goyal ;
Adrien Mazarguil ; Doherty, Declan
; Yigit, Ferruh ;
Jerin Jacob Kollanukkaran ; Thomas Monjalon

Cc: Ankur Dwivedi ; Hemant Agrawal
; Matan Azrad ;

Nicolau,

Radu ; Shahaf Shuler

;

Narayana Prasad Raju Athreya ;

dev@dpdk.org

Subject: Re: [EXT] Re: [dpdk-dev] [PATCH] ethdev: allow multiple
security sessions to use one rte flow

Hi Anoob,

On 16/12/2019 16:16, Anoob Joseph wrote:

Hi Vladimir,

Please see inline.

Thanks,
Anoob


-Original Message-
From: Medvedkin, Vladimir 
Sent: Monday, December 16, 2019 9:29 PM
To: Anoob Joseph ; Ananyev, Konstantin
; Akhil Goyal
; Adrien Mazarguil
; Doherty, Declan
; Yigit, Ferruh
; Jerin Jacob Kollanukkaran
; Thomas Monjalon 
Cc: Ankur Dwivedi ; Hemant Agrawal
; Matan Azrad

;

Nicolau,

Radu ; Shahaf Shuler
; Narayana Prasad Raju Athreya
; dev@dpdk.org
Subject: [EXT] Re: [dpdk-dev] [PATCH] ethdev: allow multiple
security sessions to use one rte flow

External Email

-
--
--
-
Hi Anoob,

On 11/12/2019 17:33, Anoob Joseph wrote:

Hi Konstantin,

Please see inline.

Thanks,
Anoob


-Original Message-
From: dev  On Behalf Of Ananyev,

Konstantin

Sent: Wednesday, December 11, 2019 4:36 PM
To: Anoob Joseph ; Akhil Goyal
; Adrien Mazarguil
; Doherty, Declan
; Yigit, Ferruh
; Jerin Jacob Kollanukkaran
; Thomas Monjalon



Cc: Ankur Dwivedi ; Hemant Agrawal
; Matan Azrad

;

Nicolau,

Radu ; Shahaf Shuler
; Narayana Prasad Raju Athreya
; dev@dpdk.org
Subject: Re: [dpdk-dev] [PATCH] ethdev: allow multiple security
sessions to use one rte flow



The rte_security API which enables inline protocol/crypto
feature mandates that for every security session an rte_flow
is

created.

This would internally translate to a rule in the hardware
which would do packet classification.

In rte_securty, one SA would be one security session. And if
an rte_flow need to be created for every session, the number
of SAs supported by an inline implementation would be
limited by the number of rte_flows the PMD would be able to

support.

If the fields SPI & IP addresses are allowed to be a range,
then this limitation can be overcome. Multiple flows will be
able to use one rule for SECURITY processing. In this case,
the security session provided as conf would be NULL.

Wonder what will be the usage model for it?
AFAIK,  RFC 4301 clearly states that either SPI value alone
or in conjunction with dst (and src) IP should clearly
identify SA for inbound SAD

lookup.

Am I missing something obvious here?

[Anoob] Existing SECURITY action type requires application to
create an 'rte_flow' per SA, which is not really required if
h/w can use SPI to uniquely

identify the security session/SA.

Existing rte_flow usage: IP (dst,src) + ESP + SPI -> security
processing enabled on one security session (ie on SA)

The above rule would uniquely identify packets for an SA. But
with the above usage, we would quickly exhaust entries
available in h/w lookup tables (which are limited on our
hardware). But if h/w can use SPI field to index

into a table (for example), then the above requirement of one
rte_flow per SA is not required.

Proposed rte_flow usage: IP (any) + ESP + SPI (any) ->
security processing enabled on all ESP packets

So this means that SA will be indexed only by spi? What about
SA's which are indexed by SPI+DIP+SIP?

Now h/w could use SPI to index into a pre-populated table to
get security session. Please do note that, SPI is not ignored
during the actual

lookup. Just that it is not used while creating 'rte_f

Re: [dpdk-dev] [PATCH v6 00/11] Add ABI compatibility checks to the meson build

[David Marchand]

Hello Kevin,

On Fri, Dec 13, 2019 at 5:41 PM Kevin Laatz  wrote:
>
> With the recent changes made to stabilize ABI versioning in DPDK, it will
> become increasingly important to check patches for ABI compatibility. We
> propose adding the ABI compatibility checking to be done as part of the
> build.
>
> The advantages to adding the ABI compatibility checking to the build are
> two-fold. Firstly, developers can easily check their patches to make sure
> they don’t break the ABI without adding any extra steps. Secondly, it
> makes the integration into existing CI seamless since there are no extra
> scripts to make the CI run. The build will run as usual and if an
> incompatibility is detected in the ABI, the build will fail and show the
> incompatibility. As an added bonus, enabling the ABI compatibility checks
> does not impact the build speed.
>
> The proposed solution works as follows:
> 1. Generate the ABI dump of the baseline. This can be done with the new
>script added in this set. This step will only need to be done when the
>ABI version changes (so once a year) and can be added to master so it
>exists by default. This step can be skipped if the dump files for the
>baseline already exist.
> 2. Build with meson. If there is an ABI incompatibility, the build will
>fail and print the incompatibility information.
>
> The patches in this set include the ABI dump file generating script, the
> dump files for drivers and libs, the meson option required to
> enable/disable the checks, and the required meson changes to run the
> compatibility checks during the build.
>
> Note: This patch set depends on: http://patches.dpdk.org/patch/63765/.  The
> generated .dump files in this patch set are based on the changes in the
> patch "build: fix soname info for 19.11 compatibility". If a decision is
> made to use a different format for the sonames, then a new version of this
> patch set will be required as the .dump files will need to be regenerated.
>
> Note: The following driver dump files are not included in these patches:
> common/mvep:missing dependency, "libmusdk"
> net/mvneta: missing dependency, "libmusdk"
> net/mvpp2:  missing dependency, "libmusdk"
> net/nfb:missing dependency, "libnfb"
> crypto/mvsam:   missing dependency, "libmusdk"
>
> They have not been included as I do not have access to these dependencies.
> Please feel free to add them if you can! (Maintainers of the above Cc'ed).

- I asked for the dump files, but I can see that it is impractical.

The dump files are huge. I did not expect that :-).
The dump files are architecture specific and maintaining multi arch
dumps would be even bigger than just what you sent for x86_64.
(not even considering the changes in ABI if some configuration items
have an impact...).

As you pointed out, people who don't have all dependencies won't
create/update those dump files.
Dealing with ABI updates (thinking of bumping the ABI version) is
likely a maintainer job, but it will be a source of issues and we
(maintainers) might miss some updates especially for drivers we can't
build.


- Why do we restrict the checks to meson?
The make build framework is going to disappear ok, but we can't leave
it untested.
People still rely on it.

Checking the ABI is orthogonal to building DPDK.
Dumping the ABI and checking it against objects can be done externally.


- For those reasons, I have been trying an alternate approach [1]: in
Travis, generate a reference dump based on the first ancestor tag,
then build the proposed patches.
All contributions get picked up by Aaron robot and would have to pass
through this check.

As an exercise, I tried to integrate Eelco patch [2], that moves
symbols from EXPERIMENTAL to a stable ABI. The check passes fine.
I also tried to bump the ABI major version. The check fails, as
expected, but I prepared a way to bypass such failures for the
releases where we will explicitely break ABI.

For maintainers that integrate patches or developers that get a CI
failure and want to fix it, we would need to help them to:
* generate dumps on a reference version, so I would tend to write some
documentation since playing with the current sources would be too
dangerous from my pov,
* run the checks, like adding the check in the
devtools/test-*-build.sh scripts that already exist, with a new
configuration item to point at the dumps per target,

Those last two points are still to be done.

WDYT?


1: 
https://github.com/david-marchand/dpdk/commit/f18de2ec157f3cc1e7b319cb19700e1b5e9cecde
2: https://patchwork.dpdk.org/patch/63970/

--
David Marchand

[dpdk-dev] [PATCH v4 02/17] net/ionic: add hardware structures definitions

[Alfredo Cardigliano]

Add hardware structures and message commands definitions for
Pensando network adapters.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 drivers/net/ionic/ionic_if.h | 2491 ++
 1 file changed, 2491 insertions(+)
 create mode 100644 drivers/net/ionic/ionic_if.h

diff --git a/drivers/net/ionic/ionic_if.h b/drivers/net/ionic/ionic_if.h
new file mode 100644
index 0..b3d1c85dc
--- /dev/null
+++ b/drivers/net/ionic/ionic_if.h
@@ -0,0 +1,2491 @@
+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-3-Clause */
+/* Copyright (c) 2017-2019 Pensando Systems, Inc.  All rights reserved. */
+
+#ifndef _IONIC_IF_H_
+#define _IONIC_IF_H_
+
+#pragma pack(push, 1)
+
+#define IONIC_DEV_INFO_SIGNATURE   0x44455649  /* 'DEVI' */
+#define IONIC_DEV_INFO_VERSION 1
+#define IONIC_IFNAMSIZ 16
+
+/**
+ * Commands
+ */
+enum ionic_cmd_opcode {
+   IONIC_CMD_NOP   = 0,
+
+   /* Device commands */
+   IONIC_CMD_IDENTIFY  = 1,
+   IONIC_CMD_INIT  = 2,
+   IONIC_CMD_RESET = 3,
+   IONIC_CMD_GETATTR   = 4,
+   IONIC_CMD_SETATTR   = 5,
+
+   /* Port commands */
+   IONIC_CMD_PORT_IDENTIFY = 10,
+   IONIC_CMD_PORT_INIT = 11,
+   IONIC_CMD_PORT_RESET= 12,
+   IONIC_CMD_PORT_GETATTR  = 13,
+   IONIC_CMD_PORT_SETATTR  = 14,
+
+   /* LIF commands */
+   IONIC_CMD_LIF_IDENTIFY  = 20,
+   IONIC_CMD_LIF_INIT  = 21,
+   IONIC_CMD_LIF_RESET = 22,
+   IONIC_CMD_LIF_GETATTR   = 23,
+   IONIC_CMD_LIF_SETATTR   = 24,
+
+   IONIC_CMD_RX_MODE_SET   = 30,
+   IONIC_CMD_RX_FILTER_ADD = 31,
+   IONIC_CMD_RX_FILTER_DEL = 32,
+
+   /* Queue commands */
+   IONIC_CMD_Q_INIT= 40,
+   IONIC_CMD_Q_CONTROL = 41,
+
+   /* RDMA commands */
+   IONIC_CMD_RDMA_RESET_LIF= 50,
+   IONIC_CMD_RDMA_CREATE_EQ= 51,
+   IONIC_CMD_RDMA_CREATE_CQ= 52,
+   IONIC_CMD_RDMA_CREATE_ADMINQ= 53,
+
+   /* QoS commands */
+   IONIC_CMD_QOS_CLASS_IDENTIFY= 240,
+   IONIC_CMD_QOS_CLASS_INIT= 241,
+   IONIC_CMD_QOS_CLASS_RESET   = 242,
+
+   /* Firmware commands */
+   IONIC_CMD_FW_DOWNLOAD   = 254,
+   IONIC_CMD_FW_CONTROL= 255,
+};
+
+/**
+ * Command Return codes
+ */
+enum ionic_status_code {
+   IONIC_RC_SUCCESS= 0,/* Success */
+   IONIC_RC_EVERSION   = 1,/* Incorrect version for request */
+   IONIC_RC_EOPCODE= 2,/* Invalid cmd opcode */
+   IONIC_RC_EIO= 3,/* I/O error */
+   IONIC_RC_EPERM  = 4,/* Permission denied */
+   IONIC_RC_EQID   = 5,/* Bad qid */
+   IONIC_RC_EQTYPE = 6,/* Bad qtype */
+   IONIC_RC_ENOENT = 7,/* No such element */
+   IONIC_RC_EINTR  = 8,/* operation interrupted */
+   IONIC_RC_EAGAIN = 9,/* Try again */
+   IONIC_RC_ENOMEM = 10,   /* Out of memory */
+   IONIC_RC_EFAULT = 11,   /* Bad address */
+   IONIC_RC_EBUSY  = 12,   /* Device or resource busy */
+   IONIC_RC_EEXIST = 13,   /* object already exists */
+   IONIC_RC_EINVAL = 14,   /* Invalid argument */
+   IONIC_RC_ENOSPC = 15,   /* No space left or alloc failure */
+   IONIC_RC_ERANGE = 16,   /* Parameter out of range */
+   IONIC_RC_BAD_ADDR   = 17,   /* Descriptor contains a bad ptr */
+   IONIC_RC_DEV_CMD= 18,   /* Device cmd attempted on AdminQ */
+   IONIC_RC_ENOSUPP= 19,   /* Operation not supported */
+   IONIC_RC_ERROR  = 29,   /* Generic error */
+
+   IONIC_RC_ERDMA  = 30,   /* Generic RDMA error */
+};
+
+enum ionic_notifyq_opcode {
+   IONIC_EVENT_LINK_CHANGE = 1,
+   IONIC_EVENT_RESET   = 2,
+   IONIC_EVENT_HEARTBEAT   = 3,
+   IONIC_EVENT_LOG = 4,
+};
+
+/**
+ * struct cmd - General admin command format
+ * @opcode: Opcode for the command
+ * @lif_index:  LIF index
+ * @cmd_data:   Opcode-specific command bytes
+ */
+struct ionic_admin_cmd {
+   u8 opcode;
+   u8 rsvd;
+   __le16 lif_index;
+   u8 cmd_data[60];
+};
+
+/**
+ * struct ionic_admin_comp - General admin command completion format
+ * @status: The status of the command (enum status_code)
+ * @comp_index: The index in the descriptor ring for whi

[dpdk-dev] [PATCH v4 01/17] net/ionic: add skeleton

[Alfredo Cardigliano]

Add makefile and config file options to compile the Pensando ionic PMD.
Add feature and version map file.
Update maintainers file.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 MAINTAINERS |  6 +++
 config/common_armv8a_linux  |  2 +
 config/common_base  |  5 +++
 config/defconfig_arm-armv7a-linuxapp-gcc|  1 +
 config/defconfig_ppc_64-power8-linuxapp-gcc |  1 +
 doc/guides/nics/features/ionic.ini  |  8 
 doc/guides/nics/index.rst   |  1 +
 doc/guides/nics/ionic.rst   | 43 +
 doc/guides/rel_notes/release_20_02.rst  |  4 ++
 drivers/net/Makefile|  1 +
 drivers/net/ionic/Makefile  | 25 
 drivers/net/ionic/meson.build   |  6 +++
 drivers/net/ionic/rte_pmd_ionic_version.map |  5 +++
 mk/rte.app.mk   |  1 +
 14 files changed, 109 insertions(+)
 create mode 100644 doc/guides/nics/features/ionic.ini
 create mode 100644 doc/guides/nics/ionic.rst
 create mode 100644 drivers/net/ionic/Makefile
 create mode 100644 drivers/net/ionic/meson.build
 create mode 100644 drivers/net/ionic/rte_pmd_ionic_version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 4395d8df1..bb4422344 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -810,6 +810,12 @@ F: doc/guides/nics/pfe.rst
 F: drivers/net/pfe/
 F: doc/guides/nics/features/pfe.ini
 
+Pensando ionic
+M: Alfredo Cardigliano 
+F: drivers/net/ionic/
+F: doc/guides/nics/ionic.rst
+F: doc/guides/nics/features/ionic.ini
+
 QLogic bnx2x
 M: Rasesh Mody 
 M: Shahed Shaikh 
diff --git a/config/common_armv8a_linux b/config/common_armv8a_linux
index 782877bb2..2057d9138 100644
--- a/config/common_armv8a_linux
+++ b/config/common_armv8a_linux
@@ -42,3 +42,5 @@ CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV=n
 CONFIG_RTE_LIBRTE_PFE_PMD=y
 
 CONFIG_RTE_SCHED_VECTOR=n
+
+CONFIG_RTE_LIBRTE_IONIC_PMD=n
diff --git a/config/common_base b/config/common_base
index 7dec7ed45..626c83d05 100644
--- a/config/common_base
+++ b/config/common_base
@@ -277,6 +277,11 @@ CONFIG_RTE_LIBRTE_E1000_DEBUG_TX=n
 CONFIG_RTE_LIBRTE_E1000_DEBUG_TX_FREE=n
 CONFIG_RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC=n
 
+#
+# Compile Pensando IONIC PMD driver
+#
+CONFIG_RTE_LIBRTE_IONIC_PMD=y
+
 #
 # Compile burst-oriented HINIC PMD driver
 #
diff --git a/config/defconfig_arm-armv7a-linuxapp-gcc 
b/config/defconfig_arm-armv7a-linuxapp-gcc
index c91423f0e..6ac7f47e4 100644
--- a/config/defconfig_arm-armv7a-linuxapp-gcc
+++ b/config/defconfig_arm-armv7a-linuxapp-gcc
@@ -57,3 +57,4 @@ CONFIG_RTE_LIBRTE_NFP_PMD=n
 CONFIG_RTE_LIBRTE_HINIC_PMD=n
 CONFIG_RTE_LIBRTE_HNS3_PMD=n
 CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV=n
+CONFIG_RTE_LIBRTE_IONIC_PMD=n
diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc 
b/config/defconfig_ppc_64-power8-linuxapp-gcc
index b7b9d6f48..c917c4774 100644
--- a/config/defconfig_ppc_64-power8-linuxapp-gcc
+++ b/config/defconfig_ppc_64-power8-linuxapp-gcc
@@ -32,3 +32,4 @@ CONFIG_RTE_LIBRTE_AVP_PMD=n
 CONFIG_RTE_LIBRTE_HINIC_PMD=n
 CONFIG_RTE_LIBRTE_HNS3_PMD=n
 CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV=n
+CONFIG_RTE_LIBRTE_IONIC_PMD=n
diff --git a/doc/guides/nics/features/ionic.ini 
b/doc/guides/nics/features/ionic.ini
new file mode 100644
index 0..3a92eedc7
--- /dev/null
+++ b/doc/guides/nics/features/ionic.ini
@@ -0,0 +1,8 @@
+;
+; Supported features of the 'ionic' network poll mode driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+x86-64   = Y
+Usage doc= Y
diff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst
index d61c27fdf..7b5fea029 100644
--- a/doc/guides/nics/index.rst
+++ b/doc/guides/nics/index.rst
@@ -33,6 +33,7 @@ Network Interface Controller Drivers
 ice
 ifc
 igb
+ionic
 ipn3ke
 ixgbe
 intel_vf
diff --git a/doc/guides/nics/ionic.rst b/doc/guides/nics/ionic.rst
new file mode 100644
index 0..e81771cb2
--- /dev/null
+++ b/doc/guides/nics/ionic.rst
@@ -0,0 +1,43 @@
+..  SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
+
+IONIC Driver
+
+
+The ionic driver provides support for Pensando server adapters. 
+It currently supports the below models:
+
+- `Naples DSC-25
+`_
+- `Naples DSC-100
+`_
+
+Please visit https://pensando.io for more information.
+
+Identifying the Adapter
+---
+
+To find if one or more Pensando PCI Ethernet devices are installed
+on the host, check for the PCI devices:
+
+   .. code-block:: console
+
+  lspci -d 1dd8:
+  b5:00.0 Ethernet controller: Device 1dd8:1002
+  b6:00.0 Ethernet controller: Device 1dd8:1002
+
+Pre-Installation Configuration
+

[dpdk-dev] [PATCH v4 00/17] Introduces net/ionic PMD

[Alfredo Cardigliano]

The patch series provides an initial version of a
poll mode driver for Pensando network adapters.
The driver name is ionic.

v4 Changes:
--
- Remove the static list of adapters
- Disable compilation on unsupported platforms
- Add BSD-3-Clause to ionic_if.h
- Add a link to the supported adapters description pages
- Fix compilation warnings
- Other minor fixes

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 

Alfredo Cardigliano (17):
  net/ionic: add skeleton
  net/ionic: add hardware structures definitions
  net/ionic: add log
  net/ionic: register and initialize the adapter
  net/ionic: add port management commands
  net/ionic: add basic lif support
  net/ionic: add doorbells
  net/ionic: add adminq support
  net/ionic: add notifyq support
  net/ionic: add basic port operations
  net/ionic: add RX filters support
  net/ionic: add Flow Control support
  net/ionic: add RX and TX handling
  net/ionic: add RSS support
  net/ionic: add stats
  net/ionic: add TX checksum support
  net/ionic: read fw version

 MAINTAINERS |6 +
 config/common_armv8a_linux  |2 +
 config/common_base  |5 +
 config/defconfig_arm-armv7a-linuxapp-gcc|1 +
 config/defconfig_ppc_64-power8-linuxapp-gcc |1 +
 doc/guides/nics/features/ionic.ini  |   36 +
 doc/guides/nics/index.rst   |1 +
 doc/guides/nics/ionic.rst   |   43 +
 doc/guides/rel_notes/release_20_02.rst  |4 +
 drivers/net/Makefile|1 +
 drivers/net/ionic/Makefile  |   34 +
 drivers/net/ionic/ionic.h   |   81 +
 drivers/net/ionic/ionic_dev.c   |  577 +
 drivers/net/ionic/ionic_dev.h   |  269 ++
 drivers/net/ionic/ionic_ethdev.c| 1345 ++
 drivers/net/ionic/ionic_ethdev.h|   22 +
 drivers/net/ionic/ionic_if.h| 2491 +++
 drivers/net/ionic/ionic_lif.c   | 1719 +
 drivers/net/ionic/ionic_lif.h   |  189 ++
 drivers/net/ionic/ionic_logs.h  |   26 +
 drivers/net/ionic/ionic_mac_api.c   |   61 +
 drivers/net/ionic/ionic_mac_api.h   |   13 +
 drivers/net/ionic/ionic_main.c  |  450 
 drivers/net/ionic/ionic_osdep.h |   79 +
 drivers/net/ionic/ionic_regs.h  |  142 ++
 drivers/net/ionic/ionic_rx_filter.c |  139 ++
 drivers/net/ionic/ionic_rx_filter.h |   47 +
 drivers/net/ionic/ionic_rxtx.c  | 1087 
 drivers/net/ionic/ionic_rxtx.h  |   44 +
 drivers/net/ionic/meson.build   |   13 +
 drivers/net/ionic/rte_pmd_ionic_version.map |5 +
 mk/rte.app.mk   |1 +
 32 files changed, 8934 insertions(+)
 create mode 100644 doc/guides/nics/features/ionic.ini
 create mode 100644 doc/guides/nics/ionic.rst
 create mode 100644 drivers/net/ionic/Makefile
 create mode 100644 drivers/net/ionic/ionic.h
 create mode 100644 drivers/net/ionic/ionic_dev.c
 create mode 100644 drivers/net/ionic/ionic_dev.h
 create mode 100644 drivers/net/ionic/ionic_ethdev.c
 create mode 100644 drivers/net/ionic/ionic_ethdev.h
 create mode 100644 drivers/net/ionic/ionic_if.h
 create mode 100644 drivers/net/ionic/ionic_lif.c
 create mode 100644 drivers/net/ionic/ionic_lif.h
 create mode 100644 drivers/net/ionic/ionic_logs.h
 create mode 100644 drivers/net/ionic/ionic_mac_api.c
 create mode 100644 drivers/net/ionic/ionic_mac_api.h
 create mode 100644 drivers/net/ionic/ionic_main.c
 create mode 100644 drivers/net/ionic/ionic_osdep.h
 create mode 100644 drivers/net/ionic/ionic_regs.h
 create mode 100644 drivers/net/ionic/ionic_rx_filter.c
 create mode 100644 drivers/net/ionic/ionic_rx_filter.h
 create mode 100644 drivers/net/ionic/ionic_rxtx.c
 create mode 100644 drivers/net/ionic/ionic_rxtx.h
 create mode 100644 drivers/net/ionic/meson.build
 create mode 100644 drivers/net/ionic/rte_pmd_ionic_version.map

-- 
2.17.1

[dpdk-dev] [PATCH v4 05/17] net/ionic: add port management commands

[Alfredo Cardigliano]

Add port management commands that apply to the physical
ports associated with the PCI device, which might be
shared among several logical interfaces.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 drivers/net/ionic/ionic.h|   6 ++
 drivers/net/ionic/ionic_dev.c| 127 ++
 drivers/net/ionic/ionic_dev.h|  18 +
 drivers/net/ionic/ionic_ethdev.c |  16 
 drivers/net/ionic/ionic_main.c   | 131 +++
 5 files changed, 298 insertions(+)

diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h
index 5c869e698..a29f0bb89 100644
--- a/drivers/net/ionic/ionic.h
+++ b/drivers/net/ionic/ionic.h
@@ -7,6 +7,8 @@
 
 #include 
 
+#include 
+
 #include "ionic_dev.h"
 #include "ionic_if.h"
 #include "ionic_osdep.h"
@@ -60,4 +62,8 @@ int ionic_identify(struct ionic_adapter *adapter);
 int ionic_init(struct ionic_adapter *adapter);
 int ionic_reset(struct ionic_adapter *adapter);
 
+int ionic_port_identify(struct ionic_adapter *adapter);
+int ionic_port_init(struct ionic_adapter *adapter);
+int ionic_port_reset(struct ionic_adapter *adapter);
+
 #endif /* _IONIC_H_ */
diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c
index a8ad5358f..d74834122 100644
--- a/drivers/net/ionic/ionic_dev.c
+++ b/drivers/net/ionic/ionic_dev.c
@@ -132,3 +132,130 @@ ionic_dev_cmd_reset(struct ionic_dev *idev)
 
ionic_dev_cmd_go(idev, &cmd);
 }
+
+/* Port commands */
+
+void
+ionic_dev_cmd_port_identify(struct ionic_dev *idev)
+{
+   union ionic_dev_cmd cmd = {
+   .port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
+   .port_init.index = 0,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_port_init(struct ionic_dev *idev)
+{
+   union ionic_dev_cmd cmd = {
+   .port_init.opcode = IONIC_CMD_PORT_INIT,
+   .port_init.index = 0,
+   .port_init.info_pa = idev->port_info_pa,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_port_reset(struct ionic_dev *idev)
+{
+   union ionic_dev_cmd cmd = {
+   .port_reset.opcode = IONIC_CMD_PORT_RESET,
+   .port_reset.index = 0,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state)
+{
+   union ionic_dev_cmd cmd = {
+   .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
+   .port_setattr.index = 0,
+   .port_setattr.attr = IONIC_PORT_ATTR_STATE,
+   .port_setattr.state = state,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed)
+{
+   union ionic_dev_cmd cmd = {
+   .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
+   .port_setattr.index = 0,
+   .port_setattr.attr = IONIC_PORT_ATTR_SPEED,
+   .port_setattr.speed = speed,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu)
+{
+   union ionic_dev_cmd cmd = {
+   .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
+   .port_setattr.index = 0,
+   .port_setattr.attr = IONIC_PORT_ATTR_MTU,
+   .port_setattr.mtu = mtu,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable)
+{
+   union ionic_dev_cmd cmd = {
+   .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
+   .port_setattr.index = 0,
+   .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
+   .port_setattr.an_enable = an_enable,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type)
+{
+   union ionic_dev_cmd cmd = {
+   .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
+   .port_setattr.index = 0,
+   .port_setattr.attr = IONIC_PORT_ATTR_FEC,
+   .port_setattr.fec_type = fec_type,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type)
+{
+   union ionic_dev_cmd cmd = {
+   .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
+   .port_setattr.index = 0,
+   .port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
+   .port_setattr.pause_type = pause_type,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode)
+{
+   union ionic_dev_cmd cmd = {
+   .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
+   .port_setattr.index = 0,
+   .port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK,
+   .port_setattr.loopback_mode = loopback_mode,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
diff --git a/drivers/net/

[dpdk-dev] [PATCH v4 03/17] net/ionic: add log

[Alfredo Cardigliano]

Add debug options to the config file.
Define macros used for logs and make use of config file options
to enable them.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 drivers/net/ionic/Makefile   |  2 +-
 drivers/net/ionic/ionic_ethdev.c | 15 +++
 drivers/net/ionic/ionic_logs.h   | 26 ++
 drivers/net/ionic/meson.build|  1 +
 4 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/ionic/ionic_ethdev.c
 create mode 100644 drivers/net/ionic/ionic_logs.h

diff --git a/drivers/net/ionic/Makefile b/drivers/net/ionic/Makefile
index 9c2f9cf2e..baa34b055 100644
--- a/drivers/net/ionic/Makefile
+++ b/drivers/net/ionic/Makefile
@@ -20,6 +20,6 @@ LDLIBS += -lrte_bus_pci
 #
 # all source are stored in SRCS-y
 #
-SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) +=
+SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_ethdev.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
new file mode 100644
index 0..f19de85a9
--- /dev/null
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
+ */
+
+#include "ionic_logs.h"
+
+int ionic_logtype;
+
+RTE_INIT(ionic_init_log)
+{
+   ionic_logtype = rte_log_register("pmd.net.ionic");
+
+   if (ionic_logtype >= 0)
+   rte_log_set_level(ionic_logtype, RTE_LOG_NOTICE);
+}
diff --git a/drivers/net/ionic/ionic_logs.h b/drivers/net/ionic/ionic_logs.h
new file mode 100644
index 0..bc10ad174
--- /dev/null
+++ b/drivers/net/ionic/ionic_logs.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
+ */
+
+#ifndef _IONIC_LOGS_H_
+#define _IONIC_LOGS_H_
+
+#include 
+
+extern int ionic_logtype;
+
+#define IONIC_PRINT(level, fmt, args...) rte_log(RTE_LOG_ ## level, \
+   ionic_logtype, "%s(): " fmt "\n", __func__, ##args)
+
+#define IONIC_PRINT_CALL() IONIC_PRINT(DEBUG, " >>")
+
+#ifndef IONIC_WARN_ON
+#define IONIC_WARN_ON(x) do { \
+   int ret = !!(x); \
+   if (unlikely(ret)) \
+   IONIC_PRINT(WARNING, "WARN_ON: \"" #x "\" at %s:%d\n", \
+   __func__, __LINE__); \
+} while (0)
+#endif
+
+#endif /* _IONIC_LOGS_H_ */
diff --git a/drivers/net/ionic/meson.build b/drivers/net/ionic/meson.build
index 5386e23ca..f5e3c36c9 100644
--- a/drivers/net/ionic/meson.build
+++ b/drivers/net/ionic/meson.build
@@ -2,5 +2,6 @@
 # Copyright(c) 2019 Pensando
 
 sources = files(
+   'ionic_ethdev.c'
 )
 
-- 
2.17.1

[dpdk-dev] [PATCH v4 09/17] net/ionic: add notifyq support

[Alfredo Cardigliano]

Add support for the notify queue, which is used for events
published by the NIC.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 drivers/net/ionic/ionic.h|   2 +
 drivers/net/ionic/ionic_ethdev.c |  97 +++
 drivers/net/ionic/ionic_lif.c| 196 ++-
 drivers/net/ionic/ionic_lif.h|   7 ++
 4 files changed, 301 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h
index 7defb5fe0..e7c8ad34b 100644
--- a/drivers/net/ionic/ionic.h
+++ b/drivers/net/ionic/ionic.h
@@ -54,9 +54,11 @@ struct ionic_adapter {
uint32_t nlifs;
uint32_t max_ntxqs_per_lif;
uint32_t max_nrxqs_per_lif;
+   uint32_t link_speed;
uint32_t nintrs;
bool intrs[IONIC_INTR_CTRL_REGS_MAX];
bool is_mgmt_nic;
+   bool link_up;
struct rte_pci_device *pci_dev;
LIST_ENTRY(ionic_adapter) pci_adapters;
 };
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index 7f3645665..01027f0d1 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -31,6 +31,30 @@ static const struct rte_pci_id pci_id_ionic_map[] = {
 static const struct eth_dev_ops ionic_eth_dev_ops = {
 };
 
+/**
+ * Interrupt handler triggered by NIC for handling
+ * specific interrupt.
+ *
+ * @param param
+ *  The address of parameter regsitered before.
+ *
+ * @return
+ *  void
+ */
+static void
+ionic_dev_interrupt_handler(void *param)
+{
+   struct ionic_adapter *adapter = (struct ionic_adapter *)param;
+   uint32_t i;
+
+   IONIC_PRINT(DEBUG, "->");
+
+   for (i = 0; i < adapter->nlifs; i++) {
+   if (adapter->lifs[i])
+   ionic_notifyq_handler(adapter->lifs[i], -1);
+   }
+}
+
 static int
 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params)
 {
@@ -100,6 +124,70 @@ eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev)
return 0;
 }
 
+static int
+ionic_configure_intr(struct ionic_adapter *adapter)
+{
+   struct rte_pci_device *pci_dev = adapter->pci_dev;
+   struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+   int err;
+
+   IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs);
+
+   if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) {
+   IONIC_PRINT(ERR, "Fail to create eventfd");
+   return -1;
+   }
+
+   if (rte_intr_dp_is_en(intr_handle))
+   IONIC_PRINT(DEBUG,
+   "Packet I/O interrupt on datapath is enabled");
+
+   if (!intr_handle->intr_vec) {
+   intr_handle->intr_vec = rte_zmalloc("intr_vec",
+   adapter->nintrs * sizeof(int), 0);
+
+   if (!intr_handle->intr_vec) {
+   IONIC_PRINT(ERR, "Failed to allocate %u vectors",
+   adapter->nintrs);
+   return -ENOMEM;
+   }
+   }
+
+   err = rte_intr_callback_register(intr_handle,
+   ionic_dev_interrupt_handler,
+   adapter);
+
+   if (err) {
+   IONIC_PRINT(ERR,
+   "Failure registering interrupts handler (%d)",
+   err);
+   return err;
+   }
+
+   /* enable intr mapping */
+   err = rte_intr_enable(intr_handle);
+
+   if (err) {
+   IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err);
+   return err;
+   }
+
+   return 0;
+}
+
+static void
+ionic_unconfigure_intr(struct ionic_adapter *adapter)
+{
+   struct rte_pci_device *pci_dev = adapter->pci_dev;
+   struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+
+   rte_intr_disable(intr_handle);
+
+   rte_intr_callback_unregister(intr_handle,
+   ionic_dev_interrupt_handler,
+   adapter);
+}
+
 static int
 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
struct rte_pci_device *pci_dev)
@@ -229,6 +317,13 @@ eth_ionic_pci_probe(struct rte_pci_driver *pci_drv 
__rte_unused,
adapter->nlifs++;
}
 
+   err = ionic_configure_intr(adapter);
+
+   if (err) {
+   IONIC_PRINT(ERR, "Failed to configure interrupts");
+   goto err_free_adapter;
+   }
+
return 0;
 
 err_free_adapter:
@@ -258,6 +353,8 @@ eth_ionic_pci_remove(struct rte_pci_device *pci_dev)
}
 
if (adapter) {
+   ionic_unconfigure_intr(adapter);
+
for (i = 0; i < adapter->nlifs; i++) {
lif = adapter->lifs[i];
rte_eth_dev_destroy(lif->eth_dev, eth_ionic_dev_uninit);
diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c
index 8425881b7..ae45e76db 100644
--- a/drivers/net/ionic/ionic_lif.c
+++ b/drivers/net/ionic/ionic_lif.c
@@ -29,7 +29,7 @@ ionic_qcq_enable(struct ionic_qcq *qcq)
 

[dpdk-dev] [PATCH v4 06/17] net/ionic: add basic lif support

[Alfredo Cardigliano]

Initialize LIFs (Logical Interfaces) which represents
external connections. The NIC can multiplex many LIFs
to a single port, but in most setups, LIF0 is the
primary control for the port.
Create a device for each LIF.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 drivers/net/ionic/Makefile   |   4 +
 drivers/net/ionic/ionic.h|   5 ++
 drivers/net/ionic/ionic_dev.c|  38 
 drivers/net/ionic/ionic_dev.h|   8 ++
 drivers/net/ionic/ionic_ethdev.c | 140 +
 drivers/net/ionic/ionic_ethdev.h |  14 +++
 drivers/net/ionic/ionic_lif.c| 145 +++
 drivers/net/ionic/ionic_lif.h|  48 ++
 drivers/net/ionic/meson.build|   4 +-
 9 files changed, 404 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/ionic/ionic_ethdev.h
 create mode 100644 drivers/net/ionic/ionic_lif.c
 create mode 100644 drivers/net/ionic/ionic_lif.h

diff --git a/drivers/net/ionic/Makefile b/drivers/net/ionic/Makefile
index 31abe5b95..2dc88cdd5 100644
--- a/drivers/net/ionic/Makefile
+++ b/drivers/net/ionic/Makefile
@@ -8,6 +8,9 @@ include $(RTE_SDK)/mk/rte.vars.mk
 #
 LIB = librte_pmd_ionic.a
 
+# Required to use rte_eth_dev_create and rte_eth_dev_destroy
+CFLAGS += -DALLOW_EXPERIMENTAL_API
+
 CFLAGS += -O3
 CFLAGS += $(WERROR_FLAGS)
 
@@ -23,6 +26,7 @@ LDLIBS += -lrte_bus_pci
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_mac_api.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_dev.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_ethdev.c
+SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_lif.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_main.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h
index a29f0bb89..b6ef63161 100644
--- a/drivers/net/ionic/ionic.h
+++ b/drivers/net/ionic/ionic.h
@@ -49,7 +49,12 @@ struct ionic_adapter {
struct ionic_dev idev;
struct ionic_dev_bar bars[IONIC_BARS_MAX];
struct ionic_identity   ident;
+   struct ionic_lif *lifs[IONIC_LIFS_MAX];
uint32_t num_bars;
+   uint32_t nlifs;
+   uint32_t max_ntxqs_per_lif;
+   uint32_t max_nrxqs_per_lif;
+   uint32_t nintrs;
bool is_mgmt_nic;
struct rte_pci_device *pci_dev;
LIST_ENTRY(ionic_adapter) pci_adapters;
diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c
index d74834122..c63709ee8 100644
--- a/drivers/net/ionic/ionic_dev.c
+++ b/drivers/net/ionic/ionic_dev.c
@@ -259,3 +259,41 @@ ionic_dev_cmd_port_loopback(struct ionic_dev *idev, 
uint8_t loopback_mode)
 
ionic_dev_cmd_go(idev, &cmd);
 }
+
+/* LIF commands */
+
+void
+ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver)
+{
+   union ionic_dev_cmd cmd = {
+   .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
+   .lif_identify.type = type,
+   .lif_identify.ver = ver,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_lif_init(struct ionic_dev *idev, uint16_t lif_index,
+  rte_iova_t info_pa)
+{
+   union ionic_dev_cmd cmd = {
+   .lif_init.opcode = IONIC_CMD_LIF_INIT,
+   .lif_init.index = lif_index,
+   .lif_init.info_pa = info_pa,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+void
+ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t lif_index)
+{
+   union ionic_dev_cmd cmd = {
+   .lif_init.opcode = IONIC_CMD_LIF_RESET,
+   .lif_init.index = lif_index,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h
index 75c50d4cb..afcfcbf56 100644
--- a/drivers/net/ionic/ionic_dev.h
+++ b/drivers/net/ionic/ionic_dev.h
@@ -9,6 +9,8 @@
 #include "ionic_if.h"
 #include "ionic_regs.h"
 
+#define IONIC_LIFS_MAX 1024
+
 #define IONIC_DEVCMD_TIMEOUT   30 /* devcmd_timeout */
 #defineIONIC_ALIGN 4096
 
@@ -142,4 +144,10 @@ void ionic_dev_cmd_port_pause(struct ionic_dev *idev, 
uint8_t pause_type);
 void ionic_dev_cmd_port_loopback(struct ionic_dev *idev,
uint8_t loopback_mode);
 
+void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type,
+   uint8_t ver);
+void ionic_dev_cmd_lif_init(struct ionic_dev *idev, uint16_t lif_index,
+   rte_iova_t addr);
+void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t lif_index);
+
 #endif /* _IONIC_DEV_H_ */
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index cbb70125b..7f3645665 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -7,11 +7,17 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ionic_logs.h"
 #include "ionic.h"
 #include "ionic_dev.h"
 #include "ionic_mac_api.h"
+#include "ionic_lif.h"
+#include "ionic_ethdev.h"
+
+static int  eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
+

[dpdk-dev] [PATCH v4 04/17] net/ionic: register and initialize the adapter

[Alfredo Cardigliano]

Register the Pensando ionic PMD (net_ionic) and define initial probe
and remove callbacks with adapter initialization.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 doc/guides/nics/features/ionic.ini |   2 +
 drivers/net/ionic/Makefile |   3 +
 drivers/net/ionic/ionic.h  |  63 +
 drivers/net/ionic/ionic_dev.c  | 134 +++
 drivers/net/ionic/ionic_dev.h  | 127 ++
 drivers/net/ionic/ionic_ethdev.c   | 118 
 drivers/net/ionic/ionic_mac_api.c  |  61 +
 drivers/net/ionic/ionic_mac_api.h  |  13 +++
 drivers/net/ionic/ionic_main.c | 133 +++
 drivers/net/ionic/ionic_osdep.h|  79 
 drivers/net/ionic/ionic_regs.h | 142 +
 drivers/net/ionic/meson.build  |   4 +
 12 files changed, 879 insertions(+)
 create mode 100644 drivers/net/ionic/ionic.h
 create mode 100644 drivers/net/ionic/ionic_dev.c
 create mode 100644 drivers/net/ionic/ionic_dev.h
 create mode 100644 drivers/net/ionic/ionic_mac_api.c
 create mode 100644 drivers/net/ionic/ionic_mac_api.h
 create mode 100644 drivers/net/ionic/ionic_main.c
 create mode 100644 drivers/net/ionic/ionic_osdep.h
 create mode 100644 drivers/net/ionic/ionic_regs.h

diff --git a/doc/guides/nics/features/ionic.ini 
b/doc/guides/nics/features/ionic.ini
index 3a92eedc7..6915d9c42 100644
--- a/doc/guides/nics/features/ionic.ini
+++ b/doc/guides/nics/features/ionic.ini
@@ -4,5 +4,7 @@
 ; Refer to default.ini for the full list of available PMD features.
 ;
 [Features]
+Linux UIO= Y
+Linux VFIO   = Y
 x86-64   = Y
 Usage doc= Y
diff --git a/drivers/net/ionic/Makefile b/drivers/net/ionic/Makefile
index baa34b055..31abe5b95 100644
--- a/drivers/net/ionic/Makefile
+++ b/drivers/net/ionic/Makefile
@@ -20,6 +20,9 @@ LDLIBS += -lrte_bus_pci
 #
 # all source are stored in SRCS-y
 #
+SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_mac_api.c
+SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_dev.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_ethdev.c
+SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_main.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h
new file mode 100644
index 0..5c869e698
--- /dev/null
+++ b/drivers/net/ionic/ionic.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
+ */
+
+#ifndef _IONIC_H_
+#define _IONIC_H_
+
+#include 
+
+#include "ionic_dev.h"
+#include "ionic_if.h"
+#include "ionic_osdep.h"
+
+#define IONIC_DRV_NAME "ionic"
+#define IONIC_DRV_DESCRIPTION  "Pensando Ethernet NIC Driver"
+#define IONIC_DRV_VERSION  "0.11.0-49"
+
+/* Vendor ID */
+#define IONIC_PENSANDO_VENDOR_ID   0x1dd8
+
+/* Device IDs */
+#define IONIC_DEV_ID_ETH_PF0x1002
+#define IONIC_DEV_ID_ETH_VF0x1003
+#define IONIC_DEV_ID_ETH_MGMT  0x1004
+
+enum ionic_mac_type {
+   IONIC_MAC_UNKNOWN = 0,
+   IONIC_MAC_CAPRI,
+   IONIC_NUM_MACS
+};
+
+struct ionic_mac_info {
+   enum ionic_mac_type type;
+};
+
+struct ionic_hw {
+   struct ionic_mac_info mac;
+   uint16_t device_id;
+   uint16_t vendor_id;
+};
+
+/*
+ * Structure to store private data for each driver instance (for each adapter).
+ */
+struct ionic_adapter {
+   struct ionic_hw hw;
+   struct ionic_dev idev;
+   struct ionic_dev_bar bars[IONIC_BARS_MAX];
+   struct ionic_identity   ident;
+   uint32_t num_bars;
+   bool is_mgmt_nic;
+   struct rte_pci_device *pci_dev;
+   LIST_ENTRY(ionic_adapter) pci_adapters;
+};
+
+int ionic_dev_cmd_wait_check(struct ionic_dev *idev, unsigned long max_wait);
+int ionic_setup(struct ionic_adapter *adapter);
+
+int ionic_identify(struct ionic_adapter *adapter);
+int ionic_init(struct ionic_adapter *adapter);
+int ionic_reset(struct ionic_adapter *adapter);
+
+#endif /* _IONIC_H_ */
diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c
new file mode 100644
index 0..a8ad5358f
--- /dev/null
+++ b/drivers/net/ionic/ionic_dev.c
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
+ */
+
+#include 
+
+#include "ionic_dev.h"
+#include "ionic.h"
+
+int
+ionic_dev_setup(struct ionic_adapter *adapter)
+{
+   struct ionic_dev_bar *bar = adapter->bars;
+   unsigned int num_bars = adapter->num_bars;
+   struct ionic_dev *idev = &adapter->idev;
+   uint32_t sig;
+   u_char *bar0_base;
+
+   /* BAR0: dev_cmd and interrupts */
+   if (num_bars < 1) {
+   IONIC_PRINT(ERR, "No bars found, aborting");
+   return -EFAULT;
+   }
+
+   if (bar->len < IONIC_BAR0_SIZE) {
+   IONIC_PRINT(ERR,
+ 

[dpdk-dev] [PATCH v4 07/17] net/ionic: add doorbells

[Alfredo Cardigliano]

Doorbell registers are used by the driver to signal to the NIC
that requests are waiting on the message queues.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 drivers/net/ionic/ionic_dev.c | 15 +++
 drivers/net/ionic/ionic_dev.h | 19 +++
 drivers/net/ionic/ionic_lif.c | 24 
 drivers/net/ionic/ionic_lif.h |  4 +++-
 4 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c
index c63709ee8..13e99ace6 100644
--- a/drivers/net/ionic/ionic_dev.c
+++ b/drivers/net/ionic/ionic_dev.c
@@ -5,6 +5,7 @@
 #include 
 
 #include "ionic_dev.h"
+#include "ionic_lif.h"
 #include "ionic.h"
 
 int
@@ -297,3 +298,17 @@ ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t 
lif_index)
 
ionic_dev_cmd_go(idev, &cmd);
 }
+
+int
+ionic_db_page_num(struct ionic_lif *lif, int pid)
+{
+   return (lif->index * 0) + pid;
+}
+
+void
+ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
+   unsigned long index)
+{
+   ionic_intr_clean(idev->intr_ctrl, index);
+   intr->index = index;
+}
diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h
index afcfcbf56..ca9807a9b 100644
--- a/drivers/net/ionic/ionic_dev.h
+++ b/drivers/net/ionic/ionic_dev.h
@@ -121,6 +121,23 @@ struct ionic_dev {
uint32_t port_info_sz;
 };
 
+#define IONIC_INTR_INDEX_NOT_ASSIGNED  (-1)
+#define IONIC_INTR_NAME_MAX_SZ (32)
+
+struct ionic_intr_info {
+   char name[IONIC_INTR_NAME_MAX_SZ];
+   int index;
+   uint32_t vector;
+   struct ionic_intr __iomem *ctrl;
+   uint64_t rearm_count;
+};
+
+struct ionic_lif;
+struct ionic_adapter;
+
+void ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
+   unsigned long index);
+
 int ionic_dev_setup(struct ionic_adapter *adapter);
 
 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);
@@ -150,4 +167,6 @@ void ionic_dev_cmd_lif_init(struct ionic_dev *idev, 
uint16_t lif_index,
rte_iova_t addr);
 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t lif_index);
 
+int ionic_db_page_num(struct ionic_lif *lif, int pid);
+
 #endif /* _IONIC_DEV_H_ */
diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c
index 0728738e7..75085b0fc 100644
--- a/drivers/net/ionic/ionic_lif.c
+++ b/drivers/net/ionic/ionic_lif.c
@@ -10,15 +10,39 @@
 #include "ionic_lif.h"
 #include "ionic_ethdev.h"
 
+static void *
+ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
+{
+   char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
+
+   if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
+   return NULL;
+
+   return (void *)&vaddr[page_num << PAGE_SHIFT];
+}
+
 int
 ionic_lif_alloc(struct ionic_lif *lif)
 {
+   struct ionic_adapter *adapter = lif->adapter;
uint32_t socket_id = rte_socket_id();
+   int dbpage_num;
 
snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
 
IONIC_PRINT(DEBUG, "Allocating Lif Info");
 
+   lif->kern_pid = 0;
+
+   dbpage_num = ionic_db_page_num(lif, 0);
+
+   lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
+
+   if (!lif->kern_dbpage) {
+   IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
+   return -ENOMEM;
+   }
+
lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
 
lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
diff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h
index 49bceaccf..6e3233d1d 100644
--- a/drivers/net/ionic/ionic_lif.h
+++ b/drivers/net/ionic/ionic_lif.h
@@ -23,8 +23,10 @@ struct ionic_lif {
uint16_t port_id;  /**< Device port identifier */
uint32_t index;
uint32_t hw_index;
-   char name[IONIC_LIF_NAME_MAX_SZ];
uint32_t state;
+   uint32_t kern_pid;
+   struct ionic_doorbell __iomem *kern_dbpage;
+   char name[IONIC_LIF_NAME_MAX_SZ];
uint32_t info_sz;
struct ionic_lif_info *info;
rte_iova_t info_pa;
-- 
2.17.1

[dpdk-dev] [PATCH v4 08/17] net/ionic: add adminq support

[Alfredo Cardigliano]

Add support for the admin queue, which is used for most
of the NIC configurations.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 drivers/net/ionic/ionic.h  |   3 +
 drivers/net/ionic/ionic_dev.c  | 255 +++
 drivers/net/ionic/ionic_dev.h  |  95 -
 drivers/net/ionic/ionic_lif.c  | 356 +
 drivers/net/ionic/ionic_lif.h  |  36 
 drivers/net/ionic/ionic_main.c | 186 +
 6 files changed, 930 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h
index b6ef63161..7defb5fe0 100644
--- a/drivers/net/ionic/ionic.h
+++ b/drivers/net/ionic/ionic.h
@@ -55,11 +55,14 @@ struct ionic_adapter {
uint32_t max_ntxqs_per_lif;
uint32_t max_nrxqs_per_lif;
uint32_t nintrs;
+   bool intrs[IONIC_INTR_CTRL_REGS_MAX];
bool is_mgmt_nic;
struct rte_pci_device *pci_dev;
LIST_ENTRY(ionic_adapter) pci_adapters;
 };
 
+int ionic_adminq_check_err(struct ionic_admin_ctx *ctx, bool timeout);
+int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx);
 int ionic_dev_cmd_wait_check(struct ionic_dev *idev, unsigned long max_wait);
 int ionic_setup(struct ionic_adapter *adapter);
 
diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c
index 13e99ace6..e2cd15792 100644
--- a/drivers/net/ionic/ionic_dev.c
+++ b/drivers/net/ionic/ionic_dev.c
@@ -299,6 +299,12 @@ ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t 
lif_index)
ionic_dev_cmd_go(idev, &cmd);
 }
 
+struct ionic_doorbell *
+ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q)
+{
+   return lif->kern_dbpage + q->hw_type;
+}
+
 int
 ionic_db_page_num(struct ionic_lif *lif, int pid)
 {
@@ -312,3 +318,252 @@ ionic_intr_init(struct ionic_dev *idev, struct 
ionic_intr_info *intr,
ionic_intr_clean(idev->intr_ctrl, index);
intr->index = index;
 }
+
+void
+ionic_dev_cmd_adminq_init(struct ionic_dev *idev,
+   struct ionic_qcq *qcq,
+   uint16_t lif_index, uint16_t intr_index)
+{
+   struct ionic_queue *q = &qcq->q;
+   struct ionic_cq *cq = &qcq->cq;
+
+   union ionic_dev_cmd cmd = {
+   .q_init.opcode = IONIC_CMD_Q_INIT,
+   .q_init.lif_index = lif_index,
+   .q_init.type = q->type,
+   .q_init.index = q->index,
+   .q_init.flags = IONIC_QINIT_F_ENA,
+   .q_init.pid = q->pid,
+   .q_init.intr_index = intr_index,
+   .q_init.ring_size = ilog2(q->num_descs),
+   .q_init.ring_base = q->base_pa,
+   .q_init.cq_ring_base = cq->base_pa,
+   };
+
+   ionic_dev_cmd_go(idev, &cmd);
+}
+
+int
+ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
+   struct ionic_intr_info *intr,
+   uint32_t num_descs, size_t desc_size)
+{
+   if (desc_size == 0) {
+   IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size);
+   return -EINVAL;
+   }
+
+   if (!rte_is_power_of_2(num_descs) ||
+   num_descs < IONIC_MIN_RING_DESC ||
+   num_descs > IONIC_MAX_RING_DESC) {
+   IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)",
+   num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC);
+   return -EINVAL;
+   }
+
+   cq->lif = lif;
+   cq->bound_intr = intr;
+   cq->num_descs = num_descs;
+   cq->desc_size = desc_size;
+   cq->tail_idx = 0;
+   cq->done_color = 1;
+
+   return 0;
+}
+
+void
+ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa)
+{
+   cq->base = base;
+   cq->base_pa = base_pa;
+}
+
+void
+ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
+{
+   cq->bound_q = q;
+   q->bound_cq = cq;
+}
+
+uint32_t
+ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
+ionic_cq_cb cb, void *cb_arg)
+{
+   uint32_t work_done = 0;
+
+   if (work_to_do == 0)
+   return 0;
+
+   while (cb(cq, cq->tail_idx, cb_arg)) {
+   cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
+   if (cq->tail_idx == 0)
+   cq->done_color = !cq->done_color;
+
+   if (++work_done == work_to_do)
+   break;
+   }
+
+   return work_done;
+}
+
+int
+ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
+struct ionic_queue *q, uint32_t index, uint32_t num_descs,
+size_t desc_size, size_t sg_desc_size, uint32_t pid)
+{
+   uint32_t ring_size;
+
+   if (desc_size == 0 || !rte_is_power_of_2(num_descs))
+   return -EINVAL;
+
+   ring_size = ilog2(num_descs);
+
+   if (ring_size < 2 || ring_size > 16)
+   return -EINVAL;
+
+   q->lif = lif;
+   q->idev = idev;
+   q->index = index;
+   q->num_descs = num_descs;
+   q-

[dpdk-dev] [PATCH v4 10/17] net/ionic: add basic port operations

[Alfredo Cardigliano]

Add support for port start/stop and handle basic features
including mtu and link up/down.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 doc/guides/nics/features/ionic.ini |   4 +
 drivers/net/ionic/ionic.h  |   1 +
 drivers/net/ionic/ionic_dev.h  |   3 +
 drivers/net/ionic/ionic_ethdev.c   | 327 +
 drivers/net/ionic/ionic_lif.c  | 270 
 drivers/net/ionic/ionic_lif.h  |  10 +
 6 files changed, 615 insertions(+)

diff --git a/doc/guides/nics/features/ionic.ini 
b/doc/guides/nics/features/ionic.ini
index 6915d9c42..c69e5cbed 100644
--- a/doc/guides/nics/features/ionic.ini
+++ b/doc/guides/nics/features/ionic.ini
@@ -4,6 +4,10 @@
 ; Refer to default.ini for the full list of available PMD features.
 ;
 [Features]
+Speed capabilities   = Y
+Link status  = Y
+Link status event= Y
+MTU update   = Y
 Linux UIO= Y
 Linux VFIO   = Y
 x86-64   = Y
diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h
index e7c8ad34b..ae4f6acc7 100644
--- a/drivers/net/ionic/ionic.h
+++ b/drivers/net/ionic/ionic.h
@@ -54,6 +54,7 @@ struct ionic_adapter {
uint32_t nlifs;
uint32_t max_ntxqs_per_lif;
uint32_t max_nrxqs_per_lif;
+   uint32_t max_mac_addrs;
uint32_t link_speed;
uint32_t nintrs;
bool intrs[IONIC_INTR_CTRL_REGS_MAX];
diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h
index a832ff405..61576621b 100644
--- a/drivers/net/ionic/ionic_dev.h
+++ b/drivers/net/ionic/ionic_dev.h
@@ -9,6 +9,9 @@
 #include "ionic_if.h"
 #include "ionic_regs.h"
 
+#define IONIC_MIN_MTU  RTE_ETHER_MIN_MTU
+#define IONIC_MAX_MTU  9194
+
 #define IONIC_MAX_RING_DESC32768
 #define IONIC_MIN_RING_DESC16
 
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index 01027f0d1..3f9988acc 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -18,6 +18,17 @@
 
 static int  eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 static int  eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev);
+static int  ionic_dev_info_get(struct rte_eth_dev *eth_dev,
+   struct rte_eth_dev_info *dev_info);
+static int  ionic_dev_configure(struct rte_eth_dev *dev);
+static int  ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
+static int  ionic_dev_start(struct rte_eth_dev *dev);
+static void ionic_dev_stop(struct rte_eth_dev *dev);
+static void ionic_dev_close(struct rte_eth_dev *dev);
+static int  ionic_dev_set_link_up(struct rte_eth_dev *dev);
+static int  ionic_dev_set_link_down(struct rte_eth_dev *dev);
+static int  ionic_dev_link_update(struct rte_eth_dev *eth_dev,
+   int wait_to_complete);
 
 int ionic_logtype;
 
@@ -29,8 +40,115 @@ static const struct rte_pci_id pci_id_ionic_map[] = {
 };
 
 static const struct eth_dev_ops ionic_eth_dev_ops = {
+   .dev_infos_get  = ionic_dev_info_get,
+   .dev_configure  = ionic_dev_configure,
+   .mtu_set= ionic_dev_mtu_set,
+   .dev_start  = ionic_dev_start,
+   .dev_stop   = ionic_dev_stop,
+   .dev_close  = ionic_dev_close,
+   .link_update= ionic_dev_link_update,
+   .dev_set_link_up= ionic_dev_set_link_up,
+   .dev_set_link_down  = ionic_dev_set_link_down,
 };
 
+/*
+ * Set device link up, enable tx.
+ */
+static int
+ionic_dev_set_link_up(struct rte_eth_dev *eth_dev)
+{
+   struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+   struct ionic_adapter *adapter = lif->adapter;
+   struct ionic_dev *idev = &adapter->idev;
+   int err;
+
+   IONIC_PRINT_CALL();
+
+   ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_UP);
+
+   err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
+
+   if (err) {
+   IONIC_PRINT(WARNING, "Failed to bring port UP");
+   return err;
+   }
+
+   return 0;
+}
+
+/*
+ * Set device link down, disable tx.
+ */
+static int
+ionic_dev_set_link_down(struct rte_eth_dev *eth_dev)
+{
+   struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+   struct ionic_adapter *adapter = lif->adapter;
+   struct ionic_dev *idev = &adapter->idev;
+   int err;
+
+   IONIC_PRINT_CALL();
+
+   ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_DOWN);
+
+   err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
+
+   if (err) {
+   IONIC_PRINT(WARNING, "Failed to bring port DOWN");
+   return err;
+   }
+
+   return 0;
+}
+
+static int
+ionic_dev_link_update(struct rte_eth_dev *eth_dev,
+   int wait_to_complete __rte_unused)
+{
+   struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+   struct ionic_adapter *adapter = lif->adapter;
+   struct rte_eth_link 

[dpdk-dev] [PATCH v4 12/17] net/ionic: add Flow Control support

[Alfredo Cardigliano]

Add support for managing Flow Control.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 doc/guides/nics/features/ionic.ini |  1 +
 drivers/net/ionic/ionic_ethdev.c   | 56 ++
 2 files changed, 57 insertions(+)

diff --git a/doc/guides/nics/features/ionic.ini 
b/doc/guides/nics/features/ionic.ini
index 3dd5dab45..05bdb2d98 100644
--- a/doc/guides/nics/features/ionic.ini
+++ b/doc/guides/nics/features/ionic.ini
@@ -12,6 +12,7 @@ Promiscuous mode = Y
 Allmulticast mode= Y
 Unicast MAC filter   = Y
 VLAN filter  = Y
+Flow control = Y
 Linux UIO= Y
 Linux VFIO   = Y
 x86-64   = Y
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index dbeb737fd..ba1d1de16 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -29,6 +29,10 @@ static int  ionic_dev_set_link_up(struct rte_eth_dev *dev);
 static int  ionic_dev_set_link_down(struct rte_eth_dev *dev);
 static int  ionic_dev_link_update(struct rte_eth_dev *eth_dev,
int wait_to_complete);
+static int  ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
+   struct rte_eth_fc_conf *fc_conf);
+static int  ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev,
+   struct rte_eth_fc_conf *fc_conf);
 
 int ionic_logtype;
 
@@ -57,6 +61,8 @@ static const struct eth_dev_ops ionic_eth_dev_ops = {
.promiscuous_disable= ionic_dev_promiscuous_disable,
.allmulticast_enable= ionic_dev_allmulticast_enable,
.allmulticast_disable   = ionic_dev_allmulticast_disable,
+   .flow_ctrl_get  = ionic_flow_ctrl_get,
+   .flow_ctrl_set  = ionic_flow_ctrl_set,
 };
 
 /*
@@ -243,6 +249,56 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev,
return 0;
 }
 
+static int
+ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
+   struct rte_eth_fc_conf *fc_conf)
+{
+   struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+   struct ionic_adapter *adapter = lif->adapter;
+   struct ionic_dev *idev = &adapter->idev;
+
+   if (idev->port_info) {
+   fc_conf->autoneg = idev->port_info->config.an_enable;
+
+   if (idev->port_info->config.pause_type)
+   fc_conf->mode = RTE_FC_FULL;
+   else
+   fc_conf->mode = RTE_FC_NONE;
+   }
+
+   return 0;
+}
+
+static int
+ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev,
+   struct rte_eth_fc_conf *fc_conf)
+{
+   struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+   struct ionic_adapter *adapter = lif->adapter;
+   struct ionic_dev *idev = &adapter->idev;
+   uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE;
+   uint8_t an_enable;
+
+   switch (fc_conf->mode) {
+   case RTE_FC_NONE:
+   pause_type = IONIC_PORT_PAUSE_TYPE_NONE;
+   break;
+   case RTE_FC_FULL:
+   pause_type = IONIC_PORT_PAUSE_TYPE_LINK;
+   break;
+   case RTE_FC_RX_PAUSE:
+   case RTE_FC_TX_PAUSE:
+   return -ENOTSUP;
+   }
+
+   an_enable = fc_conf->autoneg;
+
+   ionic_dev_cmd_port_pause(idev, pause_type);
+   ionic_dev_cmd_port_autoneg(idev, an_enable);
+
+   return 0;
+}
+
 static int
 ionic_dev_configure(struct rte_eth_dev *eth_dev)
 {
-- 
2.17.1

[dpdk-dev] [PATCH v4 14/17] net/ionic: add RSS support

[Alfredo Cardigliano]

Add code to manipulate the RSS configuration
used by the adapter.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 doc/guides/nics/features/ionic.ini |   3 +
 drivers/net/ionic/ionic_ethdev.c   | 175 +
 drivers/net/ionic/ionic_ethdev.h   |   8 ++
 drivers/net/ionic/ionic_lif.c  | 120 +++-
 drivers/net/ionic/ionic_lif.h  |  16 +++
 drivers/net/ionic/ionic_rxtx.c |   4 +
 6 files changed, 324 insertions(+), 2 deletions(-)

diff --git a/doc/guides/nics/features/ionic.ini 
b/doc/guides/nics/features/ionic.ini
index 8fde998c1..9a155251c 100644
--- a/doc/guides/nics/features/ionic.ini
+++ b/doc/guides/nics/features/ionic.ini
@@ -16,6 +16,9 @@ TSO  = Y
 Promiscuous mode = Y
 Allmulticast mode= Y
 Unicast MAC filter   = Y
+RSS hash = Y
+RSS key update   = Y
+RSS reta update  = Y
 VLAN filter  = Y
 VLAN offload = Y
 Flow control = Y
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index e49531d21..121404a1f 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -35,6 +35,14 @@ static int  ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 static int  ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev,
struct rte_eth_fc_conf *fc_conf);
 static int  ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
+static int  ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,
+   struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size);
+static int  ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev,
+   struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size);
+static int  ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
+   struct rte_eth_rss_conf *rss_conf);
+static int  ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev,
+   struct rte_eth_rss_conf *rss_conf);
 
 int ionic_logtype;
 
@@ -90,6 +98,10 @@ static const struct eth_dev_ops ionic_eth_dev_ops = {
.tx_queue_start = ionic_dev_tx_queue_start,
.tx_queue_stop  = ionic_dev_tx_queue_stop,
.vlan_offload_set   = ionic_vlan_offload_set,
+   .reta_update= ionic_dev_rss_reta_update,
+   .reta_query = ionic_dev_rss_reta_query,
+   .rss_hash_conf_get  = ionic_dev_rss_hash_conf_get,
+   .rss_hash_update= ionic_dev_rss_hash_update,
 };
 
 /*
@@ -266,6 +278,10 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev,
dev_info->min_mtu = IONIC_MIN_MTU;
dev_info->max_mtu = IONIC_MAX_MTU;
 
+   dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE;
+   dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz;
+   dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL;
+
dev_info->speed_capa =
ETH_LINK_SPEED_10G |
ETH_LINK_SPEED_25G |
@@ -408,6 +424,165 @@ ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int 
mask)
return 0;
 }
 
+static int
+ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,
+   struct rte_eth_rss_reta_entry64 *reta_conf,
+   uint16_t reta_size)
+{
+   struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+   struct ionic_adapter *adapter = lif->adapter;
+   struct ionic_identity *ident = &adapter->ident;
+   uint32_t i, j, index, num;
+
+   IONIC_PRINT_CALL();
+
+   if (!lif->rss_ind_tbl) {
+   IONIC_PRINT(ERR, "RSS RETA not initialized, "
+   "can't update the table");
+   return -EINVAL;
+   }
+
+   if (reta_size != ident->lif.eth.rss_ind_tbl_sz) {
+   IONIC_PRINT(ERR, "The size of hash lookup table configured "
+   "(%d) doesn't match the number hardware can supported "
+   "(%d)",
+   reta_size, ident->lif.eth.rss_ind_tbl_sz);
+   return -EINVAL;
+   }
+
+   num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE;
+
+   for (i = 0; i < num; i++) {
+   for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) {
+   if (reta_conf[i].mask & ((uint64_t)1 << j)) {
+   index = (i * RTE_RETA_GROUP_SIZE) + j;
+   lif->rss_ind_tbl[index] = reta_conf[i].reta[j];
+   }
+   }
+   }
+
+   return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
+}
+
+static int
+ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev,
+   struct rte_eth_rss_reta_entry64 *reta_conf,
+   uint16_t reta_size)
+{
+   struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+   struct ionic_adapter *adapter = lif->adapter;
+   struct ionic_identity *ident = &adapter->ident;
+   int i, num;
+
+   IONIC_PRINT_CALL();
+
+   if (reta_size != ident->lif.eth.rss_ind_tbl_sz) {
+   IONIC_PRINT(ERR,

[dpdk-dev] [PATCH v4 13/17] net/ionic: add RX and TX handling

[Alfredo Cardigliano]

Add RX and TX queues setup and handling.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 doc/guides/nics/features/ionic.ini |  10 +
 drivers/net/ionic/Makefile |   1 +
 drivers/net/ionic/ionic_dev.h  |   1 +
 drivers/net/ionic/ionic_ethdev.c   | 115 
 drivers/net/ionic/ionic_lif.c  | 222 ++-
 drivers/net/ionic/ionic_lif.h  |  44 ++
 drivers/net/ionic/ionic_rxtx.c | 999 +
 drivers/net/ionic/ionic_rxtx.h |  44 ++
 drivers/net/ionic/meson.build  |   1 +
 9 files changed, 1436 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/ionic/ionic_rxtx.c
 create mode 100644 drivers/net/ionic/ionic_rxtx.h

diff --git a/doc/guides/nics/features/ionic.ini 
b/doc/guides/nics/features/ionic.ini
index 05bdb2d98..8fde998c1 100644
--- a/doc/guides/nics/features/ionic.ini
+++ b/doc/guides/nics/features/ionic.ini
@@ -7,12 +7,22 @@
 Speed capabilities   = Y
 Link status  = Y
 Link status event= Y
+Queue start/stop = Y
 MTU update   = Y
+Jumbo frame  = Y
+Scattered Rx = Y
+LRO  = Y
+TSO  = Y
 Promiscuous mode = Y
 Allmulticast mode= Y
 Unicast MAC filter   = Y
 VLAN filter  = Y
+VLAN offload = Y
 Flow control = Y
+CRC offload  = Y
+L3 checksum offload  = Y
+L4 checksum offload  = Y
+Packet type parsing  = Y
 Linux UIO= Y
 Linux VFIO   = Y
 x86-64   = Y
diff --git a/drivers/net/ionic/Makefile b/drivers/net/ionic/Makefile
index 2b7cbaf9e..f74ac2d34 100644
--- a/drivers/net/ionic/Makefile
+++ b/drivers/net/ionic/Makefile
@@ -25,6 +25,7 @@ LDLIBS += -lrte_bus_pci
 #
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_mac_api.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_rx_filter.c
+SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_rxtx.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_dev.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_ethdev.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_lif.c
diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h
index 61576621b..8c1ec13a6 100644
--- a/drivers/net/ionic/ionic_dev.h
+++ b/drivers/net/ionic/ionic_dev.h
@@ -14,6 +14,7 @@
 
 #define IONIC_MAX_RING_DESC32768
 #define IONIC_MIN_RING_DESC16
+#define IONIC_DEF_TXRX_DESC4096
 
 #define IONIC_LIFS_MAX 1024
 
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index ba1d1de16..e49531d21 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -15,6 +15,7 @@
 #include "ionic_mac_api.h"
 #include "ionic_lif.h"
 #include "ionic_ethdev.h"
+#include "ionic_rxtx.h"
 
 static int  eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 static int  eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev);
@@ -33,6 +34,7 @@ static int  ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
struct rte_eth_fc_conf *fc_conf);
 static int  ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev,
struct rte_eth_fc_conf *fc_conf);
+static int  ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
 
 int ionic_logtype;
 
@@ -43,6 +45,20 @@ static const struct rte_pci_id pci_id_ionic_map[] = {
{ .vendor_id = 0, /* sentinel */ },
 };
 
+static const struct rte_eth_desc_lim rx_desc_lim = {
+   .nb_max = IONIC_MAX_RING_DESC,
+   .nb_min = IONIC_MIN_RING_DESC,
+   .nb_align = 1,
+};
+
+static const struct rte_eth_desc_lim tx_desc_lim = {
+   .nb_max = IONIC_MAX_RING_DESC,
+   .nb_min = IONIC_MIN_RING_DESC,
+   .nb_align = 1,
+   .nb_seg_max = IONIC_TX_MAX_SG_ELEMS,
+   .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS,
+};
+
 static const struct eth_dev_ops ionic_eth_dev_ops = {
.dev_infos_get  = ionic_dev_info_get,
.dev_configure  = ionic_dev_configure,
@@ -63,6 +79,17 @@ static const struct eth_dev_ops ionic_eth_dev_ops = {
.allmulticast_disable   = ionic_dev_allmulticast_disable,
.flow_ctrl_get  = ionic_flow_ctrl_get,
.flow_ctrl_set  = ionic_flow_ctrl_set,
+   .rxq_info_get   = ionic_rxq_info_get,
+   .txq_info_get   = ionic_txq_info_get,
+   .rx_queue_setup = ionic_dev_rx_queue_setup,
+   .rx_queue_release   = ionic_dev_rx_queue_release,
+   .rx_queue_start = ionic_dev_rx_queue_start,
+   .rx_queue_stop  = ionic_dev_rx_queue_stop,
+   .tx_queue_setup = ionic_dev_tx_queue_setup,
+   .tx_queue_release   = ionic_dev_tx_queue_release,
+   .tx_queue_start = ionic_dev_tx_queue_start,
+   .tx_queue_stop  = ionic_dev_tx_queue_stop,
+   .vlan_offload_set   = ionic_vlan_offload_set,
 };
 
 /*
@@ -246,6 +273,50 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev,
ETH_LINK_SPEED_50G |
ETH_LINK_SPEED_100G;
 
+   /*
+* Per-queue capabili

[dpdk-dev] [PATCH v4 16/17] net/ionic: add TX checksum support

[Alfredo Cardigliano]

Add support for TX checksumming.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 drivers/net/ionic/ionic_ethdev.c |  5 ++
 drivers/net/ionic/ionic_lif.c|  1 +
 drivers/net/ionic/ionic_lif.h|  1 +
 drivers/net/ionic/ionic_rxtx.c   | 88 +++-
 4 files changed, 93 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index fdd56134e..6267fde35 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -409,7 +409,12 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev,
0;
 
dev_info->tx_queue_offload_capa =
+   DEV_TX_OFFLOAD_IPV4_CKSUM |
+   DEV_TX_OFFLOAD_UDP_CKSUM |
+   DEV_TX_OFFLOAD_TCP_CKSUM |
DEV_TX_OFFLOAD_VLAN_INSERT |
+   DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
+   DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |
0;
 
/*
diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c
index 29fca11a1..0d066c6e4 100644
--- a/drivers/net/ionic/ionic_lif.c
+++ b/drivers/net/ionic/ionic_lif.c
@@ -1511,6 +1511,7 @@ ionic_lif_init(struct ionic_lif *lif)
| IONIC_ETH_HW_RX_HASH
| IONIC_ETH_HW_TX_SG
| IONIC_ETH_HW_RX_SG
+   | IONIC_ETH_HW_TX_CSUM
| IONIC_ETH_HW_RX_CSUM
| IONIC_ETH_HW_TSO
| IONIC_ETH_HW_TSO_IPV6
diff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h
index dd7bd11e3..d1e1541ca 100644
--- a/drivers/net/ionic/ionic_lif.h
+++ b/drivers/net/ionic/ionic_lif.h
@@ -32,6 +32,7 @@ struct ionic_tx_stats {
uint64_t bytes;
uint64_t drop;
uint64_t stop;
+   uint64_t no_csum;
uint64_t tso;
uint64_t frags;
 };
diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c
index 614215ffa..f36112ced 100644
--- a/drivers/net/ionic/ionic_rxtx.c
+++ b/drivers/net/ionic/ionic_rxtx.c
@@ -232,16 +232,59 @@ ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 
uint16_t tx_queue_id)
return 0;
 }
 
+static void
+ionic_tx_tcp_pseudo_csum(struct rte_mbuf *txm)
+{
+   struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
+   char *l3_hdr = ((char *)eth_hdr) + txm->l2_len;
+   struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
+   (l3_hdr + txm->l3_len);
+
+   if (txm->ol_flags & PKT_TX_IP_CKSUM) {
+   struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
+   ipv4_hdr->hdr_checksum = 0;
+   tcp_hdr->cksum = 0;
+   tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
+   } else {
+   struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
+   tcp_hdr->cksum = 0;
+   tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
+   }
+}
+
+static void
+ionic_tx_tcp_inner_pseudo_csum(struct rte_mbuf *txm)
+{
+   struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
+   char *l3_hdr = ((char *)eth_hdr) + txm->outer_l2_len +
+   txm->outer_l3_len + txm->l2_len;
+   struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
+   (l3_hdr + txm->l3_len);
+
+   if (txm->ol_flags & PKT_TX_IPV4) {
+   struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
+   ipv4_hdr->hdr_checksum = 0;
+   tcp_hdr->cksum = 0;
+   tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
+   } else {
+   struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
+   tcp_hdr->cksum = 0;
+   tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
+   }
+}
+
 static void
 ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,
struct rte_mbuf *txm,
rte_iova_t addr, uint8_t nsge, uint16_t len,
uint32_t hdrlen, uint32_t mss,
+   bool encap,
uint16_t vlan_tci, bool has_vlan,
bool start, bool done)
 {
uint8_t flags = 0;
flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
+   flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
 
@@ -286,10 +329,29 @@ ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm,
uint32_t len;
uint32_t offset = 0;
bool start, done;
+   bool encap;
bool has_vlan = !!(txm->ol_flags & PKT_TX_VLAN_PKT);
uint16_t vlan_tci = txm->vlan_tci;
+   uint64_t ol_flags = txm->ol_flags;
 
-   hdrlen = txm->l2_len + txm->l3_len;
+   encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
+   (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) &&
+   ((ol_flags & PKT_TX_OUTER_IPV4) ||
+   (ol_flags 

[dpdk-dev] [PATCH v4 15/17] net/ionic: add stats

[Alfredo Cardigliano]

Add basic, per queue and extended statistics for
RX and TX, both from the adapter and the driver.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 doc/guides/nics/features/ionic.ini |   3 +
 drivers/net/ionic/ionic_ethdev.c   | 253 +
 drivers/net/ionic/ionic_lif.c  | 148 +
 drivers/net/ionic/ionic_lif.h  |   9 +
 4 files changed, 413 insertions(+)

diff --git a/doc/guides/nics/features/ionic.ini 
b/doc/guides/nics/features/ionic.ini
index 9a155251c..8cd5936d6 100644
--- a/doc/guides/nics/features/ionic.ini
+++ b/doc/guides/nics/features/ionic.ini
@@ -26,6 +26,9 @@ CRC offload  = Y
 L3 checksum offload  = Y
 L4 checksum offload  = Y
 Packet type parsing  = Y
+Basic stats  = Y
+Extended stats   = Y
+Stats per queue  = Y
 Linux UIO= Y
 Linux VFIO   = Y
 x86-64   = Y
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index 121404a1f..fdd56134e 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -43,6 +43,19 @@ static int  ionic_dev_rss_hash_conf_get(struct rte_eth_dev 
*eth_dev,
struct rte_eth_rss_conf *rss_conf);
 static int  ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_conf *rss_conf);
+static int  ionic_dev_stats_get(struct rte_eth_dev *eth_dev,
+   struct rte_eth_stats *stats);
+static int  ionic_dev_stats_reset(struct rte_eth_dev *eth_dev);
+static int  ionic_dev_xstats_get(struct rte_eth_dev *dev,
+   struct rte_eth_xstat *xstats, unsigned int n);
+static int  ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev,
+   const uint64_t *ids, uint64_t *values, unsigned int n);
+static int  ionic_dev_xstats_reset(struct rte_eth_dev *dev);
+static int  ionic_dev_xstats_get_names(struct rte_eth_dev *dev,
+   struct rte_eth_xstat_name *xstats_names, unsigned int size);
+static int  ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
+   struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
+   unsigned int limit);
 
 int ionic_logtype;
 
@@ -102,8 +115,102 @@ static const struct eth_dev_ops ionic_eth_dev_ops = {
.reta_query = ionic_dev_rss_reta_query,
.rss_hash_conf_get  = ionic_dev_rss_hash_conf_get,
.rss_hash_update= ionic_dev_rss_hash_update,
+   .stats_get  = ionic_dev_stats_get,
+   .stats_reset= ionic_dev_stats_reset,
+   .xstats_get = ionic_dev_xstats_get,
+   .xstats_get_by_id   = ionic_dev_xstats_get_by_id,
+   .xstats_reset   = ionic_dev_xstats_reset,
+   .xstats_get_names   = ionic_dev_xstats_get_names,
+   .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id,
 };
 
+struct rte_ionic_xstats_name_off {
+   char name[RTE_ETH_XSTATS_NAME_SIZE];
+   unsigned int offset;
+};
+
+static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = {
+   /* RX */
+   {"rx_ucast_bytes", offsetof(struct ionic_lif_stats,
+   rx_ucast_bytes)},
+   {"rx_ucast_packets", offsetof(struct ionic_lif_stats,
+   rx_ucast_packets)},
+   {"rx_mcast_bytes", offsetof(struct ionic_lif_stats,
+   rx_mcast_bytes)},
+   {"rx_mcast_packets", offsetof(struct ionic_lif_stats,
+   rx_mcast_packets)},
+   {"rx_bcast_bytes", offsetof(struct ionic_lif_stats,
+   rx_bcast_bytes)},
+   {"rx_bcast_packets", offsetof(struct ionic_lif_stats,
+   rx_bcast_packets)},
+   /* RX drops */
+   {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats,
+   rx_ucast_drop_bytes)},
+   {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats,
+   rx_ucast_drop_packets)},
+   {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats,
+   rx_mcast_drop_bytes)},
+   {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats,
+   rx_mcast_drop_packets)},
+   {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats,
+   rx_bcast_drop_bytes)},
+   {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats,
+   rx_bcast_drop_packets)},
+   {"rx_dma_error", offsetof(struct ionic_lif_stats,
+   rx_dma_error)},
+   /* TX */
+   {"tx_ucast_bytes", offsetof(struct ionic_lif_stats,
+   tx_ucast_bytes)},
+   {"tx_ucast_packets", offsetof(struct ionic_lif_stats,
+   tx_ucast_packets)},
+   {"tx_mcast_bytes", offsetof(struct ionic_lif_stats,
+   tx_mcast_bytes)},
+   {"tx_mcast_packets", offsetof(struct ionic_lif_stats,
+   tx_mcast_packets)},
+   {"tx_bcast_bytes", offsetof(struct ionic_lif_stats,
+   tx_bcast_bytes)},

[dpdk-dev] [PATCH v4 11/17] net/ionic: add RX filters support

[Alfredo Cardigliano]

Add support for managing RX filters based on MAC and VLAN.
Hardware cannot provide the list of filters, thus we keep
a local list.
Add support for promisc and allmulticast modes.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 doc/guides/nics/features/ionic.ini  |   4 +
 drivers/net/ionic/Makefile  |   1 +
 drivers/net/ionic/ionic_ethdev.c|   8 +
 drivers/net/ionic/ionic_lif.c   | 259 +++-
 drivers/net/ionic/ionic_lif.h   |  16 ++
 drivers/net/ionic/ionic_rx_filter.c | 139 +++
 drivers/net/ionic/ionic_rx_filter.h |  47 +
 drivers/net/ionic/meson.build   |   1 +
 8 files changed, 468 insertions(+), 7 deletions(-)
 create mode 100644 drivers/net/ionic/ionic_rx_filter.c
 create mode 100644 drivers/net/ionic/ionic_rx_filter.h

diff --git a/doc/guides/nics/features/ionic.ini 
b/doc/guides/nics/features/ionic.ini
index c69e5cbed..3dd5dab45 100644
--- a/doc/guides/nics/features/ionic.ini
+++ b/doc/guides/nics/features/ionic.ini
@@ -8,6 +8,10 @@ Speed capabilities   = Y
 Link status  = Y
 Link status event= Y
 MTU update   = Y
+Promiscuous mode = Y
+Allmulticast mode= Y
+Unicast MAC filter   = Y
+VLAN filter  = Y
 Linux UIO= Y
 Linux VFIO   = Y
 x86-64   = Y
diff --git a/drivers/net/ionic/Makefile b/drivers/net/ionic/Makefile
index 2dc88cdd5..2b7cbaf9e 100644
--- a/drivers/net/ionic/Makefile
+++ b/drivers/net/ionic/Makefile
@@ -24,6 +24,7 @@ LDLIBS += -lrte_bus_pci
 # all source are stored in SRCS-y
 #
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_mac_api.c
+SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_rx_filter.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_dev.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_ethdev.c
 SRCS-$(CONFIG_RTE_LIBRTE_IONIC_PMD) += ionic_lif.c
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index 3f9988acc..dbeb737fd 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -49,6 +49,14 @@ static const struct eth_dev_ops ionic_eth_dev_ops = {
.link_update= ionic_dev_link_update,
.dev_set_link_up= ionic_dev_set_link_up,
.dev_set_link_down  = ionic_dev_set_link_down,
+   .mac_addr_add   = ionic_dev_add_mac,
+   .mac_addr_remove= ionic_dev_remove_mac,
+   .mac_addr_set   = ionic_dev_set_mac,
+   .vlan_filter_set= ionic_dev_vlan_filter_set,
+   .promiscuous_enable = ionic_dev_promiscuous_enable,
+   .promiscuous_disable= ionic_dev_promiscuous_disable,
+   .allmulticast_enable= ionic_dev_allmulticast_enable,
+   .allmulticast_disable   = ionic_dev_allmulticast_disable,
 };
 
 /*
diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c
index 518e177eb..86c05ff4e 100644
--- a/drivers/net/ionic/ionic_lif.c
+++ b/drivers/net/ionic/ionic_lif.c
@@ -9,6 +9,7 @@
 #include "ionic_logs.h"
 #include "ionic_lif.h"
 #include "ionic_ethdev.h"
+#include "ionic_rx_filter.h"
 
 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
@@ -83,23 +84,205 @@ ionic_lif_reset(struct ionic_lif *lif)
 }
 
 static int
-ionic_lif_addr_add(struct ionic_lif *lif __rte_unused,
-   const uint8_t *addr __rte_unused)
+ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
 {
-   IONIC_PRINT(INFO, "%s: stubbed", __func__);
+   struct ionic_admin_ctx ctx = {
+   .pending_work = true,
+   .cmd.rx_filter_add = {
+   .opcode = IONIC_CMD_RX_FILTER_ADD,
+   .match = IONIC_RX_FILTER_MATCH_MAC,
+   },
+   };
+   int err;
+
+   memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
+
+   err = ionic_adminq_post_wait(lif, &ctx);
+
+   if (err)
+   return err;
+
+   IONIC_PRINT(INFO, "rx_filter add (id %d)",
+   ctx.comp.rx_filter_add.filter_id);
+
+   return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
+}
+
+static int
+ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
+{
+   struct ionic_admin_ctx ctx = {
+   .pending_work = true,
+   .cmd.rx_filter_del = {
+   .opcode = IONIC_CMD_RX_FILTER_DEL,
+   },
+   };
+   struct ionic_rx_filter *f;
+   int err;
+
+   IONIC_PRINT_CALL();
+
+   rte_spinlock_lock(&lif->rx_filters.lock);
+
+   f = ionic_rx_filter_by_addr(lif, addr);
+
+   if (!f) {
+   rte_spinlock_unlock(&lif->rx_filters.lock);
+   return -ENOENT;
+   }
+
+   ctx.cmd.rx_filter_del.filter_id = f->filter_id;
+   ionic_rx_filter_free(f);
+
+   rte_spinlock_unlock(&lif->rx_filters.lock);
+
+   err = ionic_adminq_post_wait(lif, &ctx);
+
+   if (err)
+   re

[dpdk-dev] [PATCH v4 17/17] net/ionic: read fw version

[Alfredo Cardigliano]

Add support for reading the firmware version.

Signed-off-by: Alfredo Cardigliano 
Reviewed-by: Shannon Nelson 
---
 doc/guides/nics/features/ionic.ini |  1 +
 drivers/net/ionic/ionic.h  |  1 +
 drivers/net/ionic/ionic_dev.c  |  8 
 drivers/net/ionic/ionic_ethdev.c   | 20 
 4 files changed, 30 insertions(+)

diff --git a/doc/guides/nics/features/ionic.ini 
b/doc/guides/nics/features/ionic.ini
index 8cd5936d6..083c7bd99 100644
--- a/doc/guides/nics/features/ionic.ini
+++ b/doc/guides/nics/features/ionic.ini
@@ -29,6 +29,7 @@ Packet type parsing  = Y
 Basic stats  = Y
 Extended stats   = Y
 Stats per queue  = Y
+FW version   = Y
 Linux UIO= Y
 Linux VFIO   = Y
 x86-64   = Y
diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h
index ae4f6acc7..45a7879c9 100644
--- a/drivers/net/ionic/ionic.h
+++ b/drivers/net/ionic/ionic.h
@@ -60,6 +60,7 @@ struct ionic_adapter {
bool intrs[IONIC_INTR_CTRL_REGS_MAX];
bool is_mgmt_nic;
bool link_up;
+   char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
struct rte_pci_device *pci_dev;
LIST_ENTRY(ionic_adapter) pci_adapters;
 };
diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c
index e2cd15792..c3f83559f 100644
--- a/drivers/net/ionic/ionic_dev.c
+++ b/drivers/net/ionic/ionic_dev.c
@@ -16,6 +16,7 @@ ionic_dev_setup(struct ionic_adapter *adapter)
struct ionic_dev *idev = &adapter->idev;
uint32_t sig;
u_char *bar0_base;
+   unsigned int i;
 
/* BAR0: dev_cmd and interrupts */
if (num_bars < 1) {
@@ -47,6 +48,13 @@ ionic_dev_setup(struct ionic_adapter *adapter)
return -EFAULT;
}
 
+   for (i = 0; i < IONIC_DEVINFO_FWVERS_BUFLEN; i++)
+   adapter->fw_version[i] =
+   ioread8(&idev->dev_info->fw_version[i]);
+   adapter->fw_version[IONIC_DEVINFO_FWVERS_BUFLEN - 1] = '\0';
+
+   IONIC_PRINT(DEBUG, "Firmware version: %s", adapter->fw_version);
+
/* BAR1: doorbells */
bar++;
if (num_bars < 2) {
diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c
index 6267fde35..4097bb697 100644
--- a/drivers/net/ionic/ionic_ethdev.c
+++ b/drivers/net/ionic/ionic_ethdev.c
@@ -56,6 +56,8 @@ static int  ionic_dev_xstats_get_names(struct rte_eth_dev 
*dev,
 static int  ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
unsigned int limit);
+static int  ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev,
+   char *fw_version, size_t fw_size);
 
 int ionic_logtype;
 
@@ -122,6 +124,7 @@ static const struct eth_dev_ops ionic_eth_dev_ops = {
.xstats_reset   = ionic_dev_xstats_reset,
.xstats_get_names   = ionic_dev_xstats_get_names,
.xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id,
+   .fw_version_get = ionic_dev_fw_version_get,
 };
 
 struct rte_ionic_xstats_name_off {
@@ -211,6 +214,23 @@ static const struct rte_ionic_xstats_name_off 
rte_ionic_xstats_strings[] = {
 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \
sizeof(rte_ionic_xstats_strings[0]))
 
+static int
+ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev,
+   char *fw_version, size_t fw_size)
+{
+   struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
+   struct ionic_adapter *adapter = lif->adapter;
+
+   if (fw_version == NULL || fw_size <= 0)
+   return -EINVAL;
+
+   snprintf(fw_version, fw_size, "%s",
+adapter->fw_version);
+   fw_version[fw_size - 1] = '\0';
+
+   return 0;
+}
+
 /*
  * Set device link up, enable tx.
  */
-- 
2.17.1

Re: [dpdk-dev] [PATCH v4 02/17] net/ionic: add hardware structures definitions

[Stephen Hemminger]

On Thu, 19 Dec 2019 23:18:32 +0100
Alfredo Cardigliano  wrote:

> +
> +#pragma pack(push, 1)
> +

Really, packing leads to unaligned data structures and is generally
a bad idea.

Re: [dpdk-dev] [PATCH v4 04/17] net/ionic: register and initialize the adapter

[Stephen Hemminger]

On Thu, 19 Dec 2019 23:18:34 +0100
Alfredo Cardigliano  wrote:

> + adapter = rte_zmalloc("ionic", sizeof(*adapter), 0);
> +
> + if (!adapter) {

Don't need a blank line here; better to have assignment and check next to each 
other.

You probably want to use rte_zmalloc_socket to make sure that the adapter memory
is on the same numa node as the device.

Re: [dpdk-dev] [PATCH v4 04/17] net/ionic: register and initialize the adapter

[Stephen Hemminger]

On Thu, 19 Dec 2019 23:18:34 +0100
Alfredo Cardigliano  wrote:

> + adapter->pci_dev = pci_dev;
> + hw = &adapter->hw;
> +
> + hw->device_id = pci_dev->id.device_id;
> + hw->vendor_id = pci_dev->id.vendor_id;

Other drives to rte_eth_copy_pci_info(eth_dev, pci_dev) here.

Re: [dpdk-dev] [PATCH v4 04/17] net/ionic: register and initialize the adapter

[Stephen Hemminger]

On Thu, 19 Dec 2019 23:18:34 +0100
Alfredo Cardigliano  wrote:

> +static int
> +eth_ionic_pci_remove(struct rte_pci_device *pci_dev)
> +{
> + return 0;
> +}
> +

You probably want to u se rte_eth_dev_pci_generic_remove here

Re: [dpdk-dev] [PATCH v4 04/17] net/ionic: register and initialize the adapter

[Stephen Hemminger]

On Thu, 19 Dec 2019 23:18:34 +0100
Alfredo Cardigliano  wrote:

> +
> +static inline uint16_t ilog2(uint32_t n)
> +{
> + uint16_t logv = -1;
> +
> + if (n == 0)
> + return 0;
> +
> + while (n) {
> + logv++;
> + n >>= 1;
> + }
> +
> + return logv;
> +}

There already is rte_log2_u32?

Re: [dpdk-dev] [PATCH v4 15/17] net/ionic: add stats

[Stephen Hemminger]

On Thu, 19 Dec 2019 23:18:45 +0100
Alfredo Cardigliano  wrote:

> +
> +void
> +ionic_lif_get_stats(struct ionic_lif *lif, struct rte_eth_stats *stats)
> +{

It is clearer which parameter is input (vs output) if you mark lif as const 
here.

Re: [dpdk-dev] [PATCH v4 06/17] net/ionic: add basic lif support

[Stephen Hemminger]

On Thu, 19 Dec 2019 23:18:36 +0100
Alfredo Cardigliano  wrote:

> diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h
> index a29f0bb89..b6ef63161 100644
> --- a/drivers/net/ionic/ionic.h
> +++ b/drivers/net/ionic/ionic.h
> @@ -49,7 +49,12 @@ struct ionic_adapter {
>   struct ionic_dev idev;
>   struct ionic_dev_bar bars[IONIC_BARS_MAX];
>   struct ionic_identity   ident;
> + struct ionic_lif *lifs[IONIC_LIFS_MAX]

You are making 8K array on the stack, do you really need all that?

[dpdk-dev] [PATCH v2 0/5] drivers/net: cleanup Tx buffers

[Chenxu Di]

Add support to the drivers inclulding fm10k, i40e, ice, ixgbe
and igb vf for the API rte_eth_tx_done_cleanup to
 force free consumed buffers on Tx ring.

---
v2:
added code about igb vf.

Chenxu Di (5):
  net/e1000: cleanup Tx buffers
  net/fm10k: cleanup Tx buffers
  net/i40e: cleanup Tx buffers
  net/ice: cleanup Tx buffers
  net/ixgbe: cleanup Tx buffers

 drivers/net/e1000/igb_ethdev.c|  1 +
 drivers/net/fm10k/fm10k.h |  2 ++
 drivers/net/fm10k/fm10k_ethdev.c  |  1 +
 drivers/net/fm10k/fm10k_rxtx.c| 45 +++
 drivers/net/i40e/i40e_ethdev.c|  1 +
 drivers/net/i40e/i40e_ethdev_vf.c |  1 +
 drivers/net/i40e/i40e_rxtx.c  | 40 +++
 drivers/net/i40e/i40e_rxtx.h  |  1 +
 drivers/net/ice/ice_ethdev.c  |  1 +
 drivers/net/ice/ice_rxtx.c| 41 
 drivers/net/ice/ice_rxtx.h|  1 +
 drivers/net/ixgbe/ixgbe_ethdev.c  |  2 ++
 drivers/net/ixgbe/ixgbe_rxtx.c| 39 +++
 drivers/net/ixgbe/ixgbe_rxtx.h|  2 ++
 14 files changed, 178 insertions(+)

-- 
2.17.1

[dpdk-dev] [PATCH v2 4/5] net/ixgbe: cleanup Tx buffers

[Chenxu Di]

From: Di ChenxuX 

Add support to the ixgbe driver for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/ixgbe/ixgbe_ethdev.c |  2 ++
 drivers/net/ixgbe/ixgbe_rxtx.c   | 39 
 drivers/net/ixgbe/ixgbe_rxtx.h   |  2 ++
 3 files changed, 43 insertions(+)

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 2c6fd0f13..0091405db 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -601,6 +601,7 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {
.udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
.udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
.tm_ops_get   = ixgbe_tm_ops_get,
+   .tx_done_cleanup  = ixgbe_tx_done_cleanup,
 };
 
 /*
@@ -649,6 +650,7 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
.reta_query   = ixgbe_dev_rss_reta_query,
.rss_hash_update  = ixgbe_dev_rss_hash_update,
.rss_hash_conf_get= ixgbe_dev_rss_hash_conf_get,
+   .tx_done_cleanup  = ixgbe_tx_done_cleanup,
 };
 
 /* store statistics names and its offset in stats structure */
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index fa572d184..4823a9cf1 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -2306,6 +2306,45 @@ ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
}
 }
 
+int ixgbe_tx_done_cleanup(void *txq, uint32_t free_cnt)
+{
+   struct ixgbe_tx_queue *q = (struct ixgbe_tx_queue *)txq;
+   struct ixgbe_tx_entry *sw_ring;
+   uint16_t tx_id;/* Current segment being processed. */
+   uint16_t tx_cleaned;
+
+   int count = 0;
+
+   if (q == NULL)
+   return -ENODEV;
+
+   sw_ring = q->sw_ring;
+   tx_cleaned = q->last_desc_cleaned;
+   tx_id = sw_ring[q->last_desc_cleaned].next_id;
+   if (!(q->tx_ring[tx_id].wb.status &
+   IXGBE_TXD_STAT_DD))
+   return 0;
+
+   do {
+   if (sw_ring[tx_id].mbuf == NULL)
+   break;
+
+   rte_pktmbuf_free_seg(sw_ring[tx_id].mbuf);
+   sw_ring[tx_id].mbuf = NULL;
+   sw_ring[tx_id].last_id = tx_id;
+
+   /* Move to next segemnt. */
+   tx_cleaned = tx_id;
+   tx_id = sw_ring[tx_id].next_id;
+   count++;
+   } while (count != (int)free_cnt);
+
+   q->nb_tx_free += (uint16_t)count;
+   q->last_desc_cleaned = tx_cleaned;
+
+   return count;
+}
+
 static void __attribute__((cold))
 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
 {
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxtx.h
index 505d344b9..2c3770af6 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.h
+++ b/drivers/net/ixgbe/ixgbe_rxtx.h
@@ -285,6 +285,8 @@ int ixgbe_rx_vec_dev_conf_condition_check(struct 
rte_eth_dev *dev);
 int ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq);
 void ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq);
 
+int ixgbe_tx_done_cleanup(void *txq, uint32_t free_cnt);
+
 extern const uint32_t ptype_table[IXGBE_PACKET_TYPE_MAX];
 extern const uint32_t ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX];
 
-- 
2.17.1

[dpdk-dev] [PATCH v2 1/5] net/fm10k: cleanup Tx buffers

[Chenxu Di]

From: Di ChenxuX 

Add support to the fm10k driver for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/fm10k/fm10k.h|  2 ++
 drivers/net/fm10k/fm10k_ethdev.c |  1 +
 drivers/net/fm10k/fm10k_rxtx.c   | 45 
 3 files changed, 48 insertions(+)

diff --git a/drivers/net/fm10k/fm10k.h b/drivers/net/fm10k/fm10k.h
index 916b856ac..ddb1d64ec 100644
--- a/drivers/net/fm10k/fm10k.h
+++ b/drivers/net/fm10k/fm10k.h
@@ -342,6 +342,8 @@ uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf 
**tx_pkts,
 uint16_t fm10k_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
 
+int fm10k_tx_done_cleanup(void *txq, uint32_t free_cnt);
+
 int fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq);
 int fm10k_rx_vec_condition_check(struct rte_eth_dev *);
 void fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq);
diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c
index 407baa16c..c389c79de 100644
--- a/drivers/net/fm10k/fm10k_ethdev.c
+++ b/drivers/net/fm10k/fm10k_ethdev.c
@@ -2897,6 +2897,7 @@ static const struct eth_dev_ops fm10k_eth_dev_ops = {
.reta_query = fm10k_reta_query,
.rss_hash_update= fm10k_rss_hash_update,
.rss_hash_conf_get  = fm10k_rss_hash_conf_get,
+   .tx_done_cleanup= fm10k_tx_done_cleanup,
 };
 
 static int ftag_check_handler(__rte_unused const char *key,
diff --git a/drivers/net/fm10k/fm10k_rxtx.c b/drivers/net/fm10k/fm10k_rxtx.c
index 5c3112183..f67c5bf00 100644
--- a/drivers/net/fm10k/fm10k_rxtx.c
+++ b/drivers/net/fm10k/fm10k_rxtx.c
@@ -541,6 +541,51 @@ static inline void tx_free_bulk_mbuf(struct rte_mbuf 
**txep, int num)
}
 }
 
+int fm10k_tx_done_cleanup(void *txq, uint32_t free_cnt)
+{
+   struct fm10k_tx_queue *q = (struct fm10k_tx_queue *)txq;
+   uint16_t next_rs, count = 0;
+
+   if (q == NULL)
+   return -ENODEV;
+
+   next_rs = fifo_peek(&q->rs_tracker);
+   if (!(q->hw_ring[next_rs].flags & FM10K_TXD_FLAG_DONE))
+   return count;
+
+   /* the DONE flag is set on this descriptor so remove the ID
+* from the RS bit tracker and free the buffers
+*/
+   fifo_remove(&q->rs_tracker);
+
+   /* wrap around? if so, free buffers from last_free up to but NOT
+* including nb_desc
+*/
+   if (q->last_free > next_rs) {
+   count = q->nb_desc - q->last_free;
+   tx_free_bulk_mbuf(&q->sw_ring[q->last_free], count);
+   q->last_free = 0;
+
+   if (unlikely(count == (int)free_cnt))
+   return count;
+   }
+
+   /* adjust free descriptor count before the next loop */
+   q->nb_free += count + (next_rs + 1 - q->last_free);
+
+   /* free buffers from last_free, up to and including next_rs */
+   if (q->last_free <= next_rs) {
+   count = next_rs - q->last_free + 1;
+   tx_free_bulk_mbuf(&q->sw_ring[q->last_free], count);
+   q->last_free += count;
+   }
+
+   if (q->last_free == q->nb_desc)
+   q->last_free = 0;
+
+   return count;
+}
+
 static inline void tx_free_descriptors(struct fm10k_tx_queue *q)
 {
uint16_t next_rs, count = 0;
-- 
2.17.1

[dpdk-dev] [PATCH v2 2/5] net/i40e: cleanup Tx buffers

[Chenxu Di]

From: Di ChenxuX 

Add support to the i40e driver for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/i40e/i40e_ethdev.c|  1 +
 drivers/net/i40e/i40e_ethdev_vf.c |  1 +
 drivers/net/i40e/i40e_rxtx.c  | 40 +++
 drivers/net/i40e/i40e_rxtx.h  |  1 +
 4 files changed, 43 insertions(+)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 5999c964b..fad47a942 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -522,6 +522,7 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {
.mac_addr_set = i40e_set_default_mac_addr,
.mtu_set  = i40e_dev_mtu_set,
.tm_ops_get   = i40e_tm_ops_get,
+   .tx_done_cleanup  = i40e_tx_done_cleanup,
 };
 
 /* store statistics names and its offset in stats structure */
diff --git a/drivers/net/i40e/i40e_ethdev_vf.c 
b/drivers/net/i40e/i40e_ethdev_vf.c
index 5dba0928b..0ca5417d7 100644
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -215,6 +215,7 @@ static const struct eth_dev_ops i40evf_eth_dev_ops = {
.rss_hash_conf_get= i40evf_dev_rss_hash_conf_get,
.mtu_set  = i40evf_dev_mtu_set,
.mac_addr_set = i40evf_set_default_mac_addr,
+   .tx_done_cleanup  = i40e_tx_done_cleanup,
 };
 
 /*
diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
index 17dc8c78f..3280a3ff6 100644
--- a/drivers/net/i40e/i40e_rxtx.c
+++ b/drivers/net/i40e/i40e_rxtx.c
@@ -2455,6 +2455,46 @@ i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
}
 }
 
+int i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
+{
+   struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
+   struct i40e_tx_entry *sw_ring;
+   uint16_t tx_id;/* Current segment being processed. */
+   uint16_t tx_cleaned;
+
+   int count = 0;
+
+   if (q == NULL)
+   return -ENODEV;
+
+   sw_ring = q->sw_ring;
+   tx_cleaned = q->last_desc_cleaned;
+   tx_id = sw_ring[q->last_desc_cleaned].next_id;
+   if ((q->tx_ring[tx_id].cmd_type_offset_bsz &
+   rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
+   rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
+   return 0;
+
+   do {
+   if (sw_ring[tx_id].mbuf == NULL)
+   break;
+
+   rte_pktmbuf_free_seg(sw_ring[tx_id].mbuf);
+   sw_ring[tx_id].mbuf = NULL;
+   sw_ring[tx_id].last_id = tx_id;
+
+   /* Move to next segemnt. */
+   tx_cleaned = tx_id;
+   tx_id = sw_ring[tx_id].next_id;
+   count++;
+   } while (count != (int)free_cnt);
+
+   q->nb_tx_free += (uint16_t)count;
+   q->last_desc_cleaned = tx_cleaned;
+
+   return count;
+}
+
 void
 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
 {
diff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h
index 2106bb355..8f11f011a 100644
--- a/drivers/net/i40e/i40e_rxtx.h
+++ b/drivers/net/i40e/i40e_rxtx.h
@@ -212,6 +212,7 @@ void i40e_dev_free_queues(struct rte_eth_dev *dev);
 void i40e_reset_rx_queue(struct i40e_rx_queue *rxq);
 void i40e_reset_tx_queue(struct i40e_tx_queue *txq);
 void i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq);
+int i40e_tx_done_cleanup(void *txq, uint32_t free_cnt);
 int i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq);
 void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
 
-- 
2.17.1

[dpdk-dev] [PATCH v2 5/5] net/e1000: cleanup Tx buffers

[Chenxu Di]

Add support to the igb vf for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/e1000/igb_ethdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index a3e30dbe5..647d5504f 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -446,6 +446,7 @@ static const struct eth_dev_ops igbvf_eth_dev_ops = {
.tx_descriptor_status = eth_igb_tx_descriptor_status,
.tx_queue_setup   = eth_igb_tx_queue_setup,
.tx_queue_release = eth_igb_tx_queue_release,
+   .tx_done_cleanup  = eth_igb_tx_done_cleanup,
.set_mc_addr_list = eth_igb_set_mc_addr_list,
.rxq_info_get = igb_rxq_info_get,
.txq_info_get = igb_txq_info_get,
-- 
2.17.1

[dpdk-dev] [PATCH v2 3/5] net/ice: cleanup Tx buffers

[Chenxu Di]

From: Di ChenxuX 

Add support to the ice driver for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/ice/ice_ethdev.c |  1 +
 drivers/net/ice/ice_rxtx.c   | 41 
 drivers/net/ice/ice_rxtx.h   |  1 +
 3 files changed, 43 insertions(+)

diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index de189daba..b55cdbf74 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -220,6 +220,7 @@ static const struct eth_dev_ops ice_eth_dev_ops = {
.filter_ctrl  = ice_dev_filter_ctrl,
.udp_tunnel_port_add  = ice_dev_udp_tunnel_port_add,
.udp_tunnel_port_del  = ice_dev_udp_tunnel_port_del,
+   .tx_done_cleanup  = ice_tx_done_cleanup,
 };
 
 /* store statistics names and its offset in stats structure */
diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c
index 2db174456..154cc5e5f 100644
--- a/drivers/net/ice/ice_rxtx.c
+++ b/drivers/net/ice/ice_rxtx.c
@@ -863,6 +863,47 @@ ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t 
tx_queue_id)
return 0;
 }
 
+
+int ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
+{
+   struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
+   struct ice_tx_entry *sw_ring;
+   uint16_t tx_id;/* Current segment being processed. */
+   uint16_t tx_cleaned;
+
+   int count = 0;
+
+   if (q == NULL)
+   return -ENODEV;
+
+   sw_ring = q->sw_ring;
+   tx_cleaned = q->last_desc_cleaned;
+   tx_id = sw_ring[q->last_desc_cleaned].next_id;
+   if ((q->tx_ring[tx_id].cmd_type_offset_bsz &
+   rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
+   rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
+   return 0;
+
+   do {
+   if (sw_ring[tx_id].mbuf == NULL)
+   break;
+
+   rte_pktmbuf_free_seg(sw_ring[tx_id].mbuf);
+   sw_ring[tx_id].mbuf = NULL;
+   sw_ring[tx_id].last_id = tx_id;
+
+   /* Move to next segemnt. */
+   tx_cleaned = tx_id;
+   tx_id = sw_ring[tx_id].next_id;
+   count++;
+   } while (count != (int)free_cnt);
+
+   q->nb_tx_free += (uint16_t)count;
+   q->last_desc_cleaned = tx_cleaned;
+
+   return count;
+}
+
 int
 ice_rx_queue_setup(struct rte_eth_dev *dev,
   uint16_t queue_idx,
diff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h
index 9e3d2cd07..8d4232a61 100644
--- a/drivers/net/ice/ice_rxtx.h
+++ b/drivers/net/ice/ice_rxtx.h
@@ -183,6 +183,7 @@ int ice_rx_descriptor_status(void *rx_queue, uint16_t 
offset);
 int ice_tx_descriptor_status(void *tx_queue, uint16_t offset);
 void ice_set_default_ptype_table(struct rte_eth_dev *dev);
 const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev);
+int ice_tx_done_cleanup(void *txq, uint32_t free_cnt);
 
 int ice_rx_vec_dev_check(struct rte_eth_dev *dev);
 int ice_tx_vec_dev_check(struct rte_eth_dev *dev);
-- 
2.17.1

[dpdk-dev] [PATCH v2 0/3] relax io barrier for aarch64 and use smp barriers for virtual pci memory

[Gavin Hu]

Armv8's peripheral coherence order is a total order on all reads and
writes to that peripheral, that makes a compiler barrier is enough for
abstracted rte io barrier.

For virtual PCI devices, the virtual device memory is actually normal
memory and the Hypervisor view of things takes precedence and they are
within a smp configuration and smp barriers should be used, the
relaxed io barrier for aarch64 becomes insufficient.

Note for the ordering of other MMIO device memories, other than PCI,
stronger barriers might be required, which depends on the memory attributes
assigned to the memory regions. So far I did not find occurrences of such
io barriers used in non-PCI device memories within DPDK.

V2:
- remove virtio_pci_read/write64 APIs definitions, they are not needed and 
generate compiling errors like " error: unused function 'virtio_pci_write64' 
[-Werror,-Wunused-function]"
- update the reference link to kernel source code 

Gavin Hu (3):
  eal/arm64: relax the io barrier for aarch64
  net/virtio: virtual PCI requires smp barriers
  crypto/virtio: virtual PCI requires smp barriers

 drivers/crypto/virtio/virtio_pci.c | 108 +++--
 drivers/net/virtio/virtio_pci.c| 108 +++--
 .../common/include/arch/arm/rte_atomic_64.h|   6 +-
 3 files changed, 159 insertions(+), 63 deletions(-)

-- 
2.7.4

[dpdk-dev] [PATCH v2 2/3] net/virtio: virtual PCI requires smp barriers

[Gavin Hu]

Other than real PCI reads and writes to the device memory requiring
the io barriers, virtual pci memories are normal memory in the smp
configuration, which requires the smp barriers.

Since the smp barriers and io barriers are identical on x86 and PPC,
this change has only effect on aarch64.

As far as peripheral coherence order for ‘virtual’ devices, the arch
intent is that the Hypervisor view of things takes precedence – since
translations are made in holistic manner as the full stage1+stage2
regime, there is no such thing as a transaction taking on “EL1”
mapping as far as ordering. If the Hypervisor maps stage2 as Normal
but the OS at EL1 maps it as Device-nGnRE, then it’s Normal memory and
follows the ordering rules for Normal memory.

Signed-off-by: Gavin Hu 
---
 drivers/net/virtio/virtio_pci.c | 108 +---
 1 file changed, 78 insertions(+), 30 deletions(-)

diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c
index 4468e89..64aa0a0 100644
--- a/drivers/net/virtio/virtio_pci.c
+++ b/drivers/net/virtio/virtio_pci.c
@@ -24,6 +24,54 @@
 #define PCI_CAP_ID_VNDR0x09
 #define PCI_CAP_ID_MSIX0x11
 
+static __rte_always_inline uint8_t
+virtio_pci_read8(const volatile void *addr)
+{
+   uint8_t val;
+   val = rte_read8_relaxed(addr);
+   rte_smp_rmb();
+   return val;
+}
+
+static __rte_always_inline uint16_t
+virtio_pci_read16(const volatile void *addr)
+{
+   uint16_t val;
+   val = rte_read16_relaxed(addr);
+   rte_smp_rmb();
+   return val;
+}
+
+static __rte_always_inline uint32_t
+virtio_pci_read32(const volatile void *addr)
+{
+   uint32_t val;
+   val = rte_read32_relaxed(addr);
+   rte_smp_rmb();
+   return val;
+}
+
+static __rte_always_inline void
+virtio_pci_write8(uint8_t value, volatile void *addr)
+{
+   rte_smp_wmb();
+   rte_write8_relaxed(value, addr);
+}
+
+static __rte_always_inline void
+virtio_pci_write16(uint16_t value, volatile void *addr)
+{
+   rte_smp_wmb();
+   rte_write16_relaxed(value, addr);
+}
+
+static __rte_always_inline void
+virtio_pci_write32(uint32_t value, volatile void *addr)
+{
+   rte_smp_wmb();
+   rte_write32_relaxed(value, addr);
+}
+
 /*
  * The remaining space is defined by each driver as the per-driver
  * configuration space.
@@ -260,8 +308,8 @@ const struct virtio_pci_ops legacy_ops = {
 static inline void
 io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
 {
-   rte_write32(val & ((1ULL << 32) - 1), lo);
-   rte_write32(val >> 32,   hi);
+   virtio_pci_write32(val & ((1ULL << 32) - 1), lo);
+   virtio_pci_write32(val >> 32,hi);
 }
 
 static void
@@ -273,13 +321,13 @@ modern_read_dev_config(struct virtio_hw *hw, size_t 
offset,
uint8_t old_gen, new_gen;
 
do {
-   old_gen = rte_read8(&hw->common_cfg->config_generation);
+   old_gen = virtio_pci_read8(&hw->common_cfg->config_generation);
 
p = dst;
for (i = 0;  i < length; i++)
-   *p++ = rte_read8((uint8_t *)hw->dev_cfg + offset + i);
+   *p++ = virtio_pci_read8((uint8_t *)hw->dev_cfg + offset 
+ i);
 
-   new_gen = rte_read8(&hw->common_cfg->config_generation);
+   new_gen = virtio_pci_read8(&hw->common_cfg->config_generation);
} while (old_gen != new_gen);
 }
 
@@ -291,7 +339,7 @@ modern_write_dev_config(struct virtio_hw *hw, size_t offset,
const uint8_t *p = src;
 
for (i = 0;  i < length; i++)
-   rte_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + i));
+   virtio_pci_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + 
i));
 }
 
 static uint64_t
@@ -299,11 +347,11 @@ modern_get_features(struct virtio_hw *hw)
 {
uint32_t features_lo, features_hi;
 
-   rte_write32(0, &hw->common_cfg->device_feature_select);
-   features_lo = rte_read32(&hw->common_cfg->device_feature);
+   virtio_pci_write32(0, &hw->common_cfg->device_feature_select);
+   features_lo = virtio_pci_read32(&hw->common_cfg->device_feature);
 
-   rte_write32(1, &hw->common_cfg->device_feature_select);
-   features_hi = rte_read32(&hw->common_cfg->device_feature);
+   virtio_pci_write32(1, &hw->common_cfg->device_feature_select);
+   features_hi = virtio_pci_read32(&hw->common_cfg->device_feature);
 
return ((uint64_t)features_hi << 32) | features_lo;
 }
@@ -311,53 +359,53 @@ modern_get_features(struct virtio_hw *hw)
 static void
 modern_set_features(struct virtio_hw *hw, uint64_t features)
 {
-   rte_write32(0, &hw->common_cfg->guest_feature_select);
-   rte_write32(features & ((1ULL << 32) - 1),
+   virtio_pci_write32(0, &hw->common_cfg->guest_feature_select);
+   virtio_pci_write32(features & ((1ULL << 32) - 1),
&hw->common_cfg->guest_feature);
 
-   rte_w

[dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for aarch64

[Gavin Hu]

Armv8's peripheral coherence order is a total order on all reads and writes
to that peripheral.[1]

The peripheral coherence order for a memory-mapped peripheral signifies the
order in which accesses arrive at the endpoint.  For a read or a write RW1
and a read or a write RW2 to the same peripheral, then RW1 will appear in
the peripheral coherence order for the peripheral before RW2 if either of
the following cases apply:
 1. RW1 and RW2 are accesses using Non-cacheable or Device attributes and
RW1 is Ordered-before RW2.
 2. RW1 and RW2 are accesses using Device-nGnRE or Device-nGnRnE attributes
and RW1 appears in program order before RW2.

On arm platforms, all the PCI resources are mapped to nGnRE device memory
[2], the above case 2 holds true, that means the peripheral coherence order
applies here and just a compiler barrier is sufficient for rte io barriers.

[1] Section B2.3.4 of ARMARM, https://developer.arm.com/docs/ddi0487/lates
t/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
tree/drivers/pci/pci-sysfs.c#n1204

Signed-off-by: Gavin Hu 
Reviewed-by: Steve Capper 
Reviewed-by: Phil Yang 
---
 lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h 
b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index 859ae12..fd63956 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -34,11 +34,11 @@ extern "C" {
 
 #define rte_smp_rmb() dmb(ishld)
 
-#define rte_io_mb() rte_mb()
+#define rte_io_mb() rte_compiler_barrier()
 
-#define rte_io_wmb() rte_wmb()
+#define rte_io_wmb() rte_compiler_barrier()
 
-#define rte_io_rmb() rte_rmb()
+#define rte_io_rmb() rte_compiler_barrier()
 
 #define rte_cio_wmb() dmb(oshst)
 
-- 
2.7.4

[dpdk-dev] [PATCH v2 3/3] crypto/virtio: virtual PCI requires smp barriers

[Gavin Hu]

Other than real PCI reads and writes to the device memory requiring
the io barriers, virtual pci memories are normal memory in the smp
configuration, and requires the smp barriers.

Since the smp barriers and io barriers are identical on x86 and PPC,
this change has only effect on aarch64.

As far as peripheral coherence order for ‘virtual’ devices, the arch
intent is that the Hypervisor view of things takes precedence – since
translations are made in holistic manner as the full stage1+stage2
regime, there is no such thing as a transaction taking on “EL1”
mapping as far as ordering. If the Hypervisor maps stage2 as Normal
but the OS at EL1 maps it as Device-nGnRE, then it’s Normal memory and
follows the ordering rules for Normal memory.

Signed-off-by: Gavin Hu 
---
 drivers/crypto/virtio/virtio_pci.c | 108 ++---
 1 file changed, 78 insertions(+), 30 deletions(-)

diff --git a/drivers/crypto/virtio/virtio_pci.c 
b/drivers/crypto/virtio/virtio_pci.c
index 8137b3c..dd8eda8 100644
--- a/drivers/crypto/virtio/virtio_pci.c
+++ b/drivers/crypto/virtio/virtio_pci.c
@@ -24,6 +24,54 @@
 #define PCI_CAP_ID_VNDR0x09
 #define PCI_CAP_ID_MSIX0x11
 
+static __rte_always_inline uint8_t
+virtio_pci_read8(const volatile void *addr)
+{
+   uint8_t val;
+   val = rte_read8_relaxed(addr);
+   rte_smp_rmb();
+   return val;
+}
+
+static __rte_always_inline uint16_t
+virtio_pci_read16(const volatile void *addr)
+{
+   uint16_t val;
+   val = rte_read16_relaxed(addr);
+   rte_smp_rmb();
+   return val;
+}
+
+static __rte_always_inline uint32_t
+virtio_pci_read32(const volatile void *addr)
+{
+   uint32_t val;
+   val = rte_read32_relaxed(addr);
+   rte_smp_rmb();
+   return val;
+}
+
+static __rte_always_inline void
+virtio_pci_write8(uint8_t value, volatile void *addr)
+{
+   rte_smp_wmb();
+   rte_write8_relaxed(value, addr);
+}
+
+static __rte_always_inline void
+virtio_pci_write16(uint16_t value, volatile void *addr)
+{
+   rte_smp_wmb();
+   rte_write16_relaxed(value, addr);
+}
+
+static __rte_always_inline void
+virtio_pci_write32(uint32_t value, volatile void *addr)
+{
+   rte_smp_wmb();
+   rte_write32_relaxed(value, addr);
+}
+
 /*
  * The remaining space is defined by each driver as the per-driver
  * configuration space.
@@ -52,8 +100,8 @@ check_vq_phys_addr_ok(struct virtqueue *vq)
 static inline void
 io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
 {
-   rte_write32(val & ((1ULL << 32) - 1), lo);
-   rte_write32(val >> 32,   hi);
+   virtio_pci_write32(val & ((1ULL << 32) - 1), lo);
+   virtio_pci_write32(val >> 32,hi);
 }
 
 static void
@@ -65,13 +113,13 @@ modern_read_dev_config(struct virtio_crypto_hw *hw, size_t 
offset,
uint8_t old_gen, new_gen;
 
do {
-   old_gen = rte_read8(&hw->common_cfg->config_generation);
+   old_gen = virtio_pci_read8(&hw->common_cfg->config_generation);
 
p = dst;
for (i = 0;  i < length; i++)
-   *p++ = rte_read8((uint8_t *)hw->dev_cfg + offset + i);
+   *p++ = virtio_pci_read8((uint8_t *)hw->dev_cfg + offset 
+ i);
 
-   new_gen = rte_read8(&hw->common_cfg->config_generation);
+   new_gen = virtio_pci_read8(&hw->common_cfg->config_generation);
} while (old_gen != new_gen);
 }
 
@@ -83,7 +131,7 @@ modern_write_dev_config(struct virtio_crypto_hw *hw, size_t 
offset,
const uint8_t *p = src;
 
for (i = 0;  i < length; i++)
-   rte_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + i));
+   virtio_pci_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + 
i));
 }
 
 static uint64_t
@@ -91,11 +139,11 @@ modern_get_features(struct virtio_crypto_hw *hw)
 {
uint32_t features_lo, features_hi;
 
-   rte_write32(0, &hw->common_cfg->device_feature_select);
-   features_lo = rte_read32(&hw->common_cfg->device_feature);
+   virtio_pci_write32(0, &hw->common_cfg->device_feature_select);
+   features_lo = virtio_pci_read32(&hw->common_cfg->device_feature);
 
-   rte_write32(1, &hw->common_cfg->device_feature_select);
-   features_hi = rte_read32(&hw->common_cfg->device_feature);
+   virtio_pci_write32(1, &hw->common_cfg->device_feature_select);
+   features_hi = virtio_pci_read32(&hw->common_cfg->device_feature);
 
return ((uint64_t)features_hi << 32) | features_lo;
 }
@@ -103,25 +151,25 @@ modern_get_features(struct virtio_crypto_hw *hw)
 static void
 modern_set_features(struct virtio_crypto_hw *hw, uint64_t features)
 {
-   rte_write32(0, &hw->common_cfg->guest_feature_select);
-   rte_write32(features & ((1ULL << 32) - 1),
+   virtio_pci_write32(0, &hw->common_cfg->guest_feature_select);
+   virtio_pci_write32(features & ((1ULL << 32) - 1),
&hw-

[dpdk-dev] [PATCH v3 0/5] drivers/net: cleanup Tx buffers

[Chenxu Di]

Add support to the drivers inclulding fm10k, i40e, ice, ixgbe
 and igb vf for the API rte_eth_tx_done_cleanup to
 force free consumed buffers on Tx ring.

---
v2:
added code about igb vf.
v3:
changed infomation of author

Chenxu Di (5):
  net/fm10k: cleanup Tx buffers
  net/i40e: cleanup Tx buffers
  net/ice: cleanup Tx buffers
  net/ixgbe: cleanup Tx buffers
  net/e1000: cleanup Tx buffers

 drivers/net/e1000/igb_ethdev.c|  1 +
 drivers/net/fm10k/fm10k.h |  2 ++
 drivers/net/fm10k/fm10k_ethdev.c  |  1 +
 drivers/net/fm10k/fm10k_rxtx.c| 45 +++
 drivers/net/i40e/i40e_ethdev.c|  1 +
 drivers/net/i40e/i40e_ethdev_vf.c |  1 +
 drivers/net/i40e/i40e_rxtx.c  | 40 +++
 drivers/net/i40e/i40e_rxtx.h  |  1 +
 drivers/net/ice/ice_ethdev.c  |  1 +
 drivers/net/ice/ice_rxtx.c| 41 
 drivers/net/ice/ice_rxtx.h|  1 +
 drivers/net/ixgbe/ixgbe_ethdev.c  |  2 ++
 drivers/net/ixgbe/ixgbe_rxtx.c| 39 +++
 drivers/net/ixgbe/ixgbe_rxtx.h|  2 ++
 14 files changed, 178 insertions(+)

-- 
2.17.1

[dpdk-dev] [PATCH v3 1/5] net/fm10k: cleanup Tx buffers

[Chenxu Di]

Add support to the fm10k driver for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/fm10k/fm10k.h|  2 ++
 drivers/net/fm10k/fm10k_ethdev.c |  1 +
 drivers/net/fm10k/fm10k_rxtx.c   | 45 
 3 files changed, 48 insertions(+)

diff --git a/drivers/net/fm10k/fm10k.h b/drivers/net/fm10k/fm10k.h
index 916b856ac..ddb1d64ec 100644
--- a/drivers/net/fm10k/fm10k.h
+++ b/drivers/net/fm10k/fm10k.h
@@ -342,6 +342,8 @@ uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf 
**tx_pkts,
 uint16_t fm10k_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
 
+int fm10k_tx_done_cleanup(void *txq, uint32_t free_cnt);
+
 int fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq);
 int fm10k_rx_vec_condition_check(struct rte_eth_dev *);
 void fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq);
diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c
index 407baa16c..c389c79de 100644
--- a/drivers/net/fm10k/fm10k_ethdev.c
+++ b/drivers/net/fm10k/fm10k_ethdev.c
@@ -2897,6 +2897,7 @@ static const struct eth_dev_ops fm10k_eth_dev_ops = {
.reta_query = fm10k_reta_query,
.rss_hash_update= fm10k_rss_hash_update,
.rss_hash_conf_get  = fm10k_rss_hash_conf_get,
+   .tx_done_cleanup= fm10k_tx_done_cleanup,
 };
 
 static int ftag_check_handler(__rte_unused const char *key,
diff --git a/drivers/net/fm10k/fm10k_rxtx.c b/drivers/net/fm10k/fm10k_rxtx.c
index 5c3112183..f67c5bf00 100644
--- a/drivers/net/fm10k/fm10k_rxtx.c
+++ b/drivers/net/fm10k/fm10k_rxtx.c
@@ -541,6 +541,51 @@ static inline void tx_free_bulk_mbuf(struct rte_mbuf 
**txep, int num)
}
 }
 
+int fm10k_tx_done_cleanup(void *txq, uint32_t free_cnt)
+{
+   struct fm10k_tx_queue *q = (struct fm10k_tx_queue *)txq;
+   uint16_t next_rs, count = 0;
+
+   if (q == NULL)
+   return -ENODEV;
+
+   next_rs = fifo_peek(&q->rs_tracker);
+   if (!(q->hw_ring[next_rs].flags & FM10K_TXD_FLAG_DONE))
+   return count;
+
+   /* the DONE flag is set on this descriptor so remove the ID
+* from the RS bit tracker and free the buffers
+*/
+   fifo_remove(&q->rs_tracker);
+
+   /* wrap around? if so, free buffers from last_free up to but NOT
+* including nb_desc
+*/
+   if (q->last_free > next_rs) {
+   count = q->nb_desc - q->last_free;
+   tx_free_bulk_mbuf(&q->sw_ring[q->last_free], count);
+   q->last_free = 0;
+
+   if (unlikely(count == (int)free_cnt))
+   return count;
+   }
+
+   /* adjust free descriptor count before the next loop */
+   q->nb_free += count + (next_rs + 1 - q->last_free);
+
+   /* free buffers from last_free, up to and including next_rs */
+   if (q->last_free <= next_rs) {
+   count = next_rs - q->last_free + 1;
+   tx_free_bulk_mbuf(&q->sw_ring[q->last_free], count);
+   q->last_free += count;
+   }
+
+   if (q->last_free == q->nb_desc)
+   q->last_free = 0;
+
+   return count;
+}
+
 static inline void tx_free_descriptors(struct fm10k_tx_queue *q)
 {
uint16_t next_rs, count = 0;
-- 
2.17.1

[dpdk-dev] [PATCH v3 5/5] net/e1000: cleanup Tx buffers

[Chenxu Di]

Add support to the igb vf for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/e1000/igb_ethdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index a3e30dbe5..647d5504f 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -446,6 +446,7 @@ static const struct eth_dev_ops igbvf_eth_dev_ops = {
.tx_descriptor_status = eth_igb_tx_descriptor_status,
.tx_queue_setup   = eth_igb_tx_queue_setup,
.tx_queue_release = eth_igb_tx_queue_release,
+   .tx_done_cleanup  = eth_igb_tx_done_cleanup,
.set_mc_addr_list = eth_igb_set_mc_addr_list,
.rxq_info_get = igb_rxq_info_get,
.txq_info_get = igb_txq_info_get,
-- 
2.17.1

[dpdk-dev] [PATCH v3 3/5] net/ice: cleanup Tx buffers

[Chenxu Di]

Add support to the ice driver for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/ice/ice_ethdev.c |  1 +
 drivers/net/ice/ice_rxtx.c   | 41 
 drivers/net/ice/ice_rxtx.h   |  1 +
 3 files changed, 43 insertions(+)

diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index de189daba..b55cdbf74 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -220,6 +220,7 @@ static const struct eth_dev_ops ice_eth_dev_ops = {
.filter_ctrl  = ice_dev_filter_ctrl,
.udp_tunnel_port_add  = ice_dev_udp_tunnel_port_add,
.udp_tunnel_port_del  = ice_dev_udp_tunnel_port_del,
+   .tx_done_cleanup  = ice_tx_done_cleanup,
 };
 
 /* store statistics names and its offset in stats structure */
diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c
index 2db174456..154cc5e5f 100644
--- a/drivers/net/ice/ice_rxtx.c
+++ b/drivers/net/ice/ice_rxtx.c
@@ -863,6 +863,47 @@ ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t 
tx_queue_id)
return 0;
 }
 
+
+int ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
+{
+   struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
+   struct ice_tx_entry *sw_ring;
+   uint16_t tx_id;/* Current segment being processed. */
+   uint16_t tx_cleaned;
+
+   int count = 0;
+
+   if (q == NULL)
+   return -ENODEV;
+
+   sw_ring = q->sw_ring;
+   tx_cleaned = q->last_desc_cleaned;
+   tx_id = sw_ring[q->last_desc_cleaned].next_id;
+   if ((q->tx_ring[tx_id].cmd_type_offset_bsz &
+   rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
+   rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
+   return 0;
+
+   do {
+   if (sw_ring[tx_id].mbuf == NULL)
+   break;
+
+   rte_pktmbuf_free_seg(sw_ring[tx_id].mbuf);
+   sw_ring[tx_id].mbuf = NULL;
+   sw_ring[tx_id].last_id = tx_id;
+
+   /* Move to next segemnt. */
+   tx_cleaned = tx_id;
+   tx_id = sw_ring[tx_id].next_id;
+   count++;
+   } while (count != (int)free_cnt);
+
+   q->nb_tx_free += (uint16_t)count;
+   q->last_desc_cleaned = tx_cleaned;
+
+   return count;
+}
+
 int
 ice_rx_queue_setup(struct rte_eth_dev *dev,
   uint16_t queue_idx,
diff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h
index 9e3d2cd07..8d4232a61 100644
--- a/drivers/net/ice/ice_rxtx.h
+++ b/drivers/net/ice/ice_rxtx.h
@@ -183,6 +183,7 @@ int ice_rx_descriptor_status(void *rx_queue, uint16_t 
offset);
 int ice_tx_descriptor_status(void *tx_queue, uint16_t offset);
 void ice_set_default_ptype_table(struct rte_eth_dev *dev);
 const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev);
+int ice_tx_done_cleanup(void *txq, uint32_t free_cnt);
 
 int ice_rx_vec_dev_check(struct rte_eth_dev *dev);
 int ice_tx_vec_dev_check(struct rte_eth_dev *dev);
-- 
2.17.1

[dpdk-dev] [PATCH v3 2/5] net/i40e: cleanup Tx buffers

[Chenxu Di]

Add support to the i40e driver for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/i40e/i40e_ethdev.c|  1 +
 drivers/net/i40e/i40e_ethdev_vf.c |  1 +
 drivers/net/i40e/i40e_rxtx.c  | 40 +++
 drivers/net/i40e/i40e_rxtx.h  |  1 +
 4 files changed, 43 insertions(+)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 5999c964b..fad47a942 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -522,6 +522,7 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {
.mac_addr_set = i40e_set_default_mac_addr,
.mtu_set  = i40e_dev_mtu_set,
.tm_ops_get   = i40e_tm_ops_get,
+   .tx_done_cleanup  = i40e_tx_done_cleanup,
 };
 
 /* store statistics names and its offset in stats structure */
diff --git a/drivers/net/i40e/i40e_ethdev_vf.c 
b/drivers/net/i40e/i40e_ethdev_vf.c
index 5dba0928b..0ca5417d7 100644
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -215,6 +215,7 @@ static const struct eth_dev_ops i40evf_eth_dev_ops = {
.rss_hash_conf_get= i40evf_dev_rss_hash_conf_get,
.mtu_set  = i40evf_dev_mtu_set,
.mac_addr_set = i40evf_set_default_mac_addr,
+   .tx_done_cleanup  = i40e_tx_done_cleanup,
 };
 
 /*
diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
index 17dc8c78f..3280a3ff6 100644
--- a/drivers/net/i40e/i40e_rxtx.c
+++ b/drivers/net/i40e/i40e_rxtx.c
@@ -2455,6 +2455,46 @@ i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
}
 }
 
+int i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
+{
+   struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
+   struct i40e_tx_entry *sw_ring;
+   uint16_t tx_id;/* Current segment being processed. */
+   uint16_t tx_cleaned;
+
+   int count = 0;
+
+   if (q == NULL)
+   return -ENODEV;
+
+   sw_ring = q->sw_ring;
+   tx_cleaned = q->last_desc_cleaned;
+   tx_id = sw_ring[q->last_desc_cleaned].next_id;
+   if ((q->tx_ring[tx_id].cmd_type_offset_bsz &
+   rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
+   rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
+   return 0;
+
+   do {
+   if (sw_ring[tx_id].mbuf == NULL)
+   break;
+
+   rte_pktmbuf_free_seg(sw_ring[tx_id].mbuf);
+   sw_ring[tx_id].mbuf = NULL;
+   sw_ring[tx_id].last_id = tx_id;
+
+   /* Move to next segemnt. */
+   tx_cleaned = tx_id;
+   tx_id = sw_ring[tx_id].next_id;
+   count++;
+   } while (count != (int)free_cnt);
+
+   q->nb_tx_free += (uint16_t)count;
+   q->last_desc_cleaned = tx_cleaned;
+
+   return count;
+}
+
 void
 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
 {
diff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h
index 2106bb355..8f11f011a 100644
--- a/drivers/net/i40e/i40e_rxtx.h
+++ b/drivers/net/i40e/i40e_rxtx.h
@@ -212,6 +212,7 @@ void i40e_dev_free_queues(struct rte_eth_dev *dev);
 void i40e_reset_rx_queue(struct i40e_rx_queue *rxq);
 void i40e_reset_tx_queue(struct i40e_tx_queue *txq);
 void i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq);
+int i40e_tx_done_cleanup(void *txq, uint32_t free_cnt);
 int i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq);
 void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
 
-- 
2.17.1

[dpdk-dev] [PATCH v3 4/5] net/ixgbe: cleanup Tx buffers

[Chenxu Di]

Add support to the ixgbe driver for the API rte_eth_tx_done_cleanup
 to force free consumed buffers on Tx ring.

Signed-off-by: Chenxu Di 
---
 drivers/net/ixgbe/ixgbe_ethdev.c |  2 ++
 drivers/net/ixgbe/ixgbe_rxtx.c   | 39 
 drivers/net/ixgbe/ixgbe_rxtx.h   |  2 ++
 3 files changed, 43 insertions(+)

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 2c6fd0f13..0091405db 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -601,6 +601,7 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {
.udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
.udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
.tm_ops_get   = ixgbe_tm_ops_get,
+   .tx_done_cleanup  = ixgbe_tx_done_cleanup,
 };
 
 /*
@@ -649,6 +650,7 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
.reta_query   = ixgbe_dev_rss_reta_query,
.rss_hash_update  = ixgbe_dev_rss_hash_update,
.rss_hash_conf_get= ixgbe_dev_rss_hash_conf_get,
+   .tx_done_cleanup  = ixgbe_tx_done_cleanup,
 };
 
 /* store statistics names and its offset in stats structure */
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index fa572d184..4823a9cf1 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -2306,6 +2306,45 @@ ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
}
 }
 
+int ixgbe_tx_done_cleanup(void *txq, uint32_t free_cnt)
+{
+   struct ixgbe_tx_queue *q = (struct ixgbe_tx_queue *)txq;
+   struct ixgbe_tx_entry *sw_ring;
+   uint16_t tx_id;/* Current segment being processed. */
+   uint16_t tx_cleaned;
+
+   int count = 0;
+
+   if (q == NULL)
+   return -ENODEV;
+
+   sw_ring = q->sw_ring;
+   tx_cleaned = q->last_desc_cleaned;
+   tx_id = sw_ring[q->last_desc_cleaned].next_id;
+   if (!(q->tx_ring[tx_id].wb.status &
+   IXGBE_TXD_STAT_DD))
+   return 0;
+
+   do {
+   if (sw_ring[tx_id].mbuf == NULL)
+   break;
+
+   rte_pktmbuf_free_seg(sw_ring[tx_id].mbuf);
+   sw_ring[tx_id].mbuf = NULL;
+   sw_ring[tx_id].last_id = tx_id;
+
+   /* Move to next segemnt. */
+   tx_cleaned = tx_id;
+   tx_id = sw_ring[tx_id].next_id;
+   count++;
+   } while (count != (int)free_cnt);
+
+   q->nb_tx_free += (uint16_t)count;
+   q->last_desc_cleaned = tx_cleaned;
+
+   return count;
+}
+
 static void __attribute__((cold))
 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
 {
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxtx.h
index 505d344b9..2c3770af6 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.h
+++ b/drivers/net/ixgbe/ixgbe_rxtx.h
@@ -285,6 +285,8 @@ int ixgbe_rx_vec_dev_conf_condition_check(struct 
rte_eth_dev *dev);
 int ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq);
 void ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq);
 
+int ixgbe_tx_done_cleanup(void *txq, uint32_t free_cnt);
+
 extern const uint32_t ptype_table[IXGBE_PACKET_TYPE_MAX];
 extern const uint32_t ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX];
 
-- 
2.17.1

Re: [dpdk-dev] [PATCH] mempool: fix mempool obj alignment for non x86

[Gavin Hu]

Hi Jerin,

It got two coding style warnings, otherwise, 
Reviewed-by: Gavin Hu 

WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#144: FILE: lib/librte_mempool/rte_mempool.c:84:
+arch_mem_object_align(unsigned obj_size)

WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#154: FILE: lib/librte_mempool/rte_mempool.c:106:
+arch_mem_object_align(unsigned obj_size)

Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for aarch64

[Jerin Jacob]

On Fri, Dec 20, 2019 at 8:40 AM Gavin Hu  wrote:
>
> Armv8's peripheral coherence order is a total order on all reads and writes
> to that peripheral.[1]
>
> The peripheral coherence order for a memory-mapped peripheral signifies the
> order in which accesses arrive at the endpoint.  For a read or a write RW1
> and a read or a write RW2 to the same peripheral, then RW1 will appear in
> the peripheral coherence order for the peripheral before RW2 if either of
> the following cases apply:
>  1. RW1 and RW2 are accesses using Non-cacheable or Device attributes and
> RW1 is Ordered-before RW2.
>  2. RW1 and RW2 are accesses using Device-nGnRE or Device-nGnRnE attributes
> and RW1 appears in program order before RW2.


This is true if RW1 and RW2 addresses are device memory. i.e the
registers in the  PCI bar address.
If RW1 is DDR address which is been used by the controller(say NIC
ring descriptor) then there will be an issue.
For example Intel i40e driver, the admin queue update in Host DDR
memory and it updates the doorbell.
In such a case, this patch will create an issue. Correct? Have you
checked this patch with ARM64 + XL710 controllers?

Some of the legacy code is missing such barriers, that's the reason
for adding rte_io_* barrier.

>
> On arm platforms, all the PCI resources are mapped to nGnRE device memory
> [2], the above case 2 holds true, that means the peripheral coherence order
> applies here and just a compiler barrier is sufficient for rte io barriers.
>
> [1] Section B2.3.4 of ARMARM, https://developer.arm.com/docs/ddi0487/lates
> t/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
> tree/drivers/pci/pci-sysfs.c#n1204
>
> Signed-off-by: Gavin Hu 
> Reviewed-by: Steve Capper 
> Reviewed-by: Phil Yang 
> ---
>  lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h 
> b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> index 859ae12..fd63956 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> @@ -34,11 +34,11 @@ extern "C" {
>
>  #define rte_smp_rmb() dmb(ishld)
>
> -#define rte_io_mb() rte_mb()
> +#define rte_io_mb() rte_compiler_barrier()
>
> -#define rte_io_wmb() rte_wmb()
> +#define rte_io_wmb() rte_compiler_barrier()
>
> -#define rte_io_rmb() rte_rmb()
> +#define rte_io_rmb() rte_compiler_barrier()
>
>  #define rte_cio_wmb() dmb(oshst)
>
> --
> 2.7.4
>

Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for aarch64

[Jerin Jacob]

On Fri, Dec 20, 2019 at 9:03 AM Jerin Jacob  wrote:
>
> On Fri, Dec 20, 2019 at 8:40 AM Gavin Hu  wrote:
> >
> > Armv8's peripheral coherence order is a total order on all reads and writes
> > to that peripheral.[1]
> >
> > The peripheral coherence order for a memory-mapped peripheral signifies the
> > order in which accesses arrive at the endpoint.  For a read or a write RW1
> > and a read or a write RW2 to the same peripheral, then RW1 will appear in
> > the peripheral coherence order for the peripheral before RW2 if either of
> > the following cases apply:
> >  1. RW1 and RW2 are accesses using Non-cacheable or Device attributes and
> > RW1 is Ordered-before RW2.
> >  2. RW1 and RW2 are accesses using Device-nGnRE or Device-nGnRnE attributes
> > and RW1 appears in program order before RW2.
>
>
> This is true if RW1 and RW2 addresses are device memory. i.e the
> registers in the  PCI bar address.
> If RW1 is DDR address which is been used by the controller(say NIC
> ring descriptor) then there will be an issue.
> For example Intel i40e driver, the admin queue update in Host DDR
> memory and it updates the doorbell.
> In such a case, this patch will create an issue. Correct? Have you
> checked this patch with ARM64 + XL710 controllers?
>
> Some of the legacy code is missing such barriers, that's the reason
> for adding rte_io_* barrier.


More details:

https://dev.dpdk.narkive.com/DpIRqDuy/dpdk-dev-patch-v2-i40e-fix-eth-i40e-dev-init-sequence-on-thunderx

>
> >
> > On arm platforms, all the PCI resources are mapped to nGnRE device memory
> > [2], the above case 2 holds true, that means the peripheral coherence order
> > applies here and just a compiler barrier is sufficient for rte io barriers.
> >
> > [1] Section B2.3.4 of ARMARM, https://developer.arm.com/docs/ddi0487/lates
> > t/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
> > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
> > tree/drivers/pci/pci-sysfs.c#n1204
> >
> > Signed-off-by: Gavin Hu 
> > Reviewed-by: Steve Capper 
> > Reviewed-by: Phil Yang 
> > ---
> >  lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h 
> > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > index 859ae12..fd63956 100644
> > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > @@ -34,11 +34,11 @@ extern "C" {
> >
> >  #define rte_smp_rmb() dmb(ishld)
> >
> > -#define rte_io_mb() rte_mb()
> > +#define rte_io_mb() rte_compiler_barrier()
> >
> > -#define rte_io_wmb() rte_wmb()
> > +#define rte_io_wmb() rte_compiler_barrier()
> >
> > -#define rte_io_rmb() rte_rmb()
> > +#define rte_io_rmb() rte_compiler_barrier()
> >
> >  #define rte_cio_wmb() dmb(oshst)
> >
> > --
> > 2.7.4
> >

Re: [dpdk-dev] [PATCH] mempool: fix mempool obj alignment for non x86

[Jerin Jacob]

On Fri, Dec 20, 2019 at 8:56 AM Gavin Hu  wrote:
>
> Hi Jerin,
>
> It got two coding style warnings, otherwise,
> Reviewed-by: Gavin Hu 

Thanks Gavin for review. Since the existing code is using "unsigned"
in that file, I thought of not change by this patch.
If someone thinks, It is better to change then I can send v2 by fixing
"unsigned" to "unsigned int" across the file as a first patch in the
series.

>
> WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
> #144: FILE: lib/librte_mempool/rte_mempool.c:84:
> +arch_mem_object_align(unsigned obj_size)
>
> WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
> #154: FILE: lib/librte_mempool/rte_mempool.c:106:
> +arch_mem_object_align(unsigned obj_size)

Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for aarch64

[Gavin Hu]

Hi Jerin,

Thanks for review, inline comments, 

> -Original Message-
> From: Jerin Jacob 
> Sent: Friday, December 20, 2019 11:38 AM
> To: Gavin Hu 
> Cc: dpdk-dev ; nd ; David Marchand
> ; tho...@monjalon.net;
> rasl...@mellanox.com; maxime.coque...@redhat.com;
> tiwei@intel.com; hemant.agra...@nxp.com; jer...@marvell.com;
> Pavan Nikhilesh ; Honnappa Nagarahalli
> ; Ruifeng Wang
> ; Phil Yang ; Joyce Kong
> ; Steve Capper 
> Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for
> aarch64
> 
> On Fri, Dec 20, 2019 at 9:03 AM Jerin Jacob 
> wrote:
> >
> > On Fri, Dec 20, 2019 at 8:40 AM Gavin Hu  wrote:
> > >
> > > Armv8's peripheral coherence order is a total order on all reads and
> writes
> > > to that peripheral.[1]
> > >
> > > The peripheral coherence order for a memory-mapped peripheral
> signifies the
> > > order in which accesses arrive at the endpoint.  For a read or a write
> RW1
> > > and a read or a write RW2 to the same peripheral, then RW1 will appear
> in
> > > the peripheral coherence order for the peripheral before RW2 if either
> of
> > > the following cases apply:
> > >  1. RW1 and RW2 are accesses using Non-cacheable or Device attributes
> and
> > > RW1 is Ordered-before RW2.
> > >  2. RW1 and RW2 are accesses using Device-nGnRE or Device-nGnRnE
> attributes
> > > and RW1 appears in program order before RW2.
> >
> >
> > This is true if RW1 and RW2 addresses are device memory. i.e the
> > registers in the  PCI bar address.
> > If RW1 is DDR address which is been used by the controller(say NIC
> > ring descriptor) then there will be an issue.
> > For example Intel i40e driver, the admin queue update in Host DDR
> > memory and it updates the doorbell.
> > In such a case, this patch will create an issue. Correct? Have you
> > checked this patch with ARM64 + XL710 controllers?

This patch relaxes the rte_io_*mb barriers for pure PCI device memory accesses.

For mixed accesses of DDR and PCI device memory, rte_smp_*mb(DMB ISH) is not 
sufficient.
But rte_cio_*mb(DMB OSH) is sufficient and can be used.

> >
> > Some of the legacy code is missing such barriers, that's the reason
> > for adding rte_io_* barrier.
> 
> 
> More details:
> 
> https://dev.dpdk.narkive.com/DpIRqDuy/dpdk-dev-patch-v2-i40e-fix-eth-
> i40e-dev-init-sequence-on-thunderx
> 
> >
> > >
> > > On arm platforms, all the PCI resources are mapped to nGnRE device
> memory
> > > [2], the above case 2 holds true, that means the peripheral coherence
> order
> > > applies here and just a compiler barrier is sufficient for rte io 
> > > barriers.
> > >
> > > [1] Section B2.3.4 of ARMARM,
> https://developer.arm.com/docs/ddi0487/lates
> > > t/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-
> profile
> > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
> > > tree/drivers/pci/pci-sysfs.c#n1204
> > >
> > > Signed-off-by: Gavin Hu 
> > > Reviewed-by: Steve Capper 
> > > Reviewed-by: Phil Yang 
> > > ---
> > >  lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 +++---
> > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > index 859ae12..fd63956 100644
> > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > @@ -34,11 +34,11 @@ extern "C" {
> > >
> > >  #define rte_smp_rmb() dmb(ishld)
> > >
> > > -#define rte_io_mb() rte_mb()
> > > +#define rte_io_mb() rte_compiler_barrier()
> > >
> > > -#define rte_io_wmb() rte_wmb()
> > > +#define rte_io_wmb() rte_compiler_barrier()
> > >
> > > -#define rte_io_rmb() rte_rmb()
> > > +#define rte_io_rmb() rte_compiler_barrier()
> > >
> > >  #define rte_cio_wmb() dmb(oshst)
> > >
> > > --
> > > 2.7.4
> > >

Re: [dpdk-dev] [PATCH v2 1/3] eal: introduce structure marker typedefs

[Gavin Hu]

Series-reviewed-by: Gavin Hu 

Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for aarch64

[Jerin Jacob]

On Fri, Dec 20, 2019 at 9:49 AM Gavin Hu  wrote:
>
> Hi Jerin,
>
> Thanks for review, inline comments,
>
> > -Original Message-
> > From: Jerin Jacob 
> > Sent: Friday, December 20, 2019 11:38 AM
> > To: Gavin Hu 
> > Cc: dpdk-dev ; nd ; David Marchand
> > ; tho...@monjalon.net;
> > rasl...@mellanox.com; maxime.coque...@redhat.com;
> > tiwei@intel.com; hemant.agra...@nxp.com; jer...@marvell.com;
> > Pavan Nikhilesh ; Honnappa Nagarahalli
> > ; Ruifeng Wang
> > ; Phil Yang ; Joyce Kong
> > ; Steve Capper 
> > Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for
> > aarch64
> >
> > On Fri, Dec 20, 2019 at 9:03 AM Jerin Jacob 
> > wrote:
> > >
> > > On Fri, Dec 20, 2019 at 8:40 AM Gavin Hu  wrote:
> > > >
> > > > Armv8's peripheral coherence order is a total order on all reads and
> > writes
> > > > to that peripheral.[1]
> > > >
> > > > The peripheral coherence order for a memory-mapped peripheral
> > signifies the
> > > > order in which accesses arrive at the endpoint.  For a read or a write
> > RW1
> > > > and a read or a write RW2 to the same peripheral, then RW1 will appear
> > in
> > > > the peripheral coherence order for the peripheral before RW2 if either
> > of
> > > > the following cases apply:
> > > >  1. RW1 and RW2 are accesses using Non-cacheable or Device attributes
> > and
> > > > RW1 is Ordered-before RW2.
> > > >  2. RW1 and RW2 are accesses using Device-nGnRE or Device-nGnRnE
> > attributes
> > > > and RW1 appears in program order before RW2.
> > >
> > >
> > > This is true if RW1 and RW2 addresses are device memory. i.e the
> > > registers in the  PCI bar address.
> > > If RW1 is DDR address which is been used by the controller(say NIC
> > > ring descriptor) then there will be an issue.
> > > For example Intel i40e driver, the admin queue update in Host DDR
> > > memory and it updates the doorbell.
> > > In such a case, this patch will create an issue. Correct? Have you
> > > checked this patch with ARM64 + XL710 controllers?
>
> This patch relaxes the rte_io_*mb barriers for pure PCI device memory 
> accesses.

Yes. This would break cases for mixed access fro i40e drivers.

>
> For mixed accesses of DDR and PCI device memory, rte_smp_*mb(DMB ISH) is not 
> sufficient.
> But rte_cio_*mb(DMB OSH) is sufficient and can be used.

Yes. Let me share a bit of history.

1) There are a lot of drivers(initially developed in x86) that have
mixed access and don't have any barriers as x86 does not need it.
2) rte_io introduced to fix that
3) Item (2) introduced the performance issues in the fast path as an
optimization rte_cio_* introduced.

So in the current of the scheme of things, we have APIs to FIX
portability issue(rte_io) and performance issue(rte_cio).
IMO, we may not need any change in infra code now. If you think, the
documentation is missing then we can enhance it.
If we make infra change then again drivers needs to be updated and tested.

[dpdk-dev] [PATCH v7 00/17] lib/ring: APIs to support custom element size

[Honnappa Nagarahalli]

The current rte_ring hard-codes the type of the ring element to 'void *',
hence the size of the element is hard-coded to 32b/64b. Since the ring
element type is not an input to rte_ring APIs, it results in couple
of issues:

1) If an application requires to store an element which is not 64b, it
   needs to write its own ring APIs similar to rte_event_ring APIs. This
   creates additional burden on the programmers, who end up making
   work-arounds and often waste memory.
2) If there are multiple libraries that store elements of the same
   type, currently they would have to write their own rte_ring APIs. This
   results in code duplication.

This patch adds new APIs to support configurable ring element size.
The APIs support custom element sizes by allowing to define the ring
element to be a multiple of 32b.

The aim is to achieve same performance as the existing ring
implementation.

The changes to test cases are significant. The patches 3/17 to 15/17
are created to help with the review. Otherwise, they can be quashed
into a single commit.

v7
 - Merged the test cases to test both legacy APIs and rte_ring_xxx_elem APIs
   without code duplication (Konstantin, Olivier)
 - Performance test cases are merged as well (Konstantin, Olivier)
 - Macros to copy elements are converted into inline functions (Olivier)
 - Added back the changes to hash and event libraries

v6
 - Labelled as RFC to indicate the better status
 - Added unit tests to test the rte_ring_xxx_elem APIs
 - Corrected 'macro based partial memcpy' (5/6) patch
 - Added Konstantin's method after correction (6/6)
 - Check Patch shows significant warnings and errors mainly due
   copying code from existing test cases. None of them are harmful.
   I will fix them once we have an agreement.

v5
 - Use memcpy for chunks of 32B (Konstantin).
 - Both 'ring_perf_autotest' and 'ring_perf_elem_autotest' are available
   to compare the results easily.
 - Copying without memcpy is also available in 1/3, if anyone wants to
   experiment on their platform.
 - Added other platform owners to test on their respective platforms.

v4
 - Few fixes after more performance testing

v3
 - Removed macro-fest and used inline functions
   (Stephen, Bruce)

v2
 - Change Event Ring implementation to use ring templates
   (Jerin, Pavan)

Honnappa Nagarahalli (17):
  test/ring: use division for cycle count calculation
  lib/ring: apis to support configurable element size
  test/ring: add functional tests for rte_ring_xxx_elem APIs
  test/ring: test burst APIs with random empty-full test case
  test/ring: add default, single element test cases
  test/ring: rte_ring_xxx_elem test cases for exact size ring
  test/ring: negative test cases for rte_ring_xxx_elem APIs
  test/ring: remove duplicate test cases
  test/ring: removed unused variable synchro
  test/ring: modify single element enq/deq perf test cases
  test/ring: modify burst enq/deq perf test cases
  test/ring: modify bulk enq/deq perf test cases
  test/ring: modify bulk empty deq perf test cases
  test/ring: modify multi-lcore perf test cases
  test/ring: adjust run-on-all-cores perf test cases
  lib/hash: use ring with 32b element size to save memory
  lib/eventdev: use custom element size ring for event rings

 app/test/test_ring.c | 1227 +++---
 app/test/test_ring.h |  203 +
 app/test/test_ring_perf.c|  434 +
 lib/librte_eventdev/rte_event_ring.c |  147 +--
 lib/librte_eventdev/rte_event_ring.h |   45 +-
 lib/librte_hash/rte_cuckoo_hash.c|   97 +-
 lib/librte_hash/rte_cuckoo_hash.h|2 +-
 lib/librte_ring/Makefile |3 +-
 lib/librte_ring/meson.build  |4 +
 lib/librte_ring/rte_ring.c   |   41 +-
 lib/librte_ring/rte_ring.h   |1 +
 lib/librte_ring/rte_ring_elem.h  | 1002 +
 lib/librte_ring/rte_ring_version.map |2 +
 13 files changed, 2102 insertions(+), 1106 deletions(-)
 create mode 100644 app/test/test_ring.h
 create mode 100644 lib/librte_ring/rte_ring_elem.h

-- 
2.17.1

[dpdk-dev] [PATCH v7 05/17] test/ring: add default, single element test cases

[Honnappa Nagarahalli]

Add default, single element test cases for rte_ring_xxx_elem
APIs. The burst APIs are kept as is since they are being tested
with a ring created with SP/SC flags. They are further enhanced
with bulk APIs.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring.c | 129 +++
 1 file changed, 81 insertions(+), 48 deletions(-)

diff --git a/app/test/test_ring.c b/app/test/test_ring.c
index d4f40ad20..1025097c8 100644
--- a/app/test/test_ring.c
+++ b/app/test/test_ring.c
@@ -620,78 +620,111 @@ test_lookup_null(void)
 }
 
 /*
- * it tests some more basic ring operations
+ * Test default, single element, bulk and burst APIs
  */
 static int
 test_ring_basic_ex(void)
 {
int ret = -1;
-   unsigned i;
+   unsigned int i, j;
struct rte_ring *rp = NULL;
-   void **obj = NULL;
+   void *obj = NULL;
 
-   obj = rte_calloc("test_ring_basic_ex_malloc", RING_SIZE, sizeof(void 
*), 0);
-   if (obj == NULL) {
-   printf("test_ring_basic_ex fail to rte_malloc\n");
-   goto fail_test;
-   }
+   for (i = 0; i < RTE_DIM(esize); i++) {
+   obj = test_ring_calloc(RING_SIZE, esize[i]);
+   if (obj == NULL) {
+   printf("test_ring_basic_ex fail to rte_malloc\n");
+   goto fail_test;
+   }
 
-   rp = rte_ring_create("test_ring_basic_ex", RING_SIZE, SOCKET_ID_ANY,
-   RING_F_SP_ENQ | RING_F_SC_DEQ);
-   if (rp == NULL) {
-   printf("test_ring_basic_ex fail to create ring\n");
-   goto fail_test;
-   }
+   TEST_RING_CREATE("test_ring_basic_ex", esize[i], RING_SIZE,
+   SOCKET_ID_ANY,
+   RING_F_SP_ENQ | RING_F_SC_DEQ, rp);
+   if (rp == NULL) {
+   printf("test_ring_basic_ex fail to create ring\n");
+   goto fail_test;
+   }
 
-   if (rte_ring_lookup("test_ring_basic_ex") != rp) {
-   goto fail_test;
-   }
+   if (rte_ring_lookup("test_ring_basic_ex") != rp) {
+   printf("test_ring_basic_ex ring is not found\n");
+   goto fail_test;
+   }
 
-   if (rte_ring_empty(rp) != 1) {
-   printf("test_ring_basic_ex ring is not empty but it should 
be\n");
-   goto fail_test;
-   }
+   if (rte_ring_empty(rp) != 1) {
+   printf("test_ring_basic_ex ring is not empty but it 
should be\n");
+   goto fail_test;
+   }
 
-   printf("%u ring entries are now free\n", rte_ring_free_count(rp));
+   printf("%u ring entries are now free\n",
+   rte_ring_free_count(rp));
 
-   for (i = 0; i < RING_SIZE; i ++) {
-   rte_ring_enqueue(rp, obj[i]);
-   }
+   for (j = 0; j < RING_SIZE; j++) {
+   TEST_RING_ENQUEUE(rp, obj, esize[i], 1, ret,
+   TEST_RING_N | TEST_RING_SL);
+   }
 
-   if (rte_ring_full(rp) != 1) {
-   printf("test_ring_basic_ex ring is not full but it should 
be\n");
-   goto fail_test;
-   }
+   if (rte_ring_full(rp) != 1) {
+   printf("test_ring_basic_ex ring is not full but it 
should be\n");
+   goto fail_test;
+   }
 
-   for (i = 0; i < RING_SIZE; i ++) {
-   rte_ring_dequeue(rp, &obj[i]);
-   }
+   for (j = 0; j < RING_SIZE; j++) {
+   TEST_RING_DEQUEUE(rp, obj, esize[i], 1, ret,
+   TEST_RING_N | TEST_RING_SL);
+   }
 
-   if (rte_ring_empty(rp) != 1) {
-   printf("test_ring_basic_ex ring is not empty but it should 
be\n");
-   goto fail_test;
-   }
+   if (rte_ring_empty(rp) != 1) {
+   printf("test_ring_basic_ex ring is not empty but it 
should be\n");
+   goto fail_test;
+   }
 
-   /* Covering the ring burst operation */
-   ret = rte_ring_enqueue_burst(rp, obj, 2, NULL);
-   if (ret != 2) {
-   printf("test_ring_basic_ex: rte_ring_enqueue_burst fails \n");
-   goto fail_test;
-   }
+   /* Following tests use the configured flags to decide
+* SP/SC or MP/MC.
+*/
+   /* Covering the ring burst operation */
+   TEST_RING_ENQUEUE(rp, obj, esize[i], 2, ret,
+   TEST_RING_N | TEST_RING_BR);
+   if (ret != 2) {
+   printf("test_ring_basic_ex: rte_ring_enqueue_burst 
fails\n");
+   goto fail_test;
+   }
+
+ 

[dpdk-dev] [PATCH v7 04/17] test/ring: test burst APIs with random empty-full test case

[Honnappa Nagarahalli]

The random empty-full test case should be tested with burst APIs
as well. Hence the test case is consolidated in
test_ring_burst_bulk_tests function.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring.c | 91 +---
 1 file changed, 43 insertions(+), 48 deletions(-)

diff --git a/app/test/test_ring.c b/app/test/test_ring.c
index e7a8b468b..d4f40ad20 100644
--- a/app/test/test_ring.c
+++ b/app/test/test_ring.c
@@ -113,50 +113,6 @@ test_ring_print_test_string(const char *istr, unsigned int 
api_type, int esize)
printf("burst\n");
 }
 
-/*
- * helper routine for test_ring_basic
- */
-static int
-test_ring_basic_full_empty(struct rte_ring *r, void * const src[], void *dst[])
-{
-   unsigned i, rand;
-   const unsigned rsz = RING_SIZE - 1;
-
-   printf("Basic full/empty test\n");
-
-   for (i = 0; TEST_RING_FULL_EMTPY_ITER != i; i++) {
-
-   /* random shift in the ring */
-   rand = RTE_MAX(rte_rand() % RING_SIZE, 1UL);
-   printf("%s: iteration %u, random shift: %u;\n",
-   __func__, i, rand);
-   TEST_RING_VERIFY(rte_ring_enqueue_bulk(r, src, rand,
-   NULL) != 0);
-   TEST_RING_VERIFY(rte_ring_dequeue_bulk(r, dst, rand,
-   NULL) == rand);
-
-   /* fill the ring */
-   TEST_RING_VERIFY(rte_ring_enqueue_bulk(r, src, rsz, NULL) != 0);
-   TEST_RING_VERIFY(0 == rte_ring_free_count(r));
-   TEST_RING_VERIFY(rsz == rte_ring_count(r));
-   TEST_RING_VERIFY(rte_ring_full(r));
-   TEST_RING_VERIFY(0 == rte_ring_empty(r));
-
-   /* empty the ring */
-   TEST_RING_VERIFY(rte_ring_dequeue_bulk(r, dst, rsz,
-   NULL) == rsz);
-   TEST_RING_VERIFY(rsz == rte_ring_free_count(r));
-   TEST_RING_VERIFY(0 == rte_ring_count(r));
-   TEST_RING_VERIFY(0 == rte_ring_full(r));
-   TEST_RING_VERIFY(rte_ring_empty(r));
-
-   /* check data */
-   TEST_RING_VERIFY(0 == memcmp(src, dst, rsz));
-   rte_ring_dump(stdout, r);
-   }
-   return 0;
-}
-
 static int
 test_ring_basic(struct rte_ring *r)
 {
@@ -294,9 +250,6 @@ test_ring_basic(struct rte_ring *r)
goto fail;
}
 
-   if (test_ring_basic_full_empty(r, src, dst) != 0)
-   goto fail;
-
cur_src = src;
cur_dst = dst;
 
@@ -371,6 +324,8 @@ test_ring_burst_bulk_tests(unsigned int api_type)
int ret;
unsigned int i, j;
unsigned int num_elems;
+   int rand;
+   const unsigned int rsz = RING_SIZE - 1;
 
for (i = 0; i < RTE_DIM(esize); i++) {
test_ring_print_test_string("Test standard ring", api_type,
@@ -483,7 +438,6 @@ test_ring_burst_bulk_tests(unsigned int api_type)
goto fail;
TEST_RING_INCP(cur_src, esize[i], 2);
 
-
printf("Enqueue the remaining entries = MAX_BULK - 3\n");
/* Bulk APIs enqueue exact number of elements */
if ((api_type & TEST_RING_BL) == TEST_RING_BL)
@@ -546,6 +500,47 @@ test_ring_burst_bulk_tests(unsigned int api_type)
goto fail;
}
 
+   printf("Random full/empty test\n");
+   cur_src = src;
+   cur_dst = dst;
+
+   for (j = 0; j != TEST_RING_FULL_EMTPY_ITER; j++) {
+   /* random shift in the ring */
+   rand = RTE_MAX(rte_rand() % RING_SIZE, 1UL);
+   printf("%s: iteration %u, random shift: %u;\n",
+   __func__, i, rand);
+   TEST_RING_ENQUEUE(r, cur_src, esize[i], rand,
+   ret, api_type);
+   TEST_RING_VERIFY(ret != 0);
+
+   TEST_RING_DEQUEUE(r, cur_dst, esize[i], rand,
+   ret, api_type);
+   TEST_RING_VERIFY(ret == rand);
+
+   /* fill the ring */
+   TEST_RING_ENQUEUE(r, cur_src, esize[i], rsz,
+   ret, api_type);
+   TEST_RING_VERIFY(ret != 0);
+
+   TEST_RING_VERIFY(rte_ring_free_count(r) == 0);
+   TEST_RING_VERIFY(rsz == rte_ring_count(r));
+   TEST_RING_VERIFY(rte_ring_full(r));
+   TEST_RING_VERIFY(rte_ring_empty(r) == 0);
+
+   /* empty the ring */
+   TEST_RING_DEQUEUE(r, cur_dst, esize[i], rsz,
+   ret, api_type);
+   TEST_RING_VERIFY(ret == (int)rsz);
+ 

[dpdk-dev] [PATCH v7 06/17] test/ring: rte_ring_xxx_elem test cases for exact size ring

[Honnappa Nagarahalli]

Test cases for the exact size ring are changed to test
rte_ring_xxx_elem APIs.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring.c | 147 ++-
 1 file changed, 89 insertions(+), 58 deletions(-)

diff --git a/app/test/test_ring.c b/app/test/test_ring.c
index 1025097c8..294e3ee10 100644
--- a/app/test/test_ring.c
+++ b/app/test/test_ring.c
@@ -727,75 +727,106 @@ test_ring_basic_ex(void)
return -1;
 }
 
+/*
+ * Basic test cases with exact size ring.
+ */
 static int
 test_ring_with_exact_size(void)
 {
-   struct rte_ring *std_ring = NULL, *exact_sz_ring = NULL;
-   void *ptr_array[16];
-   static const unsigned int ring_sz = RTE_DIM(ptr_array);
-   unsigned int i;
+   struct rte_ring *std_r = NULL, *exact_sz_r = NULL;
+   void *obj;
+   const unsigned int ring_sz = 16;
+   unsigned int i, j;
int ret = -1;
 
-   std_ring = rte_ring_create("std", ring_sz, rte_socket_id(),
-   RING_F_SP_ENQ | RING_F_SC_DEQ);
-   if (std_ring == NULL) {
-   printf("%s: error, can't create std ring\n", __func__);
-   goto end;
-   }
-   exact_sz_ring = rte_ring_create("exact sz", ring_sz, rte_socket_id(),
-   RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ);
-   if (exact_sz_ring == NULL) {
-   printf("%s: error, can't create exact size ring\n", __func__);
-   goto end;
-   }
-
-   /*
-* Check that the exact size ring is bigger than the standard ring
-*/
-   if (rte_ring_get_size(std_ring) >= rte_ring_get_size(exact_sz_ring)) {
-   printf("%s: error, std ring (size: %u) is not smaller than 
exact size one (size %u)\n",
-   __func__,
-   rte_ring_get_size(std_ring),
-   rte_ring_get_size(exact_sz_ring));
-   goto end;
-   }
-   /*
-* check that the exact_sz_ring can hold one more element than the
-* standard ring. (16 vs 15 elements)
-*/
-   for (i = 0; i < ring_sz - 1; i++) {
-   rte_ring_enqueue(std_ring, NULL);
-   rte_ring_enqueue(exact_sz_ring, NULL);
-   }
-   if (rte_ring_enqueue(std_ring, NULL) != -ENOBUFS) {
-   printf("%s: error, unexpected successful enqueue\n", __func__);
-   goto end;
-   }
-   if (rte_ring_enqueue(exact_sz_ring, NULL) == -ENOBUFS) {
-   printf("%s: error, enqueue failed\n", __func__);
-   goto end;
-   }
+   for (i = 0; i < RTE_DIM(esize); i++) {
+   test_ring_print_test_string("Test exact size ring",
+   TEST_RING_IGNORE_API_TYPE,
+   esize[i]);
+
+   /* alloc object pointers */
+   obj = test_ring_calloc(16, esize[i]);
+   if (obj == NULL)
+   goto test_fail;
+
+   TEST_RING_CREATE("std", esize[i], ring_sz, rte_socket_id(),
+   RING_F_SP_ENQ | RING_F_SC_DEQ, std_r);
+   if (std_r == NULL) {
+   printf("%s: error, can't create std ring\n", __func__);
+   goto test_fail;
+   }
+   TEST_RING_CREATE("exact sz", esize[i], ring_sz, rte_socket_id(),
+   RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ,
+   exact_sz_r);
+   if (exact_sz_r == NULL) {
+   printf("%s: error, can't create exact size ring\n",
+   __func__);
+   goto test_fail;
+   }
 
-   /* check that dequeue returns the expected number of elements */
-   if (rte_ring_dequeue_burst(exact_sz_ring, ptr_array,
-   RTE_DIM(ptr_array), NULL) != ring_sz) {
-   printf("%s: error, failed to dequeue expected nb of elements\n",
+   /*
+* Check that the exact size ring is bigger than the
+* standard ring
+*/
+   if (rte_ring_get_size(std_r) >= rte_ring_get_size(exact_sz_r)) {
+   printf("%s: error, std ring (size: %u) is not smaller 
than exact size one (size %u)\n",
+   __func__,
+   rte_ring_get_size(std_r),
+   rte_ring_get_size(exact_sz_r));
+   goto test_fail;
+   }
+   /*
+* check that the exact_sz_ring can hold one more element
+* than the standard ring. (16 vs 15 elements)
+*/
+   for (j = 0; j < ring_sz - 1; j++) {
+   TEST_RING_ENQUEUE(std_r, obj, esize[i], 1, ret,
+

[dpdk-dev] [PATCH v7 03/17] test/ring: add functional tests for rte_ring_xxx_elem APIs

[Honnappa Nagarahalli]

Add basic infrastructure to test rte_ring_xxx_elem APIs. Add
test cases for testing burst and bulk tests.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring.c | 466 ---
 app/test/test_ring.h | 203 +++
 2 files changed, 419 insertions(+), 250 deletions(-)
 create mode 100644 app/test/test_ring.h

diff --git a/app/test/test_ring.c b/app/test/test_ring.c
index aaf1e70ad..e7a8b468b 100644
--- a/app/test/test_ring.c
+++ b/app/test/test_ring.c
@@ -23,11 +23,13 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
 #include "test.h"
+#include "test_ring.h"
 
 /*
  * Ring
@@ -67,6 +69,50 @@ static rte_atomic32_t synchro;
 
 #defineTEST_RING_FULL_EMTPY_ITER   8
 
+static int esize[] = {-1, 4, 8, 16};
+
+static void
+test_ring_mem_init(void *obj, unsigned int count, int esize)
+{
+   unsigned int i;
+
+   /* Legacy queue APIs? */
+   if (esize == -1)
+   for (i = 0; i < count; i++)
+   ((void **)obj)[i] = (void *)(unsigned long)i;
+   else
+   for (i = 0; i < (count * esize / sizeof(uint32_t)); i++)
+   ((uint32_t *)obj)[i] = i;
+}
+
+static void
+test_ring_print_test_string(const char *istr, unsigned int api_type, int esize)
+{
+   printf("\n%s: ", istr);
+
+   if (esize == -1)
+   printf("legacy APIs: ");
+   else
+   printf("elem APIs: element size %dB ", esize);
+
+   if (api_type == TEST_RING_IGNORE_API_TYPE)
+   return;
+
+   if ((api_type & TEST_RING_N) == TEST_RING_N)
+   printf(": default enqueue/dequeue: ");
+   else if ((api_type & TEST_RING_S) == TEST_RING_S)
+   printf(": SP/SC: ");
+   else if ((api_type & TEST_RING_M) == TEST_RING_M)
+   printf(": MP/MC: ");
+
+   if ((api_type & TEST_RING_SL) == TEST_RING_SL)
+   printf("single\n");
+   else if ((api_type & TEST_RING_BL) == TEST_RING_BL)
+   printf("bulk\n");
+   else if ((api_type & TEST_RING_BR) == TEST_RING_BR)
+   printf("burst\n");
+}
+
 /*
  * helper routine for test_ring_basic
  */
@@ -314,286 +360,203 @@ test_ring_basic(struct rte_ring *r)
return -1;
 }
 
+/*
+ * Burst and bulk operations with sp/sc, mp/mc and default (during creation)
+ */
 static int
-test_ring_burst_basic(struct rte_ring *r)
+test_ring_burst_bulk_tests(unsigned int api_type)
 {
+   struct rte_ring *r;
void **src = NULL, **cur_src = NULL, **dst = NULL, **cur_dst = NULL;
int ret;
-   unsigned i;
+   unsigned int i, j;
+   unsigned int num_elems;
 
-   /* alloc dummy object pointers */
-   src = malloc(RING_SIZE*2*sizeof(void *));
-   if (src == NULL)
-   goto fail;
-
-   for (i = 0; i < RING_SIZE*2 ; i++) {
-   src[i] = (void *)(unsigned long)i;
-   }
-   cur_src = src;
+   for (i = 0; i < RTE_DIM(esize); i++) {
+   test_ring_print_test_string("Test standard ring", api_type,
+   esize[i]);
 
-   /* alloc some room for copied objects */
-   dst = malloc(RING_SIZE*2*sizeof(void *));
-   if (dst == NULL)
-   goto fail;
+   /* Create the ring */
+   TEST_RING_CREATE("test_ring_burst_bulk_tests", esize[i],
+   RING_SIZE, SOCKET_ID_ANY, 0, r);
 
-   memset(dst, 0, RING_SIZE*2*sizeof(void *));
-   cur_dst = dst;
-
-   printf("Test SP & SC basic functions \n");
-   printf("enqueue 1 obj\n");
-   ret = rte_ring_sp_enqueue_burst(r, cur_src, 1, NULL);
-   cur_src += 1;
-   if (ret != 1)
-   goto fail;
-
-   printf("enqueue 2 objs\n");
-   ret = rte_ring_sp_enqueue_burst(r, cur_src, 2, NULL);
-   cur_src += 2;
-   if (ret != 2)
-   goto fail;
-
-   printf("enqueue MAX_BULK objs\n");
-   ret = rte_ring_sp_enqueue_burst(r, cur_src, MAX_BULK, NULL);
-   cur_src += MAX_BULK;
-   if (ret != MAX_BULK)
-   goto fail;
-
-   printf("dequeue 1 obj\n");
-   ret = rte_ring_sc_dequeue_burst(r, cur_dst, 1, NULL);
-   cur_dst += 1;
-   if (ret != 1)
-   goto fail;
-
-   printf("dequeue 2 objs\n");
-   ret = rte_ring_sc_dequeue_burst(r, cur_dst, 2, NULL);
-   cur_dst += 2;
-   if (ret != 2)
-   goto fail;
+   /* alloc dummy object pointers */
+   src = test_ring_calloc(RING_SIZE * 2, esize[i]);
+   if (src == NULL)
+   goto fail;
+   test_ring_mem_init(src, RING_SIZE * 2, esize[i]);
+   cur_src = src;
 
-   printf("dequeue MAX_BULK objs\n");
-   ret = rte_ring_sc_dequeue_burst(r, cur_dst, MAX_BULK, NULL);
-   cur_dst += MAX_BULK;
-   if (ret != MAX_BULK)
-   goto fail;

[dpdk-dev] [PATCH v7 07/17] test/ring: negative test cases for rte_ring_xxx_elem APIs

[Honnappa Nagarahalli]

All the negative test cases are consolidated into a single
function. This provides the ability to add test cases for
rte_ring_xxx_elem APIs easily.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring.c | 176 ++-
 1 file changed, 91 insertions(+), 85 deletions(-)

diff --git a/app/test/test_ring.c b/app/test/test_ring.c
index 294e3ee10..552e8b53a 100644
--- a/app/test/test_ring.c
+++ b/app/test/test_ring.c
@@ -113,6 +113,93 @@ test_ring_print_test_string(const char *istr, unsigned int 
api_type, int esize)
printf("burst\n");
 }
 
+/*
+ * Various negative test cases.
+ */
+static int
+test_ring_negative_tests(void)
+{
+   struct rte_ring *rp = NULL;
+   struct rte_ring *rt = NULL;
+   unsigned int i;
+
+   /* Test with esize not a multiple of 4 */
+   TEST_RING_CREATE("test_bad_element_size", 23,
+   RING_SIZE + 1, SOCKET_ID_ANY, 0, rp);
+   if (rp != NULL) {
+   printf("Test failed to detect invalid element size\n");
+   goto test_fail;
+   }
+
+
+   for (i = 0; i < RTE_DIM(esize); i++) {
+   /* Test if ring size is not power of 2 */
+   TEST_RING_CREATE("test_bad_ring_size", esize[i],
+   RING_SIZE + 1, SOCKET_ID_ANY, 0, rp);
+   if (rp != NULL) {
+   printf("Test failed to detect odd count\n");
+   goto test_fail;
+   }
+
+   /* Test if ring size is exceeding the limit */
+   TEST_RING_CREATE("test_bad_ring_size", esize[i],
+   RTE_RING_SZ_MASK + 1, SOCKET_ID_ANY,
+   0, rp);
+   if (rp != NULL) {
+   printf("Test failed to detect limits\n");
+   goto test_fail;
+   }
+
+   /* Tests if lookup returns NULL on non-existing ring */
+   rp = rte_ring_lookup("ring_not_found");
+   if (rp != NULL && rte_errno != ENOENT) {
+   printf("Test failed to detect NULL ring lookup\n");
+   goto test_fail;
+   }
+
+   /* Test to if a non-power of 2 count causes the create
+* function to fail correctly
+*/
+   TEST_RING_CREATE("test_ring_count", esize[i], 4097,
+   SOCKET_ID_ANY, 0, rp);
+   if (rp != NULL)
+   goto test_fail;
+
+   TEST_RING_CREATE("test_ring_negative", esize[i], RING_SIZE,
+   SOCKET_ID_ANY,
+   RING_F_SP_ENQ | RING_F_SC_DEQ, rp);
+   if (rp == NULL) {
+   printf("test_ring_negative fail to create ring\n");
+   goto test_fail;
+   }
+
+   if (rte_ring_lookup("test_ring_negative") != rp)
+   goto test_fail;
+
+   if (rte_ring_empty(rp) != 1) {
+   printf("test_ring_nagative ring is not empty but it 
should be\n");
+   goto test_fail;
+   }
+
+   /* Tests if it would always fail to create ring with an used
+* ring name.
+*/
+   TEST_RING_CREATE("test_ring_negative", esize[i], RING_SIZE,
+   SOCKET_ID_ANY, 0, rt);
+   if (rt != NULL)
+   goto test_fail;
+
+   rte_ring_free(rp);
+   }
+
+   return 0;
+
+test_fail:
+
+   rte_ring_free(rp);
+   return -1;
+}
+
 static int
 test_ring_basic(struct rte_ring *r)
 {
@@ -555,70 +642,6 @@ test_ring_burst_bulk_tests(unsigned int api_type)
return -1;
 }
 
-/*
- * it will always fail to create ring with a wrong ring size number in this 
function
- */
-static int
-test_ring_creation_with_wrong_size(void)
-{
-   struct rte_ring * rp = NULL;
-
-   /* Test if ring size is not power of 2 */
-   rp = rte_ring_create("test_bad_ring_size", RING_SIZE + 1, 
SOCKET_ID_ANY, 0);
-   if (NULL != rp) {
-   return -1;
-   }
-
-   /* Test if ring size is exceeding the limit */
-   rp = rte_ring_create("test_bad_ring_size", (RTE_RING_SZ_MASK + 1), 
SOCKET_ID_ANY, 0);
-   if (NULL != rp) {
-   return -1;
-   }
-   return 0;
-}
-
-/*
- * it tests if it would always fail to create ring with an used ring name
- */
-static int
-test_ring_creation_with_an_used_name(void)
-{
-   struct rte_ring * rp;
-
-   rp = rte_ring_create("test", RING_SIZE, SOCKET_ID_ANY, 0);
-   if (NULL != rp)
-   return -1;
-
-   return 0;
-}
-
-/*
- * Test to if a non-power of 2 count causes the create
- * function to fail correctly
- */
-static int
-test_create_count_odd(voi

[dpdk-dev] [PATCH v7 02/17] lib/ring: apis to support configurable element size

[Honnappa Nagarahalli]

Current APIs assume ring elements to be pointers. However, in many
use cases, the size can be different. Add new APIs to support
configurable ring element sizes.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Dharmik Thakkar 
Reviewed-by: Gavin Hu 
Reviewed-by: Ruifeng Wang 
---
 lib/librte_ring/Makefile |3 +-
 lib/librte_ring/meson.build  |4 +
 lib/librte_ring/rte_ring.c   |   41 +-
 lib/librte_ring/rte_ring.h   |1 +
 lib/librte_ring/rte_ring_elem.h  | 1002 ++
 lib/librte_ring/rte_ring_version.map |2 +
 6 files changed, 1044 insertions(+), 9 deletions(-)
 create mode 100644 lib/librte_ring/rte_ring_elem.h

diff --git a/lib/librte_ring/Makefile b/lib/librte_ring/Makefile
index 22454b084..917c560ad 100644
--- a/lib/librte_ring/Makefile
+++ b/lib/librte_ring/Makefile
@@ -6,7 +6,7 @@ include $(RTE_SDK)/mk/rte.vars.mk
 # library name
 LIB = librte_ring.a
 
-CFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3
+CFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3 -DALLOW_EXPERIMENTAL_API
 LDLIBS += -lrte_eal
 
 EXPORT_MAP := rte_ring_version.map
@@ -16,6 +16,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_RING) := rte_ring.c
 
 # install includes
 SYMLINK-$(CONFIG_RTE_LIBRTE_RING)-include := rte_ring.h \
+   rte_ring_elem.h \
rte_ring_generic.h \
rte_ring_c11_mem.h
 
diff --git a/lib/librte_ring/meson.build b/lib/librte_ring/meson.build
index ca8a435e9..f2f3ccc88 100644
--- a/lib/librte_ring/meson.build
+++ b/lib/librte_ring/meson.build
@@ -3,5 +3,9 @@
 
 sources = files('rte_ring.c')
 headers = files('rte_ring.h',
+   'rte_ring_elem.h',
'rte_ring_c11_mem.h',
'rte_ring_generic.h')
+
+# rte_ring_create_elem and rte_ring_get_memsize_elem are experimental
+allow_experimental_apis = true
diff --git a/lib/librte_ring/rte_ring.c b/lib/librte_ring/rte_ring.c
index d9b308036..3e15dc398 100644
--- a/lib/librte_ring/rte_ring.c
+++ b/lib/librte_ring/rte_ring.c
@@ -33,6 +33,7 @@
 #include 
 
 #include "rte_ring.h"
+#include "rte_ring_elem.h"
 
 TAILQ_HEAD(rte_ring_list, rte_tailq_entry);
 
@@ -46,23 +47,38 @@ EAL_REGISTER_TAILQ(rte_ring_tailq)
 
 /* return the size of memory occupied by a ring */
 ssize_t
-rte_ring_get_memsize(unsigned count)
+rte_ring_get_memsize_elem(unsigned int esize, unsigned int count)
 {
ssize_t sz;
 
+   /* Check if element size is a multiple of 4B */
+   if (esize % 4 != 0) {
+   RTE_LOG(ERR, RING, "element size is not a multiple of 4\n");
+
+   return -EINVAL;
+   }
+
/* count must be a power of 2 */
if ((!POWEROF2(count)) || (count > RTE_RING_SZ_MASK )) {
RTE_LOG(ERR, RING,
-   "Requested size is invalid, must be power of 2, and "
-   "do not exceed the size limit %u\n", RTE_RING_SZ_MASK);
+   "Requested number of elements is invalid, must be power 
of 2, and not exceed %u\n",
+   RTE_RING_SZ_MASK);
+
return -EINVAL;
}
 
-   sz = sizeof(struct rte_ring) + count * sizeof(void *);
+   sz = sizeof(struct rte_ring) + count * esize;
sz = RTE_ALIGN(sz, RTE_CACHE_LINE_SIZE);
return sz;
 }
 
+/* return the size of memory occupied by a ring */
+ssize_t
+rte_ring_get_memsize(unsigned count)
+{
+   return rte_ring_get_memsize_elem(sizeof(void *), count);
+}
+
 void
 rte_ring_reset(struct rte_ring *r)
 {
@@ -114,10 +130,10 @@ rte_ring_init(struct rte_ring *r, const char *name, 
unsigned count,
return 0;
 }
 
-/* create the ring */
+/* create the ring for a given element size */
 struct rte_ring *
-rte_ring_create(const char *name, unsigned count, int socket_id,
-   unsigned flags)
+rte_ring_create_elem(const char *name, unsigned int esize, unsigned int count,
+   int socket_id, unsigned int flags)
 {
char mz_name[RTE_MEMZONE_NAMESIZE];
struct rte_ring *r;
@@ -135,7 +151,7 @@ rte_ring_create(const char *name, unsigned count, int 
socket_id,
if (flags & RING_F_EXACT_SZ)
count = rte_align32pow2(count + 1);
 
-   ring_size = rte_ring_get_memsize(count);
+   ring_size = rte_ring_get_memsize_elem(esize, count);
if (ring_size < 0) {
rte_errno = ring_size;
return NULL;
@@ -182,6 +198,15 @@ rte_ring_create(const char *name, unsigned count, int 
socket_id,
return r;
 }
 
+/* create the ring */
+struct rte_ring *
+rte_ring_create(const char *name, unsigned count, int socket_id,
+   unsigned flags)
+{
+   return rte_ring_create_elem(name, sizeof(void *), count, socket_id,
+   flags);
+}
+
 /* free the ring */
 void
 rte_ring_free(struct rte_ring *r)
diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h
index 2a9f768a1..18fc5d845 100644
--- a/lib/l

[dpdk-dev] [PATCH v7 01/17] test/ring: use division for cycle count calculation

[Honnappa Nagarahalli]

Use division instead of modulo operation to calculate more
accurate cycle count.

Signed-off-by: Honnappa Nagarahalli 
Acked-by: Olivier Matz 
---
 app/test/test_ring_perf.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
index 70ee46ffe..6c2aca483 100644
--- a/app/test/test_ring_perf.c
+++ b/app/test/test_ring_perf.c
@@ -357,10 +357,10 @@ test_single_enqueue_dequeue(struct rte_ring *r)
}
const uint64_t mc_end = rte_rdtsc();
 
-   printf("SP/SC single enq/dequeue: %"PRIu64"\n",
-   (sc_end-sc_start) >> iter_shift);
-   printf("MP/MC single enq/dequeue: %"PRIu64"\n",
-   (mc_end-mc_start) >> iter_shift);
+   printf("SP/SC single enq/dequeue: %.2F\n",
+   ((double)(sc_end-sc_start)) / iterations);
+   printf("MP/MC single enq/dequeue: %.2F\n",
+   ((double)(mc_end-mc_start)) / iterations);
 }
 
 /*
@@ -395,13 +395,15 @@ test_burst_enqueue_dequeue(struct rte_ring *r)
}
const uint64_t mc_end = rte_rdtsc();
 
-   uint64_t mc_avg = ((mc_end-mc_start) >> iter_shift) / 
bulk_sizes[sz];
-   uint64_t sc_avg = ((sc_end-sc_start) >> iter_shift) / 
bulk_sizes[sz];
+   double mc_avg = ((double)(mc_end-mc_start) / iterations) /
+   bulk_sizes[sz];
+   double sc_avg = ((double)(sc_end-sc_start) / iterations) /
+   bulk_sizes[sz];
 
-   printf("SP/SC burst enq/dequeue (size: %u): %"PRIu64"\n", 
bulk_sizes[sz],
-   sc_avg);
-   printf("MP/MC burst enq/dequeue (size: %u): %"PRIu64"\n", 
bulk_sizes[sz],
-   mc_avg);
+   printf("SP/SC burst enq/dequeue (size: %u): %.2F\n",
+   bulk_sizes[sz], sc_avg);
+   printf("MP/MC burst enq/dequeue (size: %u): %.2F\n",
+   bulk_sizes[sz], mc_avg);
}
 }
 
-- 
2.17.1

[dpdk-dev] [PATCH v7 15/17] test/ring: adjust run-on-all-cores perf test cases

[Honnappa Nagarahalli]

Adjust run-on-all-cores test case to use legacy APIs.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring_perf.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
index b893b5779..fb95e4f2c 100644
--- a/app/test/test_ring_perf.c
+++ b/app/test/test_ring_perf.c
@@ -520,6 +520,9 @@ test_ring_perf(void)
dequeue_bulk) < 0)
return -1;
}
+   printf("\n### Testing using all slave nodes ###\n");
+   if (run_on_all_cores(r) < 0)
+   return -1;
rte_ring_free(r);
 
TEST_RING_CREATE(RING_NAME, 16, RING_SIZE, rte_socket_id(), 0, r);
@@ -567,9 +570,6 @@ test_ring_perf(void)
return -1;
}
 
-   printf("\n### Testing using all slave nodes ###\n");
-   run_on_all_cores(r);
-
rte_ring_free(r);
 
return 0;
-- 
2.17.1

[dpdk-dev] [PATCH v7 17/17] lib/eventdev: use custom element size ring for event rings

[Honnappa Nagarahalli]

Use custom element size ring APIs to replace event ring
implementation. This avoids code duplication.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
Reviewed-by: Ola Liljedahl 
---
 lib/librte_eventdev/rte_event_ring.c | 147 ++-
 lib/librte_eventdev/rte_event_ring.h |  45 
 2 files changed, 24 insertions(+), 168 deletions(-)

diff --git a/lib/librte_eventdev/rte_event_ring.c 
b/lib/librte_eventdev/rte_event_ring.c
index 50190de01..d27e23901 100644
--- a/lib/librte_eventdev/rte_event_ring.c
+++ b/lib/librte_eventdev/rte_event_ring.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2017 Intel Corporation
+ * Copyright(c) 2019 Arm Limited
  */
 
 #include 
@@ -11,13 +12,6 @@
 #include 
 #include "rte_event_ring.h"
 
-TAILQ_HEAD(rte_event_ring_list, rte_tailq_entry);
-
-static struct rte_tailq_elem rte_event_ring_tailq = {
-   .name = RTE_TAILQ_EVENT_RING_NAME,
-};
-EAL_REGISTER_TAILQ(rte_event_ring_tailq)
-
 int
 rte_event_ring_init(struct rte_event_ring *r, const char *name,
unsigned int count, unsigned int flags)
@@ -35,150 +29,21 @@ struct rte_event_ring *
 rte_event_ring_create(const char *name, unsigned int count, int socket_id,
unsigned int flags)
 {
-   char mz_name[RTE_MEMZONE_NAMESIZE];
-   struct rte_event_ring *r;
-   struct rte_tailq_entry *te;
-   const struct rte_memzone *mz;
-   ssize_t ring_size;
-   int mz_flags = 0;
-   struct rte_event_ring_list *ring_list = NULL;
-   const unsigned int requested_count = count;
-   int ret;
-
-   ring_list = RTE_TAILQ_CAST(rte_event_ring_tailq.head,
-   rte_event_ring_list);
-
-   /* for an exact size ring, round up from count to a power of two */
-   if (flags & RING_F_EXACT_SZ)
-   count = rte_align32pow2(count + 1);
-   else if (!rte_is_power_of_2(count)) {
-   rte_errno = EINVAL;
-   return NULL;
-   }
-
-   ring_size = sizeof(*r) + (count * sizeof(struct rte_event));
-
-   ret = snprintf(mz_name, sizeof(mz_name), "%s%s",
-   RTE_RING_MZ_PREFIX, name);
-   if (ret < 0 || ret >= (int)sizeof(mz_name)) {
-   rte_errno = ENAMETOOLONG;
-   return NULL;
-   }
-
-   te = rte_zmalloc("RING_TAILQ_ENTRY", sizeof(*te), 0);
-   if (te == NULL) {
-   RTE_LOG(ERR, RING, "Cannot reserve memory for tailq\n");
-   rte_errno = ENOMEM;
-   return NULL;
-   }
-
-   rte_mcfg_tailq_write_lock();
-
-   /*
-* reserve a memory zone for this ring. If we can't get rte_config or
-* we are secondary process, the memzone_reserve function will set
-* rte_errno for us appropriately - hence no check in this this function
-*/
-   mz = rte_memzone_reserve(mz_name, ring_size, socket_id, mz_flags);
-   if (mz != NULL) {
-   r = mz->addr;
-   /* Check return value in case rte_ring_init() fails on size */
-   int err = rte_event_ring_init(r, name, requested_count, flags);
-   if (err) {
-   RTE_LOG(ERR, RING, "Ring init failed\n");
-   if (rte_memzone_free(mz) != 0)
-   RTE_LOG(ERR, RING, "Cannot free memzone\n");
-   rte_free(te);
-   rte_mcfg_tailq_write_unlock();
-   return NULL;
-   }
-
-   te->data = (void *) r;
-   r->r.memzone = mz;
-
-   TAILQ_INSERT_TAIL(ring_list, te, next);
-   } else {
-   r = NULL;
-   RTE_LOG(ERR, RING, "Cannot reserve memory\n");
-   rte_free(te);
-   }
-   rte_mcfg_tailq_write_unlock();
-
-   return r;
+   return (struct rte_event_ring *)rte_ring_create_elem(name,
+   sizeof(struct rte_event),
+   count, socket_id, flags);
 }
 
 
 struct rte_event_ring *
 rte_event_ring_lookup(const char *name)
 {
-   struct rte_tailq_entry *te;
-   struct rte_event_ring *r = NULL;
-   struct rte_event_ring_list *ring_list;
-
-   ring_list = RTE_TAILQ_CAST(rte_event_ring_tailq.head,
-   rte_event_ring_list);
-
-   rte_mcfg_tailq_read_lock();
-
-   TAILQ_FOREACH(te, ring_list, next) {
-   r = (struct rte_event_ring *) te->data;
-   if (strncmp(name, r->r.name, RTE_RING_NAMESIZE) == 0)
-   break;
-   }
-
-   rte_mcfg_tailq_read_unlock();
-
-   if (te == NULL) {
-   rte_errno = ENOENT;
-   return NULL;
-   }
-
-   return r;
+   return (struct rte_event_ring *)rte_ring_lookup(name);
 }
 
 /* free the ring */
 void
 rte_event_ring_free(struct rte_event_ring *r)
 {
-   struct rte_event_ring_list *ring_list = NULL;
-   struct rte_tailq

[dpdk-dev] [PATCH v7 12/17] test/ring: modify bulk enq/deq perf test cases

[Honnappa Nagarahalli]

Modify test cases to test legacy and rte_ring_xxx_elem APIs for
bulk enqueue/dequeue test cases.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring_perf.c | 57 ++-
 1 file changed, 14 insertions(+), 43 deletions(-)

diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
index 508c688dc..8a543b6f0 100644
--- a/app/test/test_ring_perf.c
+++ b/app/test/test_ring_perf.c
@@ -433,46 +433,6 @@ test_burst_bulk_enqueue_dequeue(struct rte_ring *r, const 
int esize,
return 0;
 }
 
-/* Times enqueue and dequeue on a single lcore */
-static void
-test_bulk_enqueue_dequeue(struct rte_ring *r)
-{
-   const unsigned iter_shift = 23;
-   const unsigned iterations = 1<

[dpdk-dev] [PATCH v7 13/17] test/ring: modify bulk empty deq perf test cases

[Honnappa Nagarahalli]

Modify test cases to test legacy and rte_ring_xxx_elem APIs for
empty bulk dequeue test cases.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring_perf.c | 38 +++---
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
index 8a543b6f0..0f578c9ae 100644
--- a/app/test/test_ring_perf.c
+++ b/app/test/test_ring_perf.c
@@ -147,27 +147,24 @@ get_two_sockets(struct lcore_pair *lcp)
 
 /* Get cycle counts for dequeuing from an empty ring. Should be 2 or 3 cycles 
*/
 static void
-test_empty_dequeue(struct rte_ring *r)
+test_empty_dequeue(struct rte_ring *r, const int esize,
+   const unsigned int api_type)
 {
-   const unsigned iter_shift = 26;
-   const unsigned iterations = 1<

[dpdk-dev] [PATCH v7 09/17] test/ring: removed unused variable synchro

[Honnappa Nagarahalli]

Remove unused variable synchro

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/app/test/test_ring.c b/app/test/test_ring.c
index a082f0137..57fbd897c 100644
--- a/app/test/test_ring.c
+++ b/app/test/test_ring.c
@@ -57,8 +57,6 @@
 #define RING_SIZE 4096
 #define MAX_BULK 32
 
-static rte_atomic32_t synchro;
-
 #defineTEST_RING_VERIFY(exp)   
\
if (!(exp)) {   \
printf("error at %s:%d\tcondition " #exp " failed\n",   \
@@ -665,8 +663,6 @@ test_ring(void)
if (test_ring_basic_ex() < 0)
goto test_fail;
 
-   rte_atomic32_init(&synchro);
-
/* Burst and bulk operations with sp/sc, mp/mc and default */
for (j = TEST_RING_BL; j <= TEST_RING_BR; j <<= 1)
for (i = TEST_RING_N; i <= TEST_RING_M; i <<= 1)
-- 
2.17.1

[dpdk-dev] [PATCH v7 10/17] test/ring: modify single element enq/deq perf test cases

[Honnappa Nagarahalli]

Add test cases to test rte_ring_xxx_elem APIs for single
element enqueue/dequeue test cases.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring_perf.c | 100 ++
 1 file changed, 80 insertions(+), 20 deletions(-)

diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
index 6c2aca483..5829718c1 100644
--- a/app/test/test_ring_perf.c
+++ b/app/test/test_ring_perf.c
@@ -13,6 +13,7 @@
 #include 
 
 #include "test.h"
+#include "test_ring.h"
 
 /*
  * Ring
@@ -41,6 +42,35 @@ struct lcore_pair {
 
 static volatile unsigned lcore_count = 0;
 
+static void
+test_ring_print_test_string(unsigned int api_type, int esize,
+   unsigned int bsz, double value)
+{
+   if (esize == -1)
+   printf("legacy APIs");
+   else
+   printf("elem APIs: element size %dB", esize);
+
+   if (api_type == TEST_RING_IGNORE_API_TYPE)
+   return;
+
+   if ((api_type & TEST_RING_N) == TEST_RING_N)
+   printf(": default enqueue/dequeue: ");
+   else if ((api_type & TEST_RING_S) == TEST_RING_S)
+   printf(": SP/SC: ");
+   else if ((api_type & TEST_RING_M) == TEST_RING_M)
+   printf(": MP/MC: ");
+
+   if ((api_type & TEST_RING_SL) == TEST_RING_SL)
+   printf("single: ");
+   else if ((api_type & TEST_RING_BL) == TEST_RING_BL)
+   printf("bulk (size: %u): ", bsz);
+   else if ((api_type & TEST_RING_BR) == TEST_RING_BR)
+   printf("burst (size: %u): ", bsz);
+
+   printf("%.2F\n", value);
+}
+
 / Functions to analyse our core mask to get cores for different tests ***/
 
 static int
@@ -335,32 +365,35 @@ run_on_all_cores(struct rte_ring *r)
  * Test function that determines how long an enqueue + dequeue of a single item
  * takes on a single lcore. Result is for comparison with the bulk enq+deq.
  */
-static void
-test_single_enqueue_dequeue(struct rte_ring *r)
+static int
+test_single_enqueue_dequeue(struct rte_ring *r, const int esize,
+   const unsigned int api_type)
 {
-   const unsigned iter_shift = 24;
-   const unsigned iterations = 1<

[dpdk-dev] [PATCH v7 08/17] test/ring: remove duplicate test cases

[Honnappa Nagarahalli]

The test cases in the function test_ring_basic are already covered
by the function test_ring_burst_bulk_tests and others.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring.c | 218 ---
 1 file changed, 218 deletions(-)

diff --git a/app/test/test_ring.c b/app/test/test_ring.c
index 552e8b53a..a082f0137 100644
--- a/app/test/test_ring.c
+++ b/app/test/test_ring.c
@@ -200,206 +200,6 @@ test_ring_negative_tests(void)
return -1;
 }
 
-static int
-test_ring_basic(struct rte_ring *r)
-{
-   void **src = NULL, **cur_src = NULL, **dst = NULL, **cur_dst = NULL;
-   int ret;
-   unsigned i, num_elems;
-
-   /* alloc dummy object pointers */
-   src = malloc(RING_SIZE*2*sizeof(void *));
-   if (src == NULL)
-   goto fail;
-
-   for (i = 0; i < RING_SIZE*2 ; i++) {
-   src[i] = (void *)(unsigned long)i;
-   }
-   cur_src = src;
-
-   /* alloc some room for copied objects */
-   dst = malloc(RING_SIZE*2*sizeof(void *));
-   if (dst == NULL)
-   goto fail;
-
-   memset(dst, 0, RING_SIZE*2*sizeof(void *));
-   cur_dst = dst;
-
-   printf("enqueue 1 obj\n");
-   ret = rte_ring_sp_enqueue_bulk(r, cur_src, 1, NULL);
-   cur_src += 1;
-   if (ret == 0)
-   goto fail;
-
-   printf("enqueue 2 objs\n");
-   ret = rte_ring_sp_enqueue_bulk(r, cur_src, 2, NULL);
-   cur_src += 2;
-   if (ret == 0)
-   goto fail;
-
-   printf("enqueue MAX_BULK objs\n");
-   ret = rte_ring_sp_enqueue_bulk(r, cur_src, MAX_BULK, NULL);
-   cur_src += MAX_BULK;
-   if (ret == 0)
-   goto fail;
-
-   printf("dequeue 1 obj\n");
-   ret = rte_ring_sc_dequeue_bulk(r, cur_dst, 1, NULL);
-   cur_dst += 1;
-   if (ret == 0)
-   goto fail;
-
-   printf("dequeue 2 objs\n");
-   ret = rte_ring_sc_dequeue_bulk(r, cur_dst, 2, NULL);
-   cur_dst += 2;
-   if (ret == 0)
-   goto fail;
-
-   printf("dequeue MAX_BULK objs\n");
-   ret = rte_ring_sc_dequeue_bulk(r, cur_dst, MAX_BULK, NULL);
-   cur_dst += MAX_BULK;
-   if (ret == 0)
-   goto fail;
-
-   /* check data */
-   if (memcmp(src, dst, cur_dst - dst)) {
-   rte_hexdump(stdout, "src", src, cur_src - src);
-   rte_hexdump(stdout, "dst", dst, cur_dst - dst);
-   printf("data after dequeue is not the same\n");
-   goto fail;
-   }
-   cur_src = src;
-   cur_dst = dst;
-
-   printf("enqueue 1 obj\n");
-   ret = rte_ring_mp_enqueue_bulk(r, cur_src, 1, NULL);
-   cur_src += 1;
-   if (ret == 0)
-   goto fail;
-
-   printf("enqueue 2 objs\n");
-   ret = rte_ring_mp_enqueue_bulk(r, cur_src, 2, NULL);
-   cur_src += 2;
-   if (ret == 0)
-   goto fail;
-
-   printf("enqueue MAX_BULK objs\n");
-   ret = rte_ring_mp_enqueue_bulk(r, cur_src, MAX_BULK, NULL);
-   cur_src += MAX_BULK;
-   if (ret == 0)
-   goto fail;
-
-   printf("dequeue 1 obj\n");
-   ret = rte_ring_mc_dequeue_bulk(r, cur_dst, 1, NULL);
-   cur_dst += 1;
-   if (ret == 0)
-   goto fail;
-
-   printf("dequeue 2 objs\n");
-   ret = rte_ring_mc_dequeue_bulk(r, cur_dst, 2, NULL);
-   cur_dst += 2;
-   if (ret == 0)
-   goto fail;
-
-   printf("dequeue MAX_BULK objs\n");
-   ret = rte_ring_mc_dequeue_bulk(r, cur_dst, MAX_BULK, NULL);
-   cur_dst += MAX_BULK;
-   if (ret == 0)
-   goto fail;
-
-   /* check data */
-   if (memcmp(src, dst, cur_dst - dst)) {
-   rte_hexdump(stdout, "src", src, cur_src - src);
-   rte_hexdump(stdout, "dst", dst, cur_dst - dst);
-   printf("data after dequeue is not the same\n");
-   goto fail;
-   }
-   cur_src = src;
-   cur_dst = dst;
-
-   printf("fill and empty the ring\n");
-   for (i = 0; i

[dpdk-dev] [PATCH v7 16/17] lib/hash: use ring with 32b element size to save memory

[Honnappa Nagarahalli]

The freelist and external bucket indices are 32b. Using rings
that use 32b element sizes will save memory.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
Reviewed-by: Ola Liljedahl 
---
 lib/librte_hash/rte_cuckoo_hash.c | 97 ---
 lib/librte_hash/rte_cuckoo_hash.h |  2 +-
 2 files changed, 51 insertions(+), 48 deletions(-)

diff --git a/lib/librte_hash/rte_cuckoo_hash.c 
b/lib/librte_hash/rte_cuckoo_hash.c
index 87a4c01f2..734bec2ac 100644
--- a/lib/librte_hash/rte_cuckoo_hash.c
+++ b/lib/librte_hash/rte_cuckoo_hash.c
@@ -24,7 +24,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -136,7 +136,6 @@ rte_hash_create(const struct rte_hash_parameters *params)
char ring_name[RTE_RING_NAMESIZE];
char ext_ring_name[RTE_RING_NAMESIZE];
unsigned num_key_slots;
-   unsigned i;
unsigned int hw_trans_mem_support = 0, use_local_cache = 0;
unsigned int ext_table_support = 0;
unsigned int readwrite_concur_support = 0;
@@ -213,8 +212,8 @@ rte_hash_create(const struct rte_hash_parameters *params)
 
snprintf(ring_name, sizeof(ring_name), "HT_%s", params->name);
/* Create ring (Dummy slot index is not enqueued) */
-   r = rte_ring_create(ring_name, rte_align32pow2(num_key_slots),
-   params->socket_id, 0);
+   r = rte_ring_create_elem(ring_name, sizeof(uint32_t),
+   rte_align32pow2(num_key_slots), params->socket_id, 0);
if (r == NULL) {
RTE_LOG(ERR, HASH, "memory allocation failed\n");
goto err;
@@ -227,7 +226,7 @@ rte_hash_create(const struct rte_hash_parameters *params)
if (ext_table_support) {
snprintf(ext_ring_name, sizeof(ext_ring_name), "HT_EXT_%s",
params->name);
-   r_ext = rte_ring_create(ext_ring_name,
+   r_ext = rte_ring_create_elem(ext_ring_name, sizeof(uint32_t),
rte_align32pow2(num_buckets + 1),
params->socket_id, 0);
 
@@ -294,8 +293,8 @@ rte_hash_create(const struct rte_hash_parameters *params)
 * use bucket index for the linked list and 0 means NULL
 * for next bucket
 */
-   for (i = 1; i <= num_buckets; i++)
-   rte_ring_sp_enqueue(r_ext, (void *)((uintptr_t) i));
+   for (uint32_t i = 1; i <= num_buckets; i++)
+   rte_ring_sp_enqueue_elem(r_ext, &i, sizeof(uint32_t));
 
if (readwrite_concur_lf_support) {
ext_bkt_to_free = rte_zmalloc(NULL, sizeof(uint32_t) *
@@ -433,8 +432,8 @@ rte_hash_create(const struct rte_hash_parameters *params)
}
 
/* Populate free slots ring. Entry zero is reserved for key misses. */
-   for (i = 1; i < num_key_slots; i++)
-   rte_ring_sp_enqueue(r, (void *)((uintptr_t) i));
+   for (uint32_t i = 1; i < num_key_slots; i++)
+   rte_ring_sp_enqueue_elem(r, &i, sizeof(uint32_t));
 
te->data = (void *) h;
TAILQ_INSERT_TAIL(hash_list, te, next);
@@ -598,13 +597,13 @@ rte_hash_reset(struct rte_hash *h)
tot_ring_cnt = h->entries;
 
for (i = 1; i < tot_ring_cnt + 1; i++)
-   rte_ring_sp_enqueue(h->free_slots, (void *)((uintptr_t) i));
+   rte_ring_sp_enqueue_elem(h->free_slots, &i, sizeof(uint32_t));
 
/* Repopulate the free ext bkt ring. */
if (h->ext_table_support) {
for (i = 1; i <= h->num_buckets; i++)
-   rte_ring_sp_enqueue(h->free_ext_bkts,
-   (void *)((uintptr_t) i));
+   rte_ring_sp_enqueue_elem(h->free_ext_bkts, &i,
+   sizeof(uint32_t));
}
 
if (h->use_local_cache) {
@@ -623,13 +622,14 @@ rte_hash_reset(struct rte_hash *h)
 static inline void
 enqueue_slot_back(const struct rte_hash *h,
struct lcore_cache *cached_free_slots,
-   void *slot_id)
+   uint32_t slot_id)
 {
if (h->use_local_cache) {
cached_free_slots->objs[cached_free_slots->len] = slot_id;
cached_free_slots->len++;
} else
-   rte_ring_sp_enqueue(h->free_slots, slot_id);
+   rte_ring_sp_enqueue_elem(h->free_slots, &slot_id,
+   sizeof(uint32_t));
 }
 
 /* Search a key from bucket and update its data.
@@ -923,9 +923,8 @@ __rte_hash_add_key_with_hash(const struct rte_hash *h, 
const void *key,
uint32_t prim_bucket_idx, sec_bucket_idx;
struct rte_hash_bucket *prim_bkt, *sec_bkt, *cur_bkt;
struct rte_hash_key *new_k, *keys = h->key_store;
-   void *slot_id = NULL;
-   void *ext_bkt_id

[dpdk-dev] [PATCH v7 14/17] test/ring: modify multi-lcore perf test cases

[Honnappa Nagarahalli]

Modify test cases to test the performance of legacy and
rte_ring_xxx_elem APIs for multi lcore scenarios.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring_perf.c | 175 +-
 1 file changed, 115 insertions(+), 60 deletions(-)

diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
index 0f578c9ae..b893b5779 100644
--- a/app/test/test_ring_perf.c
+++ b/app/test/test_ring_perf.c
@@ -178,19 +178,21 @@ struct thread_params {
 };
 
 /*
- * Function that uses rdtsc to measure timing for ring enqueue. Needs pair
- * thread running dequeue_bulk function
+ * Helper function to call bulk SP/MP enqueue functions.
+ * flag == 0 -> enqueue
+ * flag == 1 -> dequeue
  */
-static int
-enqueue_bulk(void *p)
+static __rte_always_inline int
+enqueue_dequeue_bulk_helper(const unsigned int flag, const int esize,
+   struct thread_params *p)
 {
-   const unsigned iter_shift = 23;
-   const unsigned iterations = 1size;
-   unsigned i;
-   void *burst[MAX_BURST] = {0};
+   int ret;
+   const unsigned int iter_shift = 23;
+   const unsigned int iterations = 1 << iter_shift;
+   struct rte_ring *r = p->r;
+   unsigned int bsize = p->size;
+   unsigned int i;
+   void *burst = NULL;
 
 #ifdef RTE_USE_C11_MEM_MODEL
if (__atomic_add_fetch(&lcore_count, 1, __ATOMIC_RELAXED) != 2)
@@ -200,23 +202,55 @@ enqueue_bulk(void *p)
while(lcore_count != 2)
rte_pause();
 
+   burst = test_ring_calloc(MAX_BURST, esize);
+   if (burst == NULL)
+   return -1;
+
const uint64_t sp_start = rte_rdtsc();
for (i = 0; i < iterations; i++)
-   while (rte_ring_sp_enqueue_bulk(r, burst, size, NULL) == 0)
-   rte_pause();
+   do {
+   if (flag == 0)
+   TEST_RING_ENQUEUE(r, burst, esize, bsize, ret,
+   TEST_RING_S | TEST_RING_BL);
+   else if (flag == 1)
+   TEST_RING_DEQUEUE(r, burst, esize, bsize, ret,
+   TEST_RING_S | TEST_RING_BL);
+   if (ret == 0)
+   rte_pause();
+   } while (!ret);
const uint64_t sp_end = rte_rdtsc();
 
const uint64_t mp_start = rte_rdtsc();
for (i = 0; i < iterations; i++)
-   while (rte_ring_mp_enqueue_bulk(r, burst, size, NULL) == 0)
-   rte_pause();
+   do {
+   if (flag == 0)
+   TEST_RING_ENQUEUE(r, burst, esize, bsize, ret,
+   TEST_RING_M | TEST_RING_BL);
+   else if (flag == 1)
+   TEST_RING_DEQUEUE(r, burst, esize, bsize, ret,
+   TEST_RING_M | TEST_RING_BL);
+   if (ret == 0)
+   rte_pause();
+   } while (!ret);
const uint64_t mp_end = rte_rdtsc();
 
-   params->spsc = ((double)(sp_end - sp_start))/(iterations*size);
-   params->mpmc = ((double)(mp_end - mp_start))/(iterations*size);
+   p->spsc = ((double)(sp_end - sp_start))/(iterations * bsize);
+   p->mpmc = ((double)(mp_end - mp_start))/(iterations * bsize);
return 0;
 }
 
+/*
+ * Function that uses rdtsc to measure timing for ring enqueue. Needs pair
+ * thread running dequeue_bulk function
+ */
+static int
+enqueue_bulk(void *p)
+{
+   struct thread_params *params = p;
+
+   return enqueue_dequeue_bulk_helper(0, -1, params);
+}
+
 /*
  * Function that uses rdtsc to measure timing for ring dequeue. Needs pair
  * thread running enqueue_bulk function
@@ -224,45 +258,41 @@ enqueue_bulk(void *p)
 static int
 dequeue_bulk(void *p)
 {
-   const unsigned iter_shift = 23;
-   const unsigned iterations = 1size;
-   unsigned i;
-   void *burst[MAX_BURST] = {0};
 
-#ifdef RTE_USE_C11_MEM_MODEL
-   if (__atomic_add_fetch(&lcore_count, 1, __ATOMIC_RELAXED) != 2)
-#else
-   if (__sync_add_and_fetch(&lcore_count, 1) != 2)
-#endif
-   while(lcore_count != 2)
-   rte_pause();
+   return enqueue_dequeue_bulk_helper(1, -1, params);
+}
 
-   const uint64_t sc_start = rte_rdtsc();
-   for (i = 0; i < iterations; i++)
-   while (rte_ring_sc_dequeue_bulk(r, burst, size, NULL) == 0)
-   rte_pause();
-   const uint64_t sc_end = rte_rdtsc();
+/*
+ * Function that uses rdtsc to measure timing for ring enqueue. Needs pair
+ * thread running dequeue_bulk function
+ */
+static int
+enqueue_bulk_16B(void *p)
+{
+   struct thread_params *params = p;
 
-   const uint64_

[dpdk-dev] [PATCH v7 11/17] test/ring: modify burst enq/deq perf test cases

[Honnappa Nagarahalli]

Add test cases to test legacy and rte_ring_xxx_elem APIs for
burst enqueue/dequeue test cases.

Signed-off-by: Honnappa Nagarahalli 
Reviewed-by: Gavin Hu 
---
 app/test/test_ring_perf.c | 78 ---
 1 file changed, 40 insertions(+), 38 deletions(-)

diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
index 5829718c1..508c688dc 100644
--- a/app/test/test_ring_perf.c
+++ b/app/test/test_ring_perf.c
@@ -397,47 +397,40 @@ test_single_enqueue_dequeue(struct rte_ring *r, const int 
esize,
 }
 
 /*
- * Test that does both enqueue and dequeue on a core using the burst() API 
calls
- * instead of the bulk() calls used in other tests. Results should be the same
- * as for the bulk function called on a single lcore.
+ * Test that does both enqueue and dequeue on a core using the burst/bulk API
+ * calls Results should be the same as for the bulk function called on a
+ * single lcore.
  */
-static void
-test_burst_enqueue_dequeue(struct rte_ring *r)
+static int
+test_burst_bulk_enqueue_dequeue(struct rte_ring *r, const int esize,
+   const unsigned int api_type)
 {
-   const unsigned iter_shift = 23;
-   const unsigned iterations = 1<

Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for aarch64

[Gavin Hu]

Hi Jerin,

> -Original Message-
> From: Jerin Jacob 
> Sent: Friday, December 20, 2019 12:34 PM
> To: Gavin Hu 
> Cc: dpdk-dev ; nd ; David Marchand
> ; tho...@monjalon.net;
> rasl...@mellanox.com; maxime.coque...@redhat.com;
> tiwei@intel.com; hemant.agra...@nxp.com; jer...@marvell.com;
> Pavan Nikhilesh ; Honnappa Nagarahalli
> ; Ruifeng Wang
> ; Phil Yang ; Joyce Kong
> ; Steve Capper 
> Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for
> aarch64
> 
> On Fri, Dec 20, 2019 at 9:49 AM Gavin Hu  wrote:
> >
> > Hi Jerin,
> >
> > Thanks for review, inline comments,
> >
> > > -Original Message-
> > > From: Jerin Jacob 
> > > Sent: Friday, December 20, 2019 11:38 AM
> > > To: Gavin Hu 
> > > Cc: dpdk-dev ; nd ; David Marchand
> > > ; tho...@monjalon.net;
> > > rasl...@mellanox.com; maxime.coque...@redhat.com;
> > > tiwei@intel.com; hemant.agra...@nxp.com; jer...@marvell.com;
> > > Pavan Nikhilesh ; Honnappa Nagarahalli
> > > ; Ruifeng Wang
> > > ; Phil Yang ; Joyce
> Kong
> > > ; Steve Capper 
> > > Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier
> for
> > > aarch64
> > >
> > > On Fri, Dec 20, 2019 at 9:03 AM Jerin Jacob 
> > > wrote:
> > > >
> > > > On Fri, Dec 20, 2019 at 8:40 AM Gavin Hu  wrote:
> > > > >
> > > > > Armv8's peripheral coherence order is a total order on all reads and
> > > writes
> > > > > to that peripheral.[1]
> > > > >
> > > > > The peripheral coherence order for a memory-mapped peripheral
> > > signifies the
> > > > > order in which accesses arrive at the endpoint.  For a read or a write
> > > RW1
> > > > > and a read or a write RW2 to the same peripheral, then RW1 will
> appear
> > > in
> > > > > the peripheral coherence order for the peripheral before RW2 if
> either
> > > of
> > > > > the following cases apply:
> > > > >  1. RW1 and RW2 are accesses using Non-cacheable or Device
> attributes
> > > and
> > > > > RW1 is Ordered-before RW2.
> > > > >  2. RW1 and RW2 are accesses using Device-nGnRE or Device-
> nGnRnE
> > > attributes
> > > > > and RW1 appears in program order before RW2.
> > > >
> > > >
> > > > This is true if RW1 and RW2 addresses are device memory. i.e the
> > > > registers in the  PCI bar address.
> > > > If RW1 is DDR address which is been used by the controller(say NIC
> > > > ring descriptor) then there will be an issue.
> > > > For example Intel i40e driver, the admin queue update in Host DDR
> > > > memory and it updates the doorbell.
> > > > In such a case, this patch will create an issue. Correct? Have you
> > > > checked this patch with ARM64 + XL710 controllers?
> >
> > This patch relaxes the rte_io_*mb barriers for pure PCI device memory
> accesses.
> 
> Yes. This would break cases for mixed access fro i40e drivers.
> 
> >
> > For mixed accesses of DDR and PCI device memory, rte_smp_*mb(DMB
> ISH) is not sufficient.
> > But rte_cio_*mb(DMB OSH) is sufficient and can be used.
> 
> Yes. Let me share a bit of history.
> 
> 1) There are a lot of drivers(initially developed in x86) that have
> mixed access and don't have any barriers as x86 does not need it.
> 2) rte_io introduced to fix that
> 3) Item (2) introduced the performance issues in the fast path as an
> optimization rte_cio_* introduced.
Exactly, this patch is to mitigate the performance issues introduced by 
rte_io('dsb' is too much and unnecessary here).
Rte_cio instead is definitely required for mixed access. 
> 
> So in the current of the scheme of things, we have APIs to FIX
> portability issue(rte_io) and performance issue(rte_cio).
> IMO, we may not need any change in infra code now. If you think, the
> documentation is missing then we can enhance it.
> If we make infra change then again drivers needs to be updated and tested.
No changes for rte_cio, the semantics, and definitions of rte_io does not 
change either, if limited the scope to PCI, which is the case in DPDK 
context(?).
The change lies only in the implementation, right? 

Just looked at the link you shared and found i40 driver is missing rte_cio_*mb 
in i40e_asq_send_command, but the old rte_io_*mb rescued. 
Will submit a new patch in this series to used rte_cio together with new 
relaxed rte_io and do more tests. 

Yes, this is a big change, also a big optimization, for aarch64, in our tests 
it has very positive results.
But as the case in i40e, we must pay attention to where rte_cio was missing but 
rescued by old rte_io(but not by new rte_io). 

Re: [dpdk-dev] [PATCH v6 1/6] lib/eal: implement the family of rte bit operation APIs

[Honnappa Nagarahalli]

Hi Joyce,
These APIs seem to be written considering the PMD requirements. Is 
there a need to expose these to applications (external to DPDK?).

> -Original Message-
> From: Joyce Kong 
> Sent: Wednesday, December 18, 2019 12:00 AM
> To: tho...@monjalon.net; step...@networkplumber.org;
> david.march...@redhat.com; m...@smartsharesystems.com;
> jer...@marvell.com; bruce.richard...@intel.com; ravi1.ku...@amd.com;
> rm...@marvell.com; shsha...@marvell.com; xuanziya...@huawei.com;
> cloud.wangxiao...@huawei.com; zhouguoy...@huawei.com; Honnappa
> Nagarahalli ; Phil Yang
> ; Gavin Hu 
> Cc: nd ; dev@dpdk.org
> Subject: [PATCH v6 1/6] lib/eal: implement the family of rte bit operation
> APIs
> 
> There are a lot functions of bit operations scattered and duplicated in PMDs,
> consolidating them into a common API family is necessary. Furthermore,
> when the bit operation is applied to the IO devices, use __ATOMIC_ACQ_REL
> to ensure the ordering for io bit operation.
> 
> Signed-off-by: Joyce Kong 
> Reviewed-by: Gavin Hu 
> Reviewed-by: Phil Yang 
> Acked-by: Morten Brørup 
> ---
>  MAINTAINERS|   5 +
>  doc/api/doxy-api-index.md  |   5 +-
>  lib/librte_eal/common/Makefile |   1 +
>  lib/librte_eal/common/include/rte_bitops.h | 474
> +
>  lib/librte_eal/common/meson.build  |   3 +-
>  5 files changed, 485 insertions(+), 3 deletions(-)  create mode 100644
> lib/librte_eal/common/include/rte_bitops.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4395d8d..d2a29a2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -236,6 +236,11 @@ M: Cristian Dumitrescu
> 
>  F: lib/librte_eal/common/include/rte_bitmap.h
>  F: app/test/test_bitmap.c
> 
> +Bitops
> +M: Joyce Kong 
> +F: lib/librte_eal/common/include/rte_bitops.h
> +F: app/test/test_bitops.c
> +
>  MCSlock - EXPERIMENTAL
>  M: Phil Yang 
>  F: lib/librte_eal/common/include/generic/rte_mcslock.h
> diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index
> dff496b..ade7c01 100644
> --- a/doc/api/doxy-api-index.md
> +++ b/doc/api/doxy-api-index.md
> @@ -133,12 +133,13 @@ The public API headers are grouped by topics:
>[BPF](@ref rte_bpf.h)
> 
>  - **containers**:
> +  [bitmap] (@ref rte_bitmap.h),
> +  [bitops] (@ref rte_bitops.h),
>[mbuf]   (@ref rte_mbuf.h),
>[mbuf pool ops]  (@ref rte_mbuf_pool_ops.h),
>[ring]   (@ref rte_ring.h),
>[stack]  (@ref rte_stack.h),
> -  [tailq]  (@ref rte_tailq.h),
> -  [bitmap] (@ref rte_bitmap.h)
> +  [tailq]  (@ref rte_tailq.h)
> 
>  - **packet framework**:
>* [port] (@ref rte_port.h):
> diff --git a/lib/librte_eal/common/Makefile
> b/lib/librte_eal/common/Makefile index c2c6d92..dd025c1 100644
> --- a/lib/librte_eal/common/Makefile
> +++ b/lib/librte_eal/common/Makefile
> @@ -19,6 +19,7 @@ INC += rte_malloc.h rte_keepalive.h rte_time.h  INC +=
> rte_service.h rte_service_component.h  INC += rte_bitmap.h rte_vfio.h
> rte_hypervisor.h rte_test.h  INC += rte_reciprocal.h rte_fbarray.h rte_uuid.h
> +INC += rte_bitops.h
> 
>  GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h
> GENERIC_INC += rte_memcpy.h rte_cpuflags.h diff --git
> a/lib/librte_eal/common/include/rte_bitops.h
> b/lib/librte_eal/common/include/rte_bitops.h
> new file mode 100644
> index 000..34158d1
> --- /dev/null
> +++ b/lib/librte_eal/common/include/rte_bitops.h
> @@ -0,0 +1,474 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2019 Arm Limited
> + */
> +
> +#ifndef _RTE_BITOPS_H_
> +#define _RTE_BITOPS_H_
> +
> +/**
> + * @file
> + * Bit Operations
> + *
> + * This file defines a API for bit operations without/with memory ordering.
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +/* 32 bit operations
> +*/
> +
> +/**
> + * @warning
> + * @b EXPERIMENTAL: this API may change, or be removed, without prior
> +notice
> + *
> + * Get the target bit from a 32-bit value without memory ordering.
> + *
> + * @param nr
> + *   The target bit to get.
> + * @param addr
> + *   The address holding the bit.
> + * @return
> + *   The target bit.
> + */
> +__rte_experimental
> +static inline uint32_t
> +rte_get_bit32_relaxed(unsigned int nr, uint32_t *addr) {
Why not pass the memory order as a parameter? It would reduce the number of API 
calls by half.

> + RTE_ASSERT(nr < 32);
> +
> + uint32_t mask = UINT32_C(1) << nr;
> + return __atomic_load_n(addr, __ATOMIC_RELAXED) & mask; }
> +
> +/**
> + * @warning
> + * @b EXPERIMENTAL: this API may change, or be removed, without prior
> +notice
> + *
> + * Set the target bit in a 32-bit value to 1 without memory ordering.
> + *
> + * @param nr
> + *   The target bit to set.
> + * @param addr
> + *   The address holding the bit.
> + */
> +__rte_exp

Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for aarch64

[Jerin Jacob]

On Fri, Dec 20, 2019 at 12:02 PM Gavin Hu  wrote:
>
> Hi Jerin,

Hi Gavin,


> > > > > >
> > > > > > The peripheral coherence order for a memory-mapped peripheral
> > > > signifies the
> > > > > > order in which accesses arrive at the endpoint.  For a read or a 
> > > > > > write
> > > > RW1
> > > > > > and a read or a write RW2 to the same peripheral, then RW1 will
> > appear
> > > > in
> > > > > > the peripheral coherence order for the peripheral before RW2 if
> > either
> > > > of
> > > > > > the following cases apply:
> > > > > >  1. RW1 and RW2 are accesses using Non-cacheable or Device
> > attributes
> > > > and
> > > > > > RW1 is Ordered-before RW2.
> > > > > >  2. RW1 and RW2 are accesses using Device-nGnRE or Device-
> > nGnRnE
> > > > attributes
> > > > > > and RW1 appears in program order before RW2.
> > > > >
> > > > >
> > > > > This is true if RW1 and RW2 addresses are device memory. i.e the
> > > > > registers in the  PCI bar address.
> > > > > If RW1 is DDR address which is been used by the controller(say NIC
> > > > > ring descriptor) then there will be an issue.
> > > > > For example Intel i40e driver, the admin queue update in Host DDR
> > > > > memory and it updates the doorbell.
> > > > > In such a case, this patch will create an issue. Correct? Have you
> > > > > checked this patch with ARM64 + XL710 controllers?
> > >
> > > This patch relaxes the rte_io_*mb barriers for pure PCI device memory
> > accesses.
> >
> > Yes. This would break cases for mixed access fro i40e drivers.
> >
> > >
> > > For mixed accesses of DDR and PCI device memory, rte_smp_*mb(DMB
> > ISH) is not sufficient.
> > > But rte_cio_*mb(DMB OSH) is sufficient and can be used.
> >
> > Yes. Let me share a bit of history.
> >
> > 1) There are a lot of drivers(initially developed in x86) that have
> > mixed access and don't have any barriers as x86 does not need it.
> > 2) rte_io introduced to fix that
> > 3) Item (2) introduced the performance issues in the fast path as an
> > optimization rte_cio_* introduced.
> Exactly, this patch is to mitigate the performance issues introduced by 
> rte_io('dsb' is too much and unnecessary here).
> Rte_cio instead is definitely required for mixed access.
> >
> > So in the current of the scheme of things, we have APIs to FIX
> > portability issue(rte_io) and performance issue(rte_cio).
> > IMO, we may not need any change in infra code now. If you think, the
> > documentation is missing then we can enhance it.
> > If we make infra change then again drivers needs to be updated and tested.
> No changes for rte_cio, the semantics, and definitions of rte_io does not 
> change either, if limited the scope to PCI, which is the case in DPDK 
> context(?).
> The change lies only in the implementation, right?
>
> Just looked at the link you shared and found i40 driver is missing 
> rte_cio_*mb in i40e_asq_send_command, but the old rte_io_*mb rescued.
> Will submit a new patch in this series to used rte_cio together with new 
> relaxed rte_io and do more tests.
>
> Yes, this is a big change, also a big optimization, for aarch64, in our tests 
> it has very positive results.

It will be optimization only when if we are changing in the fast path.
In the slow path, it does not matter.
I think, the First step should be to use rte_cio_* wherever it is
coherent memory used in _fast path_. I think, Almost every driver
fixed that.

I am not against this patch(changing the slow path to use rte_cio*
from rte_io* and virtio changes associated with that).
If you are taking that patch, pay attention to all the drivers in the
tree which is using rte_io* for mixed access in slowpath.

> But as the case in i40e, we must pay attention to where rte_cio was missing 
> but rescued by old rte_io(but not by new rte_io).
>
>

[dpdk-dev] [PATCH v6 2/2] common/octeontx2: add polling based response mbox message

[Sunil Kumar Kori]

Currently otx2_mbox_get_rsp_xxx get response once AF driver
interrupts after completion. But this funciton will get into
deadlock if called in another interrupt context.

To avoid it, implemented another version of this function which polls
on dedicated memory for a given timeout.

Also after clearing interrupt, there could UP messages available for
processing. So irq handler must check mbox messages.

Signed-off-by: Sunil Kumar Kori 
Signed-off-by: Harman Kalra 
---
v6:
 - Removed unnecessary code.
v5:
 - Fix shared library compilation error
v4:
 - used rte_io_rmb instead of rte_rmb in mbox_poll.
v3:
 - Remove experimental tag as API is defined static.
 - Merge all changes to single patch.
v2:
 - Included Makefile and meson build changes.
 - Rebased patch on 19.11-rc4

 drivers/common/octeontx2/otx2_dev.c  | 41 +++---
 drivers/common/octeontx2/otx2_mbox.c | 51 
 drivers/common/octeontx2/otx2_mbox.h |  5 +--
 3 files changed, 70 insertions(+), 27 deletions(-)

diff --git a/drivers/common/octeontx2/otx2_dev.c 
b/drivers/common/octeontx2/otx2_dev.c
index 0fc799e4a..d61c712fa 100644
--- a/drivers/common/octeontx2/otx2_dev.c
+++ b/drivers/common/octeontx2/otx2_dev.c
@@ -577,17 +577,16 @@ otx2_pf_vf_mbox_irq(void *param)
 
intr = otx2_read64(dev->bar2 + RVU_VF_INT);
if (intr == 0)
-   return;
+   otx2_base_dbg("Proceeding to check mbox UP messages if any");
 
otx2_write64(intr, dev->bar2 + RVU_VF_INT);
otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
-   if (intr) {
-   /* First process all configuration messages */
-   otx2_process_msgs(dev, dev->mbox);
 
-   /* Process Uplink messages */
-   otx2_process_msgs_up(dev, &dev->mbox_up);
-   }
+   /* First process all configuration messages */
+   otx2_process_msgs(dev, dev->mbox);
+
+   /* Process Uplink messages */
+   otx2_process_msgs_up(dev, &dev->mbox_up);
 }
 
 static void
@@ -598,18 +597,16 @@ otx2_af_pf_mbox_irq(void *param)
 
intr = otx2_read64(dev->bar2 + RVU_PF_INT);
if (intr == 0)
-   return;
+   otx2_base_dbg("Proceeding to check mbox UP messages if any");
 
otx2_write64(intr, dev->bar2 + RVU_PF_INT);
-
otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
-   if (intr) {
-   /* First process all configuration messages */
-   otx2_process_msgs(dev, dev->mbox);
 
-   /* Process Uplink messages */
-   otx2_process_msgs_up(dev, &dev->mbox_up);
-   }
+   /* First process all configuration messages */
+   otx2_process_msgs(dev, dev->mbox);
+
+   /* Process Uplink messages */
+   otx2_process_msgs_up(dev, &dev->mbox_up);
 }
 
 static int
@@ -900,6 +897,7 @@ otx2_dev_priv_init(struct rte_pci_device *pci_dev, void 
*otx2_dev)
 {
int up_direction = MBOX_DIR_PFAF_UP;
int rc, direction = MBOX_DIR_PFAF;
+   uint64_t intr_offset = RVU_PF_INT;
struct otx2_dev *dev = otx2_dev;
uintptr_t bar2, bar4;
uint64_t bar4_addr;
@@ -924,15 +922,18 @@ otx2_dev_priv_init(struct rte_pci_device *pci_dev, void 
*otx2_dev)
if (otx2_dev_is_vf(dev)) {
direction = MBOX_DIR_VFPF;
up_direction = MBOX_DIR_VFPF_UP;
+   intr_offset = RVU_VF_INT;
}
 
/* Initialize the local mbox */
-   rc = otx2_mbox_init(&dev->mbox_local, bar4, bar2, direction, 1);
+   rc = otx2_mbox_init(&dev->mbox_local, bar4, bar2, direction, 1,
+   intr_offset);
if (rc)
goto error;
dev->mbox = &dev->mbox_local;
 
-   rc = otx2_mbox_init(&dev->mbox_up, bar4, bar2, up_direction, 1);
+   rc = otx2_mbox_init(&dev->mbox_up, bar4, bar2, up_direction, 1,
+   intr_offset);
if (rc)
goto error;
 
@@ -967,13 +968,15 @@ otx2_dev_priv_init(struct rte_pci_device *pci_dev, void 
*otx2_dev)
}
/* Init mbox object */
rc = otx2_mbox_init(&dev->mbox_vfpf, (uintptr_t)hwbase,
-   bar2, MBOX_DIR_PFVF, pci_dev->max_vfs);
+   bar2, MBOX_DIR_PFVF, pci_dev->max_vfs,
+   intr_offset);
if (rc)
goto iounmap;
 
/* PF -> VF UP messages */
rc = otx2_mbox_init(&dev->mbox_vfpf_up, (uintptr_t)hwbase,
-   bar2, MBOX_DIR_PFVF_UP, pci_dev->max_vfs);
+   bar2, MBOX_DIR_PFVF_UP, pci_dev->max_vfs,
+   intr_offset);
if (rc)
goto mbox_fini;
}
diff --git a/drivers/common/octeontx2/otx2_mbox.c 
b/drivers/common/octeontx2/otx2_mbox.c
index c359bf42

[dpdk-dev] [PATCH v6 1/2] eal: add API to check if its interrupt context

[Sunil Kumar Kori]

From: Harman Kalra 

Added an API to check if current execution is in interrupt
context. This will be helpful to handle nested interrupt cases.

Signed-off-by: Harman Kalra 
Signed-off-by: Sunil Kumar Kori 
---
v6:
 - No changes.
v5:
 - Fix shared library compilation error
v4:
 - No changes.
v3:
 - API Comment is updated as per man page.
 - Scope updated within the library/driver only.
 - Remove experimental tag
v2:
 - Rebased patch on 19.11-rc4

 lib/librte_eal/common/include/rte_eal_interrupts.h | 11 +++
 lib/librte_eal/freebsd/eal/eal_interrupts.c|  5 +
 lib/librte_eal/linux/eal/eal_interrupts.c  |  5 +
 lib/librte_eal/rte_eal_version.map |  1 +
 4 files changed, 22 insertions(+)

diff --git a/lib/librte_eal/common/include/rte_eal_interrupts.h 
b/lib/librte_eal/common/include/rte_eal_interrupts.h
index b370c0d26..19d1d45ab 100644
--- a/lib/librte_eal/common/include/rte_eal_interrupts.h
+++ b/lib/librte_eal/common/include/rte_eal_interrupts.h
@@ -220,4 +220,15 @@ rte_intr_allow_others(struct rte_intr_handle *intr_handle);
 int
 rte_intr_cap_multiple(struct rte_intr_handle *intr_handle);
 
+/**
+ * @internal
+ * Check if currently executing in interrupt context
+ *
+ * @return
+ *  - non zero in case of interrupt context
+ *  - zero in case of process context
+ */
+int
+rte_thread_is_intr(void);
+
 #endif /* _RTE_EAL_INTERRUPTS_H_ */
diff --git a/lib/librte_eal/freebsd/eal/eal_interrupts.c 
b/lib/librte_eal/freebsd/eal/eal_interrupts.c
index f6831b790..ce2a27b4a 100644
--- a/lib/librte_eal/freebsd/eal/eal_interrupts.c
+++ b/lib/librte_eal/freebsd/eal/eal_interrupts.c
@@ -671,3 +671,8 @@ rte_intr_free_epoll_fd(struct rte_intr_handle *intr_handle)
 {
RTE_SET_USED(intr_handle);
 }
+
+int rte_thread_is_intr(void)
+{
+   return pthread_equal(intr_thread, pthread_self());
+}
diff --git a/lib/librte_eal/linux/eal/eal_interrupts.c 
b/lib/librte_eal/linux/eal/eal_interrupts.c
index 14ebb108c..cb8e10709 100644
--- a/lib/librte_eal/linux/eal/eal_interrupts.c
+++ b/lib/librte_eal/linux/eal/eal_interrupts.c
@@ -1488,3 +1488,8 @@ rte_intr_cap_multiple(struct rte_intr_handle *intr_handle)
 
return 0;
 }
+
+int rte_thread_is_intr(void)
+{
+   return pthread_equal(intr_thread, pthread_self());
+}
diff --git a/lib/librte_eal/rte_eal_version.map 
b/lib/librte_eal/rte_eal_version.map
index e38d02530..06ed2e9dc 100644
--- a/lib/librte_eal/rte_eal_version.map
+++ b/lib/librte_eal/rte_eal_version.map
@@ -91,6 +91,7 @@ DPDK_20.0 {
rte_intr_free_epoll_fd;
rte_intr_rx_ctl;
rte_intr_tls_epfd;
+   rte_thread_is_intr;
rte_keepalive_create;
rte_keepalive_dispatch_pings;
rte_keepalive_mark_alive;
-- 
2.17.1

Re: [dpdk-dev] [PATCH v1] net/ice: add new device IDs

[Xu, Ting]

> -Original Message-
> From: Yigit, Ferruh 
> Sent: Thursday, December 19, 2019 8:14 PM
> To: Ye, Xiaolong ; Xu, Ting 
> Cc: dev@dpdk.org; Lu, Wenzhuo ; Yang, Qiming
> ; Zhang, Qi Z 
> Subject: Re: [dpdk-dev] [PATCH v1] net/ice: add new device IDs
> 
> On 12/19/2019 2:43 AM, Ye Xiaolong wrote:
> > On 12/18, Ting Xu wrote:
> >> This patch added new device IDs for C822N.
> >>
> >> Signed-off-by: Ting Xu 
> >> ---
> >> drivers/net/ice/ice_ethdev.c | 3 +++
> >> 1 file changed, 3 insertions(+)
> >>
> >> diff --git a/drivers/net/ice/ice_ethdev.c
> >> b/drivers/net/ice/ice_ethdev.c index de189daba..2cbd82c94 100644
> >> --- a/drivers/net/ice/ice_ethdev.c
> >> +++ b/drivers/net/ice/ice_ethdev.c
> >> @@ -163,6 +163,9 @@ static const struct rte_pci_id pci_id_ice_map[] = {
> >>{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID,
> ICE_DEV_ID_E810_XXV_BACKPLANE) },
> >>{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID,
> ICE_DEV_ID_E810_XXV_QSFP) },
> >>{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID,
> ICE_DEV_ID_E810_XXV_SFP) },
> >> +  { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID,
> ICE_DEV_ID_C822N_BACKPLANE) },
> >> +  { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_QSFP) },
> >> +  { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C822N_SFP) },
> >>{ .vendor_id = 0, /* sentinel */ },
> >> };
> >>
> >> --
> >> 2.17.1
> >>
> >
> > Acked-by: Xiaolong Ye 
> >
> > Applied to dpdk-next-net-intel, Thanks.
> >
> 
> Just to double check, if this requires any update in the NIC documentation?

Hi, Ferruh, I will update docs for ice supported NICs to add C822 later. And is 
it necessary to update the 20.02 release note as well?

[dpdk-dev] [PATCH] doc: basic update for ice

[Xiaolong Ye]

The ice PMD supports 10/25/50/100 Gbps.

Signed-off-by: Xiaolong Ye 
---
 doc/guides/nics/ice.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst
index 9b90b389e..cde3fd620 100644
--- a/doc/guides/nics/ice.rst
+++ b/doc/guides/nics/ice.rst
@@ -5,7 +5,7 @@ ICE Poll Mode Driver
 ==
 
 The ice PMD (librte_pmd_ice) provides poll mode driver support for
-10/25 Gbps Intel® Ethernet 810 Series Network Adapters based on
+10/25/50/100 Gbps Intel® Ethernet 810 Series Network Adapters based on
 the Intel Ethernet Controller E810.
 
 
-- 
2.17.1

[dpdk-dev] [PATCH] net/mlx5: fix matcher metadata register c0 field setup

[Viacheslav Ovsiienko]

The metadata register c0 field in the matcher might be split
into two independent fields - the source vport index and META
item value. These fields have no permanent assigned bits, the
configuration is queried from the kernel drivers.

MLX5_SET configures the specified 32-bit field as whole entity.
For metadata register c0 we should take into account the provided
mask in order to configure the specified subfield bits only.

Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
Cc: sta...@dpdk.org

Signed-off-by: Viacheslav Ovsiienko 
---
 drivers/net/mlx5/mlx5_flow_dv.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 4c16281..893db3e 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5742,6 +5742,7 @@ struct field_modify_info modify_tcp[] = {
MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
void *misc2_v =
MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
+   uint32_t temp;
 
data &= mask;
switch (reg_type) {
@@ -5754,8 +5755,18 @@ struct field_modify_info modify_tcp[] = {
MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
break;
case REG_C_0:
-   MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
-   MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
+   /*
+* The metadata register C0 field might be divided into
+* source vport index and META item value, we should set
+* this field accorfing to specified mask, not as whole one.
+*/
+   temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
+   temp |= mask;
+   MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
+   temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
+   temp &= ~mask;
+   temp |= data;
+   MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
break;
case REG_C_1:
MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
-- 
1.8.3.1

[dpdk-dev] [PATCH] net/mlx5: fix register c0 usage for metadata entities

[Viacheslav Ovsiienko]

The register c0 might be engaged to support META and MARK
related items and actions. Also, this register might be
used by kernel to specify the source vport index. The
register c0 is split into two 16-bit fields. Depending
on the mask returned by kernel the PMD can use upper
or lower half of register c0. This patch adds the missing
support for upper half.

Fixes: e554b672aa05 ("net/mlx5: support flow tag")
Cc: sta...@dpdk.org

Signed-off-by: Viacheslav Ovsiienko 
---
 drivers/net/mlx5/mlx5_flow_dv.c | 39 +++
 1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 893db3e..f8e153c 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1088,6 +1088,14 @@ struct field_modify_info modify_tcp[] = {
if (reg < 0)
return reg;
assert(reg > 0);
+   if (reg == REG_C_0) {
+   uint32_t msk_c0 = priv->sh->dv_regc0_mask;
+   uint32_t shl_c0 = rte_bsf32(msk_c0);
+
+   data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
+   mask = rte_cpu_to_be_32(mask) & msk_c0;
+   mask = rte_cpu_to_be_32(mask << shl_c0);
+   }
reg_c_x[0].id = reg_to_field[reg];
return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
 MLX5_MODIFICATION_TYPE_SET, error);
@@ -5836,6 +5844,15 @@ struct field_modify_info modify_tcp[] = {
/* Get the metadata register index for the mark. */
reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
assert(reg > 0);
+   if (reg == REG_C_0) {
+   struct mlx5_priv *priv = dev->data->dev_private;
+   uint32_t msk_c0 = priv->sh->dv_regc0_mask;
+   uint32_t shl_c0 = rte_bsf32(msk_c0);
+
+   mask &= msk_c0;
+   mask <<= shl_c0;
+   value <<= shl_c0;
+   }
flow_dv_match_meta_reg(matcher, key, reg, value, mask);
}
 }
@@ -5917,6 +5934,8 @@ struct field_modify_info modify_tcp[] = {
 /**
  * Add tag item to matcher
  *
+ * @param[in] dev
+ *   The devich to configure through.
  * @param[in, out] matcher
  *   Flow matcher.
  * @param[in, out] key
@@ -5925,15 +5944,27 @@ struct field_modify_info modify_tcp[] = {
  *   Flow pattern to translate.
  */
 static void
-flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
+flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
+   void *matcher, void *key,
const struct rte_flow_item *item)
 {
const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
+   uint32_t mask, value;
 
assert(tag_v);
-   flow_dv_match_meta_reg(matcher, key, tag_v->id, tag_v->data,
-  tag_m ? tag_m->data : UINT32_MAX);
+   value = tag_v->data;
+   mask = tag_m ? tag_m->data : UINT32_MAX;
+   if (tag_v->id == REG_C_0) {
+   struct mlx5_priv *priv = dev->data->dev_private;
+   uint32_t msk_c0 = priv->sh->dv_regc0_mask;
+   uint32_t shl_c0 = rte_bsf32(msk_c0);
+
+   mask &= msk_c0;
+   mask <<= shl_c0;
+   value <<= shl_c0;
+   }
+   flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
 }
 
 /**
@@ -7280,7 +7311,7 @@ struct field_modify_info modify_tcp[] = {
last_item = MLX5_FLOW_ITEM_TAG;
break;
case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
-   flow_dv_translate_mlx5_item_tag(match_mask,
+   flow_dv_translate_mlx5_item_tag(dev, match_mask,
match_value, items);
last_item = MLX5_FLOW_ITEM_TAG;
break;
-- 
1.8.3.1