from:"Yueh\-Ting Chen via Phabricator via cfe\-commits"

[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

2022-02-11 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD accepted this revision.
eopXD added a comment.
This revision is now accepted and ready to land.

LGTM.
For the record the implication in this patch correspond to the note under 
v-spec 
:

> As is the case with other RISC-V extensions, it is valid to include 
> overlapping extensions in the same ISA string. For example, RV64GCV and 
> RV64GCV_Zve64f are both valid and equivalent ISA strings, as is 
> RV64GCV_Zve64f_Zve32x_Zvl128b.


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[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

2022-02-11 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

In D113336#3313909 , @junparser wrote:

> @eopXD, hi, this patch make us lost +relax and  -save-restore  by default, 
> would you please fix it?

Sure, let me look into it.
Do you have an existing test case for your situation? (Or I will make one while 
fixing)


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[PATCH] D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-isa features back after implication

2022-02-11 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD created this revision.
eopXD added reviewers: junparser, craig.topper, asb, frasercrmck.
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johnrusso, rbar.
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Previously D113336  makes 
RISCVTargetInfo::initFeatureMap return the results
processed by RISCVISAInfo, which only consists of ISA features and misses
non-ISA features like `relax` and `save-restore`.

This patch fixes the problem.


Repository:
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https://reviews.llvm.org/D119541

Files:
  clang/lib/Basic/Targets/RISCV.cpp


Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication

2022-02-11 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 407852.
eopXD added a comment.

Add testcase.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-default-features.c


Index: clang/test/Driver/riscv-default-features.c
===
--- /dev/null
+++ clang/test/Driver/riscv-default-features.c
@@ -0,0 +1,9 @@
+// RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV32
+
+// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+
+// Dummy function
+int foo(){
+  return  3;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: clang/test/Driver/riscv-default-features.c
===
--- /dev/null
+++ clang/test/Driver/riscv-default-features.c
@@ -0,0 +1,9 @@
+// RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
+
+// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+
+// Dummy function
+int foo(){
+  return  3;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication

2022-02-13 Thread Yueh-Ting Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7f51a9e2730e: [RISCV] Fix RISCVTargetInfo::initFeatureMap, 
add non-ISA features back after… (authored by eopXD).

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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-default-features.c


Index: clang/test/Driver/riscv-default-features.c
===
--- /dev/null
+++ clang/test/Driver/riscv-default-features.c
@@ -0,0 +1,9 @@
+// RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV32
+
+// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+
+// Dummy function
+int foo(){
+  return  3;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: clang/test/Driver/riscv-default-features.c
===
--- /dev/null
+++ clang/test/Driver/riscv-default-features.c
@@ -0,0 +1,9 @@
+// RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
+
+// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+
+// Dummy function
+int foo(){
+  return  3;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

2022-02-13 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

Kindly reverse ping.
May you land this change?


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[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

2022-02-13 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

Thanks!


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[PATCH] D102904: [LoopNest][LoopFlatten] Change LoopFlattenPass to LoopNest pass

2021-05-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 346965.
eopXD added a comment.
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Apply clang-tidy.


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Files:
  SECURITY.md
  clang-tools-extra/clang-tidy/modernize/RawStringLiteralCheck.cpp
  clang/include/clang/AST/DeclCXX.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/arm_mve.td
  clang/include/clang/Driver/Options.td
  clang/include/clang/Sema/ExternalSemaSource.h
  clang/include/clang/Sema/MultiplexExternalSemaSource.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Serialization/ASTReader.h
  clang/include/clang/Serialization/ASTWriter.h
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/DeclCXX.cpp
  clang/lib/Basic/Targets/M68k.cpp
  clang/lib/Basic/Targets/M68k.h
  clang/lib/CodeGen/CGDeclCXX.cpp
  clang/lib/CodeGen/CGException.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenPGO.cpp
  clang/lib/CodeGen/CodeGenPGO.h
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/M68k.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Interpreter/IncrementalExecutor.cpp
  clang/lib/Interpreter/IncrementalExecutor.h
  clang/lib/Interpreter/Interpreter.cpp
  clang/lib/Parse/Parser.cpp
  clang/lib/Sema/MultiplexExternalSemaSource.cpp
  clang/lib/Sema/SemaAccess.cpp
  clang/lib/Sema/SemaCUDA.cpp
  clang/lib/Sema/SemaConcept.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/lib/Sema/SemaDeclCXX.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaTemplate.cpp
  clang/lib/Serialization/ASTReader.cpp
  clang/lib/Serialization/ASTReaderDecl.cpp
  clang/lib/Serialization/ASTWriter.cpp
  clang/lib/Serialization/ASTWriterDecl.cpp
  clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
  clang/test/AST/ast-dump-constant-var.cu
  clang/test/ClangScanDeps/Inputs/modules_inferred_cdb.json
  clang/test/ClangScanDeps/modules-inferred-explicit-build.m
  clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rdffr.c
  clang/test/CodeGen/asan-globals-alias.cpp
  clang/test/CodeGen/asan-globals-odr.cpp
  clang/test/CodeGen/asan-globals.cpp
  clang/test/CodeGen/asan-static-odr.cpp
  clang/test/CodeGen/attr-weakref2.c
  clang/test/CodeGen/pre-ra-sched.c
  clang/test/CodeGen/semantic-interposition.c
  clang/test/CodeGenCUDA/device-stub.cu
  clang/test/CodeGenCUDA/device-var-linkage.cu
  clang/test/CodeGenCUDA/host-used-device-var.cu
  clang/test/CodeGenCUDA/managed-var.cu
  clang/test/CodeGenCUDA/static-device-var-rdc.cu
  clang/test/CodeGenCXX/debug-info-byval.cpp
  clang/test/CodeGenCXX/wasm-eh.cpp
  clang/test/CodeGenOpenCLCXX/addrspace-constructors.clcpp
  clang/test/Driver/arm-implicit-it.s
  clang/test/Driver/arm-target-as-mimplicit-it.s
  clang/test/Driver/as-options.s
  clang/test/Driver/clang-offload-bundler.c
  clang/test/Driver/lto.c
  clang/test/Driver/m68k-fixed-register.c

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-10-26 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382225.
eopXD added a comment.

Fix test fail and clang-format error.


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Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2062,7 +2062,11 @@
 "unexpected token in '.attribute' directive"))
 return true;
 
-  if (Tag == RISCVAttrs::ARCH) {
+  if (IsIntegerValue)
+getTargetStreamer().emitAttribute(Tag, IntegerValue);
+  else if (Tag != RISCVAttrs::ARCH)
+getTargetStreamer().emitTextAttribute(Tag, StringValue);
+  else {
 StringRef Arch = StringValue;
 for (auto Feature : RISCVFeatureKV)
   if (llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
@@ -2093,35 +2097,9 @@
   setFeatureBits(RISCV::Feature64Bit, "64bit");
 else
   return Error(ValueExprLoc, "bad arch string " + Arch);
-  }
 
-  if (IsIntegerValue)
-getTargetStreamer().emitAttribute(Tag, IntegerValue);
-  else {
-if (Tag != RISCVAttrs::ARCH) {
-  getTargetStreamer().emitTextAttribute(Tag, StringValue);
-} else {
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, getSTI().getFeatureBits());
-
-  // Parse that by RISCVISAInfo->
-  unsigned XLen = getFeatureBits(RISCV::Feature64Bit) ? 64 : 32;
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
-  if (!ParseResult) {
-std::string Buffer;
-raw_string_ostream OutputErrMsg(Buffer);
-handleAllErrors(ParseResult.takeError(),
-[&](llvm::StringError &ErrMsg) {
-  OutputErrMsg << ErrMsg.getMessage();
-});
-
-return Error(ValueExprLoc, OutputErrMsg.str());
-  }
-  auto &ISAInfo = *ParseResult;
-
-  // Then emit the arch string.
-  getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
-}
+// Then emit the arch string.
+getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
   }
 
   return false;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -411,7 +411,6 @@
   assert(XLen == 32 || XLen == 64);
   std::unique_ptr ISAInfo(new RISCVISAInfo(XLen));
 
-  bool HasE = false;
   for (auto &Feature : Features) {
 StringRef ExtName = Feature;
 bool Experimental = false;
@@ -430,29 +429,19 @@
 if (ExtensionInfoIterator == ExtensionInfos.end())
   continue;
 
-if (Add) {
-  if (ExtName == "e") {
-if (XLen != 32)
-  return createStringError(
-  errc::invalid_argument,
-  "standard user-level extension 'e' requires 'rv32'");
-HasE = true;
-  }
-
+if (Add)
   ISAInfo->addExtension(ExtName, ExtensionInfoIterator->Version.Major,
 ExtensionInfoIterator->Version.Minor);
-} else
-  ISAInfo->Exts.erase(ExtName.str());
-  }
-  if (!HasE) {
-if (auto Version = findDefaultVersion("i"))
-  ISAInfo->addExtension("i", Version->Major, Version->Minor);
 else
-  llvm_unreachable("Default extension version for 'i' not found?");
+  ISAInfo->Exts.erase(ExtName.str());
   }
 
+  ISAInfo->updateImplication();
   ISAInfo->updateFLen();
 
+  if (Error Result = ISAInfo->checkDependency())
+return std::move(Result);
+
   return std::move(ISAInfo);
 }
 
@@ -478,7 +467,6 @@
   // The canonical order specified in ISA manual.
   // Ref: Table 22.1 in RISC-V User-Level ISA V2.2
   StringRef StdExts = AllStdExts;
-  bool HasF = false, HasD = false;
   char Baseline = Arch[4];
 
   // First letter should be 'e', 'i' or 'g'.
@@ -499,8 +487,6 @@
   case 'g':
 // g = imafd
 StdExts = StdExts.drop_front(4);
-HasF = true;
-HasD = true;
 break;
   }
 
@@ -581,34 +567,14 @@
 
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
-switch (C) {
-default:
-  // Currently LLVM supports only "mafdcbv".
+// Currently LLVM supports only "mafdcbv".
+StringRef SupportedStandardExtens

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-10-26 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382250.
eopXD added a comment.

Update code and test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

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Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  clang/test/Driver/riscv-arch.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2062,7 +2062,11 @@
 "unexpected token in '.attribute' directive"))
 return true;
 
-  if (Tag == RISCVAttrs::ARCH) {
+  if (IsIntegerValue)
+getTargetStreamer().emitAttribute(Tag, IntegerValue);
+  else if (Tag != RISCVAttrs::ARCH)
+getTargetStreamer().emitTextAttribute(Tag, StringValue);
+  else {
 StringRef Arch = StringValue;
 for (auto Feature : RISCVFeatureKV)
   if (llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
@@ -2070,7 +2074,7 @@
 
 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
 StringValue, /*EnableExperimentalExtension=*/true,
-/*ExperimentalExtensionVersionCheck=*/false);
+/*ExperimentalExtensionVersionCheck=*/true);
 if (!ParseResult) {
   std::string Buffer;
   raw_string_ostream OutputErrMsg(Buffer);
@@ -2093,35 +2097,9 @@
   setFeatureBits(RISCV::Feature64Bit, "64bit");
 else
   return Error(ValueExprLoc, "bad arch string " + Arch);
-  }
 
-  if (IsIntegerValue)
-getTargetStreamer().emitAttribute(Tag, IntegerValue);
-  else {
-if (Tag != RISCVAttrs::ARCH) {
-  getTargetStreamer().emitTextAttribute(Tag, StringValue);
-} else {
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, getSTI().getFeatureBits());
-
-  // Parse that by RISCVISAInfo->
-  unsigned XLen = getFeatureBits(RISCV::Feature64Bit) ? 64 : 32;
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
-  if (!ParseResult) {
-std::string Buffer;
-raw_string_ostream OutputErrMsg(Buffer);
-handleAllErrors(ParseResult.takeError(),
-[&](llvm::StringError &ErrMsg) {
-  OutputErrMsg << ErrMsg.getMessage();
-});
-
-return Error(ValueExprLoc, OutputErrMsg.str());
-  }
-  auto &ISAInfo = *ParseResult;
-
-  // Then emit the arch string.
-  getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
-}
+// Then emit the arch string.
+getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
   }
 
   return false;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -360,6 +360,11 @@
 
 if (ExperimentalExtensionVersionCheck &&
 (MajorStr.empty() && MinorStr.empty())) {
+  if (auto DefaultVersion = findDefaultVersion(Ext)) {
+Major = DefaultVersion->Major;
+Minor = DefaultVersion->Minor;
+return Error::success();
+  }
   std::string Error =
   "experimental extension requires explicit version number `" +
   Ext.str() + "`";
@@ -411,7 +416,6 @@
   assert(XLen == 32 || XLen == 64);
   std::unique_ptr ISAInfo(new RISCVISAInfo(XLen));
 
-  bool HasE = false;
   for (auto &Feature : Features) {
 StringRef ExtName = Feature;
 bool Experimental = false;
@@ -430,29 +434,19 @@
 if (ExtensionInfoIterator == ExtensionInfos.end())
   continue;
 
-if (Add) {
-  if (ExtName == "e") {
-if (XLen != 32)
-  return createStringError(
-  errc::invalid_argument,
-  "standard user-level extension 'e' requires 'rv32'");
-HasE = true;
-  }
-
+if (Add)
   ISAInfo->addExtension(ExtName, ExtensionInfoIterator->Version.Major,
 ExtensionInfoIterator->Version.Minor);
-} else
-  ISAInfo->Exts.erase(ExtName.str());
-  }
-  if (!HasE) {
-if (auto Version = findDefaultVersion("i"))
-  ISAInfo->addExtension("i", Version->Major, Version->Minor);
 else
-  llvm_unreachable("Default extension version for 'i' not found?");
+  ISAInfo->Exts.erase(ExtName.str());
   }
 
+  ISAInfo->updateImplication();
   ISAInfo->updateFLen();
 
+  if (Error Result = ISAInfo->c

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-10-26 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

The test cases are modified because unifying the logic here shows the place 
where clang / llvm deal with target feature inconsistently.
I think it would be beneficial if we have them consistent.

- Test cases with `clang -cc1` originally don't do dependency check to target 
feature specified
  - This patch add target feature so that dependency checks can pass

- Originally clang driver's `-march` enforces version to be specified, while 
llvm allows `.attribute arch` to not specify version (and picks the default one)
  - This patch lets clang search for default version if no version is specified 
(so delete `NOVERS` test case in `clang/test/Driver/riscv-arch.c`


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[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:141
+  // either v or zve* suppaort v instructions
+  bool hasStdExtV() const { return HasStdExtV || HasStdExtZve32x; }
+  bool hasStdExtZve32x() const { return HasStdExtZve32x; }

craig.topper wrote:
> frasercrmck wrote:
> > Is this correct? I thought we'd keep `hasStdExtV` as being the 
> > single-letter V extension, and Zve32x isn't that.
> I just put up D112496 to stop using hasStdExtV everywhere.
Thank you @craig.topper for the patch.
LGTM, and we can have it landed after this series on `zvl`, `zve` patch are 
done.


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[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382540.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -42,7 +42,7 @@
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
@@ -54,7 +54,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -72,8 +72,

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382543.
eopXD added a comment.

Fix clang-format.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -42,7 +42,7 @@
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
@@ -54,7 +54,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382544.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32ifdv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -42,7 +42,7 @@
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
@@ -54,7 +54,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -72,8

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:735
   const StringMap> Implications = {
-{"v", {"zvlsseg", "zvl128b"}},
+{"v", {"zvlsseg", "zvl128b", "zve64d"}},
+

khchen wrote:
> please update implication rule based on 
> https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-949542444
> 1. The Zve32f and Zve64f extensions depend upon the F extension
> 2. The Zve64d extension depends upon the D extension
> 3. The V extension depends upon the F and D
Thanks for the reminder. Addressed.



Comment at: llvm/test/CodeGen/RISCV/attributes.ll:8
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C 
%s
-; RUN: llc -mtriple=riscv32 
-mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | 
FileCheck --check-prefix=RV32V %s
+; RUN: llc -mtriple=riscv32 
-mattr=+f,+d,+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - 
| FileCheck --check-prefix=RV32V %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck 
--check-prefix=RV32ZFH %s

frasercrmck wrote:
> Why is this being changed in this patch?
You are right. This should not be changed.

Removed.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D112408/new/

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[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

Sorry I mixed zvl patch when rebasing. I will remove it ASAP.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382571.
eopXD added a comment.

Add implication: v imply d and f


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382574.
eopXD added a comment.

Address comments:

- remove duplicate `checkDependency()`
- stay consistent in my patch of using auto for `StringRef`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382582.
eopXD added a comment.

Update.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --che

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD marked an inline comment as done.
eopXD added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:181
   }
 
+  if (MinVLen) {

khchen wrote:
> please add a note in commit or comment here for those macros are proposed in 
> the PR https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21
Added in commit message.



Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:65
+  unsigned getMinVLen() const { return MinVLen; }
+  unsigned getMaxEew() const { return MaxEew; }
+  unsigned getMaxEewFp() const { return MaxEewFp; }

frasercrmck wrote:
> Aside from the discussion about EEW vs. ELEN, something about the 
> capitalization irks me. I realise we already have `XLen` but `Eew` looks... 
> wrong. If other people disagree then that's fine.
Hi Fraser,
FYI, I think there is a discussion happening 
[here](https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21#issuecomment-952307965).



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[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382628.
eopXD marked 4 inline comments as done.
eopXD added a comment.

Change:

- Address commments on restrictions in RISCVSubtarget.cpp
- Fix clang-format fail
- Fix test case fail


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | F

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:134
  "maximum!");
+  assert(RVVVectorBitsMin >= ZvlLen &&
+ "Minimum V extension vector length should be at least the length "

eopXD wrote:
> craig.topper wrote:
> > eopXD wrote:
> > > craig.topper wrote:
> > > > HsiangKai wrote:
> > > > > Should it be `RVVVectorBitsMin < ZvlLen`?
> > > > > 
> > > > > I suggest to return 0 and print a warning message for users.
> > > > This isn't a good place to print warnings. It would just be a random 
> > > > message printed to stderr without going through any of clang's 
> > > > diagnostic infrastructure.
> > > I think moving the check to `initializeSubtargetDependencies` and use 
> > > `report_fatal_error` will be a more appropriate approach?
> > I think that causes clang to generate a crash report and telling the user 
> > to file a bug.
> > 
> > Forgot to mention, all this code is also being modified by D107290
> I see, then my proposal is invalid.
> 
> I am not yet that familiar with the code base. I see `RISCVFrameLowering.cpp` 
> using `LLVMContext::diagnose`, but `RISCVSubtarget` here doesn't seem to have 
> access to `LLVMContext`. 
> 
> May you recommend a pointer to some diagnose function I can use to tell the 
> user this is an invalid setting between `RVVVectorBitsMin`(from 
> `riscv-v-vector-bits-min`) and `ZvlLen` (from `-march=zvl*b`)?
I see code under `RISCVSubtarget::initializeSubtargetDependencies` also using 
`report_fatal_error`:



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[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382879.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -35,14 +35,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-pref

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 382880.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -35,14 +35,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-pref

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-27 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:112
 return 0;
-  assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
+  assert(RVVVectorBitsMax >= 32 && RVVVectorBitsMax <= 65536 &&
  isPowerOf2_32(RVVVectorBitsMax) &&

HsiangKai wrote:
> craig.topper wrote:
> > The max should be greater than ZvlLen right?
> Should it be less than or equal to ZvlLen? I would suggest to return 0 when 
> `RVVVectorBitsMax > ZvlLen`.
> The value also needs to `>= 64`.
@HsiangKai I think you mis-typed the equation? It should be `RVVVectorBitsMax < 
ZvlLen` ;)




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

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[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-30 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383599.
eopXD added a comment.
Herald added subscribers: VincentWu, luke957.

Fix test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -35,14 +35,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+e

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-30 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383601.
eopXD added a comment.

Rebase to newest main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -35,14 +35,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --

[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

2021-10-30 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383605.
eopXD added a comment.
Herald added subscribers: VincentWu, luke957.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109215/new/

https://reviews.llvm.org/D109215

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -71,6 +71,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef &Ext) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -637,7 +659,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', multi-character extensions must be separated by 
underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -71,6 +71,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef &Ext) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -637,7 +659,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', unsupp

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-10-30 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383606.
eopXD added a comment.
Herald added subscribers: VincentWu, luke957.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  clang/test/Driver/riscv-arch.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2062,7 +2062,11 @@
 "unexpected token in '.attribute' directive"))
 return true;
 
-  if (Tag == RISCVAttrs::ARCH) {
+  if (IsIntegerValue)
+getTargetStreamer().emitAttribute(Tag, IntegerValue);
+  else if (Tag != RISCVAttrs::ARCH)
+getTargetStreamer().emitTextAttribute(Tag, StringValue);
+  else {
 StringRef Arch = StringValue;
 for (auto Feature : RISCVFeatureKV)
   if (llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
@@ -2070,7 +2074,7 @@
 
 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
 StringValue, /*EnableExperimentalExtension=*/true,
-/*ExperimentalExtensionVersionCheck=*/false);
+/*ExperimentalExtensionVersionCheck=*/true);
 if (!ParseResult) {
   std::string Buffer;
   raw_string_ostream OutputErrMsg(Buffer);
@@ -2093,35 +2097,9 @@
   setFeatureBits(RISCV::Feature64Bit, "64bit");
 else
   return Error(ValueExprLoc, "bad arch string " + Arch);
-  }
 
-  if (IsIntegerValue)
-getTargetStreamer().emitAttribute(Tag, IntegerValue);
-  else {
-if (Tag != RISCVAttrs::ARCH) {
-  getTargetStreamer().emitTextAttribute(Tag, StringValue);
-} else {
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, getSTI().getFeatureBits());
-
-  // Parse that by RISCVISAInfo->
-  unsigned XLen = getFeatureBits(RISCV::Feature64Bit) ? 64 : 32;
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
-  if (!ParseResult) {
-std::string Buffer;
-raw_string_ostream OutputErrMsg(Buffer);
-handleAllErrors(ParseResult.takeError(),
-[&](llvm::StringError &ErrMsg) {
-  OutputErrMsg << ErrMsg.getMessage();
-});
-
-return Error(ValueExprLoc, OutputErrMsg.str());
-  }
-  auto &ISAInfo = *ParseResult;
-
-  // Then emit the arch string.
-  getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
-}
+// Then emit the arch string.
+getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
   }
 
   return false;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -360,6 +360,11 @@
 
 if (ExperimentalExtensionVersionCheck &&
 (MajorStr.empty() && MinorStr.empty())) {
+  if (auto DefaultVersion = findDefaultVersion(Ext)) {
+Major = DefaultVersion->Major;
+Minor = DefaultVersion->Minor;
+return Error::success();
+  }
   std::string Error =
   "experimental extension requires explicit version number `" +
   Ext.str() + "`";
@@ -411,7 +416,6 @@
   assert(XLen == 32 || XLen == 64);
   std::unique_ptr ISAInfo(new RISCVISAInfo(XLen));
 
-  bool HasE = false;
   for (auto &Feature : Features) {
 StringRef ExtName = Feature;
 bool Experimental = false;
@@ -430,29 +434,19 @@
 if (ExtensionInfoIterator == ExtensionInfos.end())
   continue;
 
-if (Add) {
-  if (ExtName == "e") {
-if (XLen != 32)
-  return createStringError(
-  errc::invalid_argument,
-  "standard user-level extension 'e' requires 'rv32'");
-HasE = true;
-  }
-
+if (Add)
   ISAInfo->addExtension(ExtName, ExtensionInfoIterator->Version.Major,
 ExtensionInfoIterator->Version.Minor);
-} else
-  ISAInfo->Exts.erase(ExtName.str());
-  }
-  if (!HasE) {
-if (auto Version = findDefaultVersion("i"))
-  ISAInfo->addExtension("i", Version->Major, Version->Minor);
 else
-  llvm_unreachable("Default extension version for 'i' not found?");
+  ISAInfo->Exts.erase(ExtName.str());
   }
 
+  ISAInfo->updateImplication();
   ISAInfo->updateFLen();
 
+  if

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-10-30 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383607.
eopXD added a comment.

Address comment: Enforce user to specify version checks.

@asb Thank you for leaving comments for this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2062,7 +2062,11 @@
 "unexpected token in '.attribute' directive"))
 return true;
 
-  if (Tag == RISCVAttrs::ARCH) {
+  if (IsIntegerValue)
+getTargetStreamer().emitAttribute(Tag, IntegerValue);
+  else if (Tag != RISCVAttrs::ARCH)
+getTargetStreamer().emitTextAttribute(Tag, StringValue);
+  else {
 StringRef Arch = StringValue;
 for (auto Feature : RISCVFeatureKV)
   if (llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
@@ -2093,35 +2097,9 @@
   setFeatureBits(RISCV::Feature64Bit, "64bit");
 else
   return Error(ValueExprLoc, "bad arch string " + Arch);
-  }
 
-  if (IsIntegerValue)
-getTargetStreamer().emitAttribute(Tag, IntegerValue);
-  else {
-if (Tag != RISCVAttrs::ARCH) {
-  getTargetStreamer().emitTextAttribute(Tag, StringValue);
-} else {
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, getSTI().getFeatureBits());
-
-  // Parse that by RISCVISAInfo->
-  unsigned XLen = getFeatureBits(RISCV::Feature64Bit) ? 64 : 32;
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
-  if (!ParseResult) {
-std::string Buffer;
-raw_string_ostream OutputErrMsg(Buffer);
-handleAllErrors(ParseResult.takeError(),
-[&](llvm::StringError &ErrMsg) {
-  OutputErrMsg << ErrMsg.getMessage();
-});
-
-return Error(ValueExprLoc, OutputErrMsg.str());
-  }
-  auto &ISAInfo = *ParseResult;
-
-  // Then emit the arch string.
-  getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
-}
+// Then emit the arch string.
+getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
   }
 
   return false;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -411,7 +411,6 @@
   assert(XLen == 32 || XLen == 64);
   std::unique_ptr ISAInfo(new RISCVISAInfo(XLen));
 
-  bool HasE = false;
   for (auto &Feature : Features) {
 StringRef ExtName = Feature;
 bool Experimental = false;
@@ -430,29 +429,19 @@
 if (ExtensionInfoIterator == ExtensionInfos.end())
   continue;
 
-if (Add) {
-  if (ExtName == "e") {
-if (XLen != 32)
-  return createStringError(
-  errc::invalid_argument,
-  "standard user-level extension 'e' requires 'rv32'");
-HasE = true;
-  }
-
+if (Add)
   ISAInfo->addExtension(ExtName, ExtensionInfoIterator->Version.Major,
 ExtensionInfoIterator->Version.Minor);
-} else
-  ISAInfo->Exts.erase(ExtName.str());
-  }
-  if (!HasE) {
-if (auto Version = findDefaultVersion("i"))
-  ISAInfo->addExtension("i", Version->Major, Version->Minor);
 else
-  llvm_unreachable("Default extension version for 'i' not found?");
+  ISAInfo->Exts.erase(ExtName.str());
   }
 
+  ISAInfo->updateImplication();
   ISAInfo->updateFLen();
 
+  if (Error Result = ISAInfo->checkDependency())
+return std::move(Result);
+
   return std::move(ISAInfo);
 }
 
@@ -478,7 +467,6 @@
   // The canonical order specified in ISA manual.
   // Ref: Table 22.1 in RISC-V User-Level ISA V2.2
   StringRef StdExts = AllStdExts;
-  bool HasF = false, HasD = false;
   char Baseline = Arch[4];
 
   // First letter should be 'e', 'i' or 'g'.
@@ -499,8 +487,6 @@
   case 'g':
 // g = imafd
 StdExts = StdExts.drop_front(4);
-HasF = true;
-HasD = true;
 break;
   }
 
@@ -581,34 +567,14 @@
 
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
-switch (C) {
-default:
-  // Currently LLVM supports only "mafdcbv".
+// Curren

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-10-30 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383608.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,7 +70,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32iv_zvamo0p10_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl64b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl128b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl256b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl512b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl1024b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl2048b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl4096b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl8192b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl16384b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl32768b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv_zvl65536b"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -35,14 +35,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-10-31 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383647.
eopXD added a comment.

Set `ExperimentalExtensionVersionCheck=true` for RISCVISAInfo::parseArchString 
in `RISCVAsmParser.cpp`

Add version numbers for test case in `attribute-arch.s`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,44 +33,41 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv"
+.attribute arch, "rv32iv0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
-.attribute arch, "rv32izba"
+.attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
 
-.attribute arch, "rv32izbb"
+.attribute arch, "rv32izbb1p0"
 # CHECK: attribute  5, "rv32i2p0_zbb1p0"
 
-.attribute arch, "rv32izbc"
+.attribute arch, "rv32izbc1p0"
 # CHECK: attribute  5, "rv32i2p0_zbc1p0"
 
-.attribute arch, "rv32izbe"
+.attribute arch, "rv32izbe0p93"
 # CHECK: attribute  5, "rv32i2p0_zbe0p93"
 
-.attribute arch, "rv32izbf"
+.attribute arch, "rv32izbf0p93"
 # CHECK: attribute  5, "rv32i2p0_zbf0p93"
 
-.attribute arch, "rv32izbm"
+.attribute arch, "rv32izbm0p93"
 # CHECK: attribute  5, "rv32i2p0_zbm0p93"
 
-.attribute arch, "rv32izbp"
+.attribute arch, "rv32izbp0p93"
 # CHECK: attribute  5, "rv32i2p0_zbp0p93"
 
-.attribute arch, "rv32izbr"
+.attribute arch, "rv32izbr0p93"
 # CHECK: attribute  5, "rv32i2p0_zbr0p93"
 
-.attribute arch, "rv32izbs"
+.attribute arch, "rv32izbs1p0"
 # CHECK: attribute  5, "rv32i2p0_zbs1p0"
 
-.attribute arch, "rv32izbt"
+.attribute arch, "rv32izbt0p93"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
-.attribute arch, "rv32ifzfh"
+.attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
-.attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
-
-.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2062,7 +2062,11 @@
 "unexpected token in '.attribute' directive"))
 return true;
 
-  if (Tag == RISCVAttrs::ARCH) {
+  if (IsIntegerValue)
+getTargetStreamer().emitAttribute(Tag, IntegerValue);
+  else if (Tag != RISCVAttrs::ARCH)
+getTargetStreamer().emitTextAttribute(Tag, StringValue);
+  else {
 StringRef Arch = StringValue;
 for (auto Feature : RISCVFeatureKV)
   if (llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
@@ -2070,7 +2074,7 @@
 
 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
 StringValue, /*EnableExperimentalExtension=*/true,
-/*ExperimentalExtensionVersionCheck=*/false);
+/*ExperimentalExtensionVersionCheck=*/true);
 if (!ParseResult) {
   std::string Buffer;
   raw_string_ostream OutputErrMsg(Buffer);
@@ -2093,35 +2097,9 @@
   setFeatureBits(RISCV::Feature64Bit, "64bit");
 else
   return Error(ValueExprLoc, "bad arch string " + Arch);
-  }
 
-  if (IsIntegerValue)
-getTargetStreamer().emitAttribute(Tag, IntegerValue);
-  else {
-if (Tag != RISCVAttrs::ARCH) {
-  getTargetStreamer().emitTextAttribute(Tag, StringValue);
-} else {
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, getSTI().getFeatureBits());
-
-  // Parse that by RISCVISAInfo->
-  unsigned XLen = getFeatureBits(RISCV::Feature64Bit) ? 64 : 32;
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
-  if (!ParseResult) {
-std::string Buffer;
-raw_string_ostream OutputErrMsg(Buffer);
-handleAllErrors(ParseResult.takeError(),
-[&](llvm::StringError &ErrMsg) {
-  OutputErrMsg << ErrMsg.getMessage();
-});
-
-return Error(ValueExprLoc, OutputErrMsg.str());
-

[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

2021-11-01 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383732.
eopXD added a comment.

rebase.`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109215/new/

https://reviews.llvm.org/D109215

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -71,6 +71,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef &Ext) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -637,7 +659,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', multi-character extensions must be separated by 
underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -71,6 +71,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef &Ext) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -637,7 +659,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-11-01 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383733.
eopXD added a comment.

rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,44 +33,41 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv"
+.attribute arch, "rv32iv0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
-.attribute arch, "rv32izba"
+.attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
 
-.attribute arch, "rv32izbb"
+.attribute arch, "rv32izbb1p0"
 # CHECK: attribute  5, "rv32i2p0_zbb1p0"
 
-.attribute arch, "rv32izbc"
+.attribute arch, "rv32izbc1p0"
 # CHECK: attribute  5, "rv32i2p0_zbc1p0"
 
-.attribute arch, "rv32izbe"
+.attribute arch, "rv32izbe0p93"
 # CHECK: attribute  5, "rv32i2p0_zbe0p93"
 
-.attribute arch, "rv32izbf"
+.attribute arch, "rv32izbf0p93"
 # CHECK: attribute  5, "rv32i2p0_zbf0p93"
 
-.attribute arch, "rv32izbm"
+.attribute arch, "rv32izbm0p93"
 # CHECK: attribute  5, "rv32i2p0_zbm0p93"
 
-.attribute arch, "rv32izbp"
+.attribute arch, "rv32izbp0p93"
 # CHECK: attribute  5, "rv32i2p0_zbp0p93"
 
-.attribute arch, "rv32izbr"
+.attribute arch, "rv32izbr0p93"
 # CHECK: attribute  5, "rv32i2p0_zbr0p93"
 
-.attribute arch, "rv32izbs"
+.attribute arch, "rv32izbs1p0"
 # CHECK: attribute  5, "rv32i2p0_zbs1p0"
 
-.attribute arch, "rv32izbt"
+.attribute arch, "rv32izbt0p93"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
-.attribute arch, "rv32ifzfh"
+.attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
-.attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
-
-.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2062,7 +2062,11 @@
 "unexpected token in '.attribute' directive"))
 return true;
 
-  if (Tag == RISCVAttrs::ARCH) {
+  if (IsIntegerValue)
+getTargetStreamer().emitAttribute(Tag, IntegerValue);
+  else if (Tag != RISCVAttrs::ARCH)
+getTargetStreamer().emitTextAttribute(Tag, StringValue);
+  else {
 StringRef Arch = StringValue;
 for (auto Feature : RISCVFeatureKV)
   if (llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
@@ -2070,7 +2074,7 @@
 
 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
 StringValue, /*EnableExperimentalExtension=*/true,
-/*ExperimentalExtensionVersionCheck=*/false);
+/*ExperimentalExtensionVersionCheck=*/true);
 if (!ParseResult) {
   std::string Buffer;
   raw_string_ostream OutputErrMsg(Buffer);
@@ -2093,35 +2097,9 @@
   setFeatureBits(RISCV::Feature64Bit, "64bit");
 else
   return Error(ValueExprLoc, "bad arch string " + Arch);
-  }
 
-  if (IsIntegerValue)
-getTargetStreamer().emitAttribute(Tag, IntegerValue);
-  else {
-if (Tag != RISCVAttrs::ARCH) {
-  getTargetStreamer().emitTextAttribute(Tag, StringValue);
-} else {
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, getSTI().getFeatureBits());
-
-  // Parse that by RISCVISAInfo->
-  unsigned XLen = getFeatureBits(RISCV::Feature64Bit) ? 64 : 32;
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
-  if (!ParseResult) {
-std::string Buffer;
-raw_string_ostream OutputErrMsg(Buffer);
-handleAllErrors(ParseResult.takeError(),
-[&](llvm::StringError &ErrMsg) {
-  OutputErrMsg << ErrMsg.getMessage();
-});
-
-return Error(ValueExprLoc, OutputErrMsg.str());
-  }
-  auto &ISAInfo = *ParseResult;
-
-  // Then emit the arch string.
-  getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
-

[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

2021-11-01 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383773.
eopXD added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109215/new/

https://reviews.llvm.org/D109215

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -71,6 +71,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef &Ext) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -637,7 +659,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', multi-character extensions must be separated by 
underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -71,6 +71,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef &Ext) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -637,7 +659,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-11-01 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383775.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,44 +33,41 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv"
+.attribute arch, "rv32iv0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
-.attribute arch, "rv32izba"
+.attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
 
-.attribute arch, "rv32izbb"
+.attribute arch, "rv32izbb1p0"
 # CHECK: attribute  5, "rv32i2p0_zbb1p0"
 
-.attribute arch, "rv32izbc"
+.attribute arch, "rv32izbc1p0"
 # CHECK: attribute  5, "rv32i2p0_zbc1p0"
 
-.attribute arch, "rv32izbe"
+.attribute arch, "rv32izbe0p93"
 # CHECK: attribute  5, "rv32i2p0_zbe0p93"
 
-.attribute arch, "rv32izbf"
+.attribute arch, "rv32izbf0p93"
 # CHECK: attribute  5, "rv32i2p0_zbf0p93"
 
-.attribute arch, "rv32izbm"
+.attribute arch, "rv32izbm0p93"
 # CHECK: attribute  5, "rv32i2p0_zbm0p93"
 
-.attribute arch, "rv32izbp"
+.attribute arch, "rv32izbp0p93"
 # CHECK: attribute  5, "rv32i2p0_zbp0p93"
 
-.attribute arch, "rv32izbr"
+.attribute arch, "rv32izbr0p93"
 # CHECK: attribute  5, "rv32i2p0_zbr0p93"
 
-.attribute arch, "rv32izbs"
+.attribute arch, "rv32izbs1p0"
 # CHECK: attribute  5, "rv32i2p0_zbs1p0"
 
-.attribute arch, "rv32izbt"
+.attribute arch, "rv32izbt0p93"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
-.attribute arch, "rv32ifzfh"
+.attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
-.attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
-
-.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2062,7 +2062,11 @@
 "unexpected token in '.attribute' directive"))
 return true;
 
-  if (Tag == RISCVAttrs::ARCH) {
+  if (IsIntegerValue)
+getTargetStreamer().emitAttribute(Tag, IntegerValue);
+  else if (Tag != RISCVAttrs::ARCH)
+getTargetStreamer().emitTextAttribute(Tag, StringValue);
+  else {
 StringRef Arch = StringValue;
 for (auto Feature : RISCVFeatureKV)
   if (llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
@@ -2070,7 +2074,7 @@
 
 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
 StringValue, /*EnableExperimentalExtension=*/true,
-/*ExperimentalExtensionVersionCheck=*/false);
+/*ExperimentalExtensionVersionCheck=*/true);
 if (!ParseResult) {
   std::string Buffer;
   raw_string_ostream OutputErrMsg(Buffer);
@@ -2093,35 +2097,9 @@
   setFeatureBits(RISCV::Feature64Bit, "64bit");
 else
   return Error(ValueExprLoc, "bad arch string " + Arch);
-  }
 
-  if (IsIntegerValue)
-getTargetStreamer().emitAttribute(Tag, IntegerValue);
-  else {
-if (Tag != RISCVAttrs::ARCH) {
-  getTargetStreamer().emitTextAttribute(Tag, StringValue);
-} else {
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, getSTI().getFeatureBits());
-
-  // Parse that by RISCVISAInfo->
-  unsigned XLen = getFeatureBits(RISCV::Feature64Bit) ? 64 : 32;
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
-  if (!ParseResult) {
-std::string Buffer;
-raw_string_ostream OutputErrMsg(Buffer);
-handleAllErrors(ParseResult.takeError(),
-[&](llvm::StringError &ErrMsg) {
-  OutputErrMsg << ErrMsg.getMessage();
-});
-
-return Error(ValueExprLoc, OutputErrMsg.str());
-  }
-  auto &ISAInfo = *ParseResult;
-
-  // Then emit the arch string.
-  getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
-

[PATCH] D108694: [WIP][RISCV] Add the zvl extension according to the v1.0-rc2 spec

2021-11-01 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383952.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,7 +34,7 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -70,4 +70,40 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -17,7 +17,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -35,14 +35,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ;

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

2021-11-02 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD created this revision.
eopXD added reviewers: kito.cheng, craig.topper.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,8 +33,8 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -69,56 +69,56 @@
 .attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
-.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvamo0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvamo1p0_zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvamo1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

2021-11-02 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 383987.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,8 +33,8 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -69,56 +69,56 @@
 .attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
-.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvamo0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvamo1p0_zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvamo1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0

[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

2021-11-02 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a reviewer: asb.
eopXD added a comment.

@asb @jrtc27 
Hi Alex and Jessica,

Although the issue on relaxing naming rules aren't resolved in riscv-isa-manual 
[1], the v-spec v1.0 had come out including `zve` and `zvl` extensions and is 
frozen [2].
I have just finished a series of patch for adding extension `zve`, `zvl` 
support onto LLVM. (Please check the related revisions)
The patches rely on this patch to land, may you share your thought on this.

Thank you.

[1] https://github.com/riscv/riscv-isa-manual/pull/718
[2] https://github.com/riscv/riscv-v-spec/releases/tag/v1.0


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109215/new/

https://reviews.llvm.org/D109215

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[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-11-05 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

@asb Thanks for the reply.

To clarify the question, the 2 inconsistencies are:

- Test cases with `clang -cc1` originally don't do dependency check to target 
feature specified (handled by `parseFeatures`)
- Clang driver's -march enforces version to be specified, while llvm allows 
`.attribute` arch to not specify version (and picks the default one)

What this patch tries to do, letting the 2 actions (`parseFeatures` and 
`parseArchString`) rely on the same function call will mean to alter the 
behavior on one of them.
In my humble opinion, it is rather awkward to make this patch an NFC will 
unifying the logics of them.
Maybe we can first come to a conclusion on how do we unify and then implement 
them in this patch.

The main intentions of unifying them is that there will be some implications 
and dependency checks on the addition of zve and zvl,
so unifying the logics will make the addition have less code duplication.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

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[PATCH] D113336: [Clang][RISCV] Let clang_cc1 be able to imply feautes

2021-11-06 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD created this revision.
eopXD added a reviewer: craig.topper.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, asb, hiraditya.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Under ASTContext, clang only copies the features from the options with
Target->initFeatureMap, and no implications is done there. Add implication
using RISCVISAInfo.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113336

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -796,3 +796,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -65,6 +65,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -212,7 +212,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -796,3 +796,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -65,6 +65,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -212,7 +212,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

2021-11-06 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added inline comments.



Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c:3
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v 
-disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck 
--check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x 
-target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - | 
opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 

craig.topper wrote:
> Why do we need to add zve32x and zve64x to the command line? Doesn't zve64x 
> imply zve32x?
Just added D113336 to resolve this. I will rebase this patch and change test 
cases.


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[PATCH] D113336: [RISCV] Let clang_cc1 be able to imply features

2021-11-06 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 385256.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113336/new/

https://reviews.llvm.org/D113336

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -826,3 +826,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -826,3 +826,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D113336: [RISCV] Let clang_cc1 be able to imply features

2021-11-06 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 385258.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113336/new/

https://reviews.llvm.org/D113336

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D113336: [RISCV] Let clang_cc1 be able to imply features

2021-11-06 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 385275.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113336/new/

https://reviews.llvm.org/D113336

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

2021-11-06 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 385276.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112613/new/

https://reviews.llvm.org/D112613

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1021,7 +1021,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1021,7 +1021,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (g

[PATCH] D113336: [RISCV] Let clang_cc1 be able to imply features

2021-11-06 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 385277.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113336/new/

https://reviews.llvm.org/D113336

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

2021-11-06 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 385278.
eopXD added a comment.

Update code.


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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1021,7 +1021,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1021,7 +1021,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
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[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

2021-11-06 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD marked an inline comment as done.
eopXD added inline comments.



Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c:3
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v 
-disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck 
--check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x 
-target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - | 
opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 

eopXD wrote:
> craig.topper wrote:
> > Why do we need to add zve32x and zve64x to the command line? Doesn't zve64x 
> > imply zve32x?
> Just added D113336 to resolve this. I will rebase this patch and change test 
> cases.
Rebased.


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[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

2021-11-07 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 385329.
eopXD added a comment.

Rebase.


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  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -72,6 +72,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef &Ext) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -638,7 +660,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', multi-character extensions must be separated by 
underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -72,6 +72,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef &Ext) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -638,7 +660,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-11-11 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

ping, thank you.


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[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

2021-11-28 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 390187.
eopXD added a comment.

- Update code (zfh have been added recently.
- Added test case `attribute-arch-invalid.s` to show that experimental 
extensions need to specify the version explicitly.


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Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/attribute-arch-invalid.s
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,47 +33,46 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv"
+## Experimental extensions require version string to be explicitly specified
+
+.attribute arch, "rv32iv0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
-.attribute arch, "rv32izba"
+.attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
 
-.attribute arch, "rv32izbb"
+.attribute arch, "rv32izbb1p0"
 # CHECK: attribute  5, "rv32i2p0_zbb1p0"
 
-.attribute arch, "rv32izbc"
+.attribute arch, "rv32izbc1p0"
 # CHECK: attribute  5, "rv32i2p0_zbc1p0"
 
-.attribute arch, "rv32izbe"
+.attribute arch, "rv32izbe0p93"
 # CHECK: attribute  5, "rv32i2p0_zbe0p93"
 
-.attribute arch, "rv32izbf"
+.attribute arch, "rv32izbf0p93"
 # CHECK: attribute  5, "rv32i2p0_zbf0p93"
 
-.attribute arch, "rv32izbm"
+.attribute arch, "rv32izbm0p93"
 # CHECK: attribute  5, "rv32i2p0_zbm0p93"
 
-.attribute arch, "rv32izbp"
+.attribute arch, "rv32izbp0p93"
 # CHECK: attribute  5, "rv32i2p0_zbp0p93"
 
-.attribute arch, "rv32izbr"
+.attribute arch, "rv32izbr0p93"
 # CHECK: attribute  5, "rv32i2p0_zbr0p93"
 
-.attribute arch, "rv32izbs"
+.attribute arch, "rv32izbs1p0"
 # CHECK: attribute  5, "rv32i2p0_zbs1p0"
 
-.attribute arch, "rv32izbt"
+.attribute arch, "rv32izbt0p93"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
-.attribute arch, "rv32ifzfhmin"
+.attribute arch, "rv32ifzfhmin0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfhmin0p1"
 
-.attribute arch, "rv32ifzfh"
+.attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
-.attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
-
-.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/test/MC/RISCV/attribute-arch-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/attribute-arch-invalid.s
@@ -0,0 +1,48 @@
+## Invalid arch string
+
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
+
+## Version strings are required for experimental extensions
+
+.attribute arch, "rv32iv"
+# CHECK: error: invalid arch name 'rv32iv', experimental extension requires explicit version number `v`
+
+.attribute arch, "rv32izba"
+# CHECK: error: invalid arch name 'rv32izba', experimental extension requires explicit version number `zba`
+
+.attribute arch, "rv32izbb"
+# CHECK: error: invalid arch name 'rv32izbb', experimental extension requires explicit version number `zbb`
+
+.attribute arch, "rv32izbc"
+# CHECK: error: invalid arch name 'rv32izbc', experimental extension requires explicit version number `zbc`
+
+.attribute arch, "rv32izbe"
+# CHECK:  error: invalid arch name 'rv32izbe', experimental extension requires explicit version number `zbe`
+
+.attribute arch, "rv32izbf"
+# CHECK: error: invalid arch name 'rv32izbf', experimental extension requires explicit version number `zbf`
+
+.attribute arch, "rv32izbm"
+# CHECK: error: invalid arch name 'rv32izbm', experimental extension requires explicit version number `zbm`
+
+.attribute arch, "rv32izbp"
+# CHECK: error: invalid arch name 'rv32izbp', experimental extension requires explicit version number `zbp`
+
+.attribute arch, "rv32izbr"
+# CHECK: error: invalid arch name 'rv32izbr', experimental extension requires explicit version number `zbr`
+
+.attribute arch, "rv32izbs"
+# CHECK: error: invalid arch name 'rv32izbs', experimental extension requires explicit version number `zbs`
+
+.attribute arch, "rv32izbt"
+# CHECK: error:

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

2022-01-18 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1499
   foreach nf=2-8 in {
+// Vector Unit-strided Segment Instructions
+def VLSEG#nf#E64_V :

craig.topper wrote:
> The unit-stride and strided with EEW=64 don't require RV64. Just the indexed 
> versions.
Thank you for catching this.


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[PATCH] D117724: [RISCV] Remove Zvlsseg extension.

2022-01-19 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

Thank you for doing this patch, I was about to do it after I land zve.


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[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

2022-01-19 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added inline comments.



Comment at: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \
 ; RUN: -verify-machineinstrs < %s | FileCheck %s

achieveartificialintelligence wrote:
> Do we need `+f` here?
Yes. D should imply F now. Let me create a another patch for it as the current 
patch is for zve.


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[PATCH] D112986: [RISCV] Restrict zvamo, zvlsseg with zve macro-s

2022-01-19 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD abandoned this revision.
eopXD added a comment.

This revision is no longer needed as zvamo and zvlsseg will be removed from 
arch string.


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[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

2022-01-19 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401525.
eopXD added a comment.

Rebase to latest main.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

This patch needs to be landed before D112613  
because clang_cc1 needs to do correct implication from `v`, `zve32f`, `zve64f` 
and `zve64d` and this patch fixes the issue.


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[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401541.
eopXD marked an inline comment as done.
eopXD added a comment.

Update code based on @kito-cheng 's comment.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113336/new/

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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
 const std::vector &FeaturesVec) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
 const std::vector &FeaturesVec) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  return TargetInfo::initFeatureMap(Fe

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401546.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
 const std::vector &FeaturesVec) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.c

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401549.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112613/new/

https://reviews.llvm.org/D112613

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
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[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG60b6e73769f8: [RISCV] Imply extensions in 
RISCVTargetInfo::initFeatureMap (authored by eopXD).

Repository:
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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
 const std::vector &FeaturesVec) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
 const std::vector &FeaturesVec) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  r

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401554.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112613/new/

https://reviews.llvm.org/D112613

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
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[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401564.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -35,8 +35,8 @@
 
 ## Experimental extensions require version string to be explicitly specified
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,56 +74,56 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_z

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

Apply @frasercrmck 's suggested title, thanks!


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[PATCH] D112986: [RISCV] Restrict zvamo, zvlsseg with zve macro-s

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD reclaimed this revision.
eopXD added a comment.

This was closed by my misunderstanding.
For clang we still need to do some restrictions based on ELEN.
Reopening.


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[PATCH] D112613: [Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG14c5fd920b0e: [Clang][RISCV] Change TARGET_BUILTIN to 
require zve32x for vector instruction (authored by eopXD).

Repository:
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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
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[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401684.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,14 +137,19 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint16_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : uint16_t {
   Basic = 0,
   F = 1 << 1,
   D = 1 << 2,
   Zfh = 1 << 3,
   Zvlsseg = 1 << 4,
   RV64 = 1 << 5,
+  VectorMaxELen32 = 1 << 6,
+  VectorMaxELen64 = 1 << 7,
+  VectorMaxELenFp32 = 1 << 8,
+  VectorMaxELenFp64 = 1 << 9,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -165,7 +173,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -189,7 +197,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector &getIntrinsicTypes() const {
 return IntrinsicTypes;
@@ -252,7 +262,7 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream &o);
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros, raw_ostream &o);
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -790,17 +800,26 @@
   // Init RISC-V extensions
   for (const auto &T : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
 else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::F;
 else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::D;
+
+if (T->isVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen32;
+else if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+else if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "Zvlsseg")
-  RISCVExtensions |= RISCVExtension::Zvlsseg;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zvlsseg;
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -984,7 +1003,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1283,15 +1302,15 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> &Defs, raw_ostream &OS,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros = (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto &Def : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401687.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,14 +137,19 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint16_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : uint16_t {
   Basic = 0,
   F = 1 << 1,
   D = 1 << 2,
   Zfh = 1 << 3,
   Zvlsseg = 1 << 4,
   RV64 = 1 << 5,
+  VectorMaxELen32 = 1 << 6,
+  VectorMaxELen64 = 1 << 7,
+  VectorMaxELenFp32 = 1 << 8,
+  VectorMaxELenFp64 = 1 << 9,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -165,7 +173,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -189,7 +197,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector &getIntrinsicTypes() const {
 return IntrinsicTypes;
@@ -252,7 +262,7 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream &o);
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros, raw_ostream &o);
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -790,17 +800,26 @@
   // Init RISC-V extensions
   for (const auto &T : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
 else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::F;
 else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::D;
+
+if (T->isVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen32;
+else if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+else if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "Zvlsseg")
-  RISCVExtensions |= RISCVExtension::Zvlsseg;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zvlsseg;
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -984,7 +1003,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1283,15 +1302,15 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> &Defs, raw_ostream &OS,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros = (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto &Def : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {

[PATCH] D117808: [NFC][RISCV] Add end-of-line symbol in target-feature testcases

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD created this revision.
eopXD added a reviewer: craig.topper.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, asb.
eopXD requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
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https://reviews.llvm.org/D117808

Files:
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,14 +7,14 @@
 // CHECK-NOT: __riscv_m
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
-// CHECK-NOT: __riscv_a 200
+// CHECK-NOT: __riscv_a 200{{$}}
 // CHECK-NOT: __riscv_atomic
-// CHECK-NOT: __riscv_f 200
+// CHECK-NOT: __riscv_f 200{{$}}
 // CHECK-NOT: __riscv_d
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
-// CHECK-NOT: __riscv_c 200
+// CHECK-NOT: __riscv_c 200{{$}}
 // CHECK-NOT: __riscv_compressed
 // CHECK-NOT: __riscv_b
 // CHECK-NOT: __riscv_bitmanip
@@ -38,7 +38,7 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
-// CHECK-M-EXT: __riscv_m 200
+// CHECK-M-EXT: __riscv_m 200{{$}}
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -46,14 +46,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
-// CHECK-A-EXT: __riscv_a 200
+// CHECK-A-EXT: __riscv_a 200{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
-// CHECK-F-EXT: __riscv_f 200
+// CHECK-F-EXT: __riscv_f 200{{$}}
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -62,7 +62,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
-// CHECK-D-EXT: __riscv_d 200
+// CHECK-D-EXT: __riscv_d 200{{$}}
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -95,7 +95,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// CHECK-C-EXT: __riscv_c 200
+// CHECK-C-EXT: __riscv_c 200{{$}}
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -150,7 +150,7 @@
 // RUN: -march=rv64izbe0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s
 // CHECK-ZBE-NOT: __riscv_b
-// CHECK-ZBE-EXT: __riscv_zbe 93000
+// CHECK-ZBE-EXT: __riscv_zbe 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbf0p93 -x c -E -dM %s \
@@ -159,7 +159,7 @@
 // RUN: -march=rv64izbf0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBF-EXT %s
 // CHECK-ZBF-NOT: __riscv_b
-// CHECK-ZBF-EXT: __riscv_zbf 93000
+// CHECK-ZBF-EXT: __riscv_zbf 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbm0p93 -x c -E -dM %s \
@@ -168,7 +168,7 @@
 // RUN: -march=rv64izbm0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBM-EXT %s
 // CHECK-ZBM-NOT: __riscv_b
-// CHECK-ZBM-EXT: __riscv_zbm 93000
+// CHECK-ZBM-EXT: __riscv_zbm 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbp0p93 -x c -E -dM %s \
@@ -177,7 +177,7 @@
 // RUN: -march=rv64izbp0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBP-EXT %s
 // CHECK-ZBP-NOT: __riscv_b
-// CHECK-ZBP-EXT: __riscv_zbp 93000
+// CHECK-ZBP-EXT: __riscv_zbp 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbr0p93 -x c -E -dM %s \
@@ -186,7 +186,7 @@
 // RUN: -march=rv64izbr0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s
 // CHECK-ZBR-NOT: __riscv_b
-// CHECK-ZBR-EXT: __riscv_zbr 93000
+// CHECK-ZBR-EXT: __riscv_zbr 93000{{$}}
 
 // RUN: %clang -target riscv32-

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD marked an inline comment as done.
eopXD added inline comments.



Comment at: clang/test/Preprocessor/riscv-target-features.c:221
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// CHECK-V-EXT: __riscv_v 1
+// CHECK-V-EXT: __riscv_v 100
 // CHECK-V-EXT: __riscv_vector 1

craig.topper wrote:
> Does this line pass even if you don't change it since we don't match to the 
> end of the line? I might suggest we go through this file and put `{{{$}}` on 
> the end of lines, but that can be a separate change. Or we add the `#define` 
> to each line and pass --match-full-lines to FileCheck.
Created D117808


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[PATCH] D117808: [NFC][RISCV] Add end-of-line symbol in target-feature testcases

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

Missed test case for zfh is found by adding end-of-lines ;)


Repository:
  rG LLVM Github Monorepo

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[PATCH] D117808: [NFC][RISCV] Add end-of-line symbol in target-feature testcases

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb58cc9fb2348: [NFC][RISCV] Add end-of-line symbol in 
target-feature testcases (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117808/new/

https://reviews.llvm.org/D117808

Files:
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,14 +7,14 @@
 // CHECK-NOT: __riscv_m
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
-// CHECK-NOT: __riscv_a 200
+// CHECK-NOT: __riscv_a 200{{$}}
 // CHECK-NOT: __riscv_atomic
-// CHECK-NOT: __riscv_f 200
+// CHECK-NOT: __riscv_f 200{{$}}
 // CHECK-NOT: __riscv_d
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
-// CHECK-NOT: __riscv_c 200
+// CHECK-NOT: __riscv_c 200{{$}}
 // CHECK-NOT: __riscv_compressed
 // CHECK-NOT: __riscv_b
 // CHECK-NOT: __riscv_bitmanip
@@ -38,7 +38,7 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
-// CHECK-M-EXT: __riscv_m 200
+// CHECK-M-EXT: __riscv_m 200{{$}}
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -46,14 +46,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
-// CHECK-A-EXT: __riscv_a 200
+// CHECK-A-EXT: __riscv_a 200{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
-// CHECK-F-EXT: __riscv_f 200
+// CHECK-F-EXT: __riscv_f 200{{$}}
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -62,7 +62,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
-// CHECK-D-EXT: __riscv_d 200
+// CHECK-D-EXT: __riscv_d 200{{$}}
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -95,7 +95,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// CHECK-C-EXT: __riscv_c 200
+// CHECK-C-EXT: __riscv_c 200{{$}}
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -150,7 +150,7 @@
 // RUN: -march=rv64izbe0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s
 // CHECK-ZBE-NOT: __riscv_b
-// CHECK-ZBE-EXT: __riscv_zbe 93000
+// CHECK-ZBE-EXT: __riscv_zbe 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbf0p93 -x c -E -dM %s \
@@ -159,7 +159,7 @@
 // RUN: -march=rv64izbf0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBF-EXT %s
 // CHECK-ZBF-NOT: __riscv_b
-// CHECK-ZBF-EXT: __riscv_zbf 93000
+// CHECK-ZBF-EXT: __riscv_zbf 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbm0p93 -x c -E -dM %s \
@@ -168,7 +168,7 @@
 // RUN: -march=rv64izbm0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBM-EXT %s
 // CHECK-ZBM-NOT: __riscv_b
-// CHECK-ZBM-EXT: __riscv_zbm 93000
+// CHECK-ZBM-EXT: __riscv_zbm 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbp0p93 -x c -E -dM %s \
@@ -177,7 +177,7 @@
 // RUN: -march=rv64izbp0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBP-EXT %s
 // CHECK-ZBP-NOT: __riscv_b
-// CHECK-ZBP-EXT: __riscv_zbp 93000
+// CHECK-ZBP-EXT: __riscv_zbp 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbr0p93 -x c -E -dM %s \
@@ -186,7 +186,7 @@
 // RUN: -march=rv64izbr0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s
 // CHECK-ZBR-NOT: __riscv_b
-// CHECK-ZBR-EXT: __riscv_zbr 93000
+// CHECK-ZBR-EXT: __riscv_zbr 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32izbs1p0 -x c -E -dM %s \
@@ -210,7 +210,7 @@
 // RUN: -march=rv64izbt0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBT-EXT %s
 //

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401700.
eopXD marked an inline comment as done.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -35,8 +35,8 @@
 
 ## Experimental extensions require version string to be explicitly specified
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,56 +74,56 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401861.
eopXD added a comment.

Rebase.
Resolve conflict due to zvlsseg removal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -35,8 +35,8 @@
 
 ## Experimental extensions require version string to be explicitly specified
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,59 +74,59 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl8192b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401862.
eopXD marked 2 inline comments as done.
eopXD added a comment.

Rebase and addres comments.
Resolve conflcits due to zvlsseg removal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,13 +137,17 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint8_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
   Basic = 0,
   F = 1 << 1,
   D = 1 << 2,
   Zfh = 1 << 3,
   RV64 = 1 << 4,
+  VectorMaxELen64 = 1 << 5,
+  VectorMaxELenFp32 = 1 << 6,
+  VectorMaxELenFp64 = 1 << 7,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -164,7 +171,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -188,7 +195,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector &getIntrinsicTypes() const {
 return IntrinsicTypes;
@@ -251,7 +260,7 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream &o);
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros, raw_ostream &o);
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -789,15 +798,17 @@
   // Init RISC-V extensions
   for (const auto &T : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
-else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
-else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
+if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -981,7 +992,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1280,15 +1291,15 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> &Defs, raw_ostream &OS,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros = (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto &Def : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << "#endif\n\n";
-  NeedEndif = emitExtDefStr(CurExt, OS);
-  PrevExt = CurExt;
+  NeedEndif = emitMacroRestrictionStr(CurMacros, OS);
+  PrevMacros = CurMacros;
 }
 if (Def->hasAutoDef())
   PrintBody(OS, *Def);
@@ -1297,19 +1308,26 @@
 OS << "

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:149
   RV64 = 1 << 5,
+  VectorMaxELen32 = 1 << 6,
+  VectorMaxELen64 = 1 << 7,

craig.topper wrote:
> Do we need VectorMaxELen32 isn't that the minimum?
Yes you are correct. We don't need it.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:804
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
 else if (T->isFloatVector(32) || T->isFloat(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::F;

craig.topper wrote:
> Can D and F go away?
Done.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 401870.
eopXD added a comment.

Follow clang-format.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,13 +137,17 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint8_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
   Basic = 0,
   F = 1 << 1,
   D = 1 << 2,
   Zfh = 1 << 3,
   RV64 = 1 << 4,
+  VectorMaxELen64 = 1 << 5,
+  VectorMaxELenFp32 = 1 << 6,
+  VectorMaxELenFp64 = 1 << 7,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -164,7 +171,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -188,7 +195,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector &getIntrinsicTypes() const {
 return IntrinsicTypes;
@@ -251,7 +260,8 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream &o);
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
+   raw_ostream &o);
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -789,15 +799,17 @@
   // Init RISC-V extensions
   for (const auto &T : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
-else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
-else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
+if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -981,7 +993,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1280,15 +1292,16 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> &Defs, raw_ostream &OS,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros =
+  (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto &Def : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << "#endif\n\n";
-  NeedEndif = emitExtDefStr(CurExt, OS);
-  PrevExt = CurExt;
+  NeedEndif = emitMacroRestrictionStr(CurMacros, OS);
+  PrevMacros = CurMacros;
 }
 if (Def->hasAutoDef())
   PrintBody(OS, *Def);
@@ -1297,19 +1310,26 @@
 OS << "#endif\n\n";
 }
 
-bool RVVEmitter::emitExtDefStr(

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

2022-01-20 Thread Yueh-Ting Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe6de53b4de4a: [RISCV] Bump rvv-related extensions from 0.10 
to 1.0 (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -35,8 +35,8 @@
 
 ## Experimental extensions require version string to be explicitly specified
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,59 +74,59 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl8192b0p

[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD created this revision.
eopXD added reviewers: craig.topper, asb, frasercrmck.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
armkevincheng, eric-k256, vkmr, jdoerfert, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, qcolombet, MatzeB.
Herald added a reviewer: sjarus.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Extensions affected: +v, +zve*, +zvl*


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117860

Files:
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clan

[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 402034.
eopXD added a comment.

Cleanup redundant code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117860/new/

https://reviews.llvm.org/D117860

Files:
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 402036.
eopXD marked an inline comment as done.
eopXD added a comment.

Cleanup unused enum.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,13 +137,15 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint8_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
   Basic = 0,
-  F = 1 << 1,
-  D = 1 << 2,
-  Zfh = 1 << 3,
-  RV64 = 1 << 4,
+  Zfh = 1 << 1,
+  RV64 = 1 << 2,
+  VectorMaxELen64 = 1 << 3,
+  VectorMaxELenFp32 = 1 << 4,
+  VectorMaxELenFp64 = 1 << 5,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -164,7 +169,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -188,7 +193,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector &getIntrinsicTypes() const {
 return IntrinsicTypes;
@@ -251,7 +258,8 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream &o);
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
+   raw_ostream &o);
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -789,15 +797,17 @@
   // Init RISC-V extensions
   for (const auto &T : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
-else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
-else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
+if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -981,7 +991,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1280,15 +1290,16 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> &Defs, raw_ostream &OS,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros =
+  (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto &Def : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << "#endif\n\n";
-  NeedEndif = emitExtDefStr(CurExt, OS);
-  PrevExt = CurExt;
+  NeedEndif = emitMacroRestrictionStr(CurMacros, OS);
+  PrevMacros = CurMacros;
 }
 if (Def->hasAutoDef())
   PrintBody(OS, *Def);
@@ -1297,19

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtins with zve macros

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

In D112986#3261933 , @frasercrmck 
wrote:

> LGTM too. Though the commit title and message has hyphens in places I 
> wouldn't expect them. `macros` and `builtins` is fine.

Thank you to also drop by and take a look :)




Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:797
 
   // Init RISC-V extensions
   for (const auto &T : OutInTypes) {

frasercrmck wrote:
> nit: This still says "extensions"
Yeah I thought of not changing the variable name, however as other enums are 
added in keeping it as "extensions" is a bit strange to me.


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[PATCH] D112986: [Clang][RISCV] Restrict rvv builtins with zve macros

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe6ceec9c1d19: [Clang][RISCV] Restrict rvv builtins with zve 
macros (authored by eopXD).

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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,13 +137,15 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint8_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
   Basic = 0,
-  F = 1 << 1,
-  D = 1 << 2,
-  Zfh = 1 << 3,
-  RV64 = 1 << 4,
+  Zfh = 1 << 1,
+  RV64 = 1 << 2,
+  VectorMaxELen64 = 1 << 3,
+  VectorMaxELenFp32 = 1 << 4,
+  VectorMaxELenFp64 = 1 << 5,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -164,7 +169,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -188,7 +193,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector &getIntrinsicTypes() const {
 return IntrinsicTypes;
@@ -251,7 +258,8 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream &o);
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
+   raw_ostream &o);
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -789,15 +797,17 @@
   // Init RISC-V extensions
   for (const auto &T : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
-else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
-else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
+if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -981,7 +991,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr &A,
  const std::unique_ptr &B) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1280,15 +1290,16 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> &Defs, raw_ostream &OS,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros =
+  (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto &Def : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << "#endif\n\n";
-  NeedEndif = emitExtDefStr(CurExt, OS);
-  PrevExt = CurExt;
+  NeedEndif = emitMacroRestrictionStr(CurMacros, OS

[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

In D117860#3261453 , @frasercrmck 
wrote:

> Thanks for the patch! Not sure the best way to review this. The tests are 
> passing, which is a good sign. One option could be to split the "meaningful" 
> changes into a separate diff for easier viewing? We probably don't need to 
> see all the test RUN line changes, for example.

Non-testcase file changes are:

  M   clang/utils/TableGen/RISCVVEmitter.cpp
  M   llvm/lib/Support/RISCVISAInfo.cpp
  M   llvm/lib/Target/RISCV/RISCV.td

Do you mean creating separate this patch into two? Won't that cause build 
failure?


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[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

I changed the test commands in `vmul.c` and `vsmul.c` to use `zve64d` to make 
sure I don't miss anything I should move to the created files - `vmul-eew64.c` 
and `vsmul-eew64.c`


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[PATCH] D117920: [RISCV] Decouple V and Zve64*

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD created this revision.
eopXD added reviewers: craig.topper, asb.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, hiraditya.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Now with existing macros to imply elen and elen_fp for rvv, we should decouple
the implication between V and Zve*.


Repository:
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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -690,7 +690,7 @@
   bool HasE = Exts.count("e") == 1;
   bool HasD = Exts.count("d") == 1;
   bool HasF = Exts.count("f") == 1;
-  bool HasVector = Exts.count("zve32x") == 1;
+  bool HasVector = Exts.count("v") == 1 || Exts.count("zve32x") == 1;
   bool HasZve32f = Exts.count("zve32f") == 1;
   bool HasZve64d = Exts.count("zve64d") == 1;
   bool HasZvl = MinVLen != 0;
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1034,7 +1034,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-zve32x\")\n";
+"ATTRS, \"experimental-zve32x|v\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +188,7 @@
   if (ISAInfo->hasExtension("c"))
 Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x"))
+  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v"))
 Builder.defineMacro("__riscv_vector");
 }
 


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -690,7 +690,7 @@
   bool HasE = Exts.count("e") == 1;
   bool HasD = Exts.count("d") == 1;
   bool HasF = Exts.count("f") == 1;
-  bool HasVector = Exts.count("zve32x") == 1;
+  bool HasVector = Exts.count("v") == 1 || Exts.count("zve32x") == 1;
   bool HasZve32f = Exts.count("zve32f") == 1;
   bool HasZve64d = Exts.count("zve64d") == 1;
   bool HasZvl = MinVLen != 0;
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1034,7 +1034,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-zve32x\")\n";
+"ATTRS, \"experimental-zve32x|v\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +18

[PATCH] D117920: [RISCV] Decouple V and Zve64*

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 402080.
eopXD added a comment.

Update code.


Repository:
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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "zve32x", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +188,7 @@
   if (ISAInfo->hasExtension("c"))
 Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x"))
+  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v"))
 Builder.defineMacro("__riscv_vector");
 }
 


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "zve32x", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +188,7 @@
   if (ISAInfo->hasExtension("c"))
 Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x"))
+  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v"))
 Builder.defineMacro("__riscv_vector");
 }
 
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[PATCH] D117920: [RISCV] Decouple V and Zve64*

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 402085.
eopXD added a comment.

Update code.


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Files:
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "zve32x", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "zve32x", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
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[PATCH] D117920: [RISCV] Decouple V and Zve64*

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 402170.
eopXD added a comment.

Update code: adjust testcase due to change of implication.


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Files:
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  llvm/test/MC/RISCV/attribute-arch.s


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,43 +75,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
 .attribute arch, "rv32iv1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl32b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl64b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl128b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl256b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl512b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl1024b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl2048b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl4096b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl8192b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32iv1p0zvl16384b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32iv1p0zvl32768b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1

[PATCH] D117920: [RISCV] Decouple V and Zve64*

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 402172.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117920/new/

https://reviews.llvm.org/D117920

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,43 +75,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
 .attribute arch, "rv32iv1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl32b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl64b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl128b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl256b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl512b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl1024b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl2048b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl4096b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl8192b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32iv1p0zvl16384b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32iv1p0zvl32768b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_

[PATCH] D117920: [RISCV] Decouple V and Zve64*

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD abandoned this revision.
eopXD added a comment.

In D117920#3263202 , @jacquesguan 
wrote:

> I did some similar change in my revision https://reviews.llvm.org/D117854.

Yeah I guess we can do that all in one commit.
Thank you for doing it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117920/new/

https://reviews.llvm.org/D117920

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[PATCH] D117854: [RISCV] Refactor Zve* extensions.

2022-01-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

Maybe change the title to address more specifically of what this patch does?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

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[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

2022-01-22 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD updated this revision to Diff 402192.
eopXD added a comment.

Rebase.
Resolve conflict due to addition of zbkc.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117860/new/

https://reviews.llvm.org/D117860

Files:
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  clang/test/Cod

[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

2022-01-22 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

In D117913#3263493 , @khchen wrote:

> why the new test filename extension is `.c.c`?

Thanks for the reminder.


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[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

2022-01-22 Thread Yueh-Ting Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG3cf15af2daa9: [RISCV] Remove experimental prefix from 
rvv-related extensions. (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117860/new/

https://reviews.llvm.org/D117860

Files:
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  c

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

2022-01-26 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD added a comment.

Not sure if this simplifies things. Users and the compiler  can use the macro 
__riscv_v_elen and __riscv_v_elen_fp to do things to the vector-related target 
feature.

Other than that I dont hold any strong objection to this refactoring.


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[PATCH] D120297: [Driver][RISCV] Add missing rv64 test case

2022-02-21 Thread Yueh-Ting Chen via Phabricator via cfe-commits

eopXD created this revision.
eopXD added a reviewer: rogfer01.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, asb.
eopXD requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead.
Herald added a project: clang.

Add missing test case. Thanks @rogfer01 for spotting this out.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120297

Files:
  clang/test/Driver/riscv-default-features.c


Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -1,4 +1,5 @@
 // RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV32
+// RUN: %clang -target riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV64
 
 // RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"


Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -1,4 +1,5 @@
 // RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
+// RUN: %clang -target riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
 
 // RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
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