[clang] 4431d64 - Support ExtVectorType conditional operator
Author: Min-Yih Hsu
Date: 2020-06-02T16:35:42Z
New Revision: 4431d64c10cb681986e752420f1136f259daa5a7
URL:
https://github.com/llvm/llvm-project/commit/4431d64c10cb681986e752420f1136f259daa5a7
DIFF:
https://github.com/llvm/llvm-project/commit/4431d64c10cb681986e752420f1136f259daa5a7.diff
LOG: Support ExtVectorType conditional operator
Extension vectors now can be used in element-wise conditional selector.
For example:
```
R[i] = C[i]? A[i] : B[i]
```
This feature was previously only enabled in OpenCL C. Now it's also
available in C. Not that it has different behaviors than GNU vectors
(i.e. __vector_size__). Extension vectors selects on signdness of the
vector. GNU vectors on the other hand do normal bool conversions. Also,
this feature is not available in C++.
Differential Revision: https://reviews.llvm.org/D80574
Added:
Modified:
clang/docs/LanguageExtensions.rst
clang/lib/CodeGen/CGExprScalar.cpp
clang/lib/Sema/SemaExpr.cpp
clang/test/Sema/ext_vector_comparisons.c
Removed:
diff --git a/clang/docs/LanguageExtensions.rst
b/clang/docs/LanguageExtensions.rst
index 2fbf5ea5eb01..d3d73bf238f9 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -478,7 +478,7 @@ bitwise operators &,|,^,~yes yes yes
--
!, &&, ||yes --yes [#]_--
==, !=, >, <, >=, <= yes yes yes --
=yes yes yes yes
-:? [#]_ yes --yes --
+?: [#]_ yes --yes --
sizeof yes yes yes yes
C-style cast yes yes yes no
reinterpret_cast yes noyes no
@@ -489,9 +489,11 @@ const_cast no nono
no
See also :ref:`langext-__builtin_shufflevector`,
:ref:`langext-__builtin_convertvector`.
.. [#] unary operator ! is not implemented, however && and || are.
-.. [#] While OpenCL and GCC vectors both implement the comparison operator(?:)
as a
- 'select', they operate somewhat
diff erently. OpenCL selects based on signedness of
- the condition operands, but GCC vectors use normal bool conversions (that
is, != 0).
+.. [#] ternary operator(?:) has
diff erent behaviors depending on condition
+ operand's vector type. If the condition is a GNU vector (i.e.
__vector_size__),
+ it's only available in C++ and uses normal bool conversions (that is, != 0).
+ If it's an extension (OpenCL) vector, it's only available in C and OpenCL C.
+ And it selects base on signedness of the condition operands (OpenCL v1.1
s6.3.9).
Matrix Types
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp
b/clang/lib/CodeGen/CGExprScalar.cpp
index 028a2cf49c4d..b169462f535a 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -4432,8 +4432,8 @@ VisitAbstractConditionalOperator(const
AbstractConditionalOperator *E) {
// OpenCL: If the condition is a vector, we can treat this condition like
// the select function.
- if (CGF.getLangOpts().OpenCL
- && condExpr->getType()->isVectorType()) {
+ if ((CGF.getLangOpts().OpenCL && condExpr->getType()->isVectorType()) ||
+ condExpr->getType()->isExtVectorType()) {
CGF.incrementProfileCounter(E);
llvm::Value *CondV = CGF.EmitScalarExpr(condExpr);
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 2221f98b943a..5e8b1d8a37cc 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -8078,7 +8078,8 @@ QualType Sema::CheckConditionalOperands(ExprResult &Cond,
ExprResult &LHS,
// The OpenCL operator with a vector condition is sufficiently
//
diff erent to merit its own checker.
- if (getLangOpts().OpenCL && Cond.get()->getType()->isVectorType())
+ if ((getLangOpts().OpenCL && Cond.get()->getType()->isVectorType()) ||
+ Cond.get()->getType()->isExtVectorType())
return OpenCLCheckVectorConditional(*this, Cond, LHS, RHS, QuestionLoc);
// First, check the condition.
diff --git a/clang/test/Sema/ext_vector_comparisons.c
b/clang/test/Sema/ext_vector_comparisons.c
index 4c632a412f44..f1c292ff4a4d 100644
--- a/clang/test/Sema/ext_vector_comparisons.c
+++ b/clang/test/Sema/ext_vector_comparisons.c
@@ -28,3 +28,19 @@ static int4 test2() {
return vec > vec; // no-warning
return vec >= vec; // no-warning
}
+
+static int4 test3() {
+ int4 i0, i1;
+
+ return i0 > i1 ? i0 : i1; // no-error
+ return i0 ? i0 : i1; // no-error
+}
+
+static float4 test4() {
+ float4 f0, f1;
+
+ // This would actually generate implicit casting warning
+ // under Weverything flag but we don't really care here
+ return f0 > f1 ? f0 : f1; // no-error
+ return f
[clang-tools-extra] [llvm] [clang] [flang] [compiler-rt] [Legalizer] Expand fmaximum and fminimum (PR #67301)
https://github.com/mshockwave approved this pull request. LGTM. It will be great if you could add RISCV test too, but please don't let this block you. https://github.com/llvm/llvm-project/pull/67301 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang-tools-extra] [compiler-rt] [llvm] [clang] [Legalizer] Expand fmaximum and fminimum (PR #67301)
https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/67301 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [flang] [clang-tools-extra] [clang] [llvm] [Legalizer] Expand fmaximum and fminimum (PR #67301)
@@ -523,9 +523,10 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom);
-if (Subtarget.hasStdExtZfa())
+if (Subtarget.hasStdExtZfa()) {
setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
-else
+ setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f32, Legal);
+} else
mshockwave wrote:
style: please add curly braces here as well to match the if branch
https://github.com/llvm/llvm-project/pull/67301
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[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)
https://github.com/mshockwave created
https://github.com/llvm/llvm-project/pull/71197
Previously, if a linker flag (i.e. -Wl) is presented before any input
filenames, Gnu driver would use the InputInfo object of that flag to generate
stats filename for LTO backend, causing an empty filename. This patch fixes
such issue.
>From 8d5acb56b364648d1abd6bfff6815af71e131d6e Mon Sep 17 00:00:00 2001
From: Min Hsu
Date: Thu, 2 Nov 2023 17:26:17 -0700
Subject: [PATCH] [Clang][Driver][LTO] Fix empty stats filename when in LTO
mode
Previously, if a linker flag (i.e.g -Wl) is presented before any input
filenames, Gnu driver would use the InputInfo object of that flag to
generate stats filename for LTO backend, causing an empty filename.
This patch fixes such issue.
---
clang/lib/Driver/ToolChains/Gnu.cpp | 10 +-
clang/test/Driver/save-stats.c | 2 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 5237951f84cce03..8448d4bda13c434 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -535,7 +535,15 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
if (D.isUsingLTO()) {
assert(!Inputs.empty() && "Must have at least one input.");
-addLTOOptions(ToolChain, Args, CmdArgs, Output, Inputs[0],
+// Find the first filename InputInfo object.
+auto Input = llvm::find_if(
+Inputs, [](const InputInfo &II) -> bool { return II.isFilename(); });
+if (Input == Inputs.end())
+ // For a very rare case, all of the inputs to the linker are
+ // flags. If that happens, just use the first InputInfo.
+ Input = Inputs.begin();
+
+addLTOOptions(ToolChain, Args, CmdArgs, Output, *Input,
D.getLTOMode() == LTOK_Thin);
}
diff --git a/clang/test/Driver/save-stats.c b/clang/test/Driver/save-stats.c
index ca8f2a457d4488c..d6ad4e0097f3432 100644
--- a/clang/test/Driver/save-stats.c
+++ b/clang/test/Driver/save-stats.c
@@ -20,6 +20,8 @@
// CHECK-INVALID: invalid value 'bla' in '-save-stats=bla'
// RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o
obj/dir/save-stats.exe %s -### 2>&1 | FileCheck %s -check-prefix=CHECK-LTO
+// Previously `-plugin-opt=stats-file` would use empty filename if a linker
flag (i.e. -Wl) is presented before any input filename.
+// RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o
obj/dir/save-stats.exe -Wl,-plugin-opt=-dummy %s -### 2>&1 | FileCheck %s
-check-prefix=CHECK-LTO
// CHECK-LTO: "-stats-file=save-stats.stats"
// CHECK-LTO: "-o" "obj/dir{{/|}}save-stats.exe"
// CHECK-LTO: "-plugin-opt=stats-file=save-stats.stats"
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[clang] [Clang][Driver][LTO] Change the filename format for LTO'd stats file (PR #70242)
https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/70242 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][Driver][LTO] Change the filename format for LTO'd stats file (PR #70242)
mshockwave wrote: > I can understand the rationale, but adding this special case feels stranger > to me.. I'm fine with not having a special file extension for LTO'd stats file, hence closing this PR. That said, it would be really helpful if you could help me to review a related PR #71197 . https://github.com/llvm/llvm-project/pull/70242 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/71197
>From 8d5acb56b364648d1abd6bfff6815af71e131d6e Mon Sep 17 00:00:00 2001
From: Min Hsu
Date: Thu, 2 Nov 2023 17:26:17 -0700
Subject: [PATCH 1/2] [Clang][Driver][LTO] Fix empty stats filename when in LTO
mode
Previously, if a linker flag (i.e.g -Wl) is presented before any input
filenames, Gnu driver would use the InputInfo object of that flag to
generate stats filename for LTO backend, causing an empty filename.
This patch fixes such issue.
---
clang/lib/Driver/ToolChains/Gnu.cpp | 10 +-
clang/test/Driver/save-stats.c | 2 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 5237951f84cce03..8448d4bda13c434 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -535,7 +535,15 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
if (D.isUsingLTO()) {
assert(!Inputs.empty() && "Must have at least one input.");
-addLTOOptions(ToolChain, Args, CmdArgs, Output, Inputs[0],
+// Find the first filename InputInfo object.
+auto Input = llvm::find_if(
+Inputs, [](const InputInfo &II) -> bool { return II.isFilename(); });
+if (Input == Inputs.end())
+ // For a very rare case, all of the inputs to the linker are
+ // flags. If that happens, just use the first InputInfo.
+ Input = Inputs.begin();
+
+addLTOOptions(ToolChain, Args, CmdArgs, Output, *Input,
D.getLTOMode() == LTOK_Thin);
}
diff --git a/clang/test/Driver/save-stats.c b/clang/test/Driver/save-stats.c
index ca8f2a457d4488c..d6ad4e0097f3432 100644
--- a/clang/test/Driver/save-stats.c
+++ b/clang/test/Driver/save-stats.c
@@ -20,6 +20,8 @@
// CHECK-INVALID: invalid value 'bla' in '-save-stats=bla'
// RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o
obj/dir/save-stats.exe %s -### 2>&1 | FileCheck %s -check-prefix=CHECK-LTO
+// Previously `-plugin-opt=stats-file` would use empty filename if a linker
flag (i.e. -Wl) is presented before any input filename.
+// RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o
obj/dir/save-stats.exe -Wl,-plugin-opt=-dummy %s -### 2>&1 | FileCheck %s
-check-prefix=CHECK-LTO
// CHECK-LTO: "-stats-file=save-stats.stats"
// CHECK-LTO: "-o" "obj/dir{{/|}}save-stats.exe"
// CHECK-LTO: "-plugin-opt=stats-file=save-stats.stats"
>From a235c39323e7e46e81a474fb6eb45a74ea4adcc5 Mon Sep 17 00:00:00 2001
From: Min Hsu
Date: Sun, 5 Nov 2023 11:29:42 -0800
Subject: [PATCH 2/2] fixup! [Clang][Driver][LTO] Fix empty stats filename when
in LTO mode
---
clang/lib/Driver/ToolChains/Gnu.cpp | 2 +-
clang/test/Driver/save-stats.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 8448d4bda13c434..3276590729e47ea 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -540,7 +540,7 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
Inputs, [](const InputInfo &II) -> bool { return II.isFilename(); });
if (Input == Inputs.end())
// For a very rare case, all of the inputs to the linker are
- // flags. If that happens, just use the first InputInfo.
+ // InputArg. If that happens, just use the first InputInfo.
Input = Inputs.begin();
addLTOOptions(ToolChain, Args, CmdArgs, Output, *Input,
diff --git a/clang/test/Driver/save-stats.c b/clang/test/Driver/save-stats.c
index d6ad4e0097f3432..2208c229b91e56c 100644
--- a/clang/test/Driver/save-stats.c
+++ b/clang/test/Driver/save-stats.c
@@ -21,7 +21,7 @@
// RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o
obj/dir/save-stats.exe %s -### 2>&1 | FileCheck %s -check-prefix=CHECK-LTO
// Previously `-plugin-opt=stats-file` would use empty filename if a linker
flag (i.e. -Wl) is presented before any input filename.
-// RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o
obj/dir/save-stats.exe -Wl,-plugin-opt=-dummy %s -### 2>&1 | FileCheck %s
-check-prefix=CHECK-LTO
+// RUN: %clang --target=x86_64-linux-unknown -save-stats -flto -o
obj/dir/save-stats.exe -Wl,-plugin-opt=-dummy %s -### 2>&1 | FileCheck %s
-check-prefix=CHECK-LTO
// CHECK-LTO: "-stats-file=save-stats.stats"
// CHECK-LTO: "-o" "obj/dir{{/|}}save-stats.exe"
// CHECK-LTO: "-plugin-opt=stats-file=save-stats.stats"
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[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)
@@ -20,6 +20,8 @@ // CHECK-INVALID: invalid value 'bla' in '-save-stats=bla' // RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o obj/dir/save-stats.exe %s -### 2>&1 | FileCheck %s -check-prefix=CHECK-LTO +// Previously `-plugin-opt=stats-file` would use empty filename if a linker flag (i.e. -Wl) is presented before any input filename. +// RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o obj/dir/save-stats.exe -Wl,-plugin-opt=-dummy %s -### 2>&1 | FileCheck %s -check-prefix=CHECK-LTO mshockwave wrote: Done https://github.com/llvm/llvm-project/pull/71197 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)
@@ -535,7 +535,15 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
if (D.isUsingLTO()) {
assert(!Inputs.empty() && "Must have at least one input.");
-addLTOOptions(ToolChain, Args, CmdArgs, Output, Inputs[0],
+// Find the first filename InputInfo object.
+auto Input = llvm::find_if(
+Inputs, [](const InputInfo &II) -> bool { return II.isFilename(); });
+if (Input == Inputs.end())
+ // For a very rare case, all of the inputs to the linker are
+ // flags. If that happens, just use the first InputInfo.
mshockwave wrote:
Done
https://github.com/llvm/llvm-project/pull/71197
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[clang] [Clang][Driver][LTO] Fix empty stats filename when in LTO mode (PR #71197)
https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/71197 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)
mshockwave wrote: Is it possible use `TargetInfo::getGCCRegAliases` to model the aliasing between a7 and sp? Also, could you add a simple test? https://github.com/llvm/llvm-project/pull/87095 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)
https://github.com/mshockwave approved this pull request. Thank you! LGTM https://github.com/llvm/llvm-project/pull/87095 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/78489
>From 84783b38744bc2bb46cb8d62db206864709a5e22 Mon Sep 17 00:00:00 2001
From: Min Hsu
Date: Wed, 17 Jan 2024 10:28:14 -0800
Subject: [PATCH 1/2] [RISCV] Add support for Smepmp 1.0
Smepmp is a supervisor extension that prevents privileged processes from
accessing unprivileged program and data.
---
llvm/lib/Support/RISCVISAInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++
llvm/test/CodeGen/RISCV/attributes.ll | 4
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
5 files changed, 16 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 390d950486a795..f67bbd1969e1b3 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"m", {2, 0}},
{"smaia", {1, 0}},
+{"smepmp", {1, 0}},
{"ssaia", {1, 0}},
{"svinval", {1, 0}},
{"svnapot", {1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 279509575bb52a..00b5c710daac32 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -716,6 +716,13 @@ def FeatureStdExtSmaia
"AIA specifies for a hart, over all privilege levels.)",
[]>;
+def FeatureStdExtSmepmp
+: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
+ "'Smepmp' (Smepmp prevents privileged processes from "
+ "executing or accessing unprivileged programs and"
+ "data.)",
+ []>;
+
def FeatureStdExtSsaia
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Ssaia is essentially the same as Smaia except
"
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..ad6f205692fe30 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV32ZIMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZVFBFMIN %s
@@ -182,6 +183,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV64ZIMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZVFBFMIN %s
@@ -278,6 +280,7 @@
; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
+; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8"
; RV32ZVFBFMIN: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
@@ -371,6 +374,7 @@
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
+; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8"
; RV64ZVFBFMIN: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index 4f8a8dfdbcec90..bab104c5809008 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -270,6 +270,9 @@
.attribute arch, "rv32i_smaia1p0"
# CHECK: attribute 5, "rv32i2p1_smaia1p0"
+.attribute arch, "rv32i_smepmp1p0"
+# CHECK: attribute 5, "rv32i
[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)
mshockwave wrote: > Needs to be added to RISCVUsage.rst, and probably a note in the release docs > as well. It's done now. https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)
@@ -716,6 +716,13 @@ def FeatureStdExtSmaia "AIA specifies for a hart, over all privilege levels.)", []>; +def FeatureStdExtSmepmp mshockwave wrote: > Can we keep smaia and ssaia together since they come from the same > specification? I assume you were alphabetizing, but I don't think there's any > order in this file. I've reordered it here and other places for consistency. https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/78489
>From b4e14471727c59634daeec58ff60b8c32c5f2961 Mon Sep 17 00:00:00 2001
From: Min Hsu
Date: Wed, 17 Jan 2024 10:28:14 -0800
Subject: [PATCH 1/2] [RISCV] Add support for Smepmp 1.0
Smepmp is a supervisor extension that prevents privileged processes from
accessing unprivileged program and data.
---
llvm/lib/Support/RISCVISAInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++
llvm/test/CodeGen/RISCV/attributes.ll | 4
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
5 files changed, 16 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index d991878a5f1eca..bb62ea119506f5 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"m", {2, 0}},
{"smaia", {1, 0}},
+{"smepmp", {1, 0}},
{"ssaia", {1, 0}},
{"svinval", {1, 0}},
{"svnapot", {1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa334c69ddc982..5e8e09af457112 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -717,6 +717,13 @@ def FeatureStdExtSmaia
"'Smaia' (Advanced Interrupt Architecture Machine "
"Level)", []>;
+def FeatureStdExtSmepmp
+: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
+ "'Smepmp' (Smepmp prevents privileged processes from "
+ "executing or accessing unprivileged programs and"
+ "data.)",
+ []>;
+
def FeatureStdExtSsaia
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 60ef404ac345d1..ed2d88a45bd7fc 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV32ZIMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZVFBFMIN %s
@@ -182,6 +183,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV64ZIMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZVFBFMIN %s
@@ -278,6 +280,7 @@
; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
+; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
@@ -371,6 +374,7 @@
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
+; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index 0e508bb80f6b94..0eb8d493bcd36b 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -270,6 +270,9 @@
.attribute arch, "rv32i_smaia1p0"
# CHECK: attribute 5, "rv32i2p1_smaia1p0"
+.attribute arch, "rv32i_smepmp1p0"
+# CHECK: attribute 5, "rv32
[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)
@@ -56,6 +56,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"smaia", {1, 0}},
{"ssaia", {1, 0}},
+{"smepmp", {1, 0}},
mshockwave wrote:
Done.
https://github.com/llvm/llvm-project/pull/78489
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)
@@ -92,6 +92,7 @@ on support follow. ``M``Supported ``Smaia``Supported ``Ssaia``Supported + ``Smepmp`` Supported mshockwave wrote: Done. https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/78489
>From b4e14471727c59634daeec58ff60b8c32c5f2961 Mon Sep 17 00:00:00 2001
From: Min Hsu
Date: Wed, 17 Jan 2024 10:28:14 -0800
Subject: [PATCH 1/3] [RISCV] Add support for Smepmp 1.0
Smepmp is a supervisor extension that prevents privileged processes from
accessing unprivileged program and data.
---
llvm/lib/Support/RISCVISAInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++
llvm/test/CodeGen/RISCV/attributes.ll | 4
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
5 files changed, 16 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index d991878a5f1ecac..bb62ea119506f5c 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"m", {2, 0}},
{"smaia", {1, 0}},
+{"smepmp", {1, 0}},
{"ssaia", {1, 0}},
{"svinval", {1, 0}},
{"svnapot", {1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa334c69ddc982b..5e8e09af457112d 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -717,6 +717,13 @@ def FeatureStdExtSmaia
"'Smaia' (Advanced Interrupt Architecture Machine "
"Level)", []>;
+def FeatureStdExtSmepmp
+: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
+ "'Smepmp' (Smepmp prevents privileged processes from "
+ "executing or accessing unprivileged programs and"
+ "data.)",
+ []>;
+
def FeatureStdExtSsaia
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 60ef404ac345d15..ed2d88a45bd7fca 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV32ZIMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZVFBFMIN %s
@@ -182,6 +183,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV64ZIMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZVFBFMIN %s
@@ -278,6 +280,7 @@
; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
+; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
@@ -371,6 +374,7 @@
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
+; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index 0e508bb80f6b94c..0eb8d493bcd36bf 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -270,6 +270,9 @@
.attribute arch, "rv32i_smaia1p0"
# CHECK: attribute 5, "rv32i2p1_smaia1p0"
+.attribute arch, "rv32i_smepmp1p0"
+# CHECK: attribute
[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/78489
>From a69c187716153c90f50b2859212a0e5af9102fd1 Mon Sep 17 00:00:00 2001
From: Min Hsu
Date: Wed, 17 Jan 2024 10:28:14 -0800
Subject: [PATCH 1/3] [RISCV] Add support for Smepmp 1.0
Smepmp is a supervisor extension that prevents privileged processes from
accessing unprivileged program and data.
---
llvm/lib/Support/RISCVISAInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++
llvm/test/CodeGen/RISCV/attributes.ll | 4
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
5 files changed, 16 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index d991878a5f1eca..bb62ea119506f5 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"m", {2, 0}},
{"smaia", {1, 0}},
+{"smepmp", {1, 0}},
{"ssaia", {1, 0}},
{"svinval", {1, 0}},
{"svnapot", {1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa334c69ddc982..5e8e09af457112 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -717,6 +717,13 @@ def FeatureStdExtSmaia
"'Smaia' (Advanced Interrupt Architecture Machine "
"Level)", []>;
+def FeatureStdExtSmepmp
+: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
+ "'Smepmp' (Smepmp prevents privileged processes from "
+ "executing or accessing unprivileged programs and"
+ "data.)",
+ []>;
+
def FeatureStdExtSsaia
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 60ef404ac345d1..ed2d88a45bd7fc 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV32ZIMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZVFBFMIN %s
@@ -182,6 +183,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV64ZIMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZVFBFMIN %s
@@ -278,6 +280,7 @@
; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
+; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
@@ -371,6 +374,7 @@
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
+; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index 0e508bb80f6b94..0eb8d493bcd36b 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -270,6 +270,9 @@
.attribute arch, "rv32i_smaia1p0"
# CHECK: attribute 5, "rv32i2p1_smaia1p0"
+.attribute arch, "rv32i_smepmp1p0"
+# CHECK: attribute 5, "rv32
[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)
@@ -722,6 +722,11 @@ def FeatureStdExtSsaia "'Ssaia' (Advanced Interrupt Architecture Supervisor " "Level)", []>; +def FeatureStdExtSmepmp +: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", + "'Smepmp' (PMP Enhancements for memory access and " mshockwave wrote: It's fixed now. https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/78489
>From ab316ea2c76320ec2f044c43bb9f6ed82f6802c3 Mon Sep 17 00:00:00 2001
From: Min Hsu
Date: Wed, 17 Jan 2024 10:28:14 -0800
Subject: [PATCH 1/4] [RISCV] Add support for Smepmp 1.0
Smepmp is a supervisor extension that prevents privileged processes from
accessing unprivileged program and data.
---
llvm/lib/Support/RISCVISAInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++
llvm/test/CodeGen/RISCV/attributes.ll | 4
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
5 files changed, 16 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 8c9eb1bddb3cb52..3c02492e99f1db4 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"m", {2, 0}},
{"smaia", {1, 0}},
+{"smepmp", {1, 0}},
{"ssaia", {1, 0}},
{"svinval", {1, 0}},
{"svnapot", {1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 72780937dd88704..9cf8df05bd3ad54 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -743,6 +743,13 @@ def FeatureStdExtSmaia
"'Smaia' (Advanced Interrupt Architecture Machine "
"Level)", []>;
+def FeatureStdExtSmepmp
+: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
+ "'Smepmp' (Smepmp prevents privileged processes from "
+ "executing or accessing unprivileged programs and"
+ "data.)",
+ []>;
+
def FeatureStdExtSsaia
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 3e55e0fb4e6861e..d0cd6ab3093b410 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV32ZIMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZVFBFMIN %s
@@ -189,6 +190,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV64ZIMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZVFBFMIN %s
@@ -285,6 +287,7 @@
; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
+; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
@@ -385,6 +388,7 @@
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
+; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index b1a03bbfd74da9d..0c258981365929c 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -291,6 +291,9 @@
.attribute arch, "rv32i_smaia1p0"
# CHECK: attribute 5, "rv32i2p1_smaia1p0"
+.attribute arch, "rv32i_smepmp1p0"
+# CHECK: attribute
[clang] [llvm] [RISCV] Add support for Smepmp 1.0 (PR #78489)
@@ -1047,6 +1048,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
// CHECK-SSAIA-EXT: __riscv_ssaia 100{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32ismepmp1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
mshockwave wrote:
It's fixed now.
https://github.com/llvm/llvm-project/pull/78489
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)
@@ -116,6 +116,7 @@
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_ssaia {{.*$}}
+// CHECK-NOT: __riscv_smepmp {{.*$}}
mshockwave wrote:
It's fixed now.
https://github.com/llvm/llvm-project/pull/78489
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add support for Smepmp 1.0 (PR #78489)
https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/78489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/67863
>From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Fri, 29 Sep 2023 15:17:43 -0700
Subject: [PATCH 1/6] [RISCV][GISel] Add ISel supports for SHXADD from Zba
extension
This patch constitue of porting (SDISel) patterns of SHXADD
instructions.
Note that `non_imm12`, a predicate that was implemented with `PatLeaf`,
is now turned into a ComplexPattern to facilitate code reusing on
patterns that use it between SDISel and GISel.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 130 +++
llvm/lib/Target/RISCV/RISCVGISel.td | 10 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 9 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 51 +++---
.../instruction-select/zba-rv32.mir | 152 ++
.../instruction-select/zba-rv64.mir | 152 ++
7 files changed, 479 insertions(+), 27 deletions(-)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..3a98e84546f376f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -17,6 +17,7 @@
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Debug.h"
@@ -55,6 +56,14 @@ class RISCVInstructionSelector : public InstructionSelector {
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
+ ComplexRendererFns selectNonImm12(MachineOperand &Root) const;
+
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root, unsigned ShAmt)
const;
+ template
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root) const {
+return selectSHXADDOp(Root, ShAmt);
+ }
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -105,6 +114,127 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand
&Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
}
+// This complex pattern actually serves as a perdicate that is effectively
+// `!isInt<12>(Imm)`.
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectNonImm12(MachineOperand &Root) const {
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (Root.isReg() && Root.getReg())
+if (auto Val = getIConstantVRegValWithLookThrough(Root.getReg(), MRI)) {
+ // We do NOT want immediates that fit in 12 bits.
+ if (isInt<12>(Val->Value.getSExtValue()))
+return std::nullopt;
+}
+
+ return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
+}
+
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root,
+ unsigned ShAmt) const {
+ using namespace llvm::MIPatternMatch;
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (!Root.isReg())
+return std::nullopt;
+ Register RootReg = Root.getReg();
+
+ const unsigned XLen = STI.getXLen();
+ APInt Mask, C2;
+ Register RegY;
+ std::optional LeftShift;
+ // (and (shl y, c2), mask)
+ if (mi_match(RootReg, MRI,
+ m_GAnd(m_GShl(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = true;
+ // (and (lshr y, c2), mask)
+ else if (mi_match(RootReg, MRI,
+m_GAnd(m_GLShr(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = false;
+
+ if (LeftShift.has_value()) {
+if (*LeftShift)
+ Mask &= maskTrailingZeros(C2.getLimitedValue());
+else
+ Mask &= maskTrailingOnes(XLen - C2.getLimitedValue());
+
+if (Mask.isShiftedMask()) {
+ unsigned Leading = XLen - Mask.getActiveBits();
+ unsigned Trailing = Mask.countr_zero();
+ // Given (and (shl y, c2), mask) in which mask has no leading zeros and
c3
+ // trailing zeros. We can use an SRLI by c3 - c2 followed by a SHXADD.
+ if (*LeftShift && Leading == 0 && C2.ult(Trailing) && Trailing == ShAmt)
{
+Register DstReg =
+MRI.createGenericVirtualRegister(MRI.getType(RootReg));
+return {{[=](MachineInstrBuilder &MIB) {
+ MachineIRBuilder(*MIB.getInstr())
+ .buildInstr(RISCV::SRLI, {DstReg}, {RegY})
+ .addImm(Trailing - C2.getLimitedV
[clang-tools-extra] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/67863
>From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Fri, 29 Sep 2023 15:17:43 -0700
Subject: [PATCH 1/6] [RISCV][GISel] Add ISel supports for SHXADD from Zba
extension
This patch constitue of porting (SDISel) patterns of SHXADD
instructions.
Note that `non_imm12`, a predicate that was implemented with `PatLeaf`,
is now turned into a ComplexPattern to facilitate code reusing on
patterns that use it between SDISel and GISel.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 130 +++
llvm/lib/Target/RISCV/RISCVGISel.td | 10 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 9 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 51 +++---
.../instruction-select/zba-rv32.mir | 152 ++
.../instruction-select/zba-rv64.mir | 152 ++
7 files changed, 479 insertions(+), 27 deletions(-)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..3a98e84546f376f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -17,6 +17,7 @@
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Debug.h"
@@ -55,6 +56,14 @@ class RISCVInstructionSelector : public InstructionSelector {
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
+ ComplexRendererFns selectNonImm12(MachineOperand &Root) const;
+
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root, unsigned ShAmt)
const;
+ template
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root) const {
+return selectSHXADDOp(Root, ShAmt);
+ }
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -105,6 +114,127 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand
&Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
}
+// This complex pattern actually serves as a perdicate that is effectively
+// `!isInt<12>(Imm)`.
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectNonImm12(MachineOperand &Root) const {
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (Root.isReg() && Root.getReg())
+if (auto Val = getIConstantVRegValWithLookThrough(Root.getReg(), MRI)) {
+ // We do NOT want immediates that fit in 12 bits.
+ if (isInt<12>(Val->Value.getSExtValue()))
+return std::nullopt;
+}
+
+ return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
+}
+
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root,
+ unsigned ShAmt) const {
+ using namespace llvm::MIPatternMatch;
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (!Root.isReg())
+return std::nullopt;
+ Register RootReg = Root.getReg();
+
+ const unsigned XLen = STI.getXLen();
+ APInt Mask, C2;
+ Register RegY;
+ std::optional LeftShift;
+ // (and (shl y, c2), mask)
+ if (mi_match(RootReg, MRI,
+ m_GAnd(m_GShl(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = true;
+ // (and (lshr y, c2), mask)
+ else if (mi_match(RootReg, MRI,
+m_GAnd(m_GLShr(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = false;
+
+ if (LeftShift.has_value()) {
+if (*LeftShift)
+ Mask &= maskTrailingZeros(C2.getLimitedValue());
+else
+ Mask &= maskTrailingOnes(XLen - C2.getLimitedValue());
+
+if (Mask.isShiftedMask()) {
+ unsigned Leading = XLen - Mask.getActiveBits();
+ unsigned Trailing = Mask.countr_zero();
+ // Given (and (shl y, c2), mask) in which mask has no leading zeros and
c3
+ // trailing zeros. We can use an SRLI by c3 - c2 followed by a SHXADD.
+ if (*LeftShift && Leading == 0 && C2.ult(Trailing) && Trailing == ShAmt)
{
+Register DstReg =
+MRI.createGenericVirtualRegister(MRI.getType(RootReg));
+return {{[=](MachineInstrBuilder &MIB) {
+ MachineIRBuilder(*MIB.getInstr())
+ .buildInstr(RISCV::SRLI, {DstReg}, {RegY})
+ .addImm(Trailing - C2.getLimitedV
[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/67863
>From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Fri, 29 Sep 2023 15:17:43 -0700
Subject: [PATCH 1/7] [RISCV][GISel] Add ISel supports for SHXADD from Zba
extension
This patch constitue of porting (SDISel) patterns of SHXADD
instructions.
Note that `non_imm12`, a predicate that was implemented with `PatLeaf`,
is now turned into a ComplexPattern to facilitate code reusing on
patterns that use it between SDISel and GISel.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 130 +++
llvm/lib/Target/RISCV/RISCVGISel.td | 10 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 9 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 51 +++---
.../instruction-select/zba-rv32.mir | 152 ++
.../instruction-select/zba-rv64.mir | 152 ++
7 files changed, 479 insertions(+), 27 deletions(-)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..3a98e84546f376f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -17,6 +17,7 @@
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Debug.h"
@@ -55,6 +56,14 @@ class RISCVInstructionSelector : public InstructionSelector {
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
+ ComplexRendererFns selectNonImm12(MachineOperand &Root) const;
+
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root, unsigned ShAmt)
const;
+ template
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root) const {
+return selectSHXADDOp(Root, ShAmt);
+ }
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -105,6 +114,127 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand
&Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
}
+// This complex pattern actually serves as a perdicate that is effectively
+// `!isInt<12>(Imm)`.
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectNonImm12(MachineOperand &Root) const {
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (Root.isReg() && Root.getReg())
+if (auto Val = getIConstantVRegValWithLookThrough(Root.getReg(), MRI)) {
+ // We do NOT want immediates that fit in 12 bits.
+ if (isInt<12>(Val->Value.getSExtValue()))
+return std::nullopt;
+}
+
+ return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
+}
+
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root,
+ unsigned ShAmt) const {
+ using namespace llvm::MIPatternMatch;
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (!Root.isReg())
+return std::nullopt;
+ Register RootReg = Root.getReg();
+
+ const unsigned XLen = STI.getXLen();
+ APInt Mask, C2;
+ Register RegY;
+ std::optional LeftShift;
+ // (and (shl y, c2), mask)
+ if (mi_match(RootReg, MRI,
+ m_GAnd(m_GShl(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = true;
+ // (and (lshr y, c2), mask)
+ else if (mi_match(RootReg, MRI,
+m_GAnd(m_GLShr(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = false;
+
+ if (LeftShift.has_value()) {
+if (*LeftShift)
+ Mask &= maskTrailingZeros(C2.getLimitedValue());
+else
+ Mask &= maskTrailingOnes(XLen - C2.getLimitedValue());
+
+if (Mask.isShiftedMask()) {
+ unsigned Leading = XLen - Mask.getActiveBits();
+ unsigned Trailing = Mask.countr_zero();
+ // Given (and (shl y, c2), mask) in which mask has no leading zeros and
c3
+ // trailing zeros. We can use an SRLI by c3 - c2 followed by a SHXADD.
+ if (*LeftShift && Leading == 0 && C2.ult(Trailing) && Trailing == ShAmt)
{
+Register DstReg =
+MRI.createGenericVirtualRegister(MRI.getType(RootReg));
+return {{[=](MachineInstrBuilder &MIB) {
+ MachineIRBuilder(*MIB.getInstr())
+ .buildInstr(RISCV::SRLI, {DstReg}, {RegY})
+ .addImm(Trailing - C2.getLimitedV
[clang-tools-extra] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/67863
>From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Fri, 29 Sep 2023 15:17:43 -0700
Subject: [PATCH 1/7] [RISCV][GISel] Add ISel supports for SHXADD from Zba
extension
This patch constitue of porting (SDISel) patterns of SHXADD
instructions.
Note that `non_imm12`, a predicate that was implemented with `PatLeaf`,
is now turned into a ComplexPattern to facilitate code reusing on
patterns that use it between SDISel and GISel.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 130 +++
llvm/lib/Target/RISCV/RISCVGISel.td | 10 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 9 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 51 +++---
.../instruction-select/zba-rv32.mir | 152 ++
.../instruction-select/zba-rv64.mir | 152 ++
7 files changed, 479 insertions(+), 27 deletions(-)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..3a98e84546f376f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -17,6 +17,7 @@
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Debug.h"
@@ -55,6 +56,14 @@ class RISCVInstructionSelector : public InstructionSelector {
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
+ ComplexRendererFns selectNonImm12(MachineOperand &Root) const;
+
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root, unsigned ShAmt)
const;
+ template
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root) const {
+return selectSHXADDOp(Root, ShAmt);
+ }
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -105,6 +114,127 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand
&Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
}
+// This complex pattern actually serves as a perdicate that is effectively
+// `!isInt<12>(Imm)`.
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectNonImm12(MachineOperand &Root) const {
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (Root.isReg() && Root.getReg())
+if (auto Val = getIConstantVRegValWithLookThrough(Root.getReg(), MRI)) {
+ // We do NOT want immediates that fit in 12 bits.
+ if (isInt<12>(Val->Value.getSExtValue()))
+return std::nullopt;
+}
+
+ return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
+}
+
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root,
+ unsigned ShAmt) const {
+ using namespace llvm::MIPatternMatch;
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (!Root.isReg())
+return std::nullopt;
+ Register RootReg = Root.getReg();
+
+ const unsigned XLen = STI.getXLen();
+ APInt Mask, C2;
+ Register RegY;
+ std::optional LeftShift;
+ // (and (shl y, c2), mask)
+ if (mi_match(RootReg, MRI,
+ m_GAnd(m_GShl(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = true;
+ // (and (lshr y, c2), mask)
+ else if (mi_match(RootReg, MRI,
+m_GAnd(m_GLShr(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = false;
+
+ if (LeftShift.has_value()) {
+if (*LeftShift)
+ Mask &= maskTrailingZeros(C2.getLimitedValue());
+else
+ Mask &= maskTrailingOnes(XLen - C2.getLimitedValue());
+
+if (Mask.isShiftedMask()) {
+ unsigned Leading = XLen - Mask.getActiveBits();
+ unsigned Trailing = Mask.countr_zero();
+ // Given (and (shl y, c2), mask) in which mask has no leading zeros and
c3
+ // trailing zeros. We can use an SRLI by c3 - c2 followed by a SHXADD.
+ if (*LeftShift && Leading == 0 && C2.ult(Trailing) && Trailing == ShAmt)
{
+Register DstReg =
+MRI.createGenericVirtualRegister(MRI.getType(RootReg));
+return {{[=](MachineInstrBuilder &MIB) {
+ MachineIRBuilder(*MIB.getInstr())
+ .buildInstr(RISCV::SRLI, {DstReg}, {RegY})
+ .addImm(Trailing - C2.getLimitedV
[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/67863
>From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Fri, 29 Sep 2023 15:17:43 -0700
Subject: [PATCH 1/8] [RISCV][GISel] Add ISel supports for SHXADD from Zba
extension
This patch constitue of porting (SDISel) patterns of SHXADD
instructions.
Note that `non_imm12`, a predicate that was implemented with `PatLeaf`,
is now turned into a ComplexPattern to facilitate code reusing on
patterns that use it between SDISel and GISel.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 130 +++
llvm/lib/Target/RISCV/RISCVGISel.td | 10 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 9 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 51 +++---
.../instruction-select/zba-rv32.mir | 152 ++
.../instruction-select/zba-rv64.mir | 152 ++
7 files changed, 479 insertions(+), 27 deletions(-)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..3a98e84546f376f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -17,6 +17,7 @@
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Debug.h"
@@ -55,6 +56,14 @@ class RISCVInstructionSelector : public InstructionSelector {
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
+ ComplexRendererFns selectNonImm12(MachineOperand &Root) const;
+
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root, unsigned ShAmt)
const;
+ template
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root) const {
+return selectSHXADDOp(Root, ShAmt);
+ }
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -105,6 +114,127 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand
&Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
}
+// This complex pattern actually serves as a perdicate that is effectively
+// `!isInt<12>(Imm)`.
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectNonImm12(MachineOperand &Root) const {
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (Root.isReg() && Root.getReg())
+if (auto Val = getIConstantVRegValWithLookThrough(Root.getReg(), MRI)) {
+ // We do NOT want immediates that fit in 12 bits.
+ if (isInt<12>(Val->Value.getSExtValue()))
+return std::nullopt;
+}
+
+ return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
+}
+
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root,
+ unsigned ShAmt) const {
+ using namespace llvm::MIPatternMatch;
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (!Root.isReg())
+return std::nullopt;
+ Register RootReg = Root.getReg();
+
+ const unsigned XLen = STI.getXLen();
+ APInt Mask, C2;
+ Register RegY;
+ std::optional LeftShift;
+ // (and (shl y, c2), mask)
+ if (mi_match(RootReg, MRI,
+ m_GAnd(m_GShl(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = true;
+ // (and (lshr y, c2), mask)
+ else if (mi_match(RootReg, MRI,
+m_GAnd(m_GLShr(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = false;
+
+ if (LeftShift.has_value()) {
+if (*LeftShift)
+ Mask &= maskTrailingZeros(C2.getLimitedValue());
+else
+ Mask &= maskTrailingOnes(XLen - C2.getLimitedValue());
+
+if (Mask.isShiftedMask()) {
+ unsigned Leading = XLen - Mask.getActiveBits();
+ unsigned Trailing = Mask.countr_zero();
+ // Given (and (shl y, c2), mask) in which mask has no leading zeros and
c3
+ // trailing zeros. We can use an SRLI by c3 - c2 followed by a SHXADD.
+ if (*LeftShift && Leading == 0 && C2.ult(Trailing) && Trailing == ShAmt)
{
+Register DstReg =
+MRI.createGenericVirtualRegister(MRI.getType(RootReg));
+return {{[=](MachineInstrBuilder &MIB) {
+ MachineIRBuilder(*MIB.getInstr())
+ .buildInstr(RISCV::SRLI, {DstReg}, {RegY})
+ .addImm(Trailing - C2.getLimitedV
[clang-tools-extra] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/67863
>From 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Fri, 29 Sep 2023 15:17:43 -0700
Subject: [PATCH 1/8] [RISCV][GISel] Add ISel supports for SHXADD from Zba
extension
This patch constitue of porting (SDISel) patterns of SHXADD
instructions.
Note that `non_imm12`, a predicate that was implemented with `PatLeaf`,
is now turned into a ComplexPattern to facilitate code reusing on
patterns that use it between SDISel and GISel.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 130 +++
llvm/lib/Target/RISCV/RISCVGISel.td | 10 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 9 ++
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 51 +++---
.../instruction-select/zba-rv32.mir | 152 ++
.../instruction-select/zba-rv64.mir | 152 ++
7 files changed, 479 insertions(+), 27 deletions(-)
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv32.mir
create mode 100644
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..3a98e84546f376f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -17,6 +17,7 @@
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Debug.h"
@@ -55,6 +56,14 @@ class RISCVInstructionSelector : public InstructionSelector {
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
+ ComplexRendererFns selectNonImm12(MachineOperand &Root) const;
+
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root, unsigned ShAmt)
const;
+ template
+ ComplexRendererFns selectSHXADDOp(MachineOperand &Root) const {
+return selectSHXADDOp(Root, ShAmt);
+ }
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -105,6 +114,127 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand
&Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
}
+// This complex pattern actually serves as a perdicate that is effectively
+// `!isInt<12>(Imm)`.
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectNonImm12(MachineOperand &Root) const {
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (Root.isReg() && Root.getReg())
+if (auto Val = getIConstantVRegValWithLookThrough(Root.getReg(), MRI)) {
+ // We do NOT want immediates that fit in 12 bits.
+ if (isInt<12>(Val->Value.getSExtValue()))
+return std::nullopt;
+}
+
+ return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
+}
+
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root,
+ unsigned ShAmt) const {
+ using namespace llvm::MIPatternMatch;
+ MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ if (!Root.isReg())
+return std::nullopt;
+ Register RootReg = Root.getReg();
+
+ const unsigned XLen = STI.getXLen();
+ APInt Mask, C2;
+ Register RegY;
+ std::optional LeftShift;
+ // (and (shl y, c2), mask)
+ if (mi_match(RootReg, MRI,
+ m_GAnd(m_GShl(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = true;
+ // (and (lshr y, c2), mask)
+ else if (mi_match(RootReg, MRI,
+m_GAnd(m_GLShr(m_Reg(RegY), m_ICst(C2)), m_ICst(Mask
+LeftShift = false;
+
+ if (LeftShift.has_value()) {
+if (*LeftShift)
+ Mask &= maskTrailingZeros(C2.getLimitedValue());
+else
+ Mask &= maskTrailingOnes(XLen - C2.getLimitedValue());
+
+if (Mask.isShiftedMask()) {
+ unsigned Leading = XLen - Mask.getActiveBits();
+ unsigned Trailing = Mask.countr_zero();
+ // Given (and (shl y, c2), mask) in which mask has no leading zeros and
c3
+ // trailing zeros. We can use an SRLI by c3 - c2 followed by a SHXADD.
+ if (*LeftShift && Leading == 0 && C2.ult(Trailing) && Trailing == ShAmt)
{
+Register DstReg =
+MRI.createGenericVirtualRegister(MRI.getType(RootReg));
+return {{[=](MachineInstrBuilder &MIB) {
+ MachineIRBuilder(*MIB.getInstr())
+ .buildInstr(RISCV::SRLI, {DstReg}, {RegY})
+ .addImm(Trailing - C2.getLimitedV
[clang] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)
https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/67863 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)
https://github.com/mshockwave created
https://github.com/llvm/llvm-project/pull/69747
Translate `-fglobal-isel` to `-plugin-opt=-global-isel=1`.
>From 8abc9204d4148f1b224623ac54d5f58e2ab04e6b Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Fri, 20 Oct 2023 11:03:30 -0700
Subject: [PATCH] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO
Translate `-fglobal-isel` to `-plugin-opt=-global-isel=1`.
---
clang/lib/Driver/ToolChains/CommonArgs.cpp | 10 ++
clang/test/Driver/lto.c| 9 +
2 files changed, 19 insertions(+)
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 7b2966f70bf6fc6..923fac940a00d3c 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -694,6 +694,16 @@ void tools::addLTOOptions(const ToolChain &ToolChain,
const ArgList &Args,
CmdArgs.push_back(Args.MakeArgString(Twine(PluginOptPrefix) +
ParallelismOpt + Parallelism));
+ // Pass down GlobalISel options.
+ if (Arg *A = Args.getLastArg(options::OPT_fglobal_isel,
+ options::OPT_fno_global_isel)) {
+// Parsing -fno-global-isel explicitly gives architectures that enable
GISel
+// by default (e.g. AArch64) a chance to disable it.
+CmdArgs.push_back(Args.MakeArgString(
+Twine(PluginOptPrefix) + "-global-isel=" +
+(A->getOption().matches(options::OPT_fglobal_isel) ? "1" : "0")));
+ }
+
// If an explicit debugger tuning argument appeared, pass it along.
if (Arg *A =
Args.getLastArg(options::OPT_gTune_Group, options::OPT_ggdbN_Group))
{
diff --git a/clang/test/Driver/lto.c b/clang/test/Driver/lto.c
index 62bdbd6f5d3cfa3..b6c89eb99e27419 100644
--- a/clang/test/Driver/lto.c
+++ b/clang/test/Driver/lto.c
@@ -105,3 +105,12 @@
// FLTO-THIN: -flto=thin
// FLTO-THIN-NOT: "-flto"
// FLTO-THIN-NOT: -flto=full
+
+// -flto passes along an explicit GlobalISel flag.
+// RUN: %clang --target=riscv64-linux-gnu -### %s -flto -fglobal-isel 2> %t
+// RUN: FileCheck --check-prefix=CHECK-GISEL < %t %s
+// RUN: %clang --target=aarch64-linux-gnu -### %s -flto -fno-global-isel 2> %t
+// RUN: FileCheck --check-prefix=CHECK-DISABLE-GISEL < %t %s
+//
+// CHECK-GISEL: "-plugin-opt=-global-isel=1"
+// CHECK-DISABLE-GISEL: "-plugin-opt=-global-isel=0"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/69747
>From 8abc9204d4148f1b224623ac54d5f58e2ab04e6b Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Fri, 20 Oct 2023 11:03:30 -0700
Subject: [PATCH 1/2] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO
Translate `-fglobal-isel` to `-plugin-opt=-global-isel=1`.
---
clang/lib/Driver/ToolChains/CommonArgs.cpp | 10 ++
clang/test/Driver/lto.c| 9 +
2 files changed, 19 insertions(+)
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 7b2966f70bf6fc6..923fac940a00d3c 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -694,6 +694,16 @@ void tools::addLTOOptions(const ToolChain &ToolChain,
const ArgList &Args,
CmdArgs.push_back(Args.MakeArgString(Twine(PluginOptPrefix) +
ParallelismOpt + Parallelism));
+ // Pass down GlobalISel options.
+ if (Arg *A = Args.getLastArg(options::OPT_fglobal_isel,
+ options::OPT_fno_global_isel)) {
+// Parsing -fno-global-isel explicitly gives architectures that enable
GISel
+// by default (e.g. AArch64) a chance to disable it.
+CmdArgs.push_back(Args.MakeArgString(
+Twine(PluginOptPrefix) + "-global-isel=" +
+(A->getOption().matches(options::OPT_fglobal_isel) ? "1" : "0")));
+ }
+
// If an explicit debugger tuning argument appeared, pass it along.
if (Arg *A =
Args.getLastArg(options::OPT_gTune_Group, options::OPT_ggdbN_Group))
{
diff --git a/clang/test/Driver/lto.c b/clang/test/Driver/lto.c
index 62bdbd6f5d3cfa3..b6c89eb99e27419 100644
--- a/clang/test/Driver/lto.c
+++ b/clang/test/Driver/lto.c
@@ -105,3 +105,12 @@
// FLTO-THIN: -flto=thin
// FLTO-THIN-NOT: "-flto"
// FLTO-THIN-NOT: -flto=full
+
+// -flto passes along an explicit GlobalISel flag.
+// RUN: %clang --target=riscv64-linux-gnu -### %s -flto -fglobal-isel 2> %t
+// RUN: FileCheck --check-prefix=CHECK-GISEL < %t %s
+// RUN: %clang --target=aarch64-linux-gnu -### %s -flto -fno-global-isel 2> %t
+// RUN: FileCheck --check-prefix=CHECK-DISABLE-GISEL < %t %s
+//
+// CHECK-GISEL: "-plugin-opt=-global-isel=1"
+// CHECK-DISABLE-GISEL: "-plugin-opt=-global-isel=0"
>From 2c4a02e9536446281901233756b9493d3e01f64f Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Tue, 24 Oct 2023 09:11:43 -0700
Subject: [PATCH 2/2] fixup! [Clang][LTO][GISel] Propagate `-fglobal-siel` to
LTO
---
clang/lib/Driver/ToolChains/CommonArgs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 923fac940a00d3c..6ea89d7726db2d0 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -698,7 +698,7 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const
ArgList &Args,
if (Arg *A = Args.getLastArg(options::OPT_fglobal_isel,
options::OPT_fno_global_isel)) {
// Parsing -fno-global-isel explicitly gives architectures that enable
GISel
-// by default (e.g. AArch64) a chance to disable it.
+// by default a chance to disable it.
CmdArgs.push_back(Args.MakeArgString(
Twine(PluginOptPrefix) + "-global-isel=" +
(A->getOption().matches(options::OPT_fglobal_isel) ? "1" : "0")));
___
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[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)
@@ -694,6 +694,16 @@ void tools::addLTOOptions(const ToolChain &ToolChain,
const ArgList &Args,
CmdArgs.push_back(Args.MakeArgString(Twine(PluginOptPrefix) +
ParallelismOpt + Parallelism));
+ // Pass down GlobalISel options.
+ if (Arg *A = Args.getLastArg(options::OPT_fglobal_isel,
+ options::OPT_fno_global_isel)) {
+// Parsing -fno-global-isel explicitly gives architectures that enable
GISel
+// by default (e.g. AArch64) a chance to disable it.
mshockwave wrote:
Done
https://github.com/llvm/llvm-project/pull/69747
___
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[clang] [Clang][LTO][GISel] Propagate `-fglobal-siel` to LTO (PR #69747)
https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/69747 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][Driver][LTO] Change the filename format for LTO'd stats file (PR #70242)
https://github.com/mshockwave created
https://github.com/llvm/llvm-project/pull/70242
Use ".ld.stats" instead of ".stats" for
stats file generated by LTO backend. The new extension makes it easier to
search for LTO'd stats file and be consistent with LTO'd optimization remarks
files' naming convention (i.e. *.opt.ld.yaml, as opposed to *.opt.yaml for
normal opt remarks files).
>From 5f2504eb4393bbd8948b85c4dd05f2c9c244c9f7 Mon Sep 17 00:00:00 2001
From: Min Hsu
Date: Wed, 25 Oct 2023 11:42:14 -0700
Subject: [PATCH] [Clang][Driver][LTO] Change the filename format for LTO'd
stats file
Use ".ld.stats" instead of ".stats"
for stats file generated by LTO backend. The new extension makes it
easier to search for LTO'd stats file and be consistent with LTO'd
optimization remarks files' naming convention (i.e. *.opt.ld.yaml,
as opposed to *.opt.yaml for normal opt remarks files).
---
clang/lib/Driver/ToolChains/CommonArgs.cpp | 19 +++
clang/lib/Driver/ToolChains/CommonArgs.h | 3 ++-
clang/test/Driver/save-stats.c | 5 +++--
3 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index ad012d3d0d4b46f..98e20abc015c5fd 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -852,7 +852,8 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const
ArgList &Args,
Args.MakeArgString(Twine(PluginOptPrefix) + "-stack-size-section"));
// Setup statistics file output.
- SmallString<128> StatsFile = getStatsFileName(Args, Output, Input, D);
+ SmallString<128> StatsFile =
+ getStatsFileName(Args, Output, Input, D, /*IsLTO=*/true);
if (!StatsFile.empty())
CmdArgs.push_back(
Args.MakeArgString(Twine(PluginOptPrefix) + "stats-file=" +
StatsFile));
@@ -1941,7 +1942,7 @@ void tools::AddRunTimeLibs(const ToolChain &TC, const
Driver &D,
SmallString<128> tools::getStatsFileName(const llvm::opt::ArgList &Args,
const InputInfo &Output,
const InputInfo &Input,
- const Driver &D) {
+ const Driver &D, bool IsLTO) {
const Arg *A = Args.getLastArg(options::OPT_save_stats_EQ);
if (!A && !D.CCPrintInternalStats)
return {};
@@ -1957,9 +1958,19 @@ SmallString<128> tools::getStatsFileName(const
llvm::opt::ArgList &Args,
return {};
}
-StringRef BaseName = llvm::sys::path::filename(Input.getBaseInput());
+StringRef BaseName;
+// For stats files generated by the LTO backend, we're using ".ld.stats" for its name. Note that we don't query
+// `options::OPT_flto_EQ` and `options::OPT_fno_lto` here to decide `IsLTO`
+// because it also changes the stats filenames for the pre-link object
(LLVM
+// bitcode) files, which we want to keep the same.
+if (IsLTO && Output.isFilename())
+ BaseName = llvm::sys::path::filename(Output.getFilename());
+else
+ BaseName = llvm::sys::path::filename(Input.getBaseInput());
+
llvm::sys::path::append(StatsFile, BaseName);
-llvm::sys::path::replace_extension(StatsFile, "stats");
+llvm::sys::path::replace_extension(StatsFile, IsLTO ? "ld.stats" :
"stats");
} else {
assert(D.CCPrintInternalStats);
StatsFile.assign(D.CCPrintInternalStatReportFilename.empty()
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h
b/clang/lib/Driver/ToolChains/CommonArgs.h
index f364c9793c9be62..bab80af5fb2f67a 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -184,7 +184,8 @@ SmallVector
unifyTargetFeatures(ArrayRef Features);
/// to.
SmallString<128> getStatsFileName(const llvm::opt::ArgList &Args,
const InputInfo &Output,
- const InputInfo &Input, const Driver &D);
+ const InputInfo &Input, const Driver &D,
+ bool IsLTO = false);
/// \p Flag must be a flag accepted by the driver.
void addMultilibFlag(bool Enabled, const StringRef Flag,
diff --git a/clang/test/Driver/save-stats.c b/clang/test/Driver/save-stats.c
index ca8f2a457d4488c..44a6ddabde2a2e9 100644
--- a/clang/test/Driver/save-stats.c
+++ b/clang/test/Driver/save-stats.c
@@ -22,10 +22,11 @@
// RUN: %clang -target x86_64-linux-unknown -save-stats -flto -o
obj/dir/save-stats.exe %s -### 2>&1 | FileCheck %s -check-prefix=CHECK-LTO
// CHECK-LTO: "-stats-file=save-stats.stats"
// CHECK-LTO: "-o" "obj/dir{{/|}}save-stats.exe"
-// CHECK-LTO: "-plugin-opt=stats-file=save-stats.stats"
+// CHECK-LTO: "-plugin-opt=stats-file=save-stats.ld.stats"
// RUN: %clang -target x86_64-linux-unknown -save-stats=obj -flto -o
obj/dir/save-stats.exe %s -### 2>&1 | FileCheck %s -check-prefix=CHECK-LTO-OBJ
-// CHECK-
[clang] e620bea - [M68k] Allow user to preserve certain registers
Author: Min-Yih Hsu
Date: 2021-05-20T13:57:22-07:00
New Revision: e620bea21199791513f3193a71b819b20a707ab1
URL:
https://github.com/llvm/llvm-project/commit/e620bea21199791513f3193a71b819b20a707ab1
DIFF:
https://github.com/llvm/llvm-project/commit/e620bea21199791513f3193a71b819b20a707ab1.diff
LOG: [M68k] Allow user to preserve certain registers
Add `-ffixed-a[0-6]` and `-ffixed-d[0-7]` and the corresponding
subtarget features to prevent certain register from being allocated.
Differential Revision: https://reviews.llvm.org/D102805
Added:
clang/test/Driver/m68k-fixed-register.c
llvm/test/CodeGen/M68k/reserved-regs.ll
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Arch/M68k.cpp
llvm/lib/Target/M68k/M68k.td
llvm/lib/Target/M68k/M68kRegisterInfo.cpp
llvm/lib/Target/M68k/M68kSubtarget.cpp
llvm/lib/Target/M68k/M68kSubtarget.h
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 1274f7a0af2e8..d45798c1d4043 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4010,6 +4010,13 @@ def m68030 : Flag<["-"], "m68030">,
Group;
def m68040 : Flag<["-"], "m68040">, Group;
def m68060 : Flag<["-"], "m68060">, Group;
+foreach i = {0-6} in
+ def ffixed_a#i : Flag<["-"], "ffixed-a"#i>, Group,
+HelpText<"Reserve the a"#i#" register (M68k only)">;
+foreach i = {0-7} in
+ def ffixed_d#i : Flag<["-"], "ffixed-d"#i>, Group,
+HelpText<"Reserve the d"#i#" register (M68k only)">;
+
// X86 feature flags
def mx87 : Flag<["-"], "mx87">, Group;
def mno_x87 : Flag<["-"], "mno-x87">, Group;
diff --git a/clang/lib/Driver/ToolChains/Arch/M68k.cpp
b/clang/lib/Driver/ToolChains/Arch/M68k.cpp
index 66c9f5c87bfbc..119e24cedbab4 100644
--- a/clang/lib/Driver/ToolChains/Arch/M68k.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/M68k.cpp
@@ -72,6 +72,38 @@ void m68k::getM68kTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
m68k::FloatABI FloatABI = m68k::getM68kFloatABI(D, Args);
if (FloatABI == m68k::FloatABI::Soft)
Features.push_back("-hard-float");
+
+ // Handle '-ffixed-' flags
+ if (Args.hasArg(options::OPT_ffixed_a0))
+Features.push_back("+reserve-a0");
+ if (Args.hasArg(options::OPT_ffixed_a1))
+Features.push_back("+reserve-a1");
+ if (Args.hasArg(options::OPT_ffixed_a2))
+Features.push_back("+reserve-a2");
+ if (Args.hasArg(options::OPT_ffixed_a3))
+Features.push_back("+reserve-a3");
+ if (Args.hasArg(options::OPT_ffixed_a4))
+Features.push_back("+reserve-a4");
+ if (Args.hasArg(options::OPT_ffixed_a5))
+Features.push_back("+reserve-a5");
+ if (Args.hasArg(options::OPT_ffixed_a6))
+Features.push_back("+reserve-a6");
+ if (Args.hasArg(options::OPT_ffixed_d0))
+Features.push_back("+reserve-d0");
+ if (Args.hasArg(options::OPT_ffixed_d1))
+Features.push_back("+reserve-d1");
+ if (Args.hasArg(options::OPT_ffixed_d2))
+Features.push_back("+reserve-d2");
+ if (Args.hasArg(options::OPT_ffixed_d3))
+Features.push_back("+reserve-d3");
+ if (Args.hasArg(options::OPT_ffixed_d4))
+Features.push_back("+reserve-d4");
+ if (Args.hasArg(options::OPT_ffixed_d5))
+Features.push_back("+reserve-d5");
+ if (Args.hasArg(options::OPT_ffixed_d6))
+Features.push_back("+reserve-d6");
+ if (Args.hasArg(options::OPT_ffixed_d7))
+Features.push_back("+reserve-d7");
}
m68k::FloatABI m68k::getM68kFloatABI(const Driver &D, const ArgList &Args) {
diff --git a/clang/test/Driver/m68k-fixed-register.c
b/clang/test/Driver/m68k-fixed-register.c
new file mode 100644
index 0..0ee9edcfd1647
--- /dev/null
+++ b/clang/test/Driver/m68k-fixed-register.c
@@ -0,0 +1,61 @@
+// REQUIRES: m68k-registered-target
+// RUN: %clang -target m68k -ffixed-a0 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-A0 < %t %s
+// CHECK-FIXED-A0: "-target-feature" "+reserve-a0"
+
+// RUN: %clang -target m68k -ffixed-a1 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-A1 < %t %s
+// CHECK-FIXED-A1: "-target-feature" "+reserve-a1"
+
+// RUN: %clang -target m68k -ffixed-a2 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-A2 < %t %s
+// CHECK-FIXED-A2: "-target-feature" "+reserve-a2"
+
+// RUN: %clang -target m68k -ffixed-a3 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-A3 < %t %s
+// CHECK-FIXED-A3: "-target-feature" "+reserve-a3"
+
+// RUN: %clang -target m68k -ffixed-a4 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-A4 < %t %s
+// CHECK-FIXED-A4: "-target-feature" "+reserve-a4"
+
+// RUN: %clang -target m68k -ffixed-a5 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-A5 < %t %s
+// CHECK-FIXED-A5: "-target-feature" "+reserve-a5"
+
+// RUN: %clang -target m68k -ffixed-a6 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-A6 < %t %s
+// CHECK-FIXED-
[clang] dccf5c7 - [M68k] Support for inline asm operands w/ simple constraints
Author: Min-Yih Hsu
Date: 2021-05-20T14:00:09-07:00
New Revision: dccf5c7dfb9e68f8750947f5c10ad3227cd92b50
URL:
https://github.com/llvm/llvm-project/commit/dccf5c7dfb9e68f8750947f5c10ad3227cd92b50
DIFF:
https://github.com/llvm/llvm-project/commit/dccf5c7dfb9e68f8750947f5c10ad3227cd92b50.diff
LOG: [M68k] Support for inline asm operands w/ simple constraints
This patch adds supports for inline assembly operands and some simple
operand constraints, including register and constant operands.
Differential Revision: https://reviews.llvm.org/D102585
Added:
clang/test/Sema/inline-asm-validate-m68k.c
llvm/test/CodeGen/M68k/inline-asm.ll
Modified:
clang/lib/Basic/Targets/M68k.cpp
clang/lib/Basic/Targets/M68k.h
llvm/lib/Target/M68k/M68kAsmPrinter.cpp
llvm/lib/Target/M68k/M68kAsmPrinter.h
llvm/lib/Target/M68k/M68kISelLowering.cpp
llvm/lib/Target/M68k/M68kISelLowering.h
Removed:
diff --git a/clang/lib/Basic/Targets/M68k.cpp
b/clang/lib/Basic/Targets/M68k.cpp
index 8e8a69f75c8b0..9fcd58ee6401a 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -18,7 +18,9 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/TargetParser.h"
+#include
#include
+#include
namespace clang {
namespace targets {
@@ -142,18 +144,61 @@ bool M68kTargetInfo::validateAsmConstraint(
switch (*Name) {
case 'a': // address register
case 'd': // data register
- case 'f': // floating point register
info.setAllowsRegister();
return true;
- case 'K': // the constant 1
- case 'L': // constant -1^20 .. 1^19
- case 'M': // constant 1-4:
+ case 'I': // constant integer in the range [1,8]
+info.setRequiresImmediate(1, 8);
return true;
+ case 'J': // constant signed 16-bit integer
+info.setRequiresImmediate(std::numeric_limits::min(),
+ std::numeric_limits::max());
+return true;
+ case 'K': // constant that is NOT in the range of [-0x80, 0x80)
+info.setRequiresImmediate();
+return true;
+ case 'L': // constant integer in the range [-8,-1]
+info.setRequiresImmediate(-8, -1);
+return true;
+ case 'M': // constant that is NOT in the range of [-0x100, 0x100]
+info.setRequiresImmediate();
+return true;
+ case 'N': // constant integer in the range [24,31]
+info.setRequiresImmediate(24, 31);
+return true;
+ case 'O': // constant integer 16
+info.setRequiresImmediate(16);
+return true;
+ case 'P': // constant integer in the range [8,15]
+info.setRequiresImmediate(8, 15);
+return true;
+ case 'C':
+++Name;
+switch (*Name) {
+case '0': // constant integer 0
+ info.setRequiresImmediate(0);
+ return true;
+case 'i': // constant integer
+case 'j': // integer constant that doesn't fit in 16 bits
+ info.setRequiresImmediate();
+ return true;
+default:
+ break;
+}
+break;
+ default:
+break;
}
- // FIXME: Support all constraints like 'N', 'O', 'P', 'R'
return false;
}
+std::string M68kTargetInfo::convertConstraint(const char *&Constraint) const {
+ if (*Constraint == 'C')
+// Two-character constraint; add "^" hint for later parsing
+return std::string("^") + std::string(Constraint++, 2);
+
+ return std::string(1, *Constraint);
+}
+
const char *M68kTargetInfo::getClobbers() const {
// FIXME: Is this really right?
return "";
diff --git a/clang/lib/Basic/Targets/M68k.h b/clang/lib/Basic/Targets/M68k.h
index db001be76c65f..be2462bbd7acd 100644
--- a/clang/lib/Basic/Targets/M68k.h
+++ b/clang/lib/Basic/Targets/M68k.h
@@ -44,6 +44,7 @@ class LLVM_LIBRARY_VISIBILITY M68kTargetInfo : public
TargetInfo {
bool hasFeature(StringRef Feature) const override;
ArrayRef getGCCRegNames() const override;
ArrayRef getGCCRegAliases() const override;
+ std::string convertConstraint(const char *&Constraint) const override;
bool validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &info) const override;
const char *getClobbers() const override;
diff --git a/clang/test/Sema/inline-asm-validate-m68k.c
b/clang/test/Sema/inline-asm-validate-m68k.c
new file mode 100644
index 0..a0b75304eba00
--- /dev/null
+++ b/clang/test/Sema/inline-asm-validate-m68k.c
@@ -0,0 +1,86 @@
+// REQUIRES: m68k-registered-target
+// RUN: %clang_cc1 -triple m68k -fsyntax-only -verify %s -DINVALID
+// RUN: %clang_cc1 -triple m68k -fsyntax-only -verify %s
+
+#ifdef INVALID
+
+// Invalid constraint usages that can be blocked by frontend
+
+void I() {
+ static const int BelowMin = 0;
+ static const int AboveMax = 9;
+ asm ("" :: "I"(BelowMin)); // expected-error{{value '0' out of range for
constraint 'I'}}
+ asm ("" :: "I"(AboveMax)); // expected-error{{value '9' out of range for
constraint 'I'}}
+}
+
+void J() {
+ stati
[clang] 6685a3f - [cfe] Support target-specific escaped character in inline asm
Author: Min-Yih Hsu
Date: 2021-05-24T21:39:21-07:00
New Revision: 6685a3f3e4c497a3a0fd06aa4e77cb442325d1ba
URL:
https://github.com/llvm/llvm-project/commit/6685a3f3e4c497a3a0fd06aa4e77cb442325d1ba
DIFF:
https://github.com/llvm/llvm-project/commit/6685a3f3e4c497a3a0fd06aa4e77cb442325d1ba.diff
LOG: [cfe] Support target-specific escaped character in inline asm
GCC allows each target to define a set of non-letter and non-digit
escaped characters for inline assembly that will be replaced by another
string (They call this "punctuation" characters. The existing "%%" and
"%{" -- replaced by '%' and '{' at the end -- can be seen as special
cases shared by all targets).
This patch implements this feature by adding a new hook in `TargetInfo`.
Differential Revision: https://reviews.llvm.org/D103036
Added:
clang/test/CodeGen/m68k-asm.c
Modified:
clang/include/clang/Basic/TargetInfo.h
clang/lib/AST/Stmt.cpp
clang/lib/Basic/Targets/M68k.cpp
clang/lib/Basic/Targets/M68k.h
Removed:
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 29b957607f3e5..d59bad30e7428 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1091,6 +1091,12 @@ class TargetInfo : public virtual
TransferrableTargetInfo,
return std::string(1, *Constraint);
}
+ /// Replace some escaped characters with another string based on
+ /// target-specific rules
+ virtual llvm::Optional handleAsmEscapedChar(char C) const {
+return llvm::None;
+ }
+
/// Returns a string of target-specific clobbers, in LLVM format.
virtual const char *getClobbers() const = 0;
diff --git a/clang/lib/AST/Stmt.cpp b/clang/lib/AST/Stmt.cpp
index d30df296dbd57..47693ef9fee3e 100644
--- a/clang/lib/AST/Stmt.cpp
+++ b/clang/lib/AST/Stmt.cpp
@@ -646,6 +646,8 @@ unsigned
GCCAsmStmt::AnalyzeAsmString(SmallVectorImpl&Pieces,
continue;
}
+const TargetInfo &TI = C.getTargetInfo();
+
// Escaped "%" character in asm string.
if (CurPtr == StrEnd) {
// % at end of string is invalid (no escape).
@@ -656,6 +658,11 @@ unsigned
GCCAsmStmt::AnalyzeAsmString(SmallVectorImpl&Pieces,
char EscapedChar = *CurPtr++;
switch (EscapedChar) {
default:
+ // Handle target-specific escaped characters.
+ if (auto MaybeReplaceStr = TI.handleAsmEscapedChar(EscapedChar)) {
+CurStringPiece += *MaybeReplaceStr;
+continue;
+ }
break;
case '%': // %% -> %
case '{': // %{ -> {
@@ -688,7 +695,6 @@ unsigned
GCCAsmStmt::AnalyzeAsmString(SmallVectorImpl&Pieces,
EscapedChar = *CurPtr++;
}
-const TargetInfo &TI = C.getTargetInfo();
const SourceManager &SM = C.getSourceManager();
const LangOptions &LO = C.getLangOpts();
diff --git a/clang/lib/Basic/Targets/M68k.cpp
b/clang/lib/Basic/Targets/M68k.cpp
index 9fcd58ee6401a..31cb36d37636c 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -191,6 +191,30 @@ bool M68kTargetInfo::validateAsmConstraint(
return false;
}
+llvm::Optional
+M68kTargetInfo::handleAsmEscapedChar(char EscChar) const {
+ char C;
+ switch (EscChar) {
+ case '.':
+ case '#':
+C = EscChar;
+break;
+ case '/':
+C = '%';
+break;
+ case '$':
+C = 's';
+break;
+ case '&':
+C = 'd';
+break;
+ default:
+return llvm::None;
+ }
+
+ return std::string(1, C);
+}
+
std::string M68kTargetInfo::convertConstraint(const char *&Constraint) const {
if (*Constraint == 'C')
// Two-character constraint; add "^" hint for later parsing
diff --git a/clang/lib/Basic/Targets/M68k.h b/clang/lib/Basic/Targets/M68k.h
index be2462bbd7acd..a42ca674ef9cc 100644
--- a/clang/lib/Basic/Targets/M68k.h
+++ b/clang/lib/Basic/Targets/M68k.h
@@ -47,6 +47,7 @@ class LLVM_LIBRARY_VISIBILITY M68kTargetInfo : public
TargetInfo {
std::string convertConstraint(const char *&Constraint) const override;
bool validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &info) const override;
+ llvm::Optional handleAsmEscapedChar(char EscChar) const
override;
const char *getClobbers() const override;
BuiltinVaListKind getBuiltinVaListKind() const override;
bool setCPU(const std::string &Name) override;
diff --git a/clang/test/CodeGen/m68k-asm.c b/clang/test/CodeGen/m68k-asm.c
new file mode 100644
index 0..bfaf2d93ef2d2
--- /dev/null
+++ b/clang/test/CodeGen/m68k-asm.c
@@ -0,0 +1,21 @@
+// REQUIRES: m68k-registered-target
+// RUN: %clang -target m68k -S %s -o - | FileCheck %s
+
+// Test special escaped character in inline assembly
+void escaped() {
+ // '.' -> '.'
+ // CHECK: move.l #66, %d1
+ __asm__ ("move%.l #66, %%d1" ::);
+ // '#' -> '#'
+ // CHECK: move.l #66, %d1
+ __asm__ ("move.l %#66, %%d1" ::);
+ // '/' -> '%'
+
[clang] 5509748 - [cfe][driver][M68k](8/8) Clang driver support
Author: Min-Yih Hsu
Date: 2021-03-08T12:30:57-08:00
New Revision: 5509748f2ce5e06bda7da754297d09a0e68a1f30
URL:
https://github.com/llvm/llvm-project/commit/5509748f2ce5e06bda7da754297d09a0e68a1f30
DIFF:
https://github.com/llvm/llvm-project/commit/5509748f2ce5e06bda7da754297d09a0e68a1f30.diff
LOG: [cfe][driver][M68k](8/8) Clang driver support
Add M68k-specific toolchain and driver configurations / options.
Authors: myhsu, m4yers, glaubitz
Differential Revision: https://reviews.llvm.org/D88394
Added:
clang/lib/Driver/ToolChains/Arch/M68k.cpp
clang/lib/Driver/ToolChains/Arch/M68k.h
clang/test/Driver/m68k-features.cpp
clang/test/Driver/m68k-sub-archs.cpp
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/CMakeLists.txt
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Driver/ToolChains/CommonArgs.cpp
clang/lib/Driver/ToolChains/Gnu.cpp
clang/lib/Driver/ToolChains/Linux.cpp
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 9172215bc512..8e71aff2e96d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -160,6 +160,8 @@ def m_hexagon_Features_Group : OptionGroup<"">,
// These are explicitly handled.
def m_hexagon_Features_HVX_Group : OptionGroup<"">,
Group, DocName<"Hexagon">;
+def m_m68k_Features_Group: OptionGroup<"">,
+ Group, DocName<"M68k">;
def m_mips_Features_Group : OptionGroup<"">,
Group, DocName<"MIPS">;
def m_ppc_Features_Group : OptionGroup<"">,
@@ -3895,6 +3897,13 @@ def mnvs : Flag<["-"], "mnvs">,
Group,
def mno_nvs : Flag<["-"], "mno-nvs">, Group,
Flags<[CC1Option]>, HelpText<"Disable generation of new-value stores">;
+// M68k features flags
+def m68000 : Flag<["-"], "m68000">, Group;
+def m68010 : Flag<["-"], "m68010">, Group;
+def m68020 : Flag<["-"], "m68020">, Group;
+def m68030 : Flag<["-"], "m68030">, Group;
+def m68040 : Flag<["-"], "m68040">, Group;
+def m68060 : Flag<["-"], "m68060">, Group;
// X86 feature flags
def mx87 : Flag<["-"], "mx87">, Group;
diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt
index 7542daf3b8f7..f59141f9e19f 100644
--- a/clang/lib/Driver/CMakeLists.txt
+++ b/clang/lib/Driver/CMakeLists.txt
@@ -26,6 +26,7 @@ add_clang_library(clangDriver
ToolChain.cpp
ToolChains/Arch/AArch64.cpp
ToolChains/Arch/ARM.cpp
+ ToolChains/Arch/M68k.cpp
ToolChains/Arch/Mips.cpp
ToolChains/Arch/PPC.cpp
ToolChains/Arch/RISCV.cpp
diff --git a/clang/lib/Driver/ToolChains/Arch/M68k.cpp
b/clang/lib/Driver/ToolChains/Arch/M68k.cpp
new file mode 100644
index ..66c9f5c87bfb
--- /dev/null
+++ b/clang/lib/Driver/ToolChains/Arch/M68k.cpp
@@ -0,0 +1,93 @@
+//===--- M68k.cpp - M68k Helpers for Tools ---*- C++-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "M68k.h"
+#include "ToolChains/CommonArgs.h"
+#include "clang/Driver/Driver.h"
+#include "clang/Driver/DriverDiagnostic.h"
+#include "clang/Driver/Options.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/Option/ArgList.h"
+#include "llvm/Support/Host.h"
+#include "llvm/Support/Regex.h"
+#include
+
+using namespace clang::driver;
+using namespace clang::driver::tools;
+using namespace clang;
+using namespace llvm::opt;
+
+/// getM68kTargetCPU - Get the (LLVM) name of the 68000 cpu we are targeting.
+std::string m68k::getM68kTargetCPU(const ArgList &Args) {
+ if (Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ)) {
+// The canonical CPU name is captalize. However, we allow
+// starting with lower case or numbers only
+StringRef CPUName = A->getValue();
+
+if (CPUName == "native") {
+ std::string CPU = std::string(llvm::sys::getHostCPUName());
+ if (!CPU.empty() && CPU != "generic")
+return CPU;
+}
+
+if (CPUName == "common")
+ return "generic";
+
+return llvm::StringSwitch(CPUName)
+.Cases("m68000", "68000", "M68000")
+.Cases("m68010", "68010", "M68010")
+.Cases("m68020", "68020", "M68020")
+.Cases("m68030", "68030", "M68030")
+.Cases("m68040", "68040", "M68040")
+.Cases("m68060", "68060", "M68060")
+.Default(CPUName.str());
+ }
+ // FIXME: Throw error when multiple sub-architecture flag exist
+ if (Args.hasArg(clang::driver::options::OPT_m68000))
+return "M68000";
+ if (Args.hasArg(clang::driver::options::OPT_m68010))
+return "M68010";
+ if (Args.hasArg(clang::driver::options::OPT_m680
[clang] 5eb7a58 - [cfe][M68k](7/8) Clang basic support
Author: Min-Yih Hsu
Date: 2021-03-08T12:30:57-08:00
New Revision: 5eb7a5814a5c629378ba2a4a45fc65cd7f183c9c
URL:
https://github.com/llvm/llvm-project/commit/5eb7a5814a5c629378ba2a4a45fc65cd7f183c9c
DIFF:
https://github.com/llvm/llvm-project/commit/5eb7a5814a5c629378ba2a4a45fc65cd7f183c9c.diff
LOG: [cfe][M68k](7/8) Clang basic support
This is the first patch supporting M68k in Clang
- Register M68k as a target
- Target specific CodeGen support
- Target specific attribute support
Authors: myhsu, m4yers, glaubitz
Differential Revision: https://reviews.llvm.org/D88393
Added:
clang/lib/Basic/Targets/M68k.cpp
clang/lib/Basic/Targets/M68k.h
Modified:
clang/include/clang/Basic/Attr.td
clang/lib/Basic/CMakeLists.txt
clang/lib/Basic/Targets.cpp
clang/lib/CodeGen/TargetInfo.cpp
clang/lib/Sema/SemaDeclAttr.cpp
Removed:
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 8afa676c133f..9625e7f8f322 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -368,6 +368,7 @@ def TargetBPF : TargetArch<["bpfel", "bpfeb"]>;
def TargetMips32 : TargetArch<["mips", "mipsel"]>;
def TargetAnyMips : TargetArch<["mips", "mipsel", "mips64", "mips64el"]>;
def TargetMSP430 : TargetArch<["msp430"]>;
+def TargetM68k : TargetArch<["m68k"]>;
def TargetRISCV : TargetArch<["riscv32", "riscv64"]>;
def TargetX86 : TargetArch<["x86"]>;
def TargetAnyX86 : TargetArch<["x86", "x86_64"]>;
@@ -772,8 +773,9 @@ def Annotate : InheritableParamAttr {
}
def ARMInterrupt : InheritableAttr, TargetSpecificAttr {
- // NOTE: If you add any additional spellings, MSP430Interrupt's,
- // MipsInterrupt's and AnyX86Interrupt's spellings must match.
+ // NOTE: If you add any additional spellings, M68kInterrupt's,
+ // MSP430Interrupt's, MipsInterrupt's and AnyX86Interrupt's spellings
+ // must match.
let Spellings = [GCC<"interrupt">];
let Args = [EnumArgument<"Interrupt", "InterruptType",
["IRQ", "FIQ", "SWI", "ABORT", "UNDEF", ""],
@@ -1524,8 +1526,8 @@ def MSABI : DeclOrTypeAttr {
}
def MSP430Interrupt : InheritableAttr, TargetSpecificAttr {
- // NOTE: If you add any additional spellings, ARMInterrupt's, MipsInterrupt's
- // and AnyX86Interrupt's spellings must match.
+ // NOTE: If you add any additional spellings, ARMInterrupt's,
M68kInterrupt's,
+ // MipsInterrupt's and AnyX86Interrupt's spellings must match.
let Spellings = [GCC<"interrupt">];
let Args = [UnsignedArgument<"Number">];
let ParseKind = "Interrupt";
@@ -1541,7 +1543,8 @@ def Mips16 : InheritableAttr,
TargetSpecificAttr {
def MipsInterrupt : InheritableAttr, TargetSpecificAttr {
// NOTE: If you add any additional spellings, ARMInterrupt's,
- // MSP430Interrupt's and AnyX86Interrupt's spellings must match.
+ // M68kInterrupt's, MSP430Interrupt's and AnyX86Interrupt's spellings
+ // must match.
let Spellings = [GCC<"interrupt">];
let Subjects = SubjectList<[Function]>;
let Args = [EnumArgument<"Interrupt", "InterruptType",
@@ -1573,6 +1576,16 @@ def MipsShortCall : InheritableAttr,
TargetSpecificAttr {
let Documentation = [MipsShortCallStyleDocs];
}
+def M68kInterrupt : InheritableAttr, TargetSpecificAttr {
+ // NOTE: If you add any additional spellings, ARMInterrupt's, MipsInterrupt's
+ // MSP430Interrupt's and AnyX86Interrupt's spellings must match.
+ let Spellings = [GNU<"interrupt">];
+ let Args = [UnsignedArgument<"Number">];
+ let ParseKind = "Interrupt";
+ let HasCustomParsing = 1;
+ let Documentation = [Undocumented];
+}
+
def Mode : Attr {
let Spellings = [GCC<"mode">];
let Subjects = SubjectList<[Var, Enum, TypedefName, Field], ErrorDiag>;
@@ -2777,7 +2790,7 @@ def LTOVisibilityPublic : InheritableAttr {
def AnyX86Interrupt : InheritableAttr, TargetSpecificAttr {
// NOTE: If you add any additional spellings, ARMInterrupt's,
- // MSP430Interrupt's and MipsInterrupt's spellings must match.
+ // M68kInterrupt's, MSP430Interrupt's and MipsInterrupt's spellings must
match.
let Spellings = [GCC<"interrupt">];
let Subjects = SubjectList<[HasFunctionProto]>;
let ParseKind = "Interrupt";
diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt
index 709505d502ed..a3a8f8d68962 100644
--- a/clang/lib/Basic/CMakeLists.txt
+++ b/clang/lib/Basic/CMakeLists.txt
@@ -78,6 +78,7 @@ add_clang_library(clangBasic
Targets/Hexagon.cpp
Targets/Lanai.cpp
Targets/Le64.cpp
+ Targets/M68k.cpp
Targets/MSP430.cpp
Targets/Mips.cpp
Targets/NVPTX.cpp
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index 159af12a90fa..793a471194fe 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -22,6 +22,7 @@
#include "Targets/Hexagon.h"
#include "Targets/Lanai.h"
#include "Targets/Le64.h"
+#include "Targets/M68k.h"
#i
[clang] effd75b - [M68k][Driver] Rename target features and macros test files
Author: Min-Yih Hsu Date: 2022-10-25T11:24:48-07:00 New Revision: effd75bda4b1a9b26e554c1cda3e3b4c72fa0aa8 URL: https://github.com/llvm/llvm-project/commit/effd75bda4b1a9b26e554c1cda3e3b4c72fa0aa8 DIFF: https://github.com/llvm/llvm-project/commit/effd75bda4b1a9b26e554c1cda3e3b4c72fa0aa8.diff LOG: [M68k][Driver] Rename target features and macros test files test/Driver/m68k-features.cpp -> test/Driver/m68k-macros.cpp test/Driver/m68k-fixed-register.c -> test/Driver/m68k-features.cpp The original m68k-features.cpp should really be called m68k-macros.cpp since it's testing built-in macro definitions rather than sub-target features. Which are part of what m68k-fixed-register.c was previously doing. NFC. Added: clang/test/Driver/m68k-macros.cpp Modified: clang/test/Driver/m68k-features.cpp Removed: clang/test/Driver/m68k-fixed-register.c diff --git a/clang/test/Driver/m68k-features.cpp b/clang/test/Driver/m68k-features.cpp index 8f85815e7552..0ee9edcfd164 100644 --- a/clang/test/Driver/m68k-features.cpp +++ b/clang/test/Driver/m68k-features.cpp @@ -1,45 +1,61 @@ -// Check macro definitions -// RUN: %clang -target m68k-unknown-linux -m68000 -dM -E %s | FileCheck --check-prefix=CHECK-MX %s -// CHECK-MX: #define __mc68000 1 -// CHECK-MX: #define __mc68000__ 1 -// CHECK-MX: #define mc68000 1 - -// RUN: %clang -target m68k-unknown-linux -m68010 -dM -E %s | FileCheck --check-prefix=CHECK-MX10 %s -// CHECK-MX10: #define __mc68000 1 -// CHECK-MX10: #define __mc68000__ 1 -// CHECK-MX10: #define __mc68010 1 -// CHECK-MX10: #define __mc68010__ 1 -// CHECK-MX10: #define mc68000 1 -// CHECK-MX10: #define mc68010 1 - -// RUN: %clang -target m68k-unknown-linux -m68020 -dM -E %s | FileCheck --check-prefix=CHECK-MX20 %s -// CHECK-MX20: #define __mc68000 1 -// CHECK-MX20: #define __mc68000__ 1 -// CHECK-MX20: #define __mc68020 1 -// CHECK-MX20: #define __mc68020__ 1 -// CHECK-MX20: #define mc68000 1 -// CHECK-MX20: #define mc68020 1 - -// RUN: %clang -target m68k-unknown-linux -m68030 -dM -E %s | FileCheck --check-prefix=CHECK-MX30 %s -// CHECK-MX30: #define __mc68000 1 -// CHECK-MX30: #define __mc68000__ 1 -// CHECK-MX30: #define __mc68030 1 -// CHECK-MX30: #define __mc68030__ 1 -// CHECK-MX30: #define mc68000 1 -// CHECK-MX30: #define mc68030 1 - -// RUN: %clang -target m68k-unknown-linux -m68040 -dM -E %s | FileCheck --check-prefix=CHECK-MX40 %s -// CHECK-MX40: #define __mc68000 1 -// CHECK-MX40: #define __mc68000__ 1 -// CHECK-MX40: #define __mc68040 1 -// CHECK-MX40: #define __mc68040__ 1 -// CHECK-MX40: #define mc68000 1 -// CHECK-MX40: #define mc68040 1 - -// RUN: %clang -target m68k-unknown-linux -m68060 -dM -E %s | FileCheck --check-prefix=CHECK-MX60 %s -// CHECK-MX60: #define __mc68000 1 -// CHECK-MX60: #define __mc68000__ 1 -// CHECK-MX60: #define __mc68060 1 -// CHECK-MX60: #define __mc68060__ 1 -// CHECK-MX60: #define mc68000 1 -// CHECK-MX60: #define mc68060 1 +// REQUIRES: m68k-registered-target +// RUN: %clang -target m68k -ffixed-a0 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-A0 < %t %s +// CHECK-FIXED-A0: "-target-feature" "+reserve-a0" + +// RUN: %clang -target m68k -ffixed-a1 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-A1 < %t %s +// CHECK-FIXED-A1: "-target-feature" "+reserve-a1" + +// RUN: %clang -target m68k -ffixed-a2 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-A2 < %t %s +// CHECK-FIXED-A2: "-target-feature" "+reserve-a2" + +// RUN: %clang -target m68k -ffixed-a3 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-A3 < %t %s +// CHECK-FIXED-A3: "-target-feature" "+reserve-a3" + +// RUN: %clang -target m68k -ffixed-a4 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-A4 < %t %s +// CHECK-FIXED-A4: "-target-feature" "+reserve-a4" + +// RUN: %clang -target m68k -ffixed-a5 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-A5 < %t %s +// CHECK-FIXED-A5: "-target-feature" "+reserve-a5" + +// RUN: %clang -target m68k -ffixed-a6 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-A6 < %t %s +// CHECK-FIXED-A6: "-target-feature" "+reserve-a6" + +// RUN: %clang -target m68k -ffixed-d0 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-D0 < %t %s +// CHECK-FIXED-D0: "-target-feature" "+reserve-d0" + +// RUN: %clang -target m68k -ffixed-d1 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-D1 < %t %s +// CHECK-FIXED-D1: "-target-feature" "+reserve-d1" + +// RUN: %clang -target m68k -ffixed-d2 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-D2 < %t %s +// CHECK-FIXED-D2: "-target-feature" "+reserve-d2" + +// RUN: %clang -target m68k -ffixed-d3 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-D3 < %t %s +// CHECK-FIXED-D3: "-target-feature" "+reserve-d3" + +// RUN: %clang -target m68k -ffixed-d4 -### %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-FIXED-D4 < %t %s +// CHECK-FIXED-D
[clang] fd4f962 - [Clang][M68k] Add Clang support for the new M68k_RTD CC
Author: Min-Yih Hsu
Date: 2023-10-15T16:13:43-07:00
New Revision: fd4f96290ac99bf8b9284d3b32743cac0bb135ea
URL:
https://github.com/llvm/llvm-project/commit/fd4f96290ac99bf8b9284d3b32743cac0bb135ea
DIFF:
https://github.com/llvm/llvm-project/commit/fd4f96290ac99bf8b9284d3b32743cac0bb135ea.diff
LOG: [Clang][M68k] Add Clang support for the new M68k_RTD CC
This patch adds `CC_M68kRTD`, which will be used on function if either
`__attribute__((m68k_rtd))` is presented or `-mrtd` flag is given.
Differential Revision: https://reviews.llvm.org/D149867
Added:
clang/test/CodeGenCXX/m68k-rtdcall.cpp
clang/test/Sema/m68k-rtdcall.c
clang/test/SemaCXX/m68k-rtdcall.cpp
Modified:
clang/docs/ReleaseNotes.rst
clang/include/clang-c/Index.h
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/LangOptions.h
clang/include/clang/Basic/Specifiers.h
clang/include/clang/Driver/Options.td
clang/lib/AST/ASTContext.cpp
clang/lib/AST/ItaniumMangle.cpp
clang/lib/AST/Type.cpp
clang/lib/AST/TypePrinter.cpp
clang/lib/Basic/Targets/M68k.cpp
clang/lib/Basic/Targets/M68k.h
clang/lib/CodeGen/CGCall.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/lib/Sema/SemaDeclAttr.cpp
clang/lib/Sema/SemaType.cpp
clang/test/CodeGen/mrtd.c
clang/test/CodeGenCXX/default_calling_conv.cpp
clang/tools/libclang/CXType.cpp
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index be7c8bf247f7af5..6d315e9f84ddfe8 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -205,6 +205,10 @@ Modified Compiler Flags
* ``-frewrite-includes`` now guards the original #include directives with
``__CLANG_REWRITTEN_INCLUDES``, and ``__CLANG_REWRITTEN_SYSTEM_INCLUDES`` as
appropriate.
+* Introducing a new default calling convention for ``-fdefault-calling-conv``:
+ ``rtdcall``. This new default CC only works for M68k and will use the new
+ ``m68k_rtdcc`` CC on every functions that are not variadic. The ``-mrtd``
+ driver/frontend flag has the same effect when targeting M68k.
Removed Compiler Flags
-
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index 1b91feabd584c50..64ab3378957c702 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -2980,6 +2980,7 @@ enum CXCallingConv {
CXCallingConv_AArch64VectorCall = 16,
CXCallingConv_SwiftAsync = 17,
CXCallingConv_AArch64SVEPCS = 18,
+ CXCallingConv_M68kRTD = 19,
CXCallingConv_Invalid = 100,
CXCallingConv_Unexposed = 200
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 5c9eb7b8a981037..5486b36133755cc 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -2805,6 +2805,11 @@ def PreserveAll : DeclOrTypeAttr {
let Documentation = [PreserveAllDocs];
}
+def M68kRTD: DeclOrTypeAttr {
+ let Spellings = [Clang<"m68k_rtd">];
+ let Documentation = [M68kRTDDocs];
+}
+
def Target : InheritableAttr {
let Spellings = [GCC<"target">];
let Args = [StringArgument<"featuresStr">];
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index 9f9991bdae36155..cbbf69faeb308ad 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -2825,6 +2825,18 @@ See the documentation for `__vectorcall`_ on MSDN for
more details.
}];
}
+def M68kRTDDocs : Documentation {
+ let Category = DocCatCallingConvs;
+ let Content = [{
+On M68k targets, this attribute changes the calling convention of a function
+to clear parameters off the stack on return. In other words, callee is
+responsible for cleaning out the stack space allocated for incoming paramters.
+This convention does not support variadic calls or unprototyped functions in C.
+When targeting M68010 or newer CPUs, this calling convention is implemented
+using the `rtd` instruction.
+ }];
+}
+
def DocCatConsumed : DocumentationCategory<"Consumed Annotation Checking"> {
let Content = [{
Clang supports additional attributes for checking basic resource management
diff --git a/clang/include/clang/Basic/LangOptions.h
b/clang/include/clang/Basic/LangOptions.h
index e0e95f6d26f4545..20a8ada60e0fe51 100644
--- a/clang/include/clang/Basic/LangOptions.h
+++ b/clang/include/clang/Basic/LangOptions.h
@@ -134,7 +134,8 @@ class LangOptions : public LangOptionsBase {
DCC_FastCall,
DCC_StdCall,
DCC_VectorCall,
-DCC_RegCall
+DCC_RegCall,
+DCC_RtdCall
};
enum AddrSpaceMapMangling { ASMM_Target, ASMM_On, ASMM_Off };
diff --git a/clang/include/clang/Basic/Specifiers.h
b/clang/include/clang/Basic/Specifiers.h
index 6ae56703eca4127..0add
[clang] [NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (PR #66295)
https://github.com/mshockwave approved this pull request. https://github.com/llvm/llvm-project/pull/66295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 230558e - [Clang][M68k] Use `DefineStd` for target-specific macros
Author: Min-Yih Hsu
Date: 2023-09-01T23:25:08-07:00
New Revision: 230558e444c2e1af8f34f99e59433a3fb87ed758
URL:
https://github.com/llvm/llvm-project/commit/230558e444c2e1af8f34f99e59433a3fb87ed758
DIFF:
https://github.com/llvm/llvm-project/commit/230558e444c2e1af8f34f99e59433a3fb87ed758.diff
LOG: [Clang][M68k] Use `DefineStd` for target-specific macros
Use `DefineStd` for target-specific macros such that GNU-style definitions
can be correctly toggled.
Differential Revision: https://reviews.llvm.org/D158698
Added:
Modified:
clang/lib/Basic/Targets/M68k.cpp
clang/test/Driver/m68k-macros.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/M68k.cpp
b/clang/lib/Basic/Targets/M68k.cpp
index 1b0cc4d0b13ffcc..3c6274f89dab162 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -80,36 +80,24 @@ void M68kTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__m68k__");
- Builder.defineMacro("mc68000");
- Builder.defineMacro("__mc68000");
- Builder.defineMacro("__mc68000__");
+ DefineStd(Builder, "mc68000", Opts);
// For sub-architecture
switch (CPU) {
case CK_68010:
-Builder.defineMacro("mc68010");
-Builder.defineMacro("__mc68010");
-Builder.defineMacro("__mc68010__");
+DefineStd(Builder, "mc68010", Opts);
break;
case CK_68020:
-Builder.defineMacro("mc68020");
-Builder.defineMacro("__mc68020");
-Builder.defineMacro("__mc68020__");
+DefineStd(Builder, "mc68020", Opts);
break;
case CK_68030:
-Builder.defineMacro("mc68030");
-Builder.defineMacro("__mc68030");
-Builder.defineMacro("__mc68030__");
+DefineStd(Builder, "mc68030", Opts);
break;
case CK_68040:
-Builder.defineMacro("mc68040");
-Builder.defineMacro("__mc68040");
-Builder.defineMacro("__mc68040__");
+DefineStd(Builder, "mc68040", Opts);
break;
case CK_68060:
-Builder.defineMacro("mc68060");
-Builder.defineMacro("__mc68060");
-Builder.defineMacro("__mc68060__");
+DefineStd(Builder, "mc68060", Opts);
break;
default:
break;
diff --git a/clang/test/Driver/m68k-macros.cpp
b/clang/test/Driver/m68k-macros.cpp
index 19954f5a0c81b35..c61248ee0232a48 100644
--- a/clang/test/Driver/m68k-macros.cpp
+++ b/clang/test/Driver/m68k-macros.cpp
@@ -4,55 +4,61 @@
// CHECK-MX881: #define __HAVE_68881__ 1
// CHECK-NOMX881-NOT: #define __HAVE_68881__ 1
-// RUN: %clang -target m68k-unknown-linux -m68000 -dM -E %s | FileCheck
--check-prefixes=CHECK-MX,CHECK-NOMX881 %s
+// RUN: %clang -target m68k-unknown-linux -m68000 -std=c++11 -dM -E %s |
FileCheck --check-prefixes=CHECK-MX,CHECK-NOMX881 %s
+// RUN: %clang -target m68k-unknown-linux -m68000 -std=gnu++11 -dM -E %s |
FileCheck --check-prefixes=CHECK-MX,CHECK-MX-GNU,CHECK-NOMX881 %s
// RUN: %clang -target m68k-unknown-linux -m68000 -mhard-float -dM -E %s |
FileCheck --check-prefix=CHECK-MX881 %s
// RUN: %clang -target m68k-unknown-linux -m68000 -m68881 -dM -E %s |
FileCheck --check-prefix=CHECK-MX881 %s
// CHECK-MX: #define __mc68000 1
// CHECK-MX: #define __mc68000__ 1
-// CHECK-MX: #define mc68000 1
+// CHECK-MX-GNU: #define mc68000 1
-// RUN: %clang -target m68k-unknown-linux -m68010 -dM -E %s | FileCheck
--check-prefixes=CHECK-MX10,CHECK-NOMX881 %s
+// RUN: %clang -target m68k-unknown-linux -m68010 -std=c++11 -dM -E %s |
FileCheck --check-prefixes=CHECK-MX10,CHECK-NOMX881 %s
+// RUN: %clang -target m68k-unknown-linux -m68010 -std=gnu++11 -dM -E %s |
FileCheck --check-prefixes=CHECK-MX10,CHECK-MX10-GNU,CHECK-NOMX881 %s
// RUN: %clang -target m68k-unknown-linux -m68010 -mhard-float -dM -E %s |
FileCheck --check-prefix=CHECK-MX881 %s
// RUN: %clang -target m68k-unknown-linux -m68010 -m68881 -dM -E %s |
FileCheck --check-prefix=CHECK-MX881 %s
// CHECK-MX10: #define __mc68000 1
// CHECK-MX10: #define __mc68000__ 1
// CHECK-MX10: #define __mc68010 1
// CHECK-MX10: #define __mc68010__ 1
-// CHECK-MX10: #define mc68000 1
-// CHECK-MX10: #define mc68010 1
+// CHECK-MX10-GNU: #define mc68000 1
+// CHECK-MX10-GNU: #define mc68010 1
-// RUN: %clang -target m68k-unknown-linux -m68020 -dM -E %s | FileCheck
--check-prefixes=CHECK-MX20,CHECK-MX881 %s
+// RUN: %clang -target m68k-unknown-linux -m68020 -std=c++11 -dM -E %s |
FileCheck --check-prefixes=CHECK-MX20,CHECK-MX881 %s
+// RUN: %clang -target m68k-unknown-linux -m68020 -std=gnu++11 -dM -E %s |
FileCheck --check-prefixes=CHECK-MX20,CHECK-MX20-GNU,CHECK-MX881 %s
// RUN: %clang -target m68k-unknown-linux -m68020 -msoft-float -dM -E %s |
FileCheck --check-prefix=CHECK-NOMX881 %s
// CHECK-MX20: #define __mc68000 1
// CHECK-MX20: #define __mc68000__ 1
// CHECK-MX20: #define __mc68020 1
// CHECK-MX20: #define __mc68020__ 1
-// CHECK-MX20: #define mc68000 1
-// CHECK-MX20: #define mc68020 1
+// CHECK-MX20-GNU: #define mc68000 1
+// CHECK-MX20-GNU: #
[clang] Add flags to dump IR to a file before and after LLVM passes (PR #65179)
@@ -830,6 +831,182 @@ void PrintIRInstrumentation::registerCallbacks(
}
}
+void DumpIRInstrumentation::registerCallbacks(
+PassInstrumentationCallbacks &PIC) {
+
+ if (!(shouldDumpBeforeSomePass() || shouldDumpAfterSomePass()))
+return;
+
+ this->PIC = &PIC;
+
+ PIC.registerBeforeNonSkippedPassCallback(
+ [this](StringRef P, Any IR) { this->pushPass(P, IR); });
+
+ if (shouldDumpBeforeSomePass())
+PIC.registerBeforeNonSkippedPassCallback(
+[this](StringRef P, Any IR) { this->dumpBeforePass(P, IR); });
+
+ if (shouldDumpAfterSomePass()) {
+PIC.registerAfterPassCallback(
+[this](StringRef P, Any IR, const PreservedAnalyses &) {
+ this->dumpAfterPass(P, IR);
+});
+ }
+
+ // It is important the the "popPass" callback fires after the dumpAfterPass
+ // callback
+ PIC.registerAfterPassCallback(
+ [this](StringRef P, Any IR, const PreservedAnalyses &) {
+this->popPass(P);
+ });
+}
+
+void DumpIRInstrumentation::dumpBeforePass(StringRef PassID, Any IR) {
+ if (isIgnored(PassID))
mshockwave wrote:
somehow I thought the brace on line 870 marks the end of this function, my bad.
It's all good now
https://github.com/llvm/llvm-project/pull/65179
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[clang-tools-extra] Add flags to dump IR to a file before and after LLVM passes (PR #65179)
@@ -830,6 +831,182 @@ void PrintIRInstrumentation::registerCallbacks(
}
}
+void DumpIRInstrumentation::registerCallbacks(
+PassInstrumentationCallbacks &PIC) {
+
+ if (!(shouldDumpBeforeSomePass() || shouldDumpAfterSomePass()))
+return;
+
+ this->PIC = &PIC;
+
+ PIC.registerBeforeNonSkippedPassCallback(
+ [this](StringRef P, Any IR) { this->pushPass(P, IR); });
+
+ if (shouldDumpBeforeSomePass())
+PIC.registerBeforeNonSkippedPassCallback(
+[this](StringRef P, Any IR) { this->dumpBeforePass(P, IR); });
+
+ if (shouldDumpAfterSomePass()) {
+PIC.registerAfterPassCallback(
+[this](StringRef P, Any IR, const PreservedAnalyses &) {
+ this->dumpAfterPass(P, IR);
+});
+ }
+
+ // It is important the the "popPass" callback fires after the dumpAfterPass
+ // callback
+ PIC.registerAfterPassCallback(
+ [this](StringRef P, Any IR, const PreservedAnalyses &) {
+this->popPass(P);
+ });
+}
+
+void DumpIRInstrumentation::dumpBeforePass(StringRef PassID, Any IR) {
+ if (isIgnored(PassID))
mshockwave wrote:
somehow I thought the brace on line 870 marks the end of this function, my bad.
It's all good now
https://github.com/llvm/llvm-project/pull/65179
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[clang] 7335cd0 - [M68k] Add support for basic memory constraints in inline asm
Author: Min-Yih Hsu
Date: 2023-03-08T13:52:34-08:00
New Revision: 7335cd05137076c69ce4716ac8f30a99fc95c406
URL:
https://github.com/llvm/llvm-project/commit/7335cd05137076c69ce4716ac8f30a99fc95c406
DIFF:
https://github.com/llvm/llvm-project/commit/7335cd05137076c69ce4716ac8f30a99fc95c406.diff
LOG: [M68k] Add support for basic memory constraints in inline asm
This patch adds support for 'm', 'Q', and 'U' memory constraints.
Differential Revision: https://reviews.llvm.org/D143529
Added:
Modified:
clang/lib/Basic/Targets/M68k.cpp
clang/test/Sema/inline-asm-validate-m68k.c
llvm/lib/Target/M68k/M68kAsmPrinter.cpp
llvm/lib/Target/M68k/M68kAsmPrinter.h
llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
llvm/lib/Target/M68k/M68kISelLowering.cpp
llvm/lib/Target/M68k/M68kISelLowering.h
llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h
llvm/test/CodeGen/M68k/inline-asm.ll
Removed:
diff --git a/clang/lib/Basic/Targets/M68k.cpp
b/clang/lib/Basic/Targets/M68k.cpp
index cbc7c79837792..c83c5389e3b9d 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -192,6 +192,12 @@ bool M68kTargetInfo::validateAsmConstraint(
break;
}
break;
+ case 'Q': // address register indirect addressing
+ case 'U': // address register indirect w/ constant offset addressing
+// TODO: Handle 'S' (basically 'm' when pc-rel is enforced) when
+// '-mpcrel' flag is properly handled by the driver.
+info.setAllowsMemory();
+return true;
default:
break;
}
diff --git a/clang/test/Sema/inline-asm-validate-m68k.c
b/clang/test/Sema/inline-asm-validate-m68k.c
index a0b75304eba00..3abe638324452 100644
--- a/clang/test/Sema/inline-asm-validate-m68k.c
+++ b/clang/test/Sema/inline-asm-validate-m68k.c
@@ -82,5 +82,13 @@ void a(int x) {
void d(int x) {
asm ("" :: "d"(x));
}
+
+// Memory constraints
+void mem() {
+ int x;
+ asm ("" :: "m"(x));
+ asm ("" :: "Q"(x));
+ asm ("" :: "U"(x));
+}
#endif
diff --git a/llvm/lib/Target/M68k/M68kAsmPrinter.cpp
b/llvm/lib/Target/M68k/M68kAsmPrinter.cpp
index 4933d40f33885..f748450c170aa 100644
--- a/llvm/lib/Target/M68k/M68kAsmPrinter.cpp
+++ b/llvm/lib/Target/M68k/M68kAsmPrinter.cpp
@@ -76,6 +76,90 @@ bool M68kAsmPrinter::PrintAsmOperand(const MachineInstr *MI,
unsigned OpNo,
return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
}
+void M68kAsmPrinter::printDisp(const MachineInstr *MI, unsigned opNum,
+ raw_ostream &O) {
+ // Print immediate displacement without the '#' predix
+ const MachineOperand &Op = MI->getOperand(opNum);
+ if (Op.isImm()) {
+O << Op.getImm();
+return;
+ }
+ // Displacement is relocatable, so we're pretty permissive about what
+ // can be put here.
+ printOperand(MI, opNum, O);
+}
+
+void M68kAsmPrinter::printAbsMem(const MachineInstr *MI, unsigned OpNum,
+ raw_ostream &O) {
+ const MachineOperand &MO = MI->getOperand(OpNum);
+ if (MO.isImm())
+O << format("$%0" PRIx64, (uint64_t)MO.getImm());
+ else
+PrintAsmMemoryOperand(MI, OpNum, nullptr, O);
+}
+
+bool M68kAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
+ unsigned OpNo, const char
*ExtraCode,
+ raw_ostream &OS) {
+ const MachineOperand &MO = MI->getOperand(OpNo);
+ switch (MO.getType()) {
+ case MachineOperand::MO_Immediate:
+// Immediate value that goes here is the addressing mode kind we set
+// in M68kDAGToDAGISel::SelectInlineAsmMemoryOperand.
+using namespace M68k;
+// Skip the addressing mode kind operand.
+++OpNo;
+// Decode MemAddrModeKind.
+switch (static_cast(MO.getImm())) {
+case MemAddrModeKind::j:
+ printARIMem(MI, OpNo, OS);
+ break;
+case MemAddrModeKind::o:
+ printARIPIMem(MI, OpNo, OS);
+ break;
+case MemAddrModeKind::e:
+ printARIPDMem(MI, OpNo, OS);
+ break;
+case MemAddrModeKind::p:
+ printARIDMem(MI, OpNo, OS);
+ break;
+case MemAddrModeKind::f:
+case MemAddrModeKind::F:
+ printARIIMem(MI, OpNo, OS);
+ break;
+case MemAddrModeKind::k:
+ printPCIMem(MI, 0, OpNo, OS);
+ break;
+case MemAddrModeKind::q:
+ printPCDMem(MI, 0, OpNo, OS);
+ break;
+case MemAddrModeKind::b:
+ printAbsMem(MI, OpNo, OS);
+ break;
+default:
+ llvm_unreachable("Unrecognized memory addressing mode");
+}
+return false;
+ case MachineOperand::MO_GlobalAddress:
+PrintSymbolOperand(MO, OS);
+return false;
+ case MachineOperand::MO_BlockAddress:
+GetBlockAddressSymbol(MO.getBlockAddress())->print(OS, MAI);
+return false;
+ case MachineOperand::MO_Register:
+// This is a special case where it is treated as a memory reference, with
+// the register holding th
[clang] 9b61708 - [M68k] Add basic Clang support for M68881/2
Author: Min-Yih Hsu
Date: 2023-04-24T09:32:49-07:00
New Revision: 9b617081420dc579c52b53a4d8929b206b206eed
URL:
https://github.com/llvm/llvm-project/commit/9b617081420dc579c52b53a4d8929b206b206eed
DIFF:
https://github.com/llvm/llvm-project/commit/9b617081420dc579c52b53a4d8929b206b206eed.diff
LOG: [M68k] Add basic Clang support for M68881/2
- Add the `-m68881` flag
- Add floating point feature detection
- Macro definitions
Differential Revision: https://reviews.llvm.org/D147481
Added:
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/M68k.cpp
clang/lib/Basic/Targets/M68k.h
clang/lib/Driver/ToolChains/Arch/M68k.cpp
clang/lib/Driver/ToolChains/Arch/M68k.h
clang/test/Driver/m68k-features.cpp
clang/test/Driver/m68k-macros.cpp
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index d8ae398c61218..ceab53171eaee 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4650,6 +4650,8 @@ def m68030 : Flag<["-"], "m68030">,
Group;
def m68040 : Flag<["-"], "m68040">, Group;
def m68060 : Flag<["-"], "m68060">, Group;
+def m68881 : Flag<["-"], "m68881">, Group;
+
foreach i = {0-6} in
def ffixed_a#i : Flag<["-"], "ffixed-a"#i>, Group,
HelpText<"Reserve the a"#i#" register (M68k only)">;
diff --git a/clang/lib/Basic/Targets/M68k.cpp
b/clang/lib/Basic/Targets/M68k.cpp
index 437ad7253a31c..1b0cc4d0b13ff 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -27,8 +27,8 @@ namespace clang {
namespace targets {
M68kTargetInfo::M68kTargetInfo(const llvm::Triple &Triple,
- const TargetOptions &)
-: TargetInfo(Triple) {
+ const TargetOptions &Opts)
+: TargetInfo(Triple), TargetOpts(Opts) {
std::string Layout;
@@ -120,6 +120,11 @@ void M68kTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
}
+
+ // Floating point
+ if (TargetOpts.FeatureMap.lookup("isa-68881") ||
+ TargetOpts.FeatureMap.lookup("isa-68882"))
+Builder.defineMacro("__HAVE_68881__");
}
ArrayRef M68kTargetInfo::getTargetBuiltins() const {
diff --git a/clang/lib/Basic/Targets/M68k.h b/clang/lib/Basic/Targets/M68k.h
index dea9b59334919..1af00115a5059 100644
--- a/clang/lib/Basic/Targets/M68k.h
+++ b/clang/lib/Basic/Targets/M68k.h
@@ -36,6 +36,8 @@ class LLVM_LIBRARY_VISIBILITY M68kTargetInfo : public
TargetInfo {
CK_68060
} CPU = CK_Unknown;
+ const TargetOptions &TargetOpts;
+
public:
M68kTargetInfo(const llvm::Triple &Triple, const TargetOptions &);
diff --git a/clang/lib/Driver/ToolChains/Arch/M68k.cpp
b/clang/lib/Driver/ToolChains/Arch/M68k.cpp
index 628c252e83864..963f7a187d636 100644
--- a/clang/lib/Driver/ToolChains/Arch/M68k.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/M68k.cpp
@@ -65,13 +65,35 @@ std::string m68k::getM68kTargetCPU(const ArgList &Args) {
return "";
}
+static void addFloatABIFeatures(const llvm::opt::ArgList &Args,
+std::vector &Features) {
+ Arg *A = Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float,
+ options::OPT_m68881);
+ // Opt out FPU even for newer CPUs.
+ if (A && A->getOption().matches(options::OPT_msoft_float)) {
+Features.push_back("-isa-68881");
+Features.push_back("-isa-68882");
+return;
+ }
+
+ std::string CPU = m68k::getM68kTargetCPU(Args);
+ // Only enable M68881 for CPU < 68020 if the related flags are present.
+ if ((A && (CPU == "M68000" || CPU == "M68010")) ||
+ // Otherwise, by default we assume newer CPUs have M68881/2.
+ CPU == "M68020")
+Features.push_back("+isa-68881");
+ else if (CPU == "M68030" || CPU == "M68040" || CPU == "M68060")
+// Note that although CPU >= M68040 imply M68882, we still add `isa-68882`
+// anyway so that it's easier to add or not add the corresponding macro
+// definitions later, in case we want to disable 68881/2 in newer CPUs
+// (with -msoft-float, for instance).
+Features.push_back("+isa-68882");
+}
+
void m68k::getM68kTargetFeatures(const Driver &D, const llvm::Triple &Triple,
const ArgList &Args,
std::vector &Features) {
-
- m68k::FloatABI FloatABI = m68k::getM68kFloatABI(D, Args);
- if (FloatABI == m68k::FloatABI::Soft)
-Features.push_back("-hard-float");
+ addFloatABIFeatures(Args, Features);
// Handle '-ffixed-' flags
if (Args.hasArg(options::OPT_ffixed_a0))
@@ -105,21 +127,3 @@ void m68k::getM68kTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
if (Args.hasArg(options::OPT_ffixed_d7))
Features.push_back("+res
[clang] [llvm] [mlir] [TableGen] Add const variants of accessors for backend (PR #106658)
https://github.com/mshockwave approved this pull request. > I propose the following next steps (once this is committed): this timeline looks fine, do you also want to add `[[deprecated]]` once the PSA is out? Also, I can help on other LLVM TableGen backends if they haven't been updated. https://github.com/llvm/llvm-project/pull/106658 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)
mshockwave wrote: > So for this particular PR, we just need a name people are happy with (perhaps > check if the vendor has a preference?). Something like `-mcpu=rp2350-hazard3` > perhaps? +1 on `-mcpu=rp2350-hazard3` over `-mcpu=raspberrypi-rp2350` because the former is more specific to the RISC-V part of RP2350. https://github.com/llvm/llvm-project/pull/102452 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [flang] [llvm] [mlir] [polly] [test]: fix filecheck annotation typos (PR #91854)
@@ -96,7 +96,7 @@ for.end: ; preds = %for.end.loopexit, % ; Specify a smaller minimum VF (via `-epilogue-vectorization-minimum-VF=4`) and ; make sure the epilogue gets vectorized in that case. -; CHECK-MIN-D-LABLE: @f3 +; CHECK-MIN-D-LABEL: @f3 mshockwave wrote: I think this should be `CHECK-MIN-4-LABEL`, otherwise it would be conflicted with line 89. https://github.com/llvm/llvm-project/pull/91854 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [flang] [llvm] [mlir] [polly] [test]: fix filecheck annotation typos (PR #91854)
@@ -335,7 +335,7 @@ define void @cannot_sink_reduction(i32 %x, ptr %ptr, i64
%tc) {
-; CHECK-NET: ret void
+; CHECK-NEXT:ret void
mshockwave wrote:
please remove this line as it has been covered by line 333 (which was probably
generated by UTC).
https://github.com/llvm/llvm-project/pull/91854
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[clang] 59437cb - [M68k] Fix empty builtin va_list kind
Author: Min-Yih Hsu
Date: 2021-04-16T11:09:22-07:00
New Revision: 59437cb7d7c30054f0e77b2369c0aeffed3ccb14
URL:
https://github.com/llvm/llvm-project/commit/59437cb7d7c30054f0e77b2369c0aeffed3ccb14
DIFF:
https://github.com/llvm/llvm-project/commit/59437cb7d7c30054f0e77b2369c0aeffed3ccb14.diff
LOG: [M68k] Fix empty builtin va_list kind
Clang _requires_ every target to provide a va_list kind so we shouldn't
put a llvm_unreachable there. Using `VoidPtrBuiltinVaList` because m68k
doesn't have any special ABI for variadic args.
Added:
Modified:
clang/lib/Basic/Targets/M68k.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/M68k.cpp
b/clang/lib/Basic/Targets/M68k.cpp
index e10fd77d2590a..8e8a69f75c8b0 100644
--- a/clang/lib/Basic/Targets/M68k.cpp
+++ b/clang/lib/Basic/Targets/M68k.cpp
@@ -159,9 +159,8 @@ const char *M68kTargetInfo::getClobbers() const {
return "";
}
-M68kTargetInfo::BuiltinVaListKind M68kTargetInfo::getBuiltinVaListKind() const
{
- // FIXME: implement
- llvm_unreachable("Not implemented yet");
+TargetInfo::BuiltinVaListKind M68kTargetInfo::getBuiltinVaListKind() const {
+ return TargetInfo::VoidPtrBuiltinVaList;
}
} // namespace targets
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[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)
mshockwave wrote: ping https://github.com/llvm/llvm-project/pull/116878 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64; static const int16_t cSledLength = 8; #elif defined(__hexagon__) static const int16_t cSledLength = 20; +#elif SANITIZER_RISCV64 +static const int16_t cSledLength = 76; +#elif defined(__riscv) && (__riscv_xlen == 32) mshockwave wrote: We don't have `SANITIZER_RISCV32` I believe, if that's what you meant https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)
mshockwave wrote: > Perhaps `__xray_default_options()` like `__asan_default_options()`? The user > would need to provide a `.o` that defines the function, but there is more > flexibility (e.g. the function can inspect a config file). I think this will be a better idea. It simplifies the design and no longer requires changes in Clang driver and the additional LLVM Pass (i.e. XRayPreparation). I implemented that in #117921 and will close this PR in favor of that one. https://github.com/llvm/llvm-project/pull/116878 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)
https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/116878 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)
mshockwave wrote: Close this PR in favor of #117921 https://github.com/llvm/llvm-project/pull/116878 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)
@@ -0,0 +1,279 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// RISC-V processor by MIPS.
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+ int IssueWidth = 4;
+ int MicroOpBufferSize = 96; // as per the specification
+ int LoadLatency = 4;
+ int MispredictPenalty = 8; // TODO: Estimated
+ let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+
+// Handle ALQ Pipelines.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+def p8700IssueALU : ProcResource<1> { let Super = p8700ALQ; }
mshockwave wrote:
why do you want to create a Super resource hierarchy while p8700IssueALU is the
only descendent?
https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)
@@ -0,0 +1,279 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// RISC-V processor by MIPS.
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+ int IssueWidth = 4;
+ int MicroOpBufferSize = 96; // as per the specification
+ int LoadLatency = 4;
+ int MispredictPenalty = 8; // TODO: Estimated
+ let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+
+// Handle ALQ Pipelines.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+def p8700IssueALU : ProcResource<1> { let Super = p8700ALQ; }
+
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTISTD : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLDST : ProcResource<1> { let Super = p8700AGQ; }
+def p8700GpDiv : ProcResource<1>;
+def p8700GpMul : ProcResource<1>;
+def p8700WriteEitherALU : ProcResGroup<[p8700IssueALU, p8700IssueAL2]>;
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Handle zba.
+def : WriteRes;
+def : WriteRes;
+
+// Handle zbb.
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 0 in {
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 7 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8, ReleaseAtCycles = [5] in {
+def : WriteRes;
+def : WriteRes;
+}
+
+def : WriteRes;
+def : WriteRes;
+
+// Handle CTISTD Pipeline.
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+// Handle FPU Pipelines.
+def p8700FPQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueFPUS : ProcResource<1> { let Super = p8700FPQ; }
+def p8700IssueFPUL : ProcResource<1> { let Super = p8700FPQ; }
+def p8700IssueFPULoad : ProcResource<1> { let Super = p8700FPQ; }
+def p8700FpuApu : ProcResource<1>;
+def p8700FpuLong : ProcResource<1>;
+
+let Latency = 4, ReleaseAtCycles = [1, 1] in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 2, ReleaseAtCycles = [1, 1] in {
mshockwave wrote:
ReleaseAtCycles is default to 1 already I believe
https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)
@@ -22,6 +22,7 @@ def WriteIMul32 : SchedWrite;// 32-bit multiply on RV64I def WriteJmp: SchedWrite;// Jump def WriteJal: SchedWrite;// Jump and link def WriteJalr : SchedWrite;// Jump and link register +def WriteJmpReg : SchedWrite;// Jump register mshockwave wrote: which instruction uses this? https://github.com/llvm/llvm-project/pull/117865 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)
https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)
https://github.com/mshockwave created
https://github.com/llvm/llvm-project/pull/116878
This flag specifies XRay options that will automatically be applied to the
instrumented binaries during run-time even without setting `XRAY_OPTIONS`. This
is useful in cases where setting the `XRAY_OPTIONS` environment variable might
be difficult. Plus, it's a convenient way to populate XRay options when you
always want the instrumentation to be enabled.
The implementation follows what memory profiler and PGO did for their profile
file name and profile version, respectively: insert a weak linkage global
variable carrying the option string, which is then intercepted by compiler-rt
during xray's option parsing phase.
>From 95ee4bd09aa48d4f0c2c4f5fc1e81e20cd57c7e2 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Mon, 11 Nov 2024 11:40:43 -0800
Subject: [PATCH] [XRay] Add `-fxray-default-options` to pass build-time
defined XRay options
This is useful in cases where setting the `XRAY_OPTIONS` environment
variable might be difficult. Plus, it's a convenient way to populate
XRay options when you always want the instrumentation to be enabled.
The implementation follows what memory profiler and PGO did for their
profile file name and profile version, respectively: insert a weak
linkage global variable carrying the option string, which is then
intercepted by compiler-rt during xray's option parsing phase.
---
clang/include/clang/Basic/CodeGenOptions.h| 4 ++
clang/include/clang/Driver/Options.td | 6 +++
clang/lib/CodeGen/BackendUtil.cpp | 8 +++
clang/lib/CodeGen/CodeGenModule.cpp | 8 +++
clang/lib/Driver/XRayArgs.cpp | 3 ++
clang/test/CodeGen/xray-default-options.c | 7 +++
compiler-rt/lib/xray/CMakeLists.txt | 1 +
compiler-rt/lib/xray/xray_flags.cpp | 4 ++
compiler-rt/lib/xray/xray_flags.h | 6 +++
compiler-rt/lib/xray/xray_options_var.cpp | 24 +
.../xray/TestCases/Posix/default-options.cpp | 12 +
llvm/docs/XRay.rst| 15 +-
.../Instrumentation/XRayPreparation.h | 24 +
llvm/lib/Passes/PassBuilder.cpp | 1 +
llvm/lib/Passes/PassRegistry.def | 1 +
.../Transforms/Instrumentation/CMakeLists.txt | 1 +
.../Instrumentation/XRayPreparation.cpp | 49 +++
llvm/test/CodeGen/X86/xray-default-options.ll | 10
18 files changed, 183 insertions(+), 1 deletion(-)
create mode 100644 clang/test/CodeGen/xray-default-options.c
create mode 100644 compiler-rt/lib/xray/xray_options_var.cpp
create mode 100644 compiler-rt/test/xray/TestCases/Posix/default-options.cpp
create mode 100644
llvm/include/llvm/Transforms/Instrumentation/XRayPreparation.h
create mode 100644 llvm/lib/Transforms/Instrumentation/XRayPreparation.cpp
create mode 100644 llvm/test/CodeGen/X86/xray-default-options.ll
diff --git a/clang/include/clang/Basic/CodeGenOptions.h
b/clang/include/clang/Basic/CodeGenOptions.h
index 2dcf98b465661e..1e9e3b87052f51 100644
--- a/clang/include/clang/Basic/CodeGenOptions.h
+++ b/clang/include/clang/Basic/CodeGenOptions.h
@@ -399,6 +399,10 @@ class CodeGenOptions : public CodeGenOptionsBase {
/// Set of XRay instrumentation kinds to emit.
XRayInstrSet XRayInstrumentationBundle;
+ /// Default XRay options. Will be overrided by the XRAY_OPTIONS
+ /// environment variable during run-time.
+ std::string XRayDefaultOptions;
+
std::vector DefaultFunctionAttrs;
/// List of dynamic shared object files to be loaded as pass plugins.
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index f2f9c20c9bc264..c5ae8ec8fc528c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2882,6 +2882,12 @@ defm xray_instrument : BoolFOption<"xray-instrument",
"Generate XRay instrumentation sleds on function entry and exit">,
NegFlag>;
+def fxray_default_options_EQ :
+ Joined<["-"], "fxray-default-options=">,
+ Group, Visibility<[ClangOption, CC1Option]>,
+ HelpText<"Default XRay options. Can be overwritten by XRAY_OPTIONS
environment variable during run-time.">,
+ MarshallingInfoString>;
+
def fxray_instruction_threshold_EQ :
Joined<["-"], "fxray-instruction-threshold=">,
Group, Visibility<[ClangOption, CC1Option]>,
diff --git a/clang/lib/CodeGen/BackendUtil.cpp
b/clang/lib/CodeGen/BackendUtil.cpp
index bf9b04f02e9f44..1ad204a6b29a77 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -77,6 +77,7 @@
#include "llvm/Transforms/Instrumentation/SanitizerBinaryMetadata.h"
#include "llvm/Transforms/Instrumentation/SanitizerCoverage.h"
#include "llvm/Transforms/Instrumentation/ThreadSanitizer.h"
+#include "llvm/Transforms/Instrumentation/XRayPreparation.h"
#include "llvm/Transforms/ObjCARC.h"
#include "llvm/Transforms/Scalar/EarlyCSE.h"
#include "llvm/Transforms/S
[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)
https://github.com/mshockwave approved this pull request. LGTM. I don't have any strong opinion on the CPU name https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/2] [XRay][RISCV] RISCV support for XRay
Add RISC-V support for XRay. The RV64 implementation has been tested in
both QEMU and in our production environment.
Currently this requires D and C extensions, but since both RV64GC and
RVA22/RVA23 are becoming mainstream, I don't think this requirement will
be a big problem.
Based on Ashwin Poduval's previous work:
https://reviews.llvm.org/D117929
Co-authored-by: Ashwin Poduval
---
clang/lib/Driver/XRayArgs.cpp | 2 +
.../cmake/Modules/AllSupportedArchDefs.cmake | 2 +-
compiler-rt/lib/xray/CMakeLists.txt | 12 +
compiler-rt/lib/xray/xray_interface.cpp | 4 +
compiler-rt/lib/xray/xray_riscv.cpp | 296 ++
.../lib/xray/xray_trampoline_riscv32.S| 83 +
.../lib/xray/xray_trampoline_riscv64.S| 83 +
.../lib/xray/xray_trampoline_riscv_common.S | 97 ++
compiler-rt/lib/xray/xray_tsc.h | 2 +-
llvm/lib/CodeGen/XRayInstrumentation.cpp | 7 +-
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 82 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 3 +
llvm/lib/XRay/InstrumentationMap.cpp | 3 +-
.../RISCV/xray-attribute-instrumentation.ll | 24 ++
14 files changed, 695 insertions(+), 5 deletions(-)
create mode 100644 compiler-rt/lib/xray/xray_riscv.cpp
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv32.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv64.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv_common.S
create mode 100644 llvm/test/CodeGen/RISCV/xray-attribute-instrumentation.ll
diff --git a/clang/lib/Driver/XRayArgs.cpp b/clang/lib/Driver/XRayArgs.cpp
index de5c38ebc3abbd..f8c213334a2b40 100644
--- a/clang/lib/Driver/XRayArgs.cpp
+++ b/clang/lib/Driver/XRayArgs.cpp
@@ -51,6 +51,8 @@ XRayArgs::XRayArgs(const ToolChain &TC, const ArgList &Args) {
case llvm::Triple::mips64:
case llvm::Triple::mips64el:
case llvm::Triple::systemz:
+case llvm::Triple::riscv32:
+case llvm::Triple::riscv64:
break;
default:
D.Diag(diag::err_drv_unsupported_opt_for_target)
diff --git a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
index b29ae179c2b4f4..5a1e8db61023b0 100644
--- a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+++ b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
@@ -102,7 +102,7 @@ if(APPLE)
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM64})
else()
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64}
- powerpc64le ${HEXAGON} ${LOONGARCH64})
+ powerpc64le ${HEXAGON} ${LOONGARCH64} ${RISCV32} ${RISCV64})
endif()
set(ALL_XRAY_DSO_SUPPORTED_ARCH ${X86_64} ${ARM64})
set(ALL_SHADOWCALLSTACK_SUPPORTED_ARCH ${ARM64})
diff --git a/compiler-rt/lib/xray/CMakeLists.txt
b/compiler-rt/lib/xray/CMakeLists.txt
index 7e3f1a0aa616e5..e7f01a2f4f1640 100644
--- a/compiler-rt/lib/xray/CMakeLists.txt
+++ b/compiler-rt/lib/xray/CMakeLists.txt
@@ -96,6 +96,16 @@ set(hexagon_SOURCES
xray_trampoline_hexagon.S
)
+set(riscv32_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv32.S
+ )
+
+set(riscv64_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv64.S
+ )
+
set(XRAY_SOURCE_ARCHS
arm
armhf
@@ -156,6 +166,8 @@ set(XRAY_ALL_SOURCE_FILES
${mips64_SOURCES}
${mips64el_SOURCES}
${powerpc64le_SOURCES}
+ ${riscv32_SOURCES}
+ ${riscv64_SOURCES}
${XRAY_IMPL_HEADERS}
)
list(REMOVE_DUPLICATES XRAY_ALL_SOURCE_FILES)
diff --git a/compiler-rt/lib/xray/xray_interface.cpp
b/compiler-rt/lib/xray/xray_interface.cpp
index b6f0e6762f1681..e66736d9a344e1 100644
--- a/compiler-rt/lib/xray/xray_interface.cpp
+++ b/compiler-rt/lib/xray/xray_interface.cpp
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static const int16_t cSledLength = 60;
#else
#error "Unsupported CPU Architecture"
#endif /* CPU architecture */
diff --git a/compiler-rt/lib/xray/xray_riscv.cpp
b/compiler-rt/lib/xray/xray_riscv.cpp
new file mode 100644
index 00..89ce9305ef3dbe
--- /dev/null
+++ b/compiler-rt/lib/xray/xray_riscv.cpp
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -453,11 +475,71 @@ bool
RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SetupMachineFunction(MF);
emitFunctionBody();
+ // Emit the XRay table
+ emitXRayTable();
+
if (EmittedOptionArch)
RTS.emitDirectiveOptionPop();
return false;
}
+void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr *MI) {
+ emitSled(MI, SledKind::FUNCTION_ENTER);
+}
+
+void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr *MI) {
+ emitSled(MI, SledKind::FUNCTION_EXIT);
+}
+
+void RISCVAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr *MI) {
+ emitSled(MI, SledKind::TAIL_CALL);
+}
+
+void RISCVAsmPrinter::emitSled(const MachineInstr *MI, SledKind Kind) {
+ // We want to emit the jump instruction and the nops constituting the sled.
+ // The format is as follows:
+ // .Lxray_sled_N
+ // ALIGN
+ // J .tmpN
+ // 29 or 37 C.NOP instructions
+ // .tmpN
+
+ // The following variable holds the count of the number of NOPs to be patched
+ // in for XRay instrumentation during compilation.
+ // Note that RV64 and RV32 each has a sled of 76 and 60 bytes, respectively.
+ // Assuming we're using JAL to jump to .tmpN, then we only need
+ // (76 - 4)/2 = 36 NOPs for RV64 and (60 - 4)/2 = 28 for RV32. However, there
+ // is a chance that we'll use C.JAL instead, so an additional NOP is needed.
+ const uint8_t NoopsInSledCount =
mshockwave wrote:
Done.
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
+ PO_NOP = 0x0013, // nop - pseduo-instruction, same as addi x0, x0, 0
mshockwave wrote:
Fixed.
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
+ PO_NOP = 0x0013, // nop - pseduo-instruction, same as addi x0, x0, 0
+};
+
+enum RegNum : uint32_t {
+ RN_R0 = 0x0,
+ RN_RA = 0x1,
+ RN_SP = 0x2,
+ RN_T0 = 0x5,
+ RN_T1 = 0x6,
+ RN_T2 = 0x7,
+ RN_A0 = 0xa,
+};
+
+static inline uint32_t encodeRTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Rd) {
+ return Rs2 << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeITypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rd, uint32_t Imm) {
+ return Imm << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeSTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Imm) {
+ uint32_t imm_msbs = (Imm & 0xfe0) << 25;
+ uint32_t imm_lsbs = (Imm & 0x01f) << 7;
+ return imm_msbs | Rs2 << 20 | Rs1 << 15 | imm_lsbs | Opcode;
+}
+
+static inline uint32_t encodeUTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ return Imm << 12 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeJTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ uint32_t imm_msb = (Imm & 0x8) << 31;
+ uint32_t imm_lsbs = (Imm & 0x003ff) << 21;
+ uint32_t imm_11 = (Imm & 0x00400) << 20;
+ uint32_t imm_1912 = (Imm & 0x7f800) << 12;
+ return imm_msb | imm_lsbs | imm_11 | imm_1912 | Rd << 7 | Opcode;
+}
+
+#if SANITIZER_RISCV64
+static uint32_t hi20(uint64_t val) { return (val + 0x800) >> 12; }
+static uint32_t lo12(uint64_t val) { return val & 0xfff; }
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
+static uint32_t lo12(uint32_t val) { return val & 0xfff; }
+#endif
+
+static inline bool patchSled(const bool Enable, const uint32_t FuncId,
+ const XRaySledEntry &Sled,
+ void (*TracingHook)()) XRAY_NEVER_INSTRUMENT {
+ // When |Enable| == true,
+ // We replace the following compile-time stub (sled):
+ //
+ // xray_sled_n:
+ // J .tmpN
+ // 29 or 37 C.NOPs (58 or 74 bytes)
+ // .tmpN
+ //
+ // With one of the following runtime patches:
+ //
+ // xray_sled_n (32-bit):
+ //addi sp, sp, -16;create stack frame
+ //sw ra, 12(sp) ;save return address
+ //sw t2, 8(sp);save register t2
+ //sw t1, 4(sp);save register t1
+ //sw a0, 0(sp);save register a0
+ //lui t1, %hi(__xray_FunctionEntry/Exit)
+ //addi t1, t1, %lo(__xray_FunctionEntry/Exit)
+ //lui a0, %hi(function_id)
+ //addi a0, a0, %lo(function_id) ;pass function id
+ //jalr t1 ;call Tracing hook
+ //lw a0, 0(sp);restore register a0
+ //lw t1, 4(sp);restore register t1
+ //lw t2, 8(sp);restore register t2
+ //lw ra, 12(sp) ;restore return address
+ //addi sp, sp, 16 ;delete stack frame
+ //
+ // xray_sled_n (64-bit):
+ //addi sp, sp, -32;create stack frame
+
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
+ PO_NOP = 0x0013, // nop - pseduo-instruction, same as addi x0, x0, 0
+};
+
+enum RegNum : uint32_t {
+ RN_R0 = 0x0,
+ RN_RA = 0x1,
+ RN_SP = 0x2,
+ RN_T0 = 0x5,
+ RN_T1 = 0x6,
+ RN_T2 = 0x7,
+ RN_A0 = 0xa,
+};
+
+static inline uint32_t encodeRTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Rd) {
+ return Rs2 << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeITypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rd, uint32_t Imm) {
+ return Imm << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeSTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Imm) {
+ uint32_t imm_msbs = (Imm & 0xfe0) << 25;
mshockwave wrote:
I capitalized them in order to be more consistent with other places in RISCV
XRay.
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// +// +// This file is a part of XRay, a dynamic runtime instrumentation system. +// +// Implementation of riscv-specific routines (32- and 64-bit). mshockwave wrote: Fixed. https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
+ PO_NOP = 0x0013, // nop - pseduo-instruction, same as addi x0, x0, 0
+};
+
+enum RegNum : uint32_t {
+ RN_R0 = 0x0,
+ RN_RA = 0x1,
+ RN_SP = 0x2,
+ RN_T0 = 0x5,
+ RN_T1 = 0x6,
+ RN_T2 = 0x7,
+ RN_A0 = 0xa,
+};
+
+static inline uint32_t encodeRTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Rd) {
+ return Rs2 << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeITypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rd, uint32_t Imm) {
+ return Imm << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeSTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Imm) {
+ uint32_t imm_msbs = (Imm & 0xfe0) << 25;
+ uint32_t imm_lsbs = (Imm & 0x01f) << 7;
+ return imm_msbs | Rs2 << 20 | Rs1 << 15 | imm_lsbs | Opcode;
+}
+
+static inline uint32_t encodeUTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ return Imm << 12 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeJTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ uint32_t imm_msb = (Imm & 0x8) << 31;
+ uint32_t imm_lsbs = (Imm & 0x003ff) << 21;
+ uint32_t imm_11 = (Imm & 0x00400) << 20;
+ uint32_t imm_1912 = (Imm & 0x7f800) << 12;
+ return imm_msb | imm_lsbs | imm_11 | imm_1912 | Rd << 7 | Opcode;
+}
+
+#if SANITIZER_RISCV64
+static uint32_t hi20(uint64_t val) { return (val + 0x800) >> 12; }
+static uint32_t lo12(uint64_t val) { return val & 0xfff; }
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
+static uint32_t lo12(uint32_t val) { return val & 0xfff; }
+#endif
+
+static inline bool patchSled(const bool Enable, const uint32_t FuncId,
+ const XRaySledEntry &Sled,
+ void (*TracingHook)()) XRAY_NEVER_INSTRUMENT {
+ // When |Enable| == true,
+ // We replace the following compile-time stub (sled):
+ //
+ // xray_sled_n:
+ // J .tmpN
+ // 29 or 37 C.NOPs (58 or 74 bytes)
+ // .tmpN
+ //
+ // With one of the following runtime patches:
+ //
+ // xray_sled_n (32-bit):
+ //addi sp, sp, -16;create stack frame
+ //sw ra, 12(sp) ;save return address
+ //sw t2, 8(sp);save register t2
+ //sw t1, 4(sp);save register t1
+ //sw a0, 0(sp);save register a0
+ //lui t1, %hi(__xray_FunctionEntry/Exit)
+ //addi t1, t1, %lo(__xray_FunctionEntry/Exit)
+ //lui a0, %hi(function_id)
+ //addi a0, a0, %lo(function_id) ;pass function id
+ //jalr t1 ;call Tracing hook
mshockwave wrote:
Done. This shrinks the size of sled by 8 bytes.
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,97 @@ +//===-- xray_trampoline_riscv_common.s --*- ASM -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// +// +// This file is a part of XRay, a dynamic runtime instrumentation system. +// +// This implements the trampolines code shared between riscv32 and riscv64. +// +//===--===// + +#include "../builtins/assembly.h" +#include "../sanitizer_common/sanitizer_asm.h" + + .text + .p2align 2 + .global ASM_SYMBOL(__xray_FunctionEntry) + ASM_TYPE_FUNCTION(__xray_FunctionEntry) +ASM_SYMBOL(__xray_FunctionEntry): + CFI_STARTPROC +SAVE_ARG_REGISTERS + + // Load the handler function pointer into a2 + la a2, ASM_SYMBOL(_ZN6__xray19XRayPatchedFunctionE) + ld a2, 0(a2) mshockwave wrote: Oops, it's fixed now. https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,83 @@ +//===-- xray_trampoline_riscv64.s --*- ASM -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// +// +// This file is a part of XRay, a dynamic runtime instrumentation system. +// +// This implements the riscv64-specific assembler for the trampolines. +// +//===--===// + +.macro SAVE_ARG_REGISTERS + // Push return registers to stack + addisp, sp, -136 mshockwave wrote: Fixed. https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
+ PO_NOP = 0x0013, // nop - pseduo-instruction, same as addi x0, x0, 0
+};
+
+enum RegNum : uint32_t {
+ RN_R0 = 0x0,
+ RN_RA = 0x1,
+ RN_SP = 0x2,
+ RN_T0 = 0x5,
+ RN_T1 = 0x6,
+ RN_T2 = 0x7,
+ RN_A0 = 0xa,
+};
+
+static inline uint32_t encodeRTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Rd) {
+ return Rs2 << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeITypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rd, uint32_t Imm) {
+ return Imm << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeSTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Imm) {
+ uint32_t imm_msbs = (Imm & 0xfe0) << 25;
+ uint32_t imm_lsbs = (Imm & 0x01f) << 7;
+ return imm_msbs | Rs2 << 20 | Rs1 << 15 | imm_lsbs | Opcode;
+}
+
+static inline uint32_t encodeUTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ return Imm << 12 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeJTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ uint32_t imm_msb = (Imm & 0x8) << 31;
+ uint32_t imm_lsbs = (Imm & 0x003ff) << 21;
+ uint32_t imm_11 = (Imm & 0x00400) << 20;
+ uint32_t imm_1912 = (Imm & 0x7f800) << 12;
+ return imm_msb | imm_lsbs | imm_11 | imm_1912 | Rd << 7 | Opcode;
+}
+
+#if SANITIZER_RISCV64
+static uint32_t hi20(uint64_t val) { return (val + 0x800) >> 12; }
+static uint32_t lo12(uint64_t val) { return val & 0xfff; }
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
+static uint32_t lo12(uint32_t val) { return val & 0xfff; }
+#endif
+
+static inline bool patchSled(const bool Enable, const uint32_t FuncId,
+ const XRaySledEntry &Sled,
+ void (*TracingHook)()) XRAY_NEVER_INSTRUMENT {
+ // When |Enable| == true,
+ // We replace the following compile-time stub (sled):
+ //
+ // xray_sled_n:
+ // J .tmpN
+ // 29 or 37 C.NOPs (58 or 74 bytes)
+ // .tmpN
+ //
+ // With one of the following runtime patches:
+ //
+ // xray_sled_n (32-bit):
+ //addi sp, sp, -16;create stack frame
+ //sw ra, 12(sp) ;save return address
+ //sw t2, 8(sp);save register t2
+ //sw t1, 4(sp);save register t1
+ //sw a0, 0(sp);save register a0
+ //lui t1, %hi(__xray_FunctionEntry/Exit)
+ //addi t1, t1, %lo(__xray_FunctionEntry/Exit)
+ //lui a0, %hi(function_id)
+ //addi a0, a0, %lo(function_id) ;pass function id
+ //jalr t1 ;call Tracing hook
+ //lw a0, 0(sp);restore register a0
+ //lw t1, 4(sp);restore register t1
+ //lw t2, 8(sp);restore register t2
+ //lw ra, 12(sp) ;restore return address
+ //addi sp, sp, 16 ;delete stack frame
+ //
+ // xray_sled_n (64-bit):
+ //addi sp, sp, -32;create stack frame
+
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
+ PO_NOP = 0x0013, // nop - pseduo-instruction, same as addi x0, x0, 0
+};
+
+enum RegNum : uint32_t {
+ RN_R0 = 0x0,
mshockwave wrote:
Fixed.
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
mshockwave wrote:
Fixed
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
mshockwave wrote:
Fixed.
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
mshockwave wrote:
Fixed.
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64; static const int16_t cSledLength = 8; #elif defined(__hexagon__) static const int16_t cSledLength = 20; +#elif SANITIZER_RISCV64 +static const int16_t cSledLength = 76; +#elif defined(__riscv) && (__riscv_xlen == 32) mshockwave wrote: I don't quite follow. What was your suggestion? Using only __riscv_xlen? https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
mshockwave wrote:
Fixed
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,83 @@ +//===-- xray_trampoline_riscv32.s --*- ASM -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// +// +// This file is a part of XRay, a dynamic runtime instrumentation system. +// +// This implements the riscv32-specific assembler for the trampolines. +// +//===--===// + +.macro SAVE_ARG_REGISTERS + // Push argument registers to stack + addisp, sp, -100 mshockwave wrote: Fixed. https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
+ PO_NOP = 0x0013, // nop - pseduo-instruction, same as addi x0, x0, 0
+};
+
+enum RegNum : uint32_t {
+ RN_R0 = 0x0,
+ RN_RA = 0x1,
+ RN_SP = 0x2,
+ RN_T0 = 0x5,
+ RN_T1 = 0x6,
+ RN_T2 = 0x7,
+ RN_A0 = 0xa,
+};
+
+static inline uint32_t encodeRTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Rd) {
+ return Rs2 << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeITypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rd, uint32_t Imm) {
+ return Imm << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeSTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Imm) {
+ uint32_t imm_msbs = (Imm & 0xfe0) << 25;
+ uint32_t imm_lsbs = (Imm & 0x01f) << 7;
+ return imm_msbs | Rs2 << 20 | Rs1 << 15 | imm_lsbs | Opcode;
+}
+
+static inline uint32_t encodeUTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ return Imm << 12 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeJTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ uint32_t imm_msb = (Imm & 0x8) << 31;
+ uint32_t imm_lsbs = (Imm & 0x003ff) << 21;
+ uint32_t imm_11 = (Imm & 0x00400) << 20;
+ uint32_t imm_1912 = (Imm & 0x7f800) << 12;
+ return imm_msb | imm_lsbs | imm_11 | imm_1912 | Rd << 7 | Opcode;
+}
+
+#if SANITIZER_RISCV64
+static uint32_t hi20(uint64_t val) { return (val + 0x800) >> 12; }
+static uint32_t lo12(uint64_t val) { return val & 0xfff; }
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
+static uint32_t lo12(uint32_t val) { return val & 0xfff; }
+#endif
+
+static inline bool patchSled(const bool Enable, const uint32_t FuncId,
+ const XRaySledEntry &Sled,
+ void (*TracingHook)()) XRAY_NEVER_INSTRUMENT {
+ // When |Enable| == true,
+ // We replace the following compile-time stub (sled):
+ //
+ // xray_sled_n:
+ // J .tmpN
+ // 29 or 37 C.NOPs (58 or 74 bytes)
+ // .tmpN
+ //
+ // With one of the following runtime patches:
+ //
+ // xray_sled_n (32-bit):
+ //addi sp, sp, -16;create stack frame
+ //sw ra, 12(sp) ;save return address
+ //sw t2, 8(sp);save register t2
+ //sw t1, 4(sp);save register t1
+ //sw a0, 0(sp);save register a0
+ //lui t1, %hi(__xray_FunctionEntry/Exit)
+ //addi t1, t1, %lo(__xray_FunctionEntry/Exit)
+ //lui a0, %hi(function_id)
+ //addi a0, a0, %lo(function_id) ;pass function id
+ //jalr t1 ;call Tracing hook
+ //lw a0, 0(sp);restore register a0
+ //lw t1, 4(sp);restore register t1
+ //lw t2, 8(sp);restore register t2
+ //lw ra, 12(sp) ;restore return address
+ //addi sp, sp, 16 ;delete stack frame
+ //
+ // xray_sled_n (64-bit):
+ //addi sp, sp, -32;create stack frame
+
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
+ PO_NOP = 0x0013, // nop - pseduo-instruction, same as addi x0, x0, 0
+};
+
+enum RegNum : uint32_t {
+ RN_R0 = 0x0,
+ RN_RA = 0x1,
+ RN_SP = 0x2,
+ RN_T0 = 0x5,
+ RN_T1 = 0x6,
+ RN_T2 = 0x7,
+ RN_A0 = 0xa,
+};
+
+static inline uint32_t encodeRTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Rd) {
+ return Rs2 << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeITypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rd, uint32_t Imm) {
+ return Imm << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeSTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Imm) {
+ uint32_t imm_msbs = (Imm & 0xfe0) << 25;
+ uint32_t imm_lsbs = (Imm & 0x01f) << 7;
+ return imm_msbs | Rs2 << 20 | Rs1 << 15 | imm_lsbs | Opcode;
+}
+
+static inline uint32_t encodeUTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ return Imm << 12 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeJTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ uint32_t imm_msb = (Imm & 0x8) << 31;
+ uint32_t imm_lsbs = (Imm & 0x003ff) << 21;
+ uint32_t imm_11 = (Imm & 0x00400) << 20;
+ uint32_t imm_1912 = (Imm & 0x7f800) << 12;
+ return imm_msb | imm_lsbs | imm_11 | imm_1912 | Rd << 7 | Opcode;
+}
+
+#if SANITIZER_RISCV64
+static uint32_t hi20(uint64_t val) { return (val + 0x800) >> 12; }
mshockwave wrote:
Fixed.
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of riscv-specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rt, base(offset)
+ PO_SD = 0x3023, // sd rt, base(offset)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_ORI = 0x6013, // ori rd, rs1, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs, shamt
+ PO_SRLI = 0x5013, // srli rd, rs, shamt
+ PO_JALR = 0x0067, // jalr rs
+ PO_LW = 0x2003, // lw rd, base(offset)
+ PO_LD = 0x3003, // ld rd, base(offset)
+ PO_J = 0x006f,// jal #n_bytes
+ PO_NOP = 0x0013, // nop - pseduo-instruction, same as addi x0, x0, 0
+};
+
+enum RegNum : uint32_t {
+ RN_R0 = 0x0,
+ RN_RA = 0x1,
+ RN_SP = 0x2,
+ RN_T0 = 0x5,
+ RN_T1 = 0x6,
+ RN_T2 = 0x7,
+ RN_A0 = 0xa,
mshockwave wrote:
Fixed.
https://github.com/llvm/llvm-project/pull/117368
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/5] [XRay][RISCV] RISCV support for XRay
Add RISC-V support for XRay. The RV64 implementation has been tested in
both QEMU and in our production environment.
Currently this requires D and C extensions, but since both RV64GC and
RVA22/RVA23 are becoming mainstream, I don't think this requirement will
be a big problem.
Based on Ashwin Poduval's previous work:
https://reviews.llvm.org/D117929
Co-authored-by: Ashwin Poduval
---
clang/lib/Driver/XRayArgs.cpp | 2 +
.../cmake/Modules/AllSupportedArchDefs.cmake | 2 +-
compiler-rt/lib/xray/CMakeLists.txt | 12 +
compiler-rt/lib/xray/xray_interface.cpp | 4 +
compiler-rt/lib/xray/xray_riscv.cpp | 296 ++
.../lib/xray/xray_trampoline_riscv32.S| 83 +
.../lib/xray/xray_trampoline_riscv64.S| 83 +
.../lib/xray/xray_trampoline_riscv_common.S | 97 ++
compiler-rt/lib/xray/xray_tsc.h | 2 +-
llvm/lib/CodeGen/XRayInstrumentation.cpp | 7 +-
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 82 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 3 +
llvm/lib/XRay/InstrumentationMap.cpp | 3 +-
.../RISCV/xray-attribute-instrumentation.ll | 24 ++
14 files changed, 695 insertions(+), 5 deletions(-)
create mode 100644 compiler-rt/lib/xray/xray_riscv.cpp
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv32.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv64.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv_common.S
create mode 100644 llvm/test/CodeGen/RISCV/xray-attribute-instrumentation.ll
diff --git a/clang/lib/Driver/XRayArgs.cpp b/clang/lib/Driver/XRayArgs.cpp
index de5c38ebc3abbd..f8c213334a2b40 100644
--- a/clang/lib/Driver/XRayArgs.cpp
+++ b/clang/lib/Driver/XRayArgs.cpp
@@ -51,6 +51,8 @@ XRayArgs::XRayArgs(const ToolChain &TC, const ArgList &Args) {
case llvm::Triple::mips64:
case llvm::Triple::mips64el:
case llvm::Triple::systemz:
+case llvm::Triple::riscv32:
+case llvm::Triple::riscv64:
break;
default:
D.Diag(diag::err_drv_unsupported_opt_for_target)
diff --git a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
index b29ae179c2b4f4..5a1e8db61023b0 100644
--- a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+++ b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
@@ -102,7 +102,7 @@ if(APPLE)
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM64})
else()
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64}
- powerpc64le ${HEXAGON} ${LOONGARCH64})
+ powerpc64le ${HEXAGON} ${LOONGARCH64} ${RISCV32} ${RISCV64})
endif()
set(ALL_XRAY_DSO_SUPPORTED_ARCH ${X86_64} ${ARM64})
set(ALL_SHADOWCALLSTACK_SUPPORTED_ARCH ${ARM64})
diff --git a/compiler-rt/lib/xray/CMakeLists.txt
b/compiler-rt/lib/xray/CMakeLists.txt
index 7e3f1a0aa616e5..e7f01a2f4f1640 100644
--- a/compiler-rt/lib/xray/CMakeLists.txt
+++ b/compiler-rt/lib/xray/CMakeLists.txt
@@ -96,6 +96,16 @@ set(hexagon_SOURCES
xray_trampoline_hexagon.S
)
+set(riscv32_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv32.S
+ )
+
+set(riscv64_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv64.S
+ )
+
set(XRAY_SOURCE_ARCHS
arm
armhf
@@ -156,6 +166,8 @@ set(XRAY_ALL_SOURCE_FILES
${mips64_SOURCES}
${mips64el_SOURCES}
${powerpc64le_SOURCES}
+ ${riscv32_SOURCES}
+ ${riscv64_SOURCES}
${XRAY_IMPL_HEADERS}
)
list(REMOVE_DUPLICATES XRAY_ALL_SOURCE_FILES)
diff --git a/compiler-rt/lib/xray/xray_interface.cpp
b/compiler-rt/lib/xray/xray_interface.cpp
index b6f0e6762f1681..e66736d9a344e1 100644
--- a/compiler-rt/lib/xray/xray_interface.cpp
+++ b/compiler-rt/lib/xray/xray_interface.cpp
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static const int16_t cSledLength = 60;
#else
#error "Unsupported CPU Architecture"
#endif /* CPU architecture */
diff --git a/compiler-rt/lib/xray/xray_riscv.cpp
b/compiler-rt/lib/xray/xray_riscv.cpp
new file mode 100644
index 00..89ce9305ef3dbe
--- /dev/null
+++ b/compiler-rt/lib/xray/xray_riscv.cpp
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,87 @@ +//===-- xray_trampoline_riscv32.s --*- ASM -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// +// +// This file is a part of XRay, a dynamic runtime instrumentation system. +// +// This implements the riscv32-specific assembler for the trampolines. +// +//===--===// + +.macro SAVE_ARG_REGISTERS + // Push argument registers to stack + addisp, sp, -112 + .cfi_def_cfa_offset 112 + sw ra, 108(sp) + .cfi_offset ra, -4 + sw a7, 104(sp) + sw a6, 100(sp) + sw a5, 96(sp) + sw a4, 92(sp) + sw a3, 88(sp) + sw a2, 84(sp) + sw a1, 80(sp) + sw a0, 76(sp) + fsd fa7, 64(sp) + fsd fa6, 56(sp) + fsd fa5, 48(sp) + fsd fa4, 40(sp) + fsd fa3, 32(sp) + fsd fa2, 24(sp) + fsd fa1, 16(sp) + fsd fa0, 8(sp) mshockwave wrote: It's true that only some of the XRay targets implement CFI (e.g. x86_64), but I'm incline to have a correct frame address since showing the trampoline name in the stack trace is pretty useful sometimes. I have kept the CFI directives regarding CFA and removed all the other directives. https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/4] [XRay][RISCV] RISCV support for XRay
Add RISC-V support for XRay. The RV64 implementation has been tested in
both QEMU and in our production environment.
Currently this requires D and C extensions, but since both RV64GC and
RVA22/RVA23 are becoming mainstream, I don't think this requirement will
be a big problem.
Based on Ashwin Poduval's previous work:
https://reviews.llvm.org/D117929
Co-authored-by: Ashwin Poduval
---
clang/lib/Driver/XRayArgs.cpp | 2 +
.../cmake/Modules/AllSupportedArchDefs.cmake | 2 +-
compiler-rt/lib/xray/CMakeLists.txt | 12 +
compiler-rt/lib/xray/xray_interface.cpp | 4 +
compiler-rt/lib/xray/xray_riscv.cpp | 296 ++
.../lib/xray/xray_trampoline_riscv32.S| 83 +
.../lib/xray/xray_trampoline_riscv64.S| 83 +
.../lib/xray/xray_trampoline_riscv_common.S | 97 ++
compiler-rt/lib/xray/xray_tsc.h | 2 +-
llvm/lib/CodeGen/XRayInstrumentation.cpp | 7 +-
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 82 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 3 +
llvm/lib/XRay/InstrumentationMap.cpp | 3 +-
.../RISCV/xray-attribute-instrumentation.ll | 24 ++
14 files changed, 695 insertions(+), 5 deletions(-)
create mode 100644 compiler-rt/lib/xray/xray_riscv.cpp
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv32.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv64.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv_common.S
create mode 100644 llvm/test/CodeGen/RISCV/xray-attribute-instrumentation.ll
diff --git a/clang/lib/Driver/XRayArgs.cpp b/clang/lib/Driver/XRayArgs.cpp
index de5c38ebc3abbd..f8c213334a2b40 100644
--- a/clang/lib/Driver/XRayArgs.cpp
+++ b/clang/lib/Driver/XRayArgs.cpp
@@ -51,6 +51,8 @@ XRayArgs::XRayArgs(const ToolChain &TC, const ArgList &Args) {
case llvm::Triple::mips64:
case llvm::Triple::mips64el:
case llvm::Triple::systemz:
+case llvm::Triple::riscv32:
+case llvm::Triple::riscv64:
break;
default:
D.Diag(diag::err_drv_unsupported_opt_for_target)
diff --git a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
index b29ae179c2b4f4..5a1e8db61023b0 100644
--- a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+++ b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
@@ -102,7 +102,7 @@ if(APPLE)
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM64})
else()
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64}
- powerpc64le ${HEXAGON} ${LOONGARCH64})
+ powerpc64le ${HEXAGON} ${LOONGARCH64} ${RISCV32} ${RISCV64})
endif()
set(ALL_XRAY_DSO_SUPPORTED_ARCH ${X86_64} ${ARM64})
set(ALL_SHADOWCALLSTACK_SUPPORTED_ARCH ${ARM64})
diff --git a/compiler-rt/lib/xray/CMakeLists.txt
b/compiler-rt/lib/xray/CMakeLists.txt
index 7e3f1a0aa616e5..e7f01a2f4f1640 100644
--- a/compiler-rt/lib/xray/CMakeLists.txt
+++ b/compiler-rt/lib/xray/CMakeLists.txt
@@ -96,6 +96,16 @@ set(hexagon_SOURCES
xray_trampoline_hexagon.S
)
+set(riscv32_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv32.S
+ )
+
+set(riscv64_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv64.S
+ )
+
set(XRAY_SOURCE_ARCHS
arm
armhf
@@ -156,6 +166,8 @@ set(XRAY_ALL_SOURCE_FILES
${mips64_SOURCES}
${mips64el_SOURCES}
${powerpc64le_SOURCES}
+ ${riscv32_SOURCES}
+ ${riscv64_SOURCES}
${XRAY_IMPL_HEADERS}
)
list(REMOVE_DUPLICATES XRAY_ALL_SOURCE_FILES)
diff --git a/compiler-rt/lib/xray/xray_interface.cpp
b/compiler-rt/lib/xray/xray_interface.cpp
index b6f0e6762f1681..e66736d9a344e1 100644
--- a/compiler-rt/lib/xray/xray_interface.cpp
+++ b/compiler-rt/lib/xray/xray_interface.cpp
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static const int16_t cSledLength = 60;
#else
#error "Unsupported CPU Architecture"
#endif /* CPU architecture */
diff --git a/compiler-rt/lib/xray/xray_riscv.cpp
b/compiler-rt/lib/xray/xray_riscv.cpp
new file mode 100644
index 00..89ce9305ef3dbe
--- /dev/null
+++ b/compiler-rt/lib/xray/xray_riscv.cpp
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -453,11 +475,71 @@ bool
RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SetupMachineFunction(MF);
emitFunctionBody();
+ // Emit the XRay table
+ emitXRayTable();
+
if (EmittedOptionArch)
RTS.emitDirectiveOptionPop();
return false;
}
+void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr *MI) {
+ emitSled(MI, SledKind::FUNCTION_ENTER);
+}
+
+void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr *MI) {
+ emitSled(MI, SledKind::FUNCTION_EXIT);
+}
+
+void RISCVAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr *MI) {
+ emitSled(MI, SledKind::TAIL_CALL);
+}
+
+void RISCVAsmPrinter::emitSled(const MachineInstr *MI, SledKind Kind) {
+ // We want to emit the jump instruction and the nops constituting the sled.
+ // The format is as follows:
+ // .Lxray_sled_N
+ // ALIGN
+ // J .tmpN
+ // 25 or 33 C.NOP instructions
+ // .tmpN
+
+ // The following variable holds the count of the number of NOPs to be patched
+ // in for XRay instrumentation during compilation.
+ // Note that RV64 and RV32 each has a sled of 68 and 52 bytes, respectively.
+ // Assuming we're using JAL to jump to .tmpN, then we only need
+ // (68 - 4)/2 = 32 NOPs for RV64 and (52 - 4)/2 = 24 for RV32. However, there
+ // is a chance that we'll use C.JAL instead, so an additional NOP is needed.
+ const uint8_t NoopsInSledCount =
+ MI->getParent()->getParent()->getSubtarget().is64Bit()
+ ? 33
+ : 25;
+
+ OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo());
+ auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
+ OutStreamer->emitLabel(CurSled);
+ auto Target = OutContext.createTempSymbol();
+
+ const MCExpr *TargetExpr = MCSymbolRefExpr::create(
+ Target, MCSymbolRefExpr::VariantKind::VK_None, OutContext);
+
+ // Emit "J bytes" instruction, which jumps over the nop sled to the actual
+ // start of function.
+ EmitToStreamer(
+ *OutStreamer,
+ MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addExpr(TargetExpr));
+
+ // Emit NOP instructions
+ for (int8_t I = 0; I < NoopsInSledCount; ++I)
mshockwave wrote:
currently C extension is required by RISC-V XRay.
https://github.com/llvm/llvm-project/pull/117368
___
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -0,0 +1,266 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of RISC-V specific routines (32- and 64-bit).
+//
+//===--===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include
+
+namespace __xray {
+
+// The machine codes for some instructions used in runtime patching.
+enum PatchOpcodes : uint32_t {
+ PO_ADDI = 0x0013, // addi rd, rs1, imm
+ PO_ADD = 0x0033, // add rd, rs1, rs2
+ PO_SW = 0x2023, // sw rs2, imm(rs1)
+ PO_SD = 0x3023, // sd rs2, imm(rs1)
+ PO_LUI = 0x0037, // lui rd, imm
+ PO_OR = 0x6033, // or rd, rs1, rs2
+ PO_SLLI = 0x1013, // slli rd, rs1, shamt
+ PO_JALR = 0x0067, // jalr rd, rs1
+ PO_LW = 0x2003, // lw rd, imm(rs1)
+ PO_LD = 0x3003, // ld rd, imm(rs1)
+ PO_J = 0x006f,// jal imm
+ PO_NOP = PO_ADDI, // addi x0, x0, 0
+};
+
+enum RegNum : uint32_t {
+ RN_X0 = 0,
+ RN_RA = 1,
+ RN_SP = 2,
+ RN_T1 = 6,
+ RN_A0 = 10,
+};
+
+static inline uint32_t encodeRTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Rd) {
+ return Rs2 << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeITypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rd, uint32_t Imm) {
+ return Imm << 20 | Rs1 << 15 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeSTypeInstruction(uint32_t Opcode, uint32_t Rs1,
+ uint32_t Rs2, uint32_t Imm) {
+ uint32_t ImmMSB = (Imm & 0xfe0) << 25;
+ uint32_t ImmLSB = (Imm & 0x01f) << 7;
+ return ImmMSB | Rs2 << 20 | Rs1 << 15 | ImmLSB | Opcode;
+}
+
+static inline uint32_t encodeUTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ return Imm << 12 | Rd << 7 | Opcode;
+}
+
+static inline uint32_t encodeJTypeInstruction(uint32_t Opcode, uint32_t Rd,
+ uint32_t Imm) {
+ uint32_t ImmMSB = (Imm & 0x10) << 31;
mshockwave wrote:
> Actually I think they're all wrong
Oops, you're right. I'll fix them shortly.
> How was that not caught it testing?
Because the only time we hit the disable case is when these sleds are being
unpatched -- something XRay doesn't do by default. The program has to manually
call `__xray_unpatch` to do the unpatching.
https://github.com/llvm/llvm-project/pull/117368
___
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[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/6] [XRay][RISCV] RISCV support for XRay
Add RISC-V support for XRay. The RV64 implementation has been tested in
both QEMU and in our production environment.
Currently this requires D and C extensions, but since both RV64GC and
RVA22/RVA23 are becoming mainstream, I don't think this requirement will
be a big problem.
Based on Ashwin Poduval's previous work:
https://reviews.llvm.org/D117929
Co-authored-by: Ashwin Poduval
---
clang/lib/Driver/XRayArgs.cpp | 2 +
.../cmake/Modules/AllSupportedArchDefs.cmake | 2 +-
compiler-rt/lib/xray/CMakeLists.txt | 12 +
compiler-rt/lib/xray/xray_interface.cpp | 4 +
compiler-rt/lib/xray/xray_riscv.cpp | 296 ++
.../lib/xray/xray_trampoline_riscv32.S| 83 +
.../lib/xray/xray_trampoline_riscv64.S| 83 +
.../lib/xray/xray_trampoline_riscv_common.S | 97 ++
compiler-rt/lib/xray/xray_tsc.h | 2 +-
llvm/lib/CodeGen/XRayInstrumentation.cpp | 7 +-
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 82 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 3 +
llvm/lib/XRay/InstrumentationMap.cpp | 3 +-
.../RISCV/xray-attribute-instrumentation.ll | 24 ++
14 files changed, 695 insertions(+), 5 deletions(-)
create mode 100644 compiler-rt/lib/xray/xray_riscv.cpp
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv32.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv64.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv_common.S
create mode 100644 llvm/test/CodeGen/RISCV/xray-attribute-instrumentation.ll
diff --git a/clang/lib/Driver/XRayArgs.cpp b/clang/lib/Driver/XRayArgs.cpp
index de5c38ebc3abbd..f8c213334a2b40 100644
--- a/clang/lib/Driver/XRayArgs.cpp
+++ b/clang/lib/Driver/XRayArgs.cpp
@@ -51,6 +51,8 @@ XRayArgs::XRayArgs(const ToolChain &TC, const ArgList &Args) {
case llvm::Triple::mips64:
case llvm::Triple::mips64el:
case llvm::Triple::systemz:
+case llvm::Triple::riscv32:
+case llvm::Triple::riscv64:
break;
default:
D.Diag(diag::err_drv_unsupported_opt_for_target)
diff --git a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
index b29ae179c2b4f4..5a1e8db61023b0 100644
--- a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+++ b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
@@ -102,7 +102,7 @@ if(APPLE)
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM64})
else()
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64}
- powerpc64le ${HEXAGON} ${LOONGARCH64})
+ powerpc64le ${HEXAGON} ${LOONGARCH64} ${RISCV32} ${RISCV64})
endif()
set(ALL_XRAY_DSO_SUPPORTED_ARCH ${X86_64} ${ARM64})
set(ALL_SHADOWCALLSTACK_SUPPORTED_ARCH ${ARM64})
diff --git a/compiler-rt/lib/xray/CMakeLists.txt
b/compiler-rt/lib/xray/CMakeLists.txt
index 7e3f1a0aa616e5..e7f01a2f4f1640 100644
--- a/compiler-rt/lib/xray/CMakeLists.txt
+++ b/compiler-rt/lib/xray/CMakeLists.txt
@@ -96,6 +96,16 @@ set(hexagon_SOURCES
xray_trampoline_hexagon.S
)
+set(riscv32_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv32.S
+ )
+
+set(riscv64_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv64.S
+ )
+
set(XRAY_SOURCE_ARCHS
arm
armhf
@@ -156,6 +166,8 @@ set(XRAY_ALL_SOURCE_FILES
${mips64_SOURCES}
${mips64el_SOURCES}
${powerpc64le_SOURCES}
+ ${riscv32_SOURCES}
+ ${riscv64_SOURCES}
${XRAY_IMPL_HEADERS}
)
list(REMOVE_DUPLICATES XRAY_ALL_SOURCE_FILES)
diff --git a/compiler-rt/lib/xray/xray_interface.cpp
b/compiler-rt/lib/xray/xray_interface.cpp
index b6f0e6762f1681..e66736d9a344e1 100644
--- a/compiler-rt/lib/xray/xray_interface.cpp
+++ b/compiler-rt/lib/xray/xray_interface.cpp
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static const int16_t cSledLength = 60;
#else
#error "Unsupported CPU Architecture"
#endif /* CPU architecture */
diff --git a/compiler-rt/lib/xray/xray_riscv.cpp
b/compiler-rt/lib/xray/xray_riscv.cpp
new file mode 100644
index 00..89ce9305ef3dbe
--- /dev/null
+++ b/compiler-rt/lib/xray/xray_riscv.cpp
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/3] [XRay][RISCV] RISCV support for XRay
Add RISC-V support for XRay. The RV64 implementation has been tested in
both QEMU and in our production environment.
Currently this requires D and C extensions, but since both RV64GC and
RVA22/RVA23 are becoming mainstream, I don't think this requirement will
be a big problem.
Based on Ashwin Poduval's previous work:
https://reviews.llvm.org/D117929
Co-authored-by: Ashwin Poduval
---
clang/lib/Driver/XRayArgs.cpp | 2 +
.../cmake/Modules/AllSupportedArchDefs.cmake | 2 +-
compiler-rt/lib/xray/CMakeLists.txt | 12 +
compiler-rt/lib/xray/xray_interface.cpp | 4 +
compiler-rt/lib/xray/xray_riscv.cpp | 296 ++
.../lib/xray/xray_trampoline_riscv32.S| 83 +
.../lib/xray/xray_trampoline_riscv64.S| 83 +
.../lib/xray/xray_trampoline_riscv_common.S | 97 ++
compiler-rt/lib/xray/xray_tsc.h | 2 +-
llvm/lib/CodeGen/XRayInstrumentation.cpp | 7 +-
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 82 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 3 +
llvm/lib/XRay/InstrumentationMap.cpp | 3 +-
.../RISCV/xray-attribute-instrumentation.ll | 24 ++
14 files changed, 695 insertions(+), 5 deletions(-)
create mode 100644 compiler-rt/lib/xray/xray_riscv.cpp
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv32.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv64.S
create mode 100644 compiler-rt/lib/xray/xray_trampoline_riscv_common.S
create mode 100644 llvm/test/CodeGen/RISCV/xray-attribute-instrumentation.ll
diff --git a/clang/lib/Driver/XRayArgs.cpp b/clang/lib/Driver/XRayArgs.cpp
index de5c38ebc3abbd..f8c213334a2b40 100644
--- a/clang/lib/Driver/XRayArgs.cpp
+++ b/clang/lib/Driver/XRayArgs.cpp
@@ -51,6 +51,8 @@ XRayArgs::XRayArgs(const ToolChain &TC, const ArgList &Args) {
case llvm::Triple::mips64:
case llvm::Triple::mips64el:
case llvm::Triple::systemz:
+case llvm::Triple::riscv32:
+case llvm::Triple::riscv64:
break;
default:
D.Diag(diag::err_drv_unsupported_opt_for_target)
diff --git a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
index b29ae179c2b4f4..5a1e8db61023b0 100644
--- a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+++ b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
@@ -102,7 +102,7 @@ if(APPLE)
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM64})
else()
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64}
- powerpc64le ${HEXAGON} ${LOONGARCH64})
+ powerpc64le ${HEXAGON} ${LOONGARCH64} ${RISCV32} ${RISCV64})
endif()
set(ALL_XRAY_DSO_SUPPORTED_ARCH ${X86_64} ${ARM64})
set(ALL_SHADOWCALLSTACK_SUPPORTED_ARCH ${ARM64})
diff --git a/compiler-rt/lib/xray/CMakeLists.txt
b/compiler-rt/lib/xray/CMakeLists.txt
index 7e3f1a0aa616e5..e7f01a2f4f1640 100644
--- a/compiler-rt/lib/xray/CMakeLists.txt
+++ b/compiler-rt/lib/xray/CMakeLists.txt
@@ -96,6 +96,16 @@ set(hexagon_SOURCES
xray_trampoline_hexagon.S
)
+set(riscv32_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv32.S
+ )
+
+set(riscv64_SOURCES
+ xray_riscv.cpp
+ xray_trampoline_riscv64.S
+ )
+
set(XRAY_SOURCE_ARCHS
arm
armhf
@@ -156,6 +166,8 @@ set(XRAY_ALL_SOURCE_FILES
${mips64_SOURCES}
${mips64el_SOURCES}
${powerpc64le_SOURCES}
+ ${riscv32_SOURCES}
+ ${riscv64_SOURCES}
${XRAY_IMPL_HEADERS}
)
list(REMOVE_DUPLICATES XRAY_ALL_SOURCE_FILES)
diff --git a/compiler-rt/lib/xray/xray_interface.cpp
b/compiler-rt/lib/xray/xray_interface.cpp
index b6f0e6762f1681..e66736d9a344e1 100644
--- a/compiler-rt/lib/xray/xray_interface.cpp
+++ b/compiler-rt/lib/xray/xray_interface.cpp
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
+static const int16_t cSledLength = 60;
#else
#error "Unsupported CPU Architecture"
#endif /* CPU architecture */
diff --git a/compiler-rt/lib/xray/xray_riscv.cpp
b/compiler-rt/lib/xray/xray_riscv.cpp
new file mode 100644
index 00..89ce9305ef3dbe
--- /dev/null
+++ b/compiler-rt/lib/xray/xray_riscv.cpp
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===
[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64; static const int16_t cSledLength = 8; #elif defined(__hexagon__) static const int16_t cSledLength = 20; +#elif SANITIZER_RISCV64 +static const int16_t cSledLength = 76; +#elif defined(__riscv) && (__riscv_xlen == 32) mshockwave wrote: > shoud we use defined(__riscv) && (__riscv_xlen == 64) I'm fine with that. It's fixed now. https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add a generic OOO CPU (PR #120712)
https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/120712 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [IR][AsmParser] Revamp how floating-point literals in LLVM IR. (PR #121838)
@@ -3829,10 +3829,40 @@ bool LLParser::parseValID(ValID &ID, PerFunctionState
*PFS, Type *ExpectedTy) {
ID.APSIntVal = Lex.getAPSIntVal();
ID.Kind = ValID::t_APSInt;
break;
- case lltok::APFloat:
+ case lltok::APFloat: {
+assert(ExpectedTy && "Need type to parse float values");
ID.APFloatVal = Lex.getAPFloatVal();
ID.Kind = ValID::t_APFloat;
break;
+ }
+ case lltok::FloatLiteral: {
+assert(ExpectedTy && "Need type to parse float values");
+if (!ExpectedTy->isFloatingPointTy())
+ return error(ID.Loc, "floating point constant invalid for type");
+ID.APFloatVal = APFloat(ExpectedTy->getFltSemantics());
+auto Except = ID.APFloatVal.convertFromString(
+Lex.getStrVal(), RoundingMode::NearestTiesToEven);
+assert(Except && "Invalid float strings should be caught by the lexer");
+// Forbid overflowing and underflowing literals, but permit inexact
+// literals. Underflow is thrown when the result is denormal, so to allow
+// denormals, only reject underflowing literals that resulted in a zero.
+if (*Except & APFloat::opOverflow)
+ return error(ID.Loc, "floating point constant overflowed type");
+if ((*Except & APFloat::opUnderflow) && ID.APFloatVal.isZero())
+ return error(ID.Loc, "floating point constant underflowed type");
+ID.Kind = ValID::t_APFloat;
+break;
+ }
+ case lltok::FloatHexLiteral: {
+assert(ExpectedTy && "Need type to parse float values");
+auto &Semantics = ExpectedTy->getFltSemantics();
mshockwave wrote:
nit: `const auto &`
https://github.com/llvm/llvm-project/pull/121838
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[clang] [llvm] [IR][AsmParser] Revamp how floating-point literals in LLVM IR. (PR #121838)
@@ -1017,11 +1018,13 @@ lltok::Kind LLLexer::LexIdentifier() {
}
// Check for [us]0x[0-9A-Fa-f]+ which are Hexadecimal constant generated by
- // the CFE to avoid forcing it to deal with 64-bit numbers.
- if ((TokStart[0] == 'u' || TokStart[0] == 's') &&
+ // the CFE to avoid forcing it to deal with 64-bit numbers. Also check for
+ // f0x[0-9A-Fa-f]+, which is the floating-point hexadecimal literal constant.
+ if ((TokStart[0] == 'u' || TokStart[0] == 's' || TokStart[0] == 'f') &&
TokStart[1] == '0' && TokStart[2] == 'x' &&
isxdigit(static_cast(TokStart[3]))) {
-int len = CurPtr-TokStart-3;
+bool IsFloatConst = TokStart[0] == 'f';
+int len = CurPtr - TokStart - 3;
mshockwave wrote:
I know it's from the old code but since we're changing it anyway could you make
it `Len`? Also, why `int` rather than `unsigned` or `size_t`
https://github.com/llvm/llvm-project/pull/121838
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