https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/78489
>From ab316ea2c76320ec2f044c43bb9f6ed82f6802c3 Mon Sep 17 00:00:00 2001
From: Min Hsu <min....@sifive.com>
Date: Wed, 17 Jan 2024 10:28:14 -0800
Subject: [PATCH 1/4] [RISCV] Add support for Smepmp 1.0
Smepmp is a supervisor extension that prevents privileged processes from
accessing unprivileged program and data.
---
llvm/lib/Support/RISCVISAInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++++++
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
5 files changed, 16 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 8c9eb1bddb3cb52..3c02492e99f1db4 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"m", {2, 0}},
{"smaia", {1, 0}},
+ {"smepmp", {1, 0}},
{"ssaia", {1, 0}},
{"svinval", {1, 0}},
{"svnapot", {1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 72780937dd88704..9cf8df05bd3ad54 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -743,6 +743,13 @@ def FeatureStdExtSmaia
"'Smaia' (Advanced Interrupt Architecture Machine "
"Level)", []>;
+def FeatureStdExtSmepmp
+ : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
+ "'Smepmp' (Smepmp prevents privileged processes from "
+ "executing or accessing unprivileged programs and"
+ "data.)",
+ []>;
+
def FeatureStdExtSsaia
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 3e55e0fb4e6861e..d0cd6ab3093b410 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV32ZIMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZVFBFMIN %s
@@ -189,6 +190,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV64ZIMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZVFBFMIN %s
@@ -285,6 +287,7 @@
; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
+; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
@@ -385,6 +388,7 @@
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
+; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index b1a03bbfd74da9d..0c258981365929c 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -291,6 +291,9 @@
.attribute arch, "rv32i_smaia1p0"
# CHECK: attribute 5, "rv32i2p1_smaia1p0"
+.attribute arch, "rv32i_smepmp1p0"
+# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
+
.attribute arch, "rv32i_ssaia1p0"
# CHECK: attribute 5, "rv32i2p1_ssaia1p0"
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp
b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 0b8bbc7c9027ec8..9b7112fa2bfeb59 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -760,6 +760,7 @@ R"(All available -march extensions for RISC-V
zhinx 1.0
zhinxmin 1.0
smaia 1.0
+ smepmp 1.0
ssaia 1.0
svinval 1.0
svnapot 1.0
>From 51914697776c2451b6665a4b5e5531d177aaab8b Mon Sep 17 00:00:00 2001
From: Min Hsu <min....@sifive.com>
Date: Wed, 17 Jan 2024 14:18:37 -0800
Subject: [PATCH 2/4] fixup! [RISCV] Add support for Smepmp 1.0
---
clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++
llvm/docs/RISCVUsage.rst | 1 +
llvm/docs/ReleaseNotes.rst | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 12 +++++-------
llvm/test/CodeGen/RISCV/attributes.ll | 8 ++++----
llvm/test/MC/RISCV/attribute-arch.s | 6 +++---
6 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index d5ec93e292bf2a3..a325b0a763e7ab8 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -139,6 +139,7 @@
// Experimental extensions
+// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
@@ -1108,6 +1109,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32ismepmp1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64ismepmp1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
+// CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izfa -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index fc4d97b13437153..6fdc945ad27078e 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -92,6 +92,7 @@ on support follow.
``H`` Assembly Support
``M`` Supported
``Smaia`` Supported
+ ``Smepmp`` Supported
``Ssaia`` Supported
``Svinval`` Assembly Support
``Svnapot`` Assembly Support
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 4345d01021f17da..82cf130ffd18662 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -160,6 +160,7 @@ Changes to the RISC-V Backend
* Support was added for the Ziccif, Ziccrse, Ziccamoa, Zicclsm, Za64rs, Za128rs
and Zic64b extensions which were introduced as a part of the RISC-V Profiles
specification.
+* The Smepmp 1.0 extension is now supported.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9cf8df05bd3ad54..65208e560f08cc4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -743,18 +743,16 @@ def FeatureStdExtSmaia
"'Smaia' (Advanced Interrupt Architecture Machine "
"Level)", []>;
-def FeatureStdExtSmepmp
- : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
- "'Smepmp' (Smepmp prevents privileged processes from "
- "executing or accessing unprivileged programs and"
- "data.)",
- []>;
-
def FeatureStdExtSsaia
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
"Level)", []>;
+def FeatureStdExtSmepmp
+ : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
+ "'Smepmp' (PMP Enhancements for memory access and "
+ "execution prevention on Machine mode)", []>;
+
def HasHalfFPLoadStoreMove
: Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
AssemblerPredicate<(any_of FeatureStdExtZfh,
FeatureStdExtZfhmin,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index d0cd6ab3093b410..b90bef7525379d1 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,8 +88,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV32ZIMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMAIA %s
-; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SSAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZVFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZVFBFWMA %s
@@ -190,8 +190,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck
--check-prefix=RV64ZIMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck
--check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMAIA %s
-; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV64SSAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck
--check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZVFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck
--check-prefixes=CHECK,RV64ZVFBFWMA %s
@@ -287,8 +287,8 @@
; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
-; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
+; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
@@ -388,8 +388,8 @@
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
-; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
+; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index 0c258981365929c..5f9a7cabcc768ed 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -291,12 +291,12 @@
.attribute arch, "rv32i_smaia1p0"
# CHECK: attribute 5, "rv32i2p1_smaia1p0"
-.attribute arch, "rv32i_smepmp1p0"
-# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
-
.attribute arch, "rv32i_ssaia1p0"
# CHECK: attribute 5, "rv32i2p1_ssaia1p0"
+.attribute arch, "rv32i_smepmp1p0"
+# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
+
.attribute arch, "rv32i_zfbfmin1p0"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
>From 36fd5f4a5975766b19d3105c6e6e80c88fa70476 Mon Sep 17 00:00:00 2001
From: Min Hsu <min....@sifive.com>
Date: Thu, 18 Jan 2024 11:24:24 -0800
Subject: [PATCH 3/4] Shorten the description in RISCVFeatures.td
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 65208e560f08cc4..115da8c4a1a9357 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -750,8 +750,7 @@ def FeatureStdExtSsaia
def FeatureStdExtSmepmp
: SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
- "'Smepmp' (PMP Enhancements for memory access and "
- "execution prevention on Machine mode)", []>;
+ "'Smepmp' (Enhanced Physical Memory Protection)", []>;
def HasHalfFPLoadStoreMove
: Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
>From fd3ee245978c8db5c86ef84b4c7399d4d1133c2e Mon Sep 17 00:00:00 2001
From: Min Hsu <min....@sifive.com>
Date: Fri, 19 Jan 2024 09:53:05 -0800
Subject: [PATCH 4/4] Smepmp shouldn't be experimental
---
clang/test/Preprocessor/riscv-target-features.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index a325b0a763e7ab8..4fb3f0bab36b04f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -21,6 +21,7 @@
// CHECK-NOT: __riscv_muldiv {{.*$}}
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_ssaia {{.*$}}
+// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_svinval {{.*$}}
// CHECK-NOT: __riscv_svnapot {{.*$}}
// CHECK-NOT: __riscv_svpbmt {{.*$}}
@@ -139,7 +140,6 @@
// Experimental extensions
-// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
@@ -1109,10 +1109,10 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismepmp1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: %clang --target=riscv64 \
// RUN: -march=rv64ismepmp1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
// CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}}
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