[clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)

2025-02-26 Thread Luke Quinn via cfe-commits 

https://github.com/lquinn2015 updated 
https://github.com/llvm/llvm-project/pull/128710

>From d116c37108164065894b1f0d0a2338dc8001ff59 Mon Sep 17 00:00:00 2001
From: Luke Quinn 
Date: Mon, 24 Feb 2025 14:34:15 -0800
Subject: [PATCH] [RISCV] XQCIA 0.4. The spec was recently updated, this
 changes the name in the TD files associated and increments the Extension
 number in the clang driver. This is mostly a MC change as there is no other
 generated code for these instructions yet.

Signed-off-by: Luke Quinn 
---
 .../Driver/print-supported-extensions-riscv.c |  2 +-
 llvm/docs/RISCVUsage.rst  |  2 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|  2 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   |  4 +-
 llvm/test/CodeGen/RISCV/attributes.ll |  2 +-
 llvm/test/MC/RISCV/xqcia-invalid.s| 40 +--
 llvm/test/MC/RISCV/xqcia-valid.s  |  8 ++--
 .../TargetParser/RISCVISAInfoTest.cpp |  4 +-
 8 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index fcd820464e2d1..e0f917d30b979 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -193,7 +193,7 @@
 // CHECK-NEXT: smctr1.0   'Smctr' (Control Transfer 
Records Machine Level)
 // CHECK-NEXT: ssctr1.0   'Ssctr' (Control Transfer 
Records Supervisor Level)
 // CHECK-NEXT: svukte   0.3   'Svukte' 
(Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
-// CHECK-NEXT: xqcia0.2   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
+// CHECK-NEXT: xqcia0.4   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
 // CHECK-NEXT: xqciac   0.3   'Xqciac' (Qualcomm uC 
Load-Store Address Calculation Extension)
 // CHECK-NEXT: xqcicli  0.2   'Xqcicli' (Qualcomm uC 
Conditional Load Immediate Extension)
 // CHECK-NEXT: xqcicm   0.2   'Xqcicm' (Qualcomm uC 
Conditional Move Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 3c59216a40976..b53b55ff3a7cf 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -430,7 +430,7 @@ The current vendor extensions supported are:
   LLVM implements `the custom compressed opcodes present in some QingKe cores` 
by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes 
by the name "XW".
 
 ``experimental-Xqcia``
-  LLVM implements `version 0.2 of the Qualcomm uC Arithmetic extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
+  LLVM implements `version 0.4 of the Qualcomm uC Arithmetic extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
 ``experimental-Xqciac``
   LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address 
Calculation extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 1a93371a4d92f..b675c5670ceed 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1305,7 +1305,7 @@ def HasVendorXqcisls
  "'Xqcisls' (Qualcomm uC Scaled Load Store 
Extension)">;
 
 def FeatureVendorXqcia
-: RISCVExperimentalExtension<0, 2, "Qualcomm uC Arithmetic Extension">;
+: RISCVExperimentalExtension<0, 4, "Qualcomm uC Arithmetic Extension">;
 def HasVendorXqcia
 : Predicate<"Subtarget->hasVendorXqcia()">,
   AssemblerPredicate<(all_of FeatureVendorXqcia),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 3a8039fce1f49..8b74853d1d510 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -309,8 +309,8 @@ let Predicates = [HasVendorXqcisls, IsRV32], 
DecoderNamespace = "Xqcisls" in {
 
 let Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" in {
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-  def QC_SLASAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.slasat">;
-  def QC_SLLSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.sllsat">;
+  def QC_SHLSAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.shlsat">;
+  def QC_SHLUSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.shlusat">;
   def QC_ADDSAT : QCIRVInstRR<0b01110, GPRNoX0, "qc.ad

[clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)

2025-02-26 Thread Luke Quinn via cfe-commits 

https://github.com/lquinn2015 closed 
https://github.com/llvm/llvm-project/pull/128710
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[clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)

2025-02-25 Thread Luke Quinn via cfe-commits 

https://github.com/lquinn2015 updated 
https://github.com/llvm/llvm-project/pull/128710

>From c8007edad8767d3a3a117c9408d9ec5a78af76a7 Mon Sep 17 00:00:00 2001
From: Luke Quinn 
Date: Mon, 24 Feb 2025 14:34:15 -0800
Subject: [PATCH 1/3] [RISCV] XQCIA 0.4 spec renamed qc.slasat->qc.shlsat 
 qc.sllsat->qc.shlusat

Signed-off-by: Luke Quinn 
---
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td |  4 +--
 llvm/test/MC/RISCV/xqcia-invalid.s  | 40 ++---
 llvm/test/MC/RISCV/xqcia-valid.s|  8 ++---
 3 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 3a8039fce1f49..8b74853d1d510 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -309,8 +309,8 @@ let Predicates = [HasVendorXqcisls, IsRV32], 
DecoderNamespace = "Xqcisls" in {
 
 let Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" in {
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-  def QC_SLASAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.slasat">;
-  def QC_SLLSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.sllsat">;
+  def QC_SHLSAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.shlsat">;
+  def QC_SHLUSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.shlusat">;
   def QC_ADDSAT : QCIRVInstRR<0b01110, GPRNoX0, "qc.addsat">;
   def QC_ADDUSAT : QCIRVInstRR<0b0, GPRNoX0, "qc.addusat">;
   def QC_SUBSAT : QCIRVInstRR<0b1, GPRNoX0, "qc.subsat">;
diff --git a/llvm/test/MC/RISCV/xqcia-invalid.s 
b/llvm/test/MC/RISCV/xqcia-invalid.s
index aa4d7143a4919..8c341c69e3198 100644
--- a/llvm/test/MC/RISCV/xqcia-invalid.s
+++ b/llvm/test/MC/RISCV/xqcia-invalid.s
@@ -6,48 +6,48 @@
 
 # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
-qc.slasat x10, x3, 17
+qc.shlsat x10, x3, 17
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.slasat x10, x3
+qc.shlsat x10, x3
 
 # CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
-qc.slasat x0, x3, x17
+qc.shlsat x0, x3, x17
 
 # CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.slasat x10, x0, x17
+qc.shlsat x10, x0, x17
 
 # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
-qc.slasat x10, x3, x0
+qc.shlsat x10, x3, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 
'Xqcia' (Qualcomm uC Arithmetic Extension)
-qc.slasat x10, x3, x17
+qc.shlsat x10, x3, x17
 
 
-# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
-qc.sllsat x23, x25, 27
+# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
+qc.shlusat x23, x25, 27
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.sllsat x23, x25
+qc.shlusat x23, x25
 
-# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
-qc.sllsat x0, x25, x27
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.shlusat x0, x25, x27
 
-# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.sllsat x23, x0, x27
+# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction
+qc.shlusat x23, x0, x27
 
-# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
-qc.sllsat x23, x25, x0
+# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
+qc.shlusat x23, x25, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 
'Xqcia' (Qualcomm uC Arithmetic Extension)
-qc.sllsat x23, x25, x27
+qc.shlusat x23, x25, x27
 
 
 # CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero 
(x0)
diff --git a/llvm/test/MC/RISCV/xqcia-valid.s b/llvm/test/MC/RISCV/xqcia-valid.s
index 938285641ee79..18e2a7f29ccaa 100644
--- a/llvm/test/MC/RISCV/xqcia-valid.s
+++ b/llvm/test/MC/RISCV/xqcia-valid.s
@@ -10,13 +10,13 @@
 # RUN: | llvm-objdump --mattr=+experimental-xqcia --no-print-imm-hex -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
-# CH

[clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)

2025-02-25 Thread Luke Quinn via cfe-commits 

https://github.com/lquinn2015 updated 
https://github.com/llvm/llvm-project/pull/128710

>From c8007edad8767d3a3a117c9408d9ec5a78af76a7 Mon Sep 17 00:00:00 2001
From: Luke Quinn 
Date: Mon, 24 Feb 2025 14:34:15 -0800
Subject: [PATCH 1/4] [RISCV] XQCIA 0.4 spec renamed qc.slasat->qc.shlsat 
 qc.sllsat->qc.shlusat

Signed-off-by: Luke Quinn 
---
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td |  4 +--
 llvm/test/MC/RISCV/xqcia-invalid.s  | 40 ++---
 llvm/test/MC/RISCV/xqcia-valid.s|  8 ++---
 3 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 3a8039fce1f49..8b74853d1d510 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -309,8 +309,8 @@ let Predicates = [HasVendorXqcisls, IsRV32], 
DecoderNamespace = "Xqcisls" in {
 
 let Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" in {
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-  def QC_SLASAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.slasat">;
-  def QC_SLLSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.sllsat">;
+  def QC_SHLSAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.shlsat">;
+  def QC_SHLUSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.shlusat">;
   def QC_ADDSAT : QCIRVInstRR<0b01110, GPRNoX0, "qc.addsat">;
   def QC_ADDUSAT : QCIRVInstRR<0b0, GPRNoX0, "qc.addusat">;
   def QC_SUBSAT : QCIRVInstRR<0b1, GPRNoX0, "qc.subsat">;
diff --git a/llvm/test/MC/RISCV/xqcia-invalid.s 
b/llvm/test/MC/RISCV/xqcia-invalid.s
index aa4d7143a4919..8c341c69e3198 100644
--- a/llvm/test/MC/RISCV/xqcia-invalid.s
+++ b/llvm/test/MC/RISCV/xqcia-invalid.s
@@ -6,48 +6,48 @@
 
 # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
-qc.slasat x10, x3, 17
+qc.shlsat x10, x3, 17
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.slasat x10, x3
+qc.shlsat x10, x3
 
 # CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
-qc.slasat x0, x3, x17
+qc.shlsat x0, x3, x17
 
 # CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.slasat x10, x0, x17
+qc.shlsat x10, x0, x17
 
 # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
-qc.slasat x10, x3, x0
+qc.shlsat x10, x3, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 
'Xqcia' (Qualcomm uC Arithmetic Extension)
-qc.slasat x10, x3, x17
+qc.shlsat x10, x3, x17
 
 
-# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
-qc.sllsat x23, x25, 27
+# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
+qc.shlusat x23, x25, 27
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.sllsat x23, x25
+qc.shlusat x23, x25
 
-# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
-qc.sllsat x0, x25, x27
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.shlusat x0, x25, x27
 
-# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.sllsat x23, x0, x27
+# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction
+qc.shlusat x23, x0, x27
 
-# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
-qc.sllsat x23, x25, x0
+# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
+qc.shlusat x23, x25, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 
'Xqcia' (Qualcomm uC Arithmetic Extension)
-qc.sllsat x23, x25, x27
+qc.shlusat x23, x25, x27
 
 
 # CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero 
(x0)
diff --git a/llvm/test/MC/RISCV/xqcia-valid.s b/llvm/test/MC/RISCV/xqcia-valid.s
index 938285641ee79..18e2a7f29ccaa 100644
--- a/llvm/test/MC/RISCV/xqcia-valid.s
+++ b/llvm/test/MC/RISCV/xqcia-valid.s
@@ -10,13 +10,13 @@
 # RUN: | llvm-objdump --mattr=+experimental-xqcia --no-print-imm-hex -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
-# CH

[clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)

2025-02-25 Thread Luke Quinn via cfe-commits 

https://github.com/lquinn2015 updated 
https://github.com/llvm/llvm-project/pull/128710

>From c8007edad8767d3a3a117c9408d9ec5a78af76a7 Mon Sep 17 00:00:00 2001
From: Luke Quinn 
Date: Mon, 24 Feb 2025 14:34:15 -0800
Subject: [PATCH 1/5] [RISCV] XQCIA 0.4 spec renamed qc.slasat->qc.shlsat 
 qc.sllsat->qc.shlusat

Signed-off-by: Luke Quinn 
---
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td |  4 +--
 llvm/test/MC/RISCV/xqcia-invalid.s  | 40 ++---
 llvm/test/MC/RISCV/xqcia-valid.s|  8 ++---
 3 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 3a8039fce1f49..8b74853d1d510 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -309,8 +309,8 @@ let Predicates = [HasVendorXqcisls, IsRV32], 
DecoderNamespace = "Xqcisls" in {
 
 let Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" in {
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-  def QC_SLASAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.slasat">;
-  def QC_SLLSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.sllsat">;
+  def QC_SHLSAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.shlsat">;
+  def QC_SHLUSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.shlusat">;
   def QC_ADDSAT : QCIRVInstRR<0b01110, GPRNoX0, "qc.addsat">;
   def QC_ADDUSAT : QCIRVInstRR<0b0, GPRNoX0, "qc.addusat">;
   def QC_SUBSAT : QCIRVInstRR<0b1, GPRNoX0, "qc.subsat">;
diff --git a/llvm/test/MC/RISCV/xqcia-invalid.s 
b/llvm/test/MC/RISCV/xqcia-invalid.s
index aa4d7143a4919..8c341c69e3198 100644
--- a/llvm/test/MC/RISCV/xqcia-invalid.s
+++ b/llvm/test/MC/RISCV/xqcia-invalid.s
@@ -6,48 +6,48 @@
 
 # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
-qc.slasat x10, x3, 17
+qc.shlsat x10, x3, 17
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.slasat x10, x3
+qc.shlsat x10, x3
 
 # CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
-qc.slasat x0, x3, x17
+qc.shlsat x0, x3, x17
 
 # CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.slasat x10, x0, x17
+qc.shlsat x10, x0, x17
 
 # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero 
(x0)
 # CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
-qc.slasat x10, x3, x0
+qc.shlsat x10, x3, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 
'Xqcia' (Qualcomm uC Arithmetic Extension)
-qc.slasat x10, x3, x17
+qc.shlsat x10, x3, x17
 
 
-# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
-qc.sllsat x23, x25, 27
+# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
+qc.shlusat x23, x25, 27
 
 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.sllsat x23, x25
+qc.shlusat x23, x25
 
-# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
-qc.sllsat x0, x25, x27
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.shlusat x0, x25, x27
 
-# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.sllsat x23, x0, x27
+# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction
+qc.shlusat x23, x0, x27
 
-# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero 
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
-qc.sllsat x23, x25, x0
+# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero 
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
+qc.shlusat x23, x25, x0
 
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 
'Xqcia' (Qualcomm uC Arithmetic Extension)
-qc.sllsat x23, x25, x27
+qc.shlusat x23, x25, x27
 
 
 # CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero 
(x0)
diff --git a/llvm/test/MC/RISCV/xqcia-valid.s b/llvm/test/MC/RISCV/xqcia-valid.s
index 938285641ee79..18e2a7f29ccaa 100644
--- a/llvm/test/MC/RISCV/xqcia-valid.s
+++ b/llvm/test/MC/RISCV/xqcia-valid.s
@@ -10,13 +10,13 @@
 # RUN: | llvm-objdump --mattr=+experimental-xqcia --no-print-imm-hex -d - \
 # RUN: | FileCheck -check-prefix=CHECK-INST %s
 
-# CH