https://github.com/lquinn2015 updated
https://github.com/llvm/llvm-project/pull/128710
>From c8007edad8767d3a3a117c9408d9ec5a78af76a7 Mon Sep 17 00:00:00 2001
From: Luke Quinn <quic_lqu...@quicinc.com>
Date: Mon, 24 Feb 2025 14:34:15 -0800
Subject: [PATCH 1/4] [RISCV] XQCIA 0.4 spec renamed qc.slasat->qc.shlsat
qc.sllsat->qc.shlusat
Signed-off-by: Luke Quinn <quic_lqu...@quicinc.com>
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 4 +--
llvm/test/MC/RISCV/xqcia-invalid.s | 40 ++++++++++-----------
llvm/test/MC/RISCV/xqcia-valid.s | 8 ++---
3 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 3a8039fce1f49..8b74853d1d510 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -309,8 +309,8 @@ let Predicates = [HasVendorXqcisls, IsRV32],
DecoderNamespace = "Xqcisls" in {
let Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
- def QC_SLASAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.slasat">;
- def QC_SLLSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.sllsat">;
+ def QC_SHLSAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.shlsat">;
+ def QC_SHLUSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.shlusat">;
def QC_ADDSAT : QCIRVInstRR<0b01110, GPRNoX0, "qc.addsat">;
def QC_ADDUSAT : QCIRVInstRR<0b01111, GPRNoX0, "qc.addusat">;
def QC_SUBSAT : QCIRVInstRR<0b10000, GPRNoX0, "qc.subsat">;
diff --git a/llvm/test/MC/RISCV/xqcia-invalid.s
b/llvm/test/MC/RISCV/xqcia-invalid.s
index aa4d7143a4919..8c341c69e3198 100644
--- a/llvm/test/MC/RISCV/xqcia-invalid.s
+++ b/llvm/test/MC/RISCV/xqcia-invalid.s
@@ -6,48 +6,48 @@
# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero
(x0)
# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
-qc.slasat x10, x3, 17
+qc.shlsat x10, x3, 17
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.slasat x10, x3
+qc.shlsat x10, x3
# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero
(x0)
# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
-qc.slasat x0, x3, x17
+qc.shlsat x0, x3, x17
# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero
(x0)
# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.slasat x10, x0, x17
+qc.shlsat x10, x0, x17
# CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero
(x0)
# CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction
-qc.slasat x10, x3, x0
+qc.shlsat x10, x3, x0
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following:
'Xqcia' (Qualcomm uC Arithmetic Extension)
-qc.slasat x10, x3, x17
+qc.shlsat x10, x3, x17
-# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
-qc.sllsat x23, x25, 27
+# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
+qc.shlusat x23, x25, 27
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
-qc.sllsat x23, x25
+qc.shlusat x23, x25
-# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
-qc.sllsat x0, x25, x27
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.shlusat x0, x25, x27
-# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
-qc.sllsat x23, x0, x27
+# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding zero
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction
+qc.shlusat x23, x0, x27
-# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero
(x0)
-# CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction
-qc.sllsat x23, x25, x0
+# CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero
(x0)
+# CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction
+qc.shlusat x23, x25, x0
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following:
'Xqcia' (Qualcomm uC Arithmetic Extension)
-qc.sllsat x23, x25, x27
+qc.shlusat x23, x25, x27
# CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero
(x0)
diff --git a/llvm/test/MC/RISCV/xqcia-valid.s b/llvm/test/MC/RISCV/xqcia-valid.s
index 938285641ee79..18e2a7f29ccaa 100644
--- a/llvm/test/MC/RISCV/xqcia-valid.s
+++ b/llvm/test/MC/RISCV/xqcia-valid.s
@@ -10,13 +10,13 @@
# RUN: | llvm-objdump --mattr=+experimental-xqcia --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# CHECK-INST: qc.slasat a0, gp, a7
+# CHECK-INST: qc.shlsat a0, gp, a7
# CHECK-ENC: encoding: [0x0b,0xb5,0x11,0x15]
-qc.slasat x10, x3, x17
+qc.shlsat x10, x3, x17
-# CHECK-INST: qc.sllsat s7, s9, s11
+# CHECK-INST: qc.shlusat s7, s9, s11
# CHECK-ENC: encoding: [0x8b,0xbb,0xbc,0x19]
-qc.sllsat x23, x25, x27
+qc.shlusat x23, x25, x27
# CHECK-INST: qc.addsat a7, a4, t2
# CHECK-ENC: encoding: [0x8b,0x38,0x77,0x1c]
>From 929ecf99166829b5de1a699ee71d2bf95a85d39e Mon Sep 17 00:00:00 2001
From: Luke Quinn <quic_lqu...@quicinc.com>
Date: Tue, 25 Feb 2025 05:07:43 -0800
Subject: [PATCH 2/4] [RISCV] Increment Xqcia extension number its now 0.4
compliant
Signed-off-by: Luke Quinn <quic_lqu...@quicinc.com>
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +-
llvm/test/CodeGen/RISCV/attributes.ll | 2 +-
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 1a93371a4d92f..b675c5670ceed 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1305,7 +1305,7 @@ def HasVendorXqcisls
"'Xqcisls' (Qualcomm uC Scaled Load Store
Extension)">;
def FeatureVendorXqcia
- : RISCVExperimentalExtension<0, 2, "Qualcomm uC Arithmetic Extension">;
+ : RISCVExperimentalExtension<0, 4, "Qualcomm uC Arithmetic Extension">;
def HasVendorXqcia
: Predicate<"Subtarget->hasVendorXqcia()">,
AssemblerPredicate<(all_of FeatureVendorXqcia),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index daab7b236879f..037b9c3d06764 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -398,7 +398,7 @@
; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2"
-; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2"
+; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p4"
; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3"
; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2"
; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index f734b4e25551b..cfa224c4c0015 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -654,7 +654,7 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
}
for (StringRef Input :
- {"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqciac0p3",
+ {"rv64i_xqcisls0p2", "rv64i_xqcia0p4", "rv64i_xqciac0p3",
"rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2",
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p2",
"rv64i_xqcilo0p2", "rv64i_xqcilia0p2"}) {
>From ec5ab4777284f96a15a1ee59e59437e27abef1ee Mon Sep 17 00:00:00 2001
From: Luke Quinn <quic_lqu...@quicinc.com>
Date: Tue, 25 Feb 2025 10:23:15 -0800
Subject: [PATCH 3/4] Fixed driver compliance
Signed-off-by: Luke Quinn <quic_lqu...@quicinc.com>
---
clang/test/Driver/print-supported-extensions-riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c
b/clang/test/Driver/print-supported-extensions-riscv.c
index fcd820464e2d1..e0f917d30b979 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -193,7 +193,7 @@
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer
Records Machine Level)
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer
Records Supervisor Level)
// CHECK-NEXT: svukte 0.3 'Svukte'
(Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
-// CHECK-NEXT: xqcia 0.2 'Xqcia' (Qualcomm uC
Arithmetic Extension)
+// CHECK-NEXT: xqcia 0.4 'Xqcia' (Qualcomm uC
Arithmetic Extension)
// CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC
Load-Store Address Calculation Extension)
// CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC
Conditional Load Immediate Extension)
// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC
Conditional Move Extension)
>From 198480d7c775577b5b65aa70ddb9b1812adc4a88 Mon Sep 17 00:00:00 2001
From: Luke Quinn <quic_lqu...@quicinc.com>
Date: Tue, 25 Feb 2025 10:57:52 -0800
Subject: [PATCH 4/4] Missed a second test
Signed-off-by: Luke Quinn <quic_lqu...@quicinc.com>
---
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index cfa224c4c0015..418e2b431dbf2 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1119,7 +1119,7 @@ Experimental extensions
smctr 1.0
ssctr 1.0
svukte 0.3
- xqcia 0.2
+ xqcia 0.4
xqciac 0.3
xqcicli 0.2
xqcicm 0.2
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