[clang] c9ca3a3 - [AArch64] Add driver tests for HiSilicon's TSV110

2020-11-06 Thread Elvina Yakubova via cfe-commits 

Author: Elvina Yakubova
Date: 2020-11-07T01:51:37+03:00
New Revision: c9ca3a3c66a493d72cf7afc7ee975e2de399f2e5

URL: 
https://github.com/llvm/llvm-project/commit/c9ca3a3c66a493d72cf7afc7ee975e2de399f2e5
DIFF: 
https://github.com/llvm/llvm-project/commit/c9ca3a3c66a493d72cf7afc7ee975e2de399f2e5.diff

LOG: [AArch64] Add driver tests for HiSilicon's TSV110

Added: 


Modified: 
clang/test/Driver/aarch64-cpus.c

Removed: 




diff  --git a/clang/test/Driver/aarch64-cpus.c 
b/clang/test/Driver/aarch64-cpus.c
index 356674e7a707..9cdf346148c3 100644
--- a/clang/test/Driver/aarch64-cpus.c
+++ b/clang/test/Driver/aarch64-cpus.c
@@ -295,6 +295,20 @@
 // ARM64-THUNDERX3T110: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" 
"thunderx3t110" "-target-feature" "+v8.3a"
 // ARM64-THUNDERX3T110-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" 
"-target-cpu" "generic"
 
+// RUN: %clang -target aarch64 -mcpu=tsv110 -### -c %s 2>&1 | FileCheck 
-check-prefix=TSV110 %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=tsv110 -### -c %s 2>&1 | 
FileCheck -check-prefix=TSV110 %s
+// RUN: %clang -target aarch64 -mtune=tsv110 -### -c %s 2>&1 | FileCheck 
-check-prefix=TSV110-TUNE %s
+// RUN: %clang -target aarch64 -mlittle-endian -mtune=tsv110 -### -c %s 2>&1 | 
FileCheck -check-prefix=TSV110-TUNE %s
+// TSV110: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "tsv110"
+// TSV110-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target arm64 -mcpu=tsv110 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-TSV110 %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=tsv110 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-TSV110 %s
+// RUN: %clang -target arm64 -mtune=tsv110 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-TSV110-TUNE %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=tsv110 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-TSV110-TUNE %s
+// ARM64-TSV110: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "tsv110"
+// ARM64-TSV110-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" 
"generic"
+
 // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=A64FX %s
 // RUN: %clang -target aarch64 -mlittle-endian -mcpu=a64fx -### -c %s 2>&1 | 
FileCheck -check-prefix=A64FX %s
 // RUN: %clang -target aarch64 -mtune=a64fx -### -c %s 2>&1 | FileCheck 
-check-prefix=A64FX-TUNE %s



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[clang] 624bced - [OpenCL] Make Clang recognize -cl-std=1.0 as a value argument

2020-11-11 Thread Elvina Yakubova via cfe-commits 

Author: Elvina Yakubova
Date: 2020-11-11T17:01:57+03:00
New Revision: 624bced7eec09a6a70f6e04faeddd0adc1553799

URL: 
https://github.com/llvm/llvm-project/commit/624bced7eec09a6a70f6e04faeddd0adc1553799
DIFF: 
https://github.com/llvm/llvm-project/commit/624bced7eec09a6a70f6e04faeddd0adc1553799.diff

LOG: [OpenCL] Make Clang recognize -cl-std=1.0 as a value argument

This patch makes Clang recognize -cl-std=1.0 as a value argument,
before only -std=cl1.0 has to be used instead.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47981

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D91237

Added: 


Modified: 
clang/include/clang/Driver/Options.td
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/Driver/autocomplete.c
clang/test/Driver/opencl.cl
clang/test/Frontend/stdlang.c
clang/test/Preprocessor/predefined-macros.c

Removed: 




diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 867b47857295..2e6efef04dbb 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -605,7 +605,7 @@ def cl_no_signed_zeros : Flag<["-"], "cl-no-signed-zeros">, 
Group,
   HelpText<"OpenCL only. Allow use of less precise no signed zeros 
computations in the generated binary.">,
   MarshallingInfoFlag<"LangOpts->CLNoSignedZero">;
 def cl_std_EQ : Joined<["-"], "cl-std=">, Group, 
Flags<[CC1Option]>,
-  HelpText<"OpenCL language standard to compile for.">, 
Values<"cl,CL,cl1.1,CL1.1,cl1.2,CL1.2,cl2.0,CL2.0,cl3.0,CL3.0,clc++,CLC++">;
+  HelpText<"OpenCL language standard to compile for.">, 
Values<"cl,CL,cl1.0,CL1.0,cl1.1,CL1.1,cl1.2,CL1.2,cl2.0,CL2.0,cl3.0,CL3.0,clc++,CLC++">;
 def cl_denorms_are_zero : Flag<["-"], "cl-denorms-are-zero">, 
Group,
   HelpText<"OpenCL only. Allow denormals to be flushed to zero.">;
 def cl_fp32_correctly_rounded_divide_sqrt : Flag<["-"], 
"cl-fp32-correctly-rounded-divide-sqrt">, Group, 
Flags<[CC1Option]>,

diff  --git a/clang/lib/Frontend/CompilerInvocation.cpp 
b/clang/lib/Frontend/CompilerInvocation.cpp
index 590808cf69a0..0a776bfe4518 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -2596,6 +2596,7 @@ static void ParseLangArgs(LangOptions &Opts, ArgList 
&Args, InputKind IK,
 LangStandard::Kind OpenCLLangStd
   = llvm::StringSwitch(A->getValue())
 .Cases("cl", "CL", LangStandard::lang_opencl10)
+.Cases("cl1.0", "CL1.0", LangStandard::lang_opencl10)
 .Cases("cl1.1", "CL1.1", LangStandard::lang_opencl11)
 .Cases("cl1.2", "CL1.2", LangStandard::lang_opencl12)
 .Cases("cl2.0", "CL2.0", LangStandard::lang_opencl20)

diff  --git a/clang/test/Driver/autocomplete.c 
b/clang/test/Driver/autocomplete.c
index c9f66de7cd5d..89f7c6e76125 100644
--- a/clang/test/Driver/autocomplete.c
+++ b/clang/test/Driver/autocomplete.c
@@ -37,6 +37,8 @@
 
 // CLSTDALL: cl
 // CLSTDALL-NEXT: CL
+// CLSTDALL-NEXT: cl1.0
+// CLSTDALL-NEXT: CL1.0
 // CLSTDALL-NEXT: cl1.1
 // CLSTDALL-NEXT: CL1.1
 // CLSTDALL-NEXT: cl1.2

diff  --git a/clang/test/Driver/opencl.cl b/clang/test/Driver/opencl.cl
index cc0a9143ab37..44ae12330662 100644
--- a/clang/test/Driver/opencl.cl
+++ b/clang/test/Driver/opencl.cl
@@ -1,4 +1,5 @@
 // RUN: %clang -S -### -cl-std=CL %s 2>&1 | FileCheck --check-prefix=CHECK-CL 
%s
+// RUN: %clang -S -### -cl-std=CL1.0 %s 2>&1 | FileCheck 
--check-prefix=CHECK-CL10 %s
 // RUN: %clang -S -### -cl-std=CL1.1 %s 2>&1 | FileCheck 
--check-prefix=CHECK-CL11 %s
 // RUN: %clang -S -### -cl-std=CL1.2 %s 2>&1 | FileCheck 
--check-prefix=CHECK-CL12 %s
 // RUN: %clang -S -### -cl-std=CL2.0 %s 2>&1 | FileCheck 
--check-prefix=CHECK-CL20 %s
@@ -20,6 +21,7 @@
 // RUN: not %clang -cl-std=invalid -DOPENCL %s 2>&1 | FileCheck 
--check-prefix=CHECK-INVALID %s
 
 // CHECK-CL: "-cc1" {{.*}} "-cl-std=CL"
+// CHECK-CL10: "-cc1" {{.*}} "-cl-std=CL1.0"
 // CHECK-CL11: "-cc1" {{.*}} "-cl-std=CL1.1"
 // CHECK-CL12: "-cc1" {{.*}} "-cl-std=CL1.2"
 // CHECK-CL20: "-cc1" {{.*}} "-cl-std=CL2.0"

diff  --git a/clang/test/Frontend/stdlang.c b/clang/test/Frontend/stdlang.c
index 35a2116859d5..0cb67deef23b 100644
--- a/clang/test/Frontend/stdlang.c
+++ b/clang/test/Frontend/stdlang.c
@@ -1,6 +1,7 @@
 // RUN: %clang_cc1 -x cuda -std=c++11 -DCUDA %s
 // RUN: %clang_cc1 -x cl -DOPENCL %s
 // RUN: %clang_cc1 -x cl -cl-std=cl -DOPENCL %s
+// RUN: %clang_cc1 -x cl -cl-std=cl1.0 -DOPENCL %s
 // RUN: %clang_cc1 -x cl -cl-std=cl1.1 -DOPENCL %s
 // RUN: %clang_cc1 -x cl -cl-std=cl1.2 -DOPENCL %s
 // RUN: %clang_cc1 -x cl -cl-std=cl2.0 -DOPENCL %s

diff  --git a/clang/test/Preprocessor/predefined-macros.c 
b/clang/test/Preprocessor/predefined-macros.c
index 6c80517ec4d4..e406b9a70570 100644
--- a/clang/test/Preprocessor/predefined-macros.c
+++ b/clang/test/Preprocessor/predefined-macros.c
@@ -123,6 +123,8 @@
 
 // RUN: %clang_cc1 %s -E -

[clang] [llvm] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)

2024-10-07 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova updated 
https://github.com/llvm/llvm-project/pull/97749

>From 6ba67c2f67d6f5039b3f9dbfc283c0c17ba34c89 Mon Sep 17 00:00:00 2001
From: Neil Hickey 
Date: Wed, 3 Jul 2024 07:22:46 -0700
Subject: [PATCH 1/2] [AArch64] Add getHostCPUFeatures to query for enabled
 features in cpuinfo

---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index f083e40df13144..1e2ac4e501bafd 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,15 +135,21 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, 
StringRef March,
   return true;
 }
 
-static bool
-getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu,
-   const ArgList &Args,
-   llvm::AArch64::ExtensionSet &Extensions) {
+static bool getAArch64ArchFeaturesFromMcpu(
+const Driver &D, StringRef Mcpu, const ArgList &Args,
+llvm::AArch64::ExtensionSet &Extensions, std::vector &Features) 
{
   StringRef CPU;
   std::string McpuLowerCase = Mcpu.lower();
   if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions))
 return false;
 
+  if (Mcpu == "native") {
+llvm::StringMap HostFeatures = llvm::sys::getHostCPUFeatures();
+for (auto &[Feature, Enabled] : HostFeatures) {
+  Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature));
+}
+  }
+
   return true;
 }
 
@@ -210,11 +216,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
 success =
 getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions);
   else if ((A = Args.getLastArg(options::OPT_mcpu_EQ)))
-success =
-getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions);
+success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, 
Extensions,
+ Features);
   else if (isCPUDeterminedByTriple(Triple))
 success = getAArch64ArchFeaturesFromMcpu(
-D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions);
+D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions, Features);
   else
 // Default to 'A' profile if the architecture is not specified.
 success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions);

>From db66fb7a218d1362e20143f5e1f3f40509e8abb5 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Mon, 23 Sep 2024 03:00:19 -0700
Subject: [PATCH 2/2] [clang][AArch64] Add LLVM_CPUINFO environment variable

Add LLVM_CPUINFO environment variable to test mock /proc/cpuinfo
files for -mcpu=native
---
 clang/test/Driver/Inputs/cpunative/cortex-a57 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a72 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a76 |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-n1  |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-v2  |   8 +
 clang/test/Driver/aarch64-mcpu-native.c   | 137 ++
 llvm/lib/TargetParser/Host.cpp|   4 +
 7 files changed, 181 insertions(+)
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a57
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a72
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a76
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-n1
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-v2
 create mode 100644 clang/test/Driver/aarch64-mcpu-native.c

diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a57 
b/clang/test/Driver/Inputs/cpunative/cortex-a57
new file mode 100644
index 00..e1903012ab79cc
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a57
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 200.00
+Features: fp asimd evtstrm crc32 cpuid
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd07
+CPU revision: 1
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a72 
b/clang/test/Driver/Inputs/cpunative/cortex-a72
new file mode 100644
index 00..7aed4a6fa73236
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a72
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 250.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid asimdrdm
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part: 0xd08
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a76 
b/clang/test/Driver/Inputs/cpunative/cortex-a76
new file mode 100644
index 00..21822cfcec60b0
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a76
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 500.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm ssbs jscvt fcma
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+

[clang] [llvm] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)

2024-10-07 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova updated 
https://github.com/llvm/llvm-project/pull/97749

>From 6ba67c2f67d6f5039b3f9dbfc283c0c17ba34c89 Mon Sep 17 00:00:00 2001
From: Neil Hickey 
Date: Wed, 3 Jul 2024 07:22:46 -0700
Subject: [PATCH 1/2] [AArch64] Add getHostCPUFeatures to query for enabled
 features in cpuinfo

---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index f083e40df13144..1e2ac4e501bafd 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,15 +135,21 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, 
StringRef March,
   return true;
 }
 
-static bool
-getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu,
-   const ArgList &Args,
-   llvm::AArch64::ExtensionSet &Extensions) {
+static bool getAArch64ArchFeaturesFromMcpu(
+const Driver &D, StringRef Mcpu, const ArgList &Args,
+llvm::AArch64::ExtensionSet &Extensions, std::vector &Features) 
{
   StringRef CPU;
   std::string McpuLowerCase = Mcpu.lower();
   if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions))
 return false;
 
+  if (Mcpu == "native") {
+llvm::StringMap HostFeatures = llvm::sys::getHostCPUFeatures();
+for (auto &[Feature, Enabled] : HostFeatures) {
+  Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature));
+}
+  }
+
   return true;
 }
 
@@ -210,11 +216,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
 success =
 getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions);
   else if ((A = Args.getLastArg(options::OPT_mcpu_EQ)))
-success =
-getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions);
+success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, 
Extensions,
+ Features);
   else if (isCPUDeterminedByTriple(Triple))
 success = getAArch64ArchFeaturesFromMcpu(
-D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions);
+D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions, Features);
   else
 // Default to 'A' profile if the architecture is not specified.
 success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions);

>From 9f1a5b60a98107530407773f4166cf7619e0728c Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Tue, 8 Oct 2024 03:48:51 +0530
Subject: [PATCH 2/2] [clang][AArch64] Add LLVM_CPUINFO environment variable

Add LLVM_CPUINFO environment variable to test mock /proc/cpuinfo
files for -mcpu=native
---
 clang/test/Driver/Inputs/cpunative/cortex-a57 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a72 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a76 |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-n1  |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-v2  |   8 +
 clang/test/Driver/aarch64-mcpu-native.c   | 137 ++
 llvm/lib/TargetParser/Host.cpp|   4 +
 7 files changed, 181 insertions(+)
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a57
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a72
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a76
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-n1
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-v2
 create mode 100644 clang/test/Driver/aarch64-mcpu-native.c

diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a57 
b/clang/test/Driver/Inputs/cpunative/cortex-a57
new file mode 100644
index 00..e1903012ab79cc
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a57
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 200.00
+Features: fp asimd evtstrm crc32 cpuid
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd07
+CPU revision: 1
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a72 
b/clang/test/Driver/Inputs/cpunative/cortex-a72
new file mode 100644
index 00..7aed4a6fa73236
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a72
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 250.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid asimdrdm
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part: 0xd08
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a76 
b/clang/test/Driver/Inputs/cpunative/cortex-a76
new file mode 100644
index 00..21822cfcec60b0
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a76
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 500.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm ssbs jscvt fcma
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+C

[clang] [llvm] Revert "[clang][AArch64] Add getHostCPUFeatures to query for enabled … (PR #114066)

2024-10-29 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova closed 
https://github.com/llvm/llvm-project/pull/114066
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[clang] [llvm] Revert "[clang][AArch64] Add getHostCPUFeatures to query for enabled … (PR #114066)

2024-10-29 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova created 
https://github.com/llvm/llvm-project/pull/114066

…features in cpu info (#97749)"

This reverts commit d732c0b13c55259177f2936516b6087d634078e0.

This is breaking buildbots 
https://lab.llvm.org/buildbot/#/builders/190/builds/8413, 
https://lab.llvm.org/buildbot/#/builders/56/builds/10880 and a few others.


>From 64c94581f63fa11de0984d70aac754de495d2ae3 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Tue, 29 Oct 2024 07:35:27 -0700
Subject: [PATCH] Revert "[clang][AArch64] Add getHostCPUFeatures to query for
 enabled features in cpu info (#97749)"

This reverts commit d732c0b13c55259177f2936516b6087d634078e0.
---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp  |  20 +--
 clang/test/Driver/Inputs/cpunative/cortex-a57 |   8 -
 clang/test/Driver/Inputs/cpunative/cortex-a72 |   8 -
 clang/test/Driver/Inputs/cpunative/cortex-a76 |   8 -
 .../test/Driver/Inputs/cpunative/neoverse-n1  |   8 -
 .../test/Driver/Inputs/cpunative/neoverse-v2  |   8 -
 clang/test/Driver/aarch64-mcpu-native.c   | 138 --
 llvm/lib/TargetParser/Host.cpp|  10 +-
 8 files changed, 10 insertions(+), 198 deletions(-)
 delete mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a57
 delete mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a72
 delete mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a76
 delete mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-n1
 delete mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-v2
 delete mode 100644 clang/test/Driver/aarch64-mcpu-native.c

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 1e2ac4e501bafd..f083e40df13144 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,21 +135,15 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, 
StringRef March,
   return true;
 }
 
-static bool getAArch64ArchFeaturesFromMcpu(
-const Driver &D, StringRef Mcpu, const ArgList &Args,
-llvm::AArch64::ExtensionSet &Extensions, std::vector &Features) 
{
+static bool
+getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu,
+   const ArgList &Args,
+   llvm::AArch64::ExtensionSet &Extensions) {
   StringRef CPU;
   std::string McpuLowerCase = Mcpu.lower();
   if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions))
 return false;
 
-  if (Mcpu == "native") {
-llvm::StringMap HostFeatures = llvm::sys::getHostCPUFeatures();
-for (auto &[Feature, Enabled] : HostFeatures) {
-  Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature));
-}
-  }
-
   return true;
 }
 
@@ -216,11 +210,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
 success =
 getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions);
   else if ((A = Args.getLastArg(options::OPT_mcpu_EQ)))
-success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, 
Extensions,
- Features);
+success =
+getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions);
   else if (isCPUDeterminedByTriple(Triple))
 success = getAArch64ArchFeaturesFromMcpu(
-D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions, Features);
+D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions);
   else
 // Default to 'A' profile if the architecture is not specified.
 success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions);
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a57 
b/clang/test/Driver/Inputs/cpunative/cortex-a57
deleted file mode 100644
index e1903012ab79cc..00
--- a/clang/test/Driver/Inputs/cpunative/cortex-a57
+++ /dev/null
@@ -1,8 +0,0 @@
-processor   : 0
-BogoMIPS: 200.00
-Features: fp asimd evtstrm crc32 cpuid
-CPU implementer : 0x41
-CPU architecture: 8
-CPU variant : 0x1
-CPU part: 0xd07
-CPU revision: 1
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a72 
b/clang/test/Driver/Inputs/cpunative/cortex-a72
deleted file mode 100644
index 7aed4a6fa73236..00
--- a/clang/test/Driver/Inputs/cpunative/cortex-a72
+++ /dev/null
@@ -1,8 +0,0 @@
-processor   : 0
-BogoMIPS: 250.00
-Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid asimdrdm
-CPU implementer : 0x41
-CPU architecture: 8
-CPU variant : 0x0
-CPU part: 0xd08
-CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a76 
b/clang/test/Driver/Inputs/cpunative/cortex-a76
deleted file mode 100644
index 21822cfcec60b0..00
--- a/clang/test/Driver/Inputs/cpunative/cortex-a76
+++ /dev/null
@@ -1,8 +0,0 @@
-processor   : 0
-BogoMIPS: 500.00
-Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm ssbs jscvt fcma
-CPU implementer : 0x41
-CPU architecture: 8
-CPU variant

[clang] [llvm] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)

2024-10-29 Thread Elvina Yakubova via cfe-commits 


@@ -0,0 +1,137 @@
+// RUN: export LLVM_CPUINFO=%S/Inputs/cpunative/neoverse-v2
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=native | 
FileCheck --strict-whitespace --check-prefix=CHECK-FEAT-NV2 
--implicit-check-not=FEAT_ %s
+

ElvinaYakubova wrote:

thanks, you're right, added it

https://github.com/llvm/llvm-project/pull/97749
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[clang] [llvm] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)

2024-10-29 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova updated 
https://github.com/llvm/llvm-project/pull/97749

>From e46cbb0dd668f8be6b93c1b9adee671b995fa478 Mon Sep 17 00:00:00 2001
From: Neil Hickey 
Date: Wed, 3 Jul 2024 07:22:46 -0700
Subject: [PATCH 1/2] [AArch64] Add getHostCPUFeatures to query for enabled
 features in cpuinfo

---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index f083e40df13144..1e2ac4e501bafd 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,15 +135,21 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, 
StringRef March,
   return true;
 }
 
-static bool
-getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu,
-   const ArgList &Args,
-   llvm::AArch64::ExtensionSet &Extensions) {
+static bool getAArch64ArchFeaturesFromMcpu(
+const Driver &D, StringRef Mcpu, const ArgList &Args,
+llvm::AArch64::ExtensionSet &Extensions, std::vector &Features) 
{
   StringRef CPU;
   std::string McpuLowerCase = Mcpu.lower();
   if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions))
 return false;
 
+  if (Mcpu == "native") {
+llvm::StringMap HostFeatures = llvm::sys::getHostCPUFeatures();
+for (auto &[Feature, Enabled] : HostFeatures) {
+  Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature));
+}
+  }
+
   return true;
 }
 
@@ -210,11 +216,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
 success =
 getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions);
   else if ((A = Args.getLastArg(options::OPT_mcpu_EQ)))
-success =
-getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions);
+success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, 
Extensions,
+ Features);
   else if (isCPUDeterminedByTriple(Triple))
 success = getAArch64ArchFeaturesFromMcpu(
-D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions);
+D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions, Features);
   else
 // Default to 'A' profile if the architecture is not specified.
 success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions);

>From 50d917f1e042de4023f73a33f39e60ee65a84411 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Tue, 8 Oct 2024 03:48:51 +0530
Subject: [PATCH 2/2] [clang][AArch64] Add LLVM_CPUINFO environment variable

Add LLVM_CPUINFO environment variable to test mock /proc/cpuinfo
files for -mcpu=native
---
 clang/test/Driver/Inputs/cpunative/cortex-a57 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a72 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a76 |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-n1  |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-v2  |   8 +
 clang/test/Driver/aarch64-mcpu-native.c   | 138 ++
 llvm/lib/TargetParser/Host.cpp|  10 +-
 7 files changed, 185 insertions(+), 3 deletions(-)
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a57
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a72
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a76
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-n1
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-v2
 create mode 100644 clang/test/Driver/aarch64-mcpu-native.c

diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a57 
b/clang/test/Driver/Inputs/cpunative/cortex-a57
new file mode 100644
index 00..e1903012ab79cc
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a57
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 200.00
+Features: fp asimd evtstrm crc32 cpuid
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd07
+CPU revision: 1
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a72 
b/clang/test/Driver/Inputs/cpunative/cortex-a72
new file mode 100644
index 00..7aed4a6fa73236
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a72
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 250.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid asimdrdm
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part: 0xd08
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a76 
b/clang/test/Driver/Inputs/cpunative/cortex-a76
new file mode 100644
index 00..21822cfcec60b0
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a76
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 500.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm ssbs jscvt fcma
+CPU implementer : 0x41
+CPU architecture: 8
+CPU var

[clang] [llvm] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)

2024-10-28 Thread Elvina Yakubova via cfe-commits 


@@ -70,6 +70,10 @@ static std::unique_ptr
 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() {
   llvm::ErrorOr> Text =
   llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
+  if (const char *cpuinfoIntercept = std::getenv("LLVM_CPUINFO")) {

ElvinaYakubova wrote:

Thanks, changed that

https://github.com/llvm/llvm-project/pull/97749
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[clang] [llvm] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)

2024-10-28 Thread Elvina Yakubova via cfe-commits 

ElvinaYakubova wrote:

Sorry for the delays in response. I addressed the comments and rebased the 
branch

https://github.com/llvm/llvm-project/pull/97749
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[clang] [llvm] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)

2024-10-28 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova updated 
https://github.com/llvm/llvm-project/pull/97749

>From e46cbb0dd668f8be6b93c1b9adee671b995fa478 Mon Sep 17 00:00:00 2001
From: Neil Hickey 
Date: Wed, 3 Jul 2024 07:22:46 -0700
Subject: [PATCH 1/2] [AArch64] Add getHostCPUFeatures to query for enabled
 features in cpuinfo

---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index f083e40df13144..1e2ac4e501bafd 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,15 +135,21 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, 
StringRef March,
   return true;
 }
 
-static bool
-getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu,
-   const ArgList &Args,
-   llvm::AArch64::ExtensionSet &Extensions) {
+static bool getAArch64ArchFeaturesFromMcpu(
+const Driver &D, StringRef Mcpu, const ArgList &Args,
+llvm::AArch64::ExtensionSet &Extensions, std::vector &Features) 
{
   StringRef CPU;
   std::string McpuLowerCase = Mcpu.lower();
   if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions))
 return false;
 
+  if (Mcpu == "native") {
+llvm::StringMap HostFeatures = llvm::sys::getHostCPUFeatures();
+for (auto &[Feature, Enabled] : HostFeatures) {
+  Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature));
+}
+  }
+
   return true;
 }
 
@@ -210,11 +216,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
 success =
 getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions);
   else if ((A = Args.getLastArg(options::OPT_mcpu_EQ)))
-success =
-getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions);
+success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, 
Extensions,
+ Features);
   else if (isCPUDeterminedByTriple(Triple))
 success = getAArch64ArchFeaturesFromMcpu(
-D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions);
+D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions, Features);
   else
 // Default to 'A' profile if the architecture is not specified.
 success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions);

>From faceffdac240f80e8f21ca3a35daa6fa8ac16a06 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Tue, 8 Oct 2024 03:48:51 +0530
Subject: [PATCH 2/2] [clang][AArch64] Add LLVM_CPUINFO environment variable

Add LLVM_CPUINFO environment variable to test mock /proc/cpuinfo
files for -mcpu=native
---
 clang/test/Driver/Inputs/cpunative/cortex-a57 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a72 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a76 |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-n1  |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-v2  |   8 +
 clang/test/Driver/aarch64-mcpu-native.c   | 137 ++
 llvm/lib/TargetParser/Host.cpp|  10 +-
 7 files changed, 184 insertions(+), 3 deletions(-)
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a57
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a72
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a76
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-n1
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-v2
 create mode 100644 clang/test/Driver/aarch64-mcpu-native.c

diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a57 
b/clang/test/Driver/Inputs/cpunative/cortex-a57
new file mode 100644
index 00..e1903012ab79cc
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a57
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 200.00
+Features: fp asimd evtstrm crc32 cpuid
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd07
+CPU revision: 1
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a72 
b/clang/test/Driver/Inputs/cpunative/cortex-a72
new file mode 100644
index 00..7aed4a6fa73236
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a72
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 250.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid asimdrdm
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part: 0xd08
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a76 
b/clang/test/Driver/Inputs/cpunative/cortex-a76
new file mode 100644
index 00..21822cfcec60b0
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a76
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 500.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm ssbs jscvt fcma
+CPU implementer : 0x41
+CPU architecture: 8
+CPU var

[clang] [llvm] Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (PR #115467)

2024-11-12 Thread Elvina Yakubova via cfe-commits 

ElvinaYakubova wrote:

Oh yes, you were right, thanks for the explanation. 
I modified the test to run it only in case the host is AArch64.

https://github.com/llvm/llvm-project/pull/115467
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[clang] [llvm] Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (PR #115467)

2024-11-12 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova updated 
https://github.com/llvm/llvm-project/pull/115467

>From 8453bd11fa366b4865dce64b55d2a548c8b74a42 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Fri, 8 Nov 2024 03:11:44 -0800
Subject: [PATCH 1/3] Reland [clang][AArch64] Add getHostCPUFeatures to query
 for enabled features in cpu info

---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp  |  20 ++-
 clang/test/Driver/Inputs/cpunative/cortex-a57 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a72 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a76 |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-n1  |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-v2  |   8 +
 clang/test/Driver/aarch64-mcpu-native.c   | 138 ++
 clang/test/lit.cfg.py |   3 +
 llvm/lib/TargetParser/Host.cpp|  10 +-
 9 files changed, 201 insertions(+), 10 deletions(-)
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a57
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a72
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a76
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-n1
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-v2
 create mode 100644 clang/test/Driver/aarch64-mcpu-native.c

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index f083e40df13144..1e2ac4e501bafd 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,15 +135,21 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, 
StringRef March,
   return true;
 }
 
-static bool
-getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu,
-   const ArgList &Args,
-   llvm::AArch64::ExtensionSet &Extensions) {
+static bool getAArch64ArchFeaturesFromMcpu(
+const Driver &D, StringRef Mcpu, const ArgList &Args,
+llvm::AArch64::ExtensionSet &Extensions, std::vector &Features) 
{
   StringRef CPU;
   std::string McpuLowerCase = Mcpu.lower();
   if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions))
 return false;
 
+  if (Mcpu == "native") {
+llvm::StringMap HostFeatures = llvm::sys::getHostCPUFeatures();
+for (auto &[Feature, Enabled] : HostFeatures) {
+  Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature));
+}
+  }
+
   return true;
 }
 
@@ -210,11 +216,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
 success =
 getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions);
   else if ((A = Args.getLastArg(options::OPT_mcpu_EQ)))
-success =
-getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions);
+success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, 
Extensions,
+ Features);
   else if (isCPUDeterminedByTriple(Triple))
 success = getAArch64ArchFeaturesFromMcpu(
-D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions);
+D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions, Features);
   else
 // Default to 'A' profile if the architecture is not specified.
 success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions);
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a57 
b/clang/test/Driver/Inputs/cpunative/cortex-a57
new file mode 100644
index 00..e1903012ab79cc
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a57
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 200.00
+Features: fp asimd evtstrm crc32 cpuid
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd07
+CPU revision: 1
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a72 
b/clang/test/Driver/Inputs/cpunative/cortex-a72
new file mode 100644
index 00..7aed4a6fa73236
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a72
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 250.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid asimdrdm
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part: 0xd08
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a76 
b/clang/test/Driver/Inputs/cpunative/cortex-a76
new file mode 100644
index 00..21822cfcec60b0
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a76
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 500.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm ssbs jscvt fcma
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd0b
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/neoverse-n1 
b/clang/test/Driver/Inputs/cpunative/neoverse-n1
new file mode 100644
index 00..571e8840b09f08
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/neoverse

[clang] [llvm] Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (PR #115467)

2024-11-13 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova closed 
https://github.com/llvm/llvm-project/pull/115467
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[clang] [llvm] Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (PR #115467)

2024-11-12 Thread Elvina Yakubova via cfe-commits 

ElvinaYakubova wrote:

@davemgreen all tests are shown as passed, and I noticed the same failure on 
some other PRs. Can this be an infrastructure problem then? 
Regarding the original error - it was showing "unsupported argument 'native' to 
option '-mcpu='" for the cases where the target was AArch64 and the host was 
X86, that's why I added a check to compare host and target. And also there was 
a crash for Darwin systems, since we added this feature only for AArch64+linux 
case.

https://github.com/llvm/llvm-project/pull/115467
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[clang] [llvm] Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (PR #115467)

2024-11-12 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova updated 
https://github.com/llvm/llvm-project/pull/115467

>From 8453bd11fa366b4865dce64b55d2a548c8b74a42 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Fri, 8 Nov 2024 03:11:44 -0800
Subject: [PATCH 1/2] Reland [clang][AArch64] Add getHostCPUFeatures to query
 for enabled features in cpu info

---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp  |  20 ++-
 clang/test/Driver/Inputs/cpunative/cortex-a57 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a72 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a76 |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-n1  |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-v2  |   8 +
 clang/test/Driver/aarch64-mcpu-native.c   | 138 ++
 clang/test/lit.cfg.py |   3 +
 llvm/lib/TargetParser/Host.cpp|  10 +-
 9 files changed, 201 insertions(+), 10 deletions(-)
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a57
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a72
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a76
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-n1
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-v2
 create mode 100644 clang/test/Driver/aarch64-mcpu-native.c

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index f083e40df13144..1e2ac4e501bafd 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,15 +135,21 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, 
StringRef March,
   return true;
 }
 
-static bool
-getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu,
-   const ArgList &Args,
-   llvm::AArch64::ExtensionSet &Extensions) {
+static bool getAArch64ArchFeaturesFromMcpu(
+const Driver &D, StringRef Mcpu, const ArgList &Args,
+llvm::AArch64::ExtensionSet &Extensions, std::vector &Features) 
{
   StringRef CPU;
   std::string McpuLowerCase = Mcpu.lower();
   if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions))
 return false;
 
+  if (Mcpu == "native") {
+llvm::StringMap HostFeatures = llvm::sys::getHostCPUFeatures();
+for (auto &[Feature, Enabled] : HostFeatures) {
+  Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature));
+}
+  }
+
   return true;
 }
 
@@ -210,11 +216,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
 success =
 getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions);
   else if ((A = Args.getLastArg(options::OPT_mcpu_EQ)))
-success =
-getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions);
+success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, 
Extensions,
+ Features);
   else if (isCPUDeterminedByTriple(Triple))
 success = getAArch64ArchFeaturesFromMcpu(
-D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions);
+D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions, Features);
   else
 // Default to 'A' profile if the architecture is not specified.
 success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions);
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a57 
b/clang/test/Driver/Inputs/cpunative/cortex-a57
new file mode 100644
index 00..e1903012ab79cc
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a57
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 200.00
+Features: fp asimd evtstrm crc32 cpuid
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd07
+CPU revision: 1
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a72 
b/clang/test/Driver/Inputs/cpunative/cortex-a72
new file mode 100644
index 00..7aed4a6fa73236
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a72
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 250.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid asimdrdm
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part: 0xd08
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a76 
b/clang/test/Driver/Inputs/cpunative/cortex-a76
new file mode 100644
index 00..21822cfcec60b0
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a76
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 500.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm ssbs jscvt fcma
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd0b
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/neoverse-n1 
b/clang/test/Driver/Inputs/cpunative/neoverse-n1
new file mode 100644
index 00..571e8840b09f08
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/neoverse

[clang] [llvm] Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (PR #115467)

2024-11-12 Thread Elvina Yakubova via cfe-commits 


@@ -210,6 +210,9 @@ def have_host_clang_repl_cuda():
 config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%host_cxx", config.host_cxx))
 
+# Determine whether the test target is compatible with execution on the host.
+if config.host_arch in config.target_triple:
+config.available_features.add("host-arch-compatible")

ElvinaYakubova wrote:

Thanks for the suggestion, renamed it 

https://github.com/llvm/llvm-project/pull/115467
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[clang] [llvm] [CMake] Preserve clang-prebolt (PR #109351)

2024-09-23 Thread Elvina Yakubova via cfe-commits 

ElvinaYakubova wrote:

@aaupov this happens on AArch64 target, and only with -split-strategy=cdsplit 
enabled. Changing it to profile2, for example, fixes the issue

https://github.com/llvm/llvm-project/pull/109351
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[clang] [llvm] Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (PR #115467)

2024-11-08 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova created 
https://github.com/llvm/llvm-project/pull/115467

…eatures in cpu info

>From 8453bd11fa366b4865dce64b55d2a548c8b74a42 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Fri, 8 Nov 2024 03:11:44 -0800
Subject: [PATCH] Reland [clang][AArch64] Add getHostCPUFeatures to query for
 enabled features in cpu info

---
 clang/lib/Driver/ToolChains/Arch/AArch64.cpp  |  20 ++-
 clang/test/Driver/Inputs/cpunative/cortex-a57 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a72 |   8 +
 clang/test/Driver/Inputs/cpunative/cortex-a76 |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-n1  |   8 +
 .../test/Driver/Inputs/cpunative/neoverse-v2  |   8 +
 clang/test/Driver/aarch64-mcpu-native.c   | 138 ++
 clang/test/lit.cfg.py |   3 +
 llvm/lib/TargetParser/Host.cpp|  10 +-
 9 files changed, 201 insertions(+), 10 deletions(-)
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a57
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a72
 create mode 100644 clang/test/Driver/Inputs/cpunative/cortex-a76
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-n1
 create mode 100644 clang/test/Driver/Inputs/cpunative/neoverse-v2
 create mode 100644 clang/test/Driver/aarch64-mcpu-native.c

diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index f083e40df13144..1e2ac4e501bafd 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -135,15 +135,21 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, 
StringRef March,
   return true;
 }
 
-static bool
-getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu,
-   const ArgList &Args,
-   llvm::AArch64::ExtensionSet &Extensions) {
+static bool getAArch64ArchFeaturesFromMcpu(
+const Driver &D, StringRef Mcpu, const ArgList &Args,
+llvm::AArch64::ExtensionSet &Extensions, std::vector &Features) 
{
   StringRef CPU;
   std::string McpuLowerCase = Mcpu.lower();
   if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions))
 return false;
 
+  if (Mcpu == "native") {
+llvm::StringMap HostFeatures = llvm::sys::getHostCPUFeatures();
+for (auto &[Feature, Enabled] : HostFeatures) {
+  Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature));
+}
+  }
+
   return true;
 }
 
@@ -210,11 +216,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
 success =
 getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions);
   else if ((A = Args.getLastArg(options::OPT_mcpu_EQ)))
-success =
-getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions);
+success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, 
Extensions,
+ Features);
   else if (isCPUDeterminedByTriple(Triple))
 success = getAArch64ArchFeaturesFromMcpu(
-D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions);
+D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions, Features);
   else
 // Default to 'A' profile if the architecture is not specified.
 success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions);
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a57 
b/clang/test/Driver/Inputs/cpunative/cortex-a57
new file mode 100644
index 00..e1903012ab79cc
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a57
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 200.00
+Features: fp asimd evtstrm crc32 cpuid
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd07
+CPU revision: 1
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a72 
b/clang/test/Driver/Inputs/cpunative/cortex-a72
new file mode 100644
index 00..7aed4a6fa73236
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a72
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 250.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid asimdrdm
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part: 0xd08
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a76 
b/clang/test/Driver/Inputs/cpunative/cortex-a76
new file mode 100644
index 00..21822cfcec60b0
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/cortex-a76
@@ -0,0 +1,8 @@
+processor   : 0
+BogoMIPS: 500.00
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid 
asimdrdm ssbs jscvt fcma
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x1
+CPU part: 0xd0b
+CPU revision: 2
diff --git a/clang/test/Driver/Inputs/cpunative/neoverse-n1 
b/clang/test/Driver/Inputs/cpunative/neoverse-n1
new file mode 100644
index 00..571e8840b09f08
--- /dev/null
+++ b/clang/test/Driver/Inputs/

[clang] [llvm] Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (PR #115467)

2024-11-08 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova edited 
https://github.com/llvm/llvm-project/pull/115467
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[clang] [llvm] [AArch64] Add optional extensions enabled on Grace (PR #127620)

2025-02-19 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova updated 
https://github.com/llvm/llvm-project/pull/127620

>From 814aace81379e6e95fd83a3384fd52e11730a5ac Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Thu, 13 Feb 2025 05:45:21 -0800
Subject: [PATCH] [AArch64] Add optional extensions enabled on Grace

Enable optional ISA extensions on Grace when mcpu=grace
is used: sve2-sm4, sve2-aes, sve2-sha3.

Grace is no longer an alias, but a separate CPU definition.
---
 clang/test/Driver/aarch64-mcpu.c  |  2 +-
 .../print-enabled-extensions/aarch64-grace.c  | 62 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  |  5 +-
 llvm/test/CodeGen/AArch64/cpus.ll |  1 +
 .../TargetParser/TargetParserTest.cpp |  2 +-
 5 files changed, 68 insertions(+), 4 deletions(-)
 create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-grace.c

diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 97303510d6881..447ee4bd3a6f9 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -92,7 +92,7 @@
 // COBALT-100: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
 
 // RUN: %clang --target=aarch64 -mcpu=grace -### -c %s 2>&1 | FileCheck 
-check-prefix=GRACE %s
-// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v2"
+// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "grace"
 
 // == Check whether -mcpu and -mtune accept mixed-case values.
 // RUN: %clang --target=aarch64 -mcpu=Cortex-a53 -### -c %s 2>&1 | FileCheck 
-check-prefix=CASE-INSENSITIVE-CA53 %s
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c 
b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
new file mode 100644
index 0..fde6aee468cdc
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
@@ -0,0 +1,62 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=grace | 
FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s)
Description
+// CHECK-NEXT: FEAT_AES, FEAT_PMULL   
Enable AES support
+// CHECK-NEXT: FEAT_AMUv1 
Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AdvSIMD   
Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16  
Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI   
Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX 
Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CRC32 
Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2
Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_DIT   
Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB   
Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2  
Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd   
Enable dot product support
+// CHECK-NEXT: FEAT_ETE   
Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FCMA  
Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FHM   
Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16  
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FRINTTS   
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an 
integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM 
Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_I8MM  
Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT 
Enable Armv8.3-A JavaScript FP conversion instructions
+// CHE

[clang] [llvm] [AArch64] Add optional extensions enabled on Grace (PR #127620)

2025-02-19 Thread Elvina Yakubova via cfe-commits 

ElvinaYakubova wrote:

Thanks, addressed Dave's comment

https://github.com/llvm/llvm-project/pull/127620
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[clang] [llvm] [AArch64] Add optional extensions enabled on Grace (PR #127620)

2025-02-19 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova closed 
https://github.com/llvm/llvm-project/pull/127620
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[clang] [llvm] [AArch64] Add optional extensions enabled on Grace (PR #127620)

2025-02-18 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova edited 
https://github.com/llvm/llvm-project/pull/127620
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[clang] [llvm] [AArch64] Add optional extensions enabled on Grace (PR #127620)

2025-02-18 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova updated 
https://github.com/llvm/llvm-project/pull/127620

>From 4c29499a36117ab9681f99a16e017b33c2322317 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Thu, 13 Feb 2025 05:45:21 -0800
Subject: [PATCH] [AArch64] Add optional extensions enabled on Grace

Enable optional ISA extensions on Grace when mcpu=grace
is used: aes, sha2, sve2-sm4, sve2-aes, sve2-sha3.

Grace is no longer an alias, but a separate CPU definition.
---
 clang/test/Driver/aarch64-mcpu.c  |  2 +-
 .../print-enabled-extensions/aarch64-grace.c  | 62 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  |  6 +-
 llvm/test/CodeGen/AArch64/cpus.ll |  1 +
 .../TargetParser/TargetParserTest.cpp |  2 +-
 5 files changed, 69 insertions(+), 4 deletions(-)
 create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-grace.c

diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 97303510d6881..447ee4bd3a6f9 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -92,7 +92,7 @@
 // COBALT-100: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
 
 // RUN: %clang --target=aarch64 -mcpu=grace -### -c %s 2>&1 | FileCheck 
-check-prefix=GRACE %s
-// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v2"
+// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "grace"
 
 // == Check whether -mcpu and -mtune accept mixed-case values.
 // RUN: %clang --target=aarch64 -mcpu=Cortex-a53 -### -c %s 2>&1 | FileCheck 
-check-prefix=CASE-INSENSITIVE-CA53 %s
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c 
b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
new file mode 100644
index 0..fde6aee468cdc
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
@@ -0,0 +1,62 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=grace | 
FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s)
Description
+// CHECK-NEXT: FEAT_AES, FEAT_PMULL   
Enable AES support
+// CHECK-NEXT: FEAT_AMUv1 
Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AdvSIMD   
Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16  
Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI   
Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX 
Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CRC32 
Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2
Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_DIT   
Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB   
Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2  
Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd   
Enable dot product support
+// CHECK-NEXT: FEAT_ETE   
Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FCMA  
Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FHM   
Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16  
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FRINTTS   
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an 
integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM 
Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_I8MM  
Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT 
Enable Armv8.3-A JavaScript FP conversion instructi

[clang] [llvm] [AArch64] Add optional extensions enabled on Grace (PR #127620)

2025-02-18 Thread Elvina Yakubova via cfe-commits 


@@ -944,6 +944,15 @@ def ProcessorFeatures {
   list Falkor   = [HasV8_0aOps, FeatureCRC, FeatureSHA2, 
FeatureAES,
  FeatureFPARMv8, FeatureNEON, 
FeaturePerfMon,
  FeatureRDM];
+  list Grace=  [HasV9_0aOps, FeatureBF16, FeatureSPE,

ElvinaYakubova wrote:

Thanks a lot, it looks much better with !listconcat 

https://github.com/llvm/llvm-project/pull/127620
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[clang] [llvm] [AArch64] Add optional extensions enabled on Grace (PR #127620)

2025-02-18 Thread Elvina Yakubova via cfe-commits 

https://github.com/ElvinaYakubova created 
https://github.com/llvm/llvm-project/pull/127620

Enable optional ISA extensions on Grace when mcpu=grace is used

>From 9be1c6f17270507343e564afb21ffa49d84f2c58 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova 
Date: Thu, 13 Feb 2025 05:45:21 -0800
Subject: [PATCH] [AArch64] Add optional extensions enabled on Grace

Enable optional ISA extensions on Grace when mcpu=grace is used
---
 clang/test/Driver/aarch64-mcpu.c  |  2 +-
 .../print-enabled-extensions/aarch64-grace.c  | 63 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 12 +++-
 llvm/test/CodeGen/AArch64/cpus.ll |  1 +
 .../TargetParser/TargetParserTest.cpp |  1 +
 5 files changed, 77 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-grace.c

diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 97303510d6881..447ee4bd3a6f9 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -92,7 +92,7 @@
 // COBALT-100: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
 
 // RUN: %clang --target=aarch64 -mcpu=grace -### -c %s 2>&1 | FileCheck 
-check-prefix=GRACE %s
-// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v2"
+// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "grace"
 
 // == Check whether -mcpu and -mtune accept mixed-case values.
 // RUN: %clang --target=aarch64 -mcpu=Cortex-a53 -### -c %s 2>&1 | FileCheck 
-check-prefix=CASE-INSENSITIVE-CA53 %s
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c 
b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
new file mode 100644
index 0..8fb9a21ac18d4
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
@@ -0,0 +1,63 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=grace | 
FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s)
Description
+// CHECK-NEXT: FEAT_AES, FEAT_PMULL   
Enable AES support
+// CHECK-NEXT: FEAT_AMUv1 
Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AdvSIMD   
Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16  
Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI   
Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX 
Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CRC32 
Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2
Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_Crypto
Enable cryptographic instructions
+// CHECK-NEXT: FEAT_DIT   
Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB   
Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2  
Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd   
Enable dot product support
+// CHECK-NEXT: FEAT_ETE   
Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FCMA  
Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FHM   
Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16  
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FRINTTS   
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an 
integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM 
Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_I8MM  
Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT