https://github.com/ElvinaYakubova updated
https://github.com/llvm/llvm-project/pull/127620
>From 4c29499a36117ab9681f99a16e017b33c2322317 Mon Sep 17 00:00:00 2001
From: Elvina Yakubova <eyakub...@nvidia.com>
Date: Thu, 13 Feb 2025 05:45:21 -0800
Subject: [PATCH] [AArch64] Add optional extensions enabled on Grace
Enable optional ISA extensions on Grace when mcpu=grace
is used: aes, sha2, sve2-sm4, sve2-aes, sve2-sha3.
Grace is no longer an alias, but a separate CPU definition.
---
clang/test/Driver/aarch64-mcpu.c | 2 +-
.../print-enabled-extensions/aarch64-grace.c | 62 +++++++++++++++++++
llvm/lib/Target/AArch64/AArch64Processors.td | 6 +-
llvm/test/CodeGen/AArch64/cpus.ll | 1 +
.../TargetParser/TargetParserTest.cpp | 2 +-
5 files changed, 69 insertions(+), 4 deletions(-)
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-grace.c
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 97303510d6881..447ee4bd3a6f9 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -92,7 +92,7 @@
// COBALT-100: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"neoverse-n2"
// RUN: %clang --target=aarch64 -mcpu=grace -### -c %s 2>&1 | FileCheck
-check-prefix=GRACE %s
-// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v2"
+// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "grace"
// ================== Check whether -mcpu and -mtune accept mixed-case values.
// RUN: %clang --target=aarch64 -mcpu=Cortex-a53 -### -c %s 2>&1 | FileCheck
-check-prefix=CASE-INSENSITIVE-CA53 %s
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
new file mode 100644
index 0000000000000..fde6aee468cdc
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
@@ -0,0 +1,62 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=grace |
FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s)
Description
+// CHECK-NEXT: FEAT_AES, FEAT_PMULL
Enable AES support
+// CHECK-NEXT: FEAT_AMUv1
Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AdvSIMD
Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16
Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI
Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX
Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CRC32
Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2
Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_DIT
Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB
Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2
Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd
Enable dot product support
+// CHECK-NEXT: FEAT_ETE
Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FCMA
Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FHM
Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP
Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16
Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FRINTTS
Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an
integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM
Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2
Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_I8MM
Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT
Enable Armv8.3-A JavaScript FP conversion instructions
+// CHECK-NEXT: FEAT_LOR
Enable Armv8.1-A Limited Ordering Regions extension
+// CHECK-NEXT: FEAT_LRCPC
Enable support for RCPC extension
+// CHECK-NEXT: FEAT_LRCPC2
Enable Armv8.4-A RCPC instructions with Immediate Offsets
+// CHECK-NEXT: FEAT_LSE
Enable Armv8.1-A Large System Extension (LSE) atomic instructions
+// CHECK-NEXT: FEAT_LSE2
Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
+// CHECK-NEXT: FEAT_MPAM
Enable Armv8.4-A Memory system Partitioning and Monitoring extension
+// CHECK-NEXT: FEAT_MTE, FEAT_MTE2
Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_NV, FEAT_NV2
Enable Armv8.4-A Nested Virtualization Enchancement
+// CHECK-NEXT: FEAT_PAN
Enable Armv8.1-A Privileged Access-Never extension
+// CHECK-NEXT: FEAT_PAN2
Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PAuth
Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMUv3
Enable Armv8.0-A PMUv3 Performance Monitors extension
+// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1
Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
+// CHECK-NEXT: FEAT_RDM
Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
+// CHECK-NEXT: FEAT_RNG
Enable Random Number generation instructions
+// CHECK-NEXT: FEAT_SB
Enable Armv8.5-A Speculation Barrier
+// CHECK-NEXT: FEAT_SEL2
Enable Armv8.4-A Secure Exception Level 2 extension
+// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256
Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512
Enable SHA512 and SHA3 support
+// CHECK-NEXT: FEAT_SM4, FEAT_SM3
Enable SM3 and SM4 support
+// CHECK-NEXT: FEAT_SPE
Enable Statistical Profiling extension
+// CHECK-NEXT: FEAT_SPECRES
Enable Armv8.5-A execution and data prediction invalidation instructions
+// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2
Enable Speculative Store Bypass Safe bit
+// CHECK-NEXT: FEAT_SVE
Enable Scalable Vector Extension (SVE) instructions
+// CHECK-NEXT: FEAT_SVE2
Enable Scalable Vector Extension 2 (SVE2) instructions
+// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128
Enable SVE AES and quadword SVE polynomial multiply instructions
+// CHECK-NEXT: FEAT_SVE_BitPerm
Enable bit permutation SVE2 instructions
+// CHECK-NEXT: FEAT_SVE_SHA3
Enable SHA3 SVE2 instructions
+// CHECK-NEXT: FEAT_SVE_SM4
Enable SM4 SVE2 instructions
+// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE
Enable Armv8.4-A TLB Range and Maintenance instructions
+// CHECK-NEXT: FEAT_TRBE
Enable Trace Buffer Extension
+// CHECK-NEXT: FEAT_TRF
Enable Armv8.4-A Trace extension
+// CHECK-NEXT: FEAT_UAO
Enable Armv8.2-A UAO PState
+// CHECK-NEXT: FEAT_VHE
Enable Armv8.1-A Virtual Host extension
\ No newline at end of file
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index b977b6aaaf619..f0e1c8a8c8fb9 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -1059,7 +1059,6 @@ def ProcessorFeatures {
FeatureJS, FeatureLSE, FeaturePAuth,
FeatureRAS, FeatureRCPC,
FeatureCCIDX,
FeatureRDM];
-
list<SubtargetFeature> Oryon = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
FeatureRandGen,
FeaturePAuth, FeatureSM4, FeatureSHA2,
@@ -1068,6 +1067,8 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8,
FeatureMatMulInt8,
FeatureSSBS, FeatureCCIDX,
FeatureJS, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM];
+ list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureAES,
FeatureSHA2, FeatureSVE2SM4,
+ FeatureSVEAES, FeatureSVE2SHA3]);
// ETE and TRBE are future architecture extensions. We temporarily enable
them
// by default for users targeting generic AArch64. The extensions do not
@@ -1151,6 +1152,8 @@ def : ProcessorModel<"cortex-x4", NeoverseV2Model,
ProcessorFeatures.X4,
[TuneX4]>;
def : ProcessorModel<"cortex-x925", NeoverseV2Model, ProcessorFeatures.X925,
[TuneX925]>;
+def : ProcessorModel<"grace", NeoverseV2Model, ProcessorFeatures.Grace,
+ [TuneNeoverseV2]>;
def : ProcessorModel<"neoverse-e1", CortexA53Model,
ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
def : ProcessorModel<"neoverse-n1", NeoverseN1Model,
@@ -1166,7 +1169,6 @@ def : ProcessorModel<"neoverse-v1", NeoverseV1Model,
ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
def : ProcessorModel<"neoverse-v2", NeoverseV2Model,
ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>;
-def : ProcessorAlias<"grace", "neoverse-v2">;
def : ProcessorModel<"neoverse-v3", NeoverseV2Model,
ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>;
def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model,
diff --git a/llvm/test/CodeGen/AArch64/cpus.ll
b/llvm/test/CodeGen/AArch64/cpus.ll
index e9722f348f411..363f0a0598e23 100644
--- a/llvm/test/CodeGen/AArch64/cpus.ll
+++ b/llvm/test/CodeGen/AArch64/cpus.ll
@@ -18,6 +18,7 @@
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a77 2>&1 |
FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a78 2>&1 |
FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-x1 2>&1 |
FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=grace 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 |
FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 |
FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n2 2>&1 |
FileCheck %s
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 93ac7381b02ef..5d771a1a153f7 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1167,6 +1167,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUTestParams("a64fx", "armv8.2-a"),
AArch64CPUTestParams("fujitsu-monaka", "armv9.3-a"),
AArch64CPUTestParams("carmel", "armv8.2-a"),
+ AArch64CPUTestParams("grace", "armv9-a"),
AArch64CPUTestParams("saphira", "armv8.4-a"),
AArch64CPUTestParams("oryon-1", "armv8.6-a")),
AArch64CPUTestParams::PrintToStringParamName);
@@ -1247,7 +1248,6 @@ TEST_P(AArch64CPUAliasTestFixture, testCPUAlias) {
INSTANTIATE_TEST_SUITE_P(
AArch64CPUAliasTests, AArch64CPUAliasTestFixture,
::testing::Values(AArch64CPUAliasTestParams({"neoverse-n2", "cobalt-100"}),
- AArch64CPUAliasTestParams({"neoverse-v2", "grace"}),
AArch64CPUAliasTestParams({"apple-a7", "cyclone",
"apple-a8", "apple-a9"}),
AArch64CPUAliasTestParams({"apple-a12", "apple-s4",
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