[PATCH] D47137: [Sparc] Add floating-point register names

2018-05-21 Thread Daniel Cederman via Phabricator via cfe-commits 
dcederman created this revision.
dcederman added a reviewer: jyknight.
Herald added subscribers: cfe-commits, jrtc27, fedor.sergeev.

Repository:
  rC Clang

https://reviews.llvm.org/D47137

Files:
  lib/Basic/Targets/Sparc.cpp


Index: lib/Basic/Targets/Sparc.cpp
===
--- lib/Basic/Targets/Sparc.cpp
+++ lib/Basic/Targets/Sparc.cpp
@@ -22,7 +22,10 @@
 const char *const SparcTargetInfo::GCCRegNames[] = {
 "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8",  "r9",  
"r10",
 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", 
"r21",
-"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",  "f8",  "f9",  
"f10",
+"f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", 
"f21",
+"f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
 };
 
 ArrayRef SparcTargetInfo::getGCCRegNames() const {


Index: lib/Basic/Targets/Sparc.cpp
===
--- lib/Basic/Targets/Sparc.cpp
+++ lib/Basic/Targets/Sparc.cpp
@@ -22,7 +22,10 @@
 const char *const SparcTargetInfo::GCCRegNames[] = {
 "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8",  "r9",  "r10",
 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
-"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",  "f8",  "f9",  "f10",
+"f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
+"f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
 };
 
 ArrayRef SparcTargetInfo::getGCCRegNames() const {
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[PATCH] D47138: [Sparc] Use the leon arch for Leon3's when using an external assembler

2018-05-21 Thread Daniel Cederman via Phabricator via cfe-commits 
dcederman created this revision.
dcederman added a reviewer: jyknight.
Herald added subscribers: cfe-commits, jrtc27, fedor.sergeev.

This allows the use of the casa instruction available in most Leon3's.


Repository:
  rC Clang

https://reviews.llvm.org/D47138

Files:
  lib/Driver/ToolChains/Arch/Sparc.cpp


Index: lib/Driver/ToolChains/Arch/Sparc.cpp
===
--- lib/Driver/ToolChains/Arch/Sparc.cpp
+++ lib/Driver/ToolChains/Arch/Sparc.cpp
@@ -48,11 +48,11 @@
 .Case("leon2", "-Av8")
 .Case("at697e", "-Av8")
 .Case("at697f", "-Av8")
-.Case("leon3", "-Av8")
+.Case("leon3", "-Aleon")
 .Case("ut699", "-Av8")
-.Case("gr712rc", "-Av8")
-.Case("leon4", "-Av8")
-.Case("gr740", "-Av8")
+.Case("gr712rc", "-Aleon")
+.Case("leon4", "-Aleon")
+.Case("gr740", "-Aleon")
 .Default("-Av8");
   }
 }


Index: lib/Driver/ToolChains/Arch/Sparc.cpp
===
--- lib/Driver/ToolChains/Arch/Sparc.cpp
+++ lib/Driver/ToolChains/Arch/Sparc.cpp
@@ -48,11 +48,11 @@
 .Case("leon2", "-Av8")
 .Case("at697e", "-Av8")
 .Case("at697f", "-Av8")
-.Case("leon3", "-Av8")
+.Case("leon3", "-Aleon")
 .Case("ut699", "-Av8")
-.Case("gr712rc", "-Av8")
-.Case("leon4", "-Av8")
-.Case("gr740", "-Av8")
+.Case("gr712rc", "-Aleon")
+.Case("leon4", "-Aleon")
+.Case("gr740", "-Aleon")
 .Default("-Av8");
   }
 }
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[PATCH] D47138: [Sparc] Use the leon arch for Leon3's when using an external assembler

2018-05-22 Thread Daniel Cederman via Phabricator via cfe-commits 
dcederman updated this revision to Diff 147965.
dcederman added a comment.

Also use the leon arch for the Myriad processors.


https://reviews.llvm.org/D47138

Files:
  lib/Driver/ToolChains/Arch/Sparc.cpp


Index: lib/Driver/ToolChains/Arch/Sparc.cpp
===
--- lib/Driver/ToolChains/Arch/Sparc.cpp
+++ lib/Driver/ToolChains/Arch/Sparc.cpp
@@ -45,14 +45,29 @@
 .Case("niagara2", "-Av8plusb")
 .Case("niagara3", "-Av8plusd")
 .Case("niagara4", "-Av8plusd")
+.Case("ma2100", "-Aleon")
+.Case("ma2150", "-Aleon")
+.Case("ma2155", "-Aleon")
+.Case("ma2450", "-Aleon")
+.Case("ma2455", "-Aleon")
+.Case("ma2x5x", "-Aleon")
+.Case("ma2080", "-Aleon")
+.Case("ma2085", "-Aleon")
+.Case("ma2480", "-Aleon")
+.Case("ma2485", "-Aleon")
+.Case("ma2x8x", "-Aleon")
+.Case("myriad2", "-Aleon")
+.Case("myriad2.1", "-Aleon")
+.Case("myriad2.2", "-Aleon")
+.Case("myriad2.3", "-Aleon")
 .Case("leon2", "-Av8")
 .Case("at697e", "-Av8")
 .Case("at697f", "-Av8")
-.Case("leon3", "-Av8")
+.Case("leon3", "-Aleon")
 .Case("ut699", "-Av8")
-.Case("gr712rc", "-Av8")
-.Case("leon4", "-Av8")
-.Case("gr740", "-Av8")
+.Case("gr712rc", "-Aleon")
+.Case("leon4", "-Aleon")
+.Case("gr740", "-Aleon")
 .Default("-Av8");
   }
 }


Index: lib/Driver/ToolChains/Arch/Sparc.cpp
===
--- lib/Driver/ToolChains/Arch/Sparc.cpp
+++ lib/Driver/ToolChains/Arch/Sparc.cpp
@@ -45,14 +45,29 @@
 .Case("niagara2", "-Av8plusb")
 .Case("niagara3", "-Av8plusd")
 .Case("niagara4", "-Av8plusd")
+.Case("ma2100", "-Aleon")
+.Case("ma2150", "-Aleon")
+.Case("ma2155", "-Aleon")
+.Case("ma2450", "-Aleon")
+.Case("ma2455", "-Aleon")
+.Case("ma2x5x", "-Aleon")
+.Case("ma2080", "-Aleon")
+.Case("ma2085", "-Aleon")
+.Case("ma2480", "-Aleon")
+.Case("ma2485", "-Aleon")
+.Case("ma2x8x", "-Aleon")
+.Case("myriad2", "-Aleon")
+.Case("myriad2.1", "-Aleon")
+.Case("myriad2.2", "-Aleon")
+.Case("myriad2.3", "-Aleon")
 .Case("leon2", "-Av8")
 .Case("at697e", "-Av8")
 .Case("at697f", "-Av8")
-.Case("leon3", "-Av8")
+.Case("leon3", "-Aleon")
 .Case("ut699", "-Av8")
-.Case("gr712rc", "-Av8")
-.Case("leon4", "-Av8")
-.Case("gr740", "-Av8")
+.Case("gr712rc", "-Aleon")
+.Case("leon4", "-Aleon")
+.Case("gr740", "-Aleon")
 .Default("-Av8");
   }
 }
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[PATCH] D47138: [Sparc] Use the leon arch for Leon3's when using an external assembler

2018-05-22 Thread Daniel Cederman via Phabricator via cfe-commits 
dcederman added a comment.

In https://reviews.llvm.org/D47138#1106509, @jyknight wrote:

> Separately, I think it'd be a good idea to refactor to put this info into the 
> SparcCPUInfo struct, so that it's harder for them to get out of sync.


I did not find a good way to access the SparcCPUInfo struct from here. No other 
arch under Toolchains seems to access TargetInfo.


https://reviews.llvm.org/D47138



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[PATCH] D47138: [Sparc] Use the leon arch for Leon3's when using an external assembler

2018-05-23 Thread Daniel Cederman via Phabricator via cfe-commits 
dcederman updated this revision to Diff 148170.
dcederman added a comment.

Added missing tests.


https://reviews.llvm.org/D47138

Files:
  lib/Driver/ToolChains/Arch/Sparc.cpp
  test/Driver/sparc-as.c

Index: test/Driver/sparc-as.c
===
--- test/Driver/sparc-as.c
+++ test/Driver/sparc-as.c
@@ -76,6 +76,66 @@
 // RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
 // RUN: | FileCheck -check-prefix=SPARC-V8PLUSD %s
 
+// RUN: %clang -mcpu=ma2100 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2150 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2155 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2450 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2455 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2x5x -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2080 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2085 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2480 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2485 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2x8x -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=myriad2 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=myriad2.1 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=myriad2.2 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=myriad2.3 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
 // RUN: %clang -mcpu=leon2 -no-canonical-prefixes -target sparc \
 // RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
 // RUN: | FileCheck -check-prefix=SPARC-V8 %s
@@ -90,26 +150,27 @@
 
 // RUN: %clang -mcpu=leon3 -no-canonical-prefixes -target sparc \
 // RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
-// RUN: | FileCheck -check-prefix=SPARC-V8 %s
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
 
 // RUN: %clang -mcpu=ut699 -no-canonical-prefixes -target sparc \
 // RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
 // RUN: | FileCheck -check-prefix=SPARC-V8 %s
 
 // RUN: %clang -mcpu=gr712rc -no-canonical-prefixes -target sparc \
 // RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
-// RUN: | FileCheck -check-prefix=SPARC-V8 %s
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
 
 // RUN: %clang -mcpu=leon4 -no-canonical-prefixes -target sparc \
 // RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
-// RUN: | FileCheck -check-prefix=SPARC-V8 %s
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
 
 // RUN: %clang -mcpu=gr740 -no-canonical-prefixes -target sparc \
 // RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
-// RUN: | FileCheck -check-prefix=SPARC-V8 %s
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
 
 // SPARC: as{{.*}}" "-32" "-Av8" "-o"
 // SPARC-V8: as{{.*}}" "-32" "-Av8" "-o"
+// SPARC-LEON: as{

[PATCH] D47137: [Sparc] Add floating-point register names

2018-05-23 Thread Daniel Cederman via Phabricator via cfe-commits 
dcederman updated this revision to Diff 148205.
dcederman added a comment.
Herald added a subscriber: eraman.

Added test cases, f32-f63,  d0-d31, and q0-q15.


https://reviews.llvm.org/D47137

Files:
  lib/Basic/Targets/Sparc.cpp
  test/CodeGen/sparcv8-inline-asm.c
  test/CodeGen/sparcv9-inline-asm.c

Index: test/CodeGen/sparcv9-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/sparcv9-inline-asm.c
@@ -0,0 +1,40 @@
+// RUN: %clang_cc1 -triple sparcv9-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+void test_gcc_registers(void) {
+register unsigned int regO6 asm("o6") = 0;
+register unsigned int regSP asm("sp") = 1;
+register unsigned int reg14 asm("r14") = 2;
+register unsigned int regI6 asm("i6") = 3;
+register unsigned int regFP asm("fp") = 4;
+register unsigned int reg30 asm("r30") = 5;
+
+register float fQ5 asm("q5") = 6.0;
+register float fD10 asm("d10") = 7.0;
+register float fF20 asm("f20") = 8.0;
+
+register double dQ10 asm("q10") = 9.0;
+register double dD20 asm("d20") = 10.0;
+register double dF40 asm("f40") = 11.0;
+
+register long double qQ10 asm("q10") = 12.0;
+register long double qD20 asm("d20") = 13.0;
+register long double qF40 asm("f40") = 14.0;
+
+// Test remapping register names in register ... asm("rN") statments.
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
+asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
+asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
+
+// CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("fadds %0,%1,%2" : : "f" (fQ5), "f" (fD10), "f"(fF20));
+
+// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f40},{f40},{f40}"
+asm volatile("faddd %0,%1,%2" : : "f" (dQ10), "f" (dD20), "f"(dF40));
+
+// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"
+asm volatile("faddq %0,%1,%2" : : "f" (qQ10), "f" (qD20), "f"(qF40));
+
+}
Index: test/CodeGen/sparcv8-inline-asm.c
===
--- test/CodeGen/sparcv8-inline-asm.c
+++ test/CodeGen/sparcv8-inline-asm.c
@@ -1,11 +1,50 @@
 // RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
 
 // CHECK: define float @fabsf(float %a)
-// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}}) #1
+// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}})
 float fabsf(float a) {
   float res;
   __asm __volatile__("fabss  %1, %0;"
  : /* reg out*/ "=e"(res)
  : /* reg in */ "f"(a));
   return res;
 }
+
+void test_gcc_registers(void) {
+register unsigned int regO6 asm("o6") = 0;
+register unsigned int regSP asm("sp") = 1;
+register unsigned int reg14 asm("r14") = 2;
+register unsigned int regI6 asm("i6") = 3;
+register unsigned int regFP asm("fp") = 4;
+register unsigned int reg30 asm("r30") = 5;
+
+register float fQ5 asm("q5") = 6.0;
+register float fD10 asm("d10") = 7.0;
+register float fF20 asm("f20") = 8.0;
+
+register double dQ5 asm("q5") = 9.0;
+register double dD10 asm("d10") = 10.0;
+register double dF20 asm("f20") = 11.0;
+
+register long double qQ5 asm("q5") = 12.0;
+register long double qD10 asm("d10") = 13.0;
+register long double qF20 asm("f20") = 14.0;
+
+// Test remapping register names in register ... asm("rN") statments.
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
+asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
+asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
+
+ // CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("fadds %0,%1,%2" : : "f" (fQ5), "f" (fD10), "f"(fF20));
+
+// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("faddd %0,%1,%2" : : "f" (dQ5), "f" (dD10), "f"(dF20));
+
+// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("faddq %0,%1,%2" : : "f" (qQ5), "f" (qD10), "f"(qF20));
+
+}
Index: lib/Basic/Targets/Sparc.cpp
===
--- lib/Basic/Targets/Sparc.cpp
+++ lib/Basic/Targets/Sparc.cpp
@@ -20,24 +20,50 @@
 using namespace clang::targets;
 
 const char *const SparcTargetInfo::GCCRegNames[] = {
+// Integer registers
 "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8",  "r9",  "r10",
 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
-"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+"r

[PATCH] D47138: [Sparc] Use the leon arch for Leon3's when using an external assembler

2018-05-23 Thread Daniel Cederman via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rC333157:  [Sparc] Use the leon arch for Leon3's when 
using an external assembler (authored by dcederman, committed by ).

Repository:
  rC Clang

https://reviews.llvm.org/D47138

Files:
  lib/Driver/ToolChains/Arch/Sparc.cpp
  test/Driver/sparc-as.c

Index: lib/Driver/ToolChains/Arch/Sparc.cpp
===
--- lib/Driver/ToolChains/Arch/Sparc.cpp
+++ lib/Driver/ToolChains/Arch/Sparc.cpp
@@ -45,14 +45,29 @@
 .Case("niagara2", "-Av8plusb")
 .Case("niagara3", "-Av8plusd")
 .Case("niagara4", "-Av8plusd")
+.Case("ma2100", "-Aleon")
+.Case("ma2150", "-Aleon")
+.Case("ma2155", "-Aleon")
+.Case("ma2450", "-Aleon")
+.Case("ma2455", "-Aleon")
+.Case("ma2x5x", "-Aleon")
+.Case("ma2080", "-Aleon")
+.Case("ma2085", "-Aleon")
+.Case("ma2480", "-Aleon")
+.Case("ma2485", "-Aleon")
+.Case("ma2x8x", "-Aleon")
+.Case("myriad2", "-Aleon")
+.Case("myriad2.1", "-Aleon")
+.Case("myriad2.2", "-Aleon")
+.Case("myriad2.3", "-Aleon")
 .Case("leon2", "-Av8")
 .Case("at697e", "-Av8")
 .Case("at697f", "-Av8")
-.Case("leon3", "-Av8")
+.Case("leon3", "-Aleon")
 .Case("ut699", "-Av8")
-.Case("gr712rc", "-Av8")
-.Case("leon4", "-Av8")
-.Case("gr740", "-Av8")
+.Case("gr712rc", "-Aleon")
+.Case("leon4", "-Aleon")
+.Case("gr740", "-Aleon")
 .Default("-Av8");
   }
 }
Index: test/Driver/sparc-as.c
===
--- test/Driver/sparc-as.c
+++ test/Driver/sparc-as.c
@@ -76,6 +76,66 @@
 // RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
 // RUN: | FileCheck -check-prefix=SPARC-V8PLUSD %s
 
+// RUN: %clang -mcpu=ma2100 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2150 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2155 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2450 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2455 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2x5x -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2080 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2085 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2480 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2485 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=ma2x8x -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=myriad2 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=myriad2.1 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=myriad2.2 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
+// RUN: %clang -mcpu=myriad2.3 -no-canonical-prefixes -target sparc \
+// RUN: -no-integrated-as --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \
+// RUN: | FileCheck -check-prefix=SPARC-LEON %s
+
 // RUN: %clang -mcpu=leon2 -no-canonical-prefixes -t

[PATCH] D47137: [Sparc] Add floating-point register names

2018-05-24 Thread Daniel Cederman via Phabricator via cfe-commits 
dcederman updated this revision to Diff 148351.
dcederman added a comment.

Removed the non-existing registers f33, f35, and so on. I also removed the dX 
and qX aliases. After trying them they felt more confusing than helpful.


https://reviews.llvm.org/D47137

Files:
  lib/Basic/Targets/Sparc.cpp
  test/CodeGen/sparcv8-inline-asm.c
  test/CodeGen/sparcv9-inline-asm.c

Index: test/CodeGen/sparcv9-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/sparcv9-inline-asm.c
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple sparcv9-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+void test_gcc_registers(void) {
+register unsigned int regO6 asm("o6") = 0;
+register unsigned int regSP asm("sp") = 1;
+register unsigned int reg14 asm("r14") = 2;
+register unsigned int regI6 asm("i6") = 3;
+register unsigned int regFP asm("fp") = 4;
+register unsigned int reg30 asm("r30") = 5;
+
+register float fF20 asm("f20") = 8.0;
+register double dF40 asm("f40") = 11.0;
+register long double qF40 asm("f40") = 14.0;
+
+// Test remapping register names in register ... asm("rN") statments.
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
+asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
+asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
+
+// CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("fadds %0,%1,%2" : : "f" (fF20), "f" (fF20), "f"(fF20));
+
+// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f40},{f40},{f40}"
+asm volatile("faddd %0,%1,%2" : : "f" (dF40), "f" (dF40), "f"(dF40));
+
+// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"
+asm volatile("faddq %0,%1,%2" : : "f" (qF40), "f" (qF40), "f"(qF40));
+
+}
Index: test/CodeGen/sparcv8-inline-asm.c
===
--- test/CodeGen/sparcv8-inline-asm.c
+++ test/CodeGen/sparcv8-inline-asm.c
@@ -1,7 +1,7 @@
 // RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
 
 // CHECK: define float @fabsf(float %a)
-// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}}) #1
+// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}})
 float fabsf(float a) {
   float res;
   __asm __volatile__("fabss  %1, %0;"
@@ -9,3 +9,34 @@
  : /* reg in */ "f"(a));
   return res;
 }
+
+void test_gcc_registers(void) {
+register unsigned int regO6 asm("o6") = 0;
+register unsigned int regSP asm("sp") = 1;
+register unsigned int reg14 asm("r14") = 2;
+register unsigned int regI6 asm("i6") = 3;
+register unsigned int regFP asm("fp") = 4;
+register unsigned int reg30 asm("r30") = 5;
+
+register float fF20 asm("f20") = 8.0;
+register double dF20 asm("f20") = 11.0;
+register long double qF20 asm("f20") = 14.0;
+
+// Test remapping register names in register ... asm("rN") statments.
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
+asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
+asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
+
+ // CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("fadds %0,%1,%2" : : "f" (fF20), "f" (fF20), "f"(fF20));
+
+// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("faddd %0,%1,%2" : : "f" (dF20), "f" (dF20), "f"(dF20));
+
+// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("faddq %0,%1,%2" : : "f" (qF20), "f" (qF20), "f"(qF20));
+
+}
Index: lib/Basic/Targets/Sparc.cpp
===
--- lib/Basic/Targets/Sparc.cpp
+++ lib/Basic/Targets/Sparc.cpp
@@ -20,9 +20,17 @@
 using namespace clang::targets;
 
 const char *const SparcTargetInfo::GCCRegNames[] = {
+// Integer registers
 "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8",  "r9",  "r10",
 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
-"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+
+// Floating-point registers
+"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",  "f8",  "f9",  "f10",
+"f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
+"f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "f32",
+"f34", "f36", "f38", "f40", "f42", "f44", "f46", "f48", "f50", "f52", "f54",
+"f56", "f58", "f60", "f62",
 };
 
 ArrayRef SparcTargetInfo::getGCCRegName

[PATCH] D47137: [Sparc] Add floating-point register names

2018-05-29 Thread Daniel Cederman via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rL333510: [Sparc] Add floating-point register names (authored 
by dcederman, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D47137?vs=148351&id=149045#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D47137

Files:
  cfe/trunk/lib/Basic/Targets/Sparc.cpp
  cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
  cfe/trunk/test/CodeGen/sparcv9-inline-asm.c

Index: cfe/trunk/test/CodeGen/sparcv9-inline-asm.c
===
--- cfe/trunk/test/CodeGen/sparcv9-inline-asm.c
+++ cfe/trunk/test/CodeGen/sparcv9-inline-asm.c
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple sparcv9-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+void test_gcc_registers(void) {
+register unsigned int regO6 asm("o6") = 0;
+register unsigned int regSP asm("sp") = 1;
+register unsigned int reg14 asm("r14") = 2;
+register unsigned int regI6 asm("i6") = 3;
+register unsigned int regFP asm("fp") = 4;
+register unsigned int reg30 asm("r30") = 5;
+
+register float fF20 asm("f20") = 8.0;
+register double dF40 asm("f40") = 11.0;
+register long double qF40 asm("f40") = 14.0;
+
+// Test remapping register names in register ... asm("rN") statments.
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
+asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
+asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
+
+// CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("fadds %0,%1,%2" : : "f" (fF20), "f" (fF20), "f"(fF20));
+
+// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f40},{f40},{f40}"
+asm volatile("faddd %0,%1,%2" : : "f" (dF40), "f" (dF40), "f"(dF40));
+
+// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"
+asm volatile("faddq %0,%1,%2" : : "f" (qF40), "f" (qF40), "f"(qF40));
+
+}
Index: cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
===
--- cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
+++ cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
@@ -1,11 +1,42 @@
 // RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
 
 // CHECK: define float @fabsf(float %a)
-// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}}) #1
+// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}})
 float fabsf(float a) {
   float res;
   __asm __volatile__("fabss  %1, %0;"
  : /* reg out*/ "=e"(res)
  : /* reg in */ "f"(a));
   return res;
 }
+
+void test_gcc_registers(void) {
+register unsigned int regO6 asm("o6") = 0;
+register unsigned int regSP asm("sp") = 1;
+register unsigned int reg14 asm("r14") = 2;
+register unsigned int regI6 asm("i6") = 3;
+register unsigned int regFP asm("fp") = 4;
+register unsigned int reg30 asm("r30") = 5;
+
+register float fF20 asm("f20") = 8.0;
+register double dF20 asm("f20") = 11.0;
+register long double qF20 asm("f20") = 14.0;
+
+// Test remapping register names in register ... asm("rN") statments.
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
+asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
+
+// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
+asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
+
+ // CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("fadds %0,%1,%2" : : "f" (fF20), "f" (fF20), "f"(fF20));
+
+// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("faddd %0,%1,%2" : : "f" (dF20), "f" (dF20), "f"(dF20));
+
+// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f20},{f20},{f20}"
+asm volatile("faddq %0,%1,%2" : : "f" (qF20), "f" (qF20), "f"(qF20));
+
+}
Index: cfe/trunk/lib/Basic/Targets/Sparc.cpp
===
--- cfe/trunk/lib/Basic/Targets/Sparc.cpp
+++ cfe/trunk/lib/Basic/Targets/Sparc.cpp
@@ -20,9 +20,17 @@
 using namespace clang::targets;
 
 const char *const SparcTargetInfo::GCCRegNames[] = {
+// Integer registers
 "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8",  "r9",  "r10",
 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
-"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+
+// Floating-point registers
+"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",  "f8",  "f9",  "f10",
+"f11", "f12", "f13", "f14", "f15", "f16",