dcederman updated this revision to Diff 148205.
dcederman added a comment.
Herald added a subscriber: eraman.
Added test cases, f32-f63, d0-d31, and q0-q15.
https://reviews.llvm.org/D47137
Files:
lib/Basic/Targets/Sparc.cpp
test/CodeGen/sparcv8-inline-asm.c
test/CodeGen/sparcv9-inline-asm.c
Index: test/CodeGen/sparcv9-inline-asm.c
===================================================================
--- /dev/null
+++ test/CodeGen/sparcv9-inline-asm.c
@@ -0,0 +1,40 @@
+// RUN: %clang_cc1 -triple sparcv9-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+void test_gcc_registers(void) {
+ register unsigned int regO6 asm("o6") = 0;
+ register unsigned int regSP asm("sp") = 1;
+ register unsigned int reg14 asm("r14") = 2;
+ register unsigned int regI6 asm("i6") = 3;
+ register unsigned int regFP asm("fp") = 4;
+ register unsigned int reg30 asm("r30") = 5;
+
+ register float fQ5 asm("q5") = 6.0;
+ register float fD10 asm("d10") = 7.0;
+ register float fF20 asm("f20") = 8.0;
+
+ register double dQ10 asm("q10") = 9.0;
+ register double dD20 asm("d20") = 10.0;
+ register double dF40 asm("f40") = 11.0;
+
+ register long double qQ10 asm("q10") = 12.0;
+ register long double qD20 asm("d20") = 13.0;
+ register long double qF40 asm("f40") = 14.0;
+
+ // Test remapping register names in register ... asm("rN") statments.
+
+ // CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
+ asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
+
+ // CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
+ asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
+
+ // CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
+ asm volatile("fadds %0,%1,%2" : : "f" (fQ5), "f" (fD10), "f"(fF20));
+
+ // CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f40},{f40},{f40}"
+ asm volatile("faddd %0,%1,%2" : : "f" (dQ10), "f" (dD20), "f"(dF40));
+
+ // CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"
+ asm volatile("faddq %0,%1,%2" : : "f" (qQ10), "f" (qD20), "f"(qF40));
+
+}
Index: test/CodeGen/sparcv8-inline-asm.c
===================================================================
--- test/CodeGen/sparcv8-inline-asm.c
+++ test/CodeGen/sparcv8-inline-asm.c
@@ -1,11 +1,50 @@
// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
// CHECK: define float @fabsf(float %a)
-// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}}) #1
+// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}})
float fabsf(float a) {
float res;
__asm __volatile__("fabss %1, %0;"
: /* reg out*/ "=e"(res)
: /* reg in */ "f"(a));
return res;
}
+
+void test_gcc_registers(void) {
+ register unsigned int regO6 asm("o6") = 0;
+ register unsigned int regSP asm("sp") = 1;
+ register unsigned int reg14 asm("r14") = 2;
+ register unsigned int regI6 asm("i6") = 3;
+ register unsigned int regFP asm("fp") = 4;
+ register unsigned int reg30 asm("r30") = 5;
+
+ register float fQ5 asm("q5") = 6.0;
+ register float fD10 asm("d10") = 7.0;
+ register float fF20 asm("f20") = 8.0;
+
+ register double dQ5 asm("q5") = 9.0;
+ register double dD10 asm("d10") = 10.0;
+ register double dF20 asm("f20") = 11.0;
+
+ register long double qQ5 asm("q5") = 12.0;
+ register long double qD10 asm("d10") = 13.0;
+ register long double qF20 asm("f20") = 14.0;
+
+ // Test remapping register names in register ... asm("rN") statments.
+
+ // CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
+ asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
+
+ // CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
+ asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
+
+ // CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
+ asm volatile("fadds %0,%1,%2" : : "f" (fQ5), "f" (fD10), "f"(fF20));
+
+ // CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"
+ asm volatile("faddd %0,%1,%2" : : "f" (dQ5), "f" (dD10), "f"(dF20));
+
+ // CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f20},{f20},{f20}"
+ asm volatile("faddq %0,%1,%2" : : "f" (qQ5), "f" (qD10), "f"(qF20));
+
+}
Index: lib/Basic/Targets/Sparc.cpp
===================================================================
--- lib/Basic/Targets/Sparc.cpp
+++ lib/Basic/Targets/Sparc.cpp
@@ -20,24 +20,50 @@
using namespace clang::targets;
const char *const SparcTargetInfo::GCCRegNames[] = {
+ // Integer registers
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
- "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+ "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+
+ // Floating-point registers
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10",
+ "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
+ "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "f32",
+ "f33", "f34", "f35", "f36", "f37", "f38", "f39", "f40", "f41", "f42", "f43",
+ "f44", "f45", "f46", "f47", "f48", "f49", "f50", "f51", "f52", "f53", "f54",
+ "f55", "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
};
ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
return llvm::makeArrayRef(GCCRegNames);
}
const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
+ // Integer registers
{{"g0"}, "r0"}, {{"g1"}, "r1"}, {{"g2"}, "r2"}, {{"g3"}, "r3"},
{{"g4"}, "r4"}, {{"g5"}, "r5"}, {{"g6"}, "r6"}, {{"g7"}, "r7"},
{{"o0"}, "r8"}, {{"o1"}, "r9"}, {{"o2"}, "r10"}, {{"o3"}, "r11"},
{{"o4"}, "r12"}, {{"o5"}, "r13"}, {{"o6", "sp"}, "r14"}, {{"o7"}, "r15"},
{{"l0"}, "r16"}, {{"l1"}, "r17"}, {{"l2"}, "r18"}, {{"l3"}, "r19"},
{{"l4"}, "r20"}, {{"l5"}, "r21"}, {{"l6"}, "r22"}, {{"l7"}, "r23"},
{{"i0"}, "r24"}, {{"i1"}, "r25"}, {{"i2"}, "r26"}, {{"i3"}, "r27"},
{{"i4"}, "r28"}, {{"i5"}, "r29"}, {{"i6", "fp"}, "r30"}, {{"i7"}, "r31"},
+
+ // Double precision floating-point register
+ {{"d0"}, "f0"}, {{"d1"}, "f2"}, {{"d2"}, "f4"}, {{"d3"}, "f6"},
+ {{"d4"}, "f8"}, {{"d5"}, "f10"}, {{"d6"}, "f12"}, {{"d7"}, "f14"},
+ {{"d8"}, "f16"}, {{"d9"}, "f18"}, {{"d10"}, "f20"}, {{"d11"}, "f22"},
+ {{"d12"}, "f24"}, {{"d13"}, "f26"}, {{"d14"}, "f28"}, {{"d15"}, "f30"},
+ {{"d16"}, "f32"}, {{"d17"}, "f34"}, {{"d18"}, "f36"}, {{"d19"}, "f38"},
+ {{"d20"}, "f40"}, {{"d21"}, "f42"}, {{"d22"}, "f44"}, {{"d23"}, "f46"},
+ {{"d24"}, "f48"}, {{"d25"}, "f50"}, {{"d26"}, "f52"}, {{"d27"}, "f54"},
+ {{"d28"}, "f56"}, {{"d29"}, "f58"}, {{"d30"}, "f60"}, {{"d31"}, "f62"},
+
+ // Quad precision floating-point register
+ {{"q0"}, "f0"}, {{"q1"}, "f4"}, {{"q2"}, "f8"}, {{"q3"}, "f12"},
+ {{"q4"}, "f16"}, {{"q5"}, "f20"}, {{"q6"}, "f24"}, {{"q7"}, "f28"},
+ {{"q8"}, "f32"}, {{"q9"}, "f36"}, {{"q10"}, "f40"}, {{"q11"}, "f44"},
+ {{"q12"}, "f48"}, {{"q13"}, "f52"}, {{"q14"}, "f56"}, {{"q15"}, "f60"},
};
ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
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