[llvm] [clang] Remove experimental from Vector Crypto extensions (PR #69000)
4vtomat wrote: > > Since it's possible that **ISA spec** and **intrinsics spec** are not > > synchronized, so the updates add an dummy extension called > > **zexperimental**, once `-menable-experimental-extensions` is specified, > > the feature `zexperimental` is automatically added. > > If `let RequiredFeatures = ["Zexperimental"] ` is added in `.td` file, it > > will check if `zexperimental` exists, if not, the corresponding intrinsics > > would not be added, hence causing an **intrinsics undeclared** error. > > Thanks for looking into this. It's perhaps surprising we've gone so long > without having the infrastructure to make an extension non-experimental > without making its not-yet-finalized intrinsics non-experimental. Introducing > a new required feature seems like a reasonable way of doing this, but > introducing a dummy extension seems unnecessary (unless I'm missing > something?). > > I could see a solution involving a Clang flag (e.g. > `-menable-experimental-intrinsics`), or perhaps a solution where the user > must use a certain `#define` (I know riscv_vector.h is implemented using a > pragma, but presumably that could still query defines). There may be other > options too. > > Another piece of info that would be helpful to better understand is what the > process is for finalising intrinsic additions (@eopXD might know?). If it's > just the case that we have to wait another month before moving an extension > from experimental to experimental then maybe extra infro to separate > experimental intrinsics from instructions is less interesting. If it's more > indeterminate than that, we probably need it. > > I'll put this on the agenda for Thursday's RISC-V LLVM sync-up call in the > hope we can resolve it there. Yeah, we don't need a new extension actually, thanks for pointing out! https://github.com/llvm/llvm-project/pull/69000 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] Remove experimental from Vector Crypto extensions (PR #69000)
@@ -106,6 +106,8 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zdinx", RISCVExtensionVersion{1, 0}},
+{"zexperimental", RISCVExtensionVersion{1, 0}},
+
4vtomat wrote:
No, we don't~
https://github.com/llvm/llvm-project/pull/69000
___
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[clang] [llvm] [RISCV] Convert all floating point vector type operands to integer vector type (PR #69559)
4vtomat wrote: ping https://github.com/llvm/llvm-project/pull/69559 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Remove experimental from Vector Crypto extensions (PR #69000)
4vtomat wrote: > Do we need to add the "experimental" feature to RISCVFeatures.td? If the > feature string shows up in the function attributes, won't the backend print > that it doesn't recognize the feature name when it parses the string? Yes, we do, I forgot it lol~ https://github.com/llvm/llvm-project/pull/69000 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Remove experimental from Vector Crypto extensions (PR #69000)
4vtomat wrote: This update add "experimental" to `RISCVFeatures.td`, also add a member variable `HasExperimental` to record whether the target has this feature. https://github.com/llvm/llvm-project/pull/69000 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] Remove experimental from Vector Crypto extensions (PR #69000)
4vtomat wrote: moved to the new [one](https://github.com/llvm/llvm-project/pull/74213) https://github.com/llvm/llvm-project/pull/69000 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] Remove experimental from Vector Crypto extensions (PR #69000)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/69000 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Convert all floating point vector type operands to integer vector type (PR #69559)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/69559 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Remove experimental from Vector Crypto extensions (PR #69000)
4vtomat wrote: Since it's possible that **ISA spec** and **intrinsics spec** are not synchronized, so the updates add an dummy extension called **zexperimental**, once `-menable-experimental-extensions` is specified, the feature `zexperimental` is automatically added. If specifying `let RequiredFeatures = ["Zexperimental"] ` is added in `.td` file, it will check if `zexperimental` exists, if not, the corresponding intrinsics would not be added, hence causing an **intrinsics undeclared** error. https://github.com/llvm/llvm-project/pull/69000 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/66860
>From a43d20450eef2d41e88ab867de2656e2fd9631b7 Mon Sep 17 00:00:00 2001
From: 4vtomat
Date: Tue, 19 Sep 2023 23:06:01 -0700
Subject: [PATCH 1/3] [RISCV] Fix wrong implication for zvknhb.
---
clang/include/clang/Basic/riscv_vector.td| 9 -
.../include/clang/Support/RISCVVIntrinsicUtils.h | 5 +++--
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 1 +
clang/test/Sema/zvk-invalid-zvknha.c | 11 +++
clang/utils/TableGen/RISCVVEmitter.cpp | 1 +
llvm/lib/Support/RISCVISAInfo.cpp| 2 --
llvm/lib/Target/RISCV/RISCVFeatures.td | 16 +++-
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 16 +++-
llvm/test/CodeGen/RISCV/attributes.ll| 16
llvm/test/CodeGen/RISCV/rvv/vsha2ch.ll | 6 ++
llvm/test/CodeGen/RISCV/rvv/vsha2cl.ll | 6 ++
llvm/test/CodeGen/RISCV/rvv/vsha2ms.ll | 6 ++
llvm/test/MC/RISCV/attribute-arch.s | 8
llvm/test/MC/RISCV/rvv/zvknh.s | 6 +++---
14 files changed, 79 insertions(+), 30 deletions(-)
create mode 100644 clang/test/Sema/zvk-invalid-zvknha.c
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 8bbfd1cef5106a5..1d24b4e75f9dd5f 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2588,8 +2588,15 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked =
false in {
defm vaesz : RVVOutBuiltinSetZvk;
}
- // zvknha or zvknhb
+ // zvknha
let RequiredFeatures = ["Zvknha"] in {
+defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"i">;
+defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"i">;
+defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"i">;
+ }
+
+ // zvknhb
+ let RequiredFeatures = ["Zvknhb"] in {
defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"il">;
defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"il">;
defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"il">;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 90d99b7efa8aff9..c455bb2c45889f3 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -493,8 +493,9 @@ enum RVVRequire : uint16_t {
RVV_REQ_Zvkg = 1 << 8,
RVV_REQ_Zvkned = 1 << 9,
RVV_REQ_Zvknha = 1 << 10,
- RVV_REQ_Zvksed = 1 << 11,
- RVV_REQ_Zvksh = 1 << 12,
+ RVV_REQ_Zvknhb = 1 << 11,
+ RVV_REQ_Zvksed = 1 << 12,
+ RVV_REQ_Zvksh = 1 << 13,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
};
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index acdf3260007bc3a..1ba68f54b6db19c 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -213,6 +213,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
{"experimental-zvkg", RVV_REQ_Zvkg},
{"experimental-zvkned", RVV_REQ_Zvkned},
{"experimental-zvknha", RVV_REQ_Zvknha},
+ {"experimental-zvknhb", RVV_REQ_Zvknhb},
{"experimental-zvksed", RVV_REQ_Zvksed},
{"experimental-zvksh", RVV_REQ_Zvksh}};
diff --git a/clang/test/Sema/zvk-invalid-zvknha.c
b/clang/test/Sema/zvk-invalid-zvknha.c
new file mode 100644
index 000..0ce2e321a175f5f
--- /dev/null
+++ b/clang/test/Sema/zvk-invalid-zvknha.c
@@ -0,0 +1,11 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature
+experimental-zvknha %s -fsyntax-only -verify
+
+#include
+
+void test_zvk_features() {
+ // zvknhb
+ __riscv_vsha2ch_vv_u64m1(); // expected-error {{call to undeclared function
'__riscv_vsha2ch_vv_u64m1'; ISO C99 and later do not support implicit function
declarations}}
+ __riscv_vsha2cl_vv_u64m1(); // expected-error {{call to undeclared function
'__riscv_vsha2cl_vv_u64m1'; ISO C99 and later do not support implicit function
declarations}}
+ __riscv_vsha2ms_vv_u64m1(); // expected-error {{call to undeclared function
'__riscv_vsha2ms_vv_u64m1'; ISO C99 and later do not support implicit function
declarations}}
+}
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index 07d31642188eafd..d697099e47733fa 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -664,6 +664,7 @@ void RVVEmitter::createRVVIntrinsics(
.Case("Zvkg", RVV_REQ_Zvkg)
.Case("Zvkned", RVV_REQ_Zvkned)
.Case("Zvknha", RVV_REQ_Zvknha)
+ .Case("Zvknhb", RVV_REQ_Zvknhb)
.Case("Zvksed", RVV_REQ_Zvksed)
.Case("Zvksh", RVV_REQ_Zvksh)
[llvm] [clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/66860 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/68296
>From 625c45da9928c3da295bba28708c992a42f3cd52 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 4 Oct 2023 10:23:52 -0700
Subject: [PATCH] [RISCV][SiFive] Support Xsfvfwmaccqqq extensions
Bfloat16 Matrix Multiply Accumulate Instruction
https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf
---
.../clang/Basic/riscv_sifive_vector.td| 12 ++
.../clang/Support/RISCVVIntrinsicUtils.h | 23 ++-
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 1 +
.../non-overloaded/sf_vfwmacc_4x4x4.c | 57 +
.../non-policy/overloaded/sf_vfwmacc_4x4x4.c | 57 +
.../policy/non-overloaded/sf_vfwmacc_4x4x4.c | 57 +
.../policy/overloaded/sf_vfwmacc_4x4x4.c | 57 +
.../test/Preprocessor/riscv-target-features.c | 9 +
.../test/Sema/rvv-required-features-invalid.c | 4 +
clang/test/Sema/rvv-required-features.c | 7 +-
clang/utils/TableGen/RISCVVEmitter.cpp| 1 +
llvm/include/llvm/IR/IntrinsicsRISCVXsf.td| 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 3 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 3 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 8 +
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td| 22 ++
.../CodeGen/RISCV/rvv/sf_vfwmacc_4x4x4.ll | 195 ++
llvm/test/MC/RISCV/rvv/xsfvfwmacc.s | 15 ++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
19 files changed, 523 insertions(+), 12 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/sf_vfwmacc_4x4x4.c
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/sf_vfwmacc_4x4x4.c
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/sf_vfwmacc_4x4x4.c
create mode 100644 llvm/test/CodeGen/RISCV/rvv/sf_vfwmacc_4x4x4.ll
create mode 100644 llvm/test/MC/RISCV/rvv/xsfvfwmacc.s
diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td
b/clang/include/clang/Basic/riscv_sifive_vector.td
index fb8561a05a0d453..7b98ac8906667b6 100644
--- a/clang/include/clang/Basic/riscv_sifive_vector.td
+++ b/clang/include/clang/Basic/riscv_sifive_vector.td
@@ -104,6 +104,14 @@ let SupportOverloading = false in {
}
}
+multiclass RVVVFWMACCBuiltinSet> suffixes_prototypes> {
+ let OverloadedName = NAME,
+ Name = NAME,
+ HasMasked = false,
+ Log2LMUL = [-2, -1, 0, 1, 2] in
+defm NAME : RVVOutOp1Op2BuiltinSet;
+}
+
multiclass RVVVQMACCBuiltinSet> suffixes_prototypes> {
let OverloadedName = NAME,
Name = NAME,
@@ -127,3 +135,7 @@ let UnMaskedPolicyScheme = HasPolicyOperand in
defm sf_vqmaccus_4x8x4 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
defm sf_vqmaccsu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
}
+
+let UnMaskedPolicyScheme = HasPolicyOperand in
+ let RequiredFeatures = ["Xsfvfwmaccqqq"] in
+defm sf_vfwmacc_4x4x4 : RVVVFWMACCBuiltinSet<[["", "w", "wwSvv"]]>;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index c455bb2c45889f3..3c7064c31686333 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -485,17 +485,18 @@ enum RVVRequire : uint16_t {
RVV_REQ_RV64 = 1 << 0,
RVV_REQ_ZvfhminOrZvfh = 1 << 1,
RVV_REQ_Xsfvcp = 1 << 2,
- RVV_REQ_Xsfvqmaccdod = 1 << 3,
- RVV_REQ_Xsfvqmaccqoq = 1 << 4,
- RVV_REQ_Zvbb = 1 << 5,
- RVV_REQ_Zvbc = 1 << 6,
- RVV_REQ_Zvkb = 1 << 7,
- RVV_REQ_Zvkg = 1 << 8,
- RVV_REQ_Zvkned = 1 << 9,
- RVV_REQ_Zvknha = 1 << 10,
- RVV_REQ_Zvknhb = 1 << 11,
- RVV_REQ_Zvksed = 1 << 12,
- RVV_REQ_Zvksh = 1 << 13,
+ RVV_REQ_Xsfvfwmaccqqq = 1 << 3,
+ RVV_REQ_Xsfvqmaccdod = 1 << 4,
+ RVV_REQ_Xsfvqmaccqoq = 1 << 5,
+ RVV_REQ_Zvbb = 1 << 6,
+ RVV_REQ_Zvbc = 1 << 7,
+ RVV_REQ_Zvkb = 1 << 8,
+ RVV_REQ_Zvkg = 1 << 9,
+ RVV_REQ_Zvkned = 1 << 10,
+ RVV_REQ_Zvknha = 1 << 11,
+ RVV_REQ_Zvknhb = 1 << 12,
+ RVV_REQ_Zvksed = 1 << 13,
+ RVV_REQ_Zvksh = 1 << 14,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
};
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 1ba68f54b6db19c..e32b12b0e9e816a 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -205,6 +205,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
static const std::pair FeatureCheckList[] = {
{"64bit", RVV_REQ_RV64},
{"xsfvcp", RVV_REQ_Xsfvcp},
+ {"xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq},
{"xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod},
{"xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq},
{"experimental-zvbb", RVV_RE
[llvm] [clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/68296 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support Xsfvfnrclipxfqf extensions (PR #68297)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/68297 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
4vtomat wrote: Good catch！ LGTM, leave final decision to others~ https://github.com/llvm/llvm-project/pull/71140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Update the interface of sifive vqmaccqoq (PR #74284)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/74284 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/73765
>From 320061a69ed129947eab1097d6308af434134a35 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 29 Nov 2023 00:27:25 -0800
Subject: [PATCH 1/3] [RISCV] Implement multi-lib reuse rule for RISC-V
bare-metal toolchain
Extend the multi-lib re-use selection mechanism for RISC-V.
This function will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
is a subset of march=rv32imc.
- march that contains atomic extension can't reuse multi-lib that
doesn't have atomic, vice versa. e.g. multi-lib=march=rv32im and
march=rv32ima are not compatible, because software and hardware
atomic operation can't work together correctly.
---
clang/lib/Driver/ToolChains/Gnu.cpp | 127 +-
.../riscv-toolchain-gcc-multilib-reuse.c | 86
2 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index b875991844..c373a194ee4064 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -30,6 +30,7 @@
#include "llvm/Option/ArgList.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Path.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/TargetParser/TargetParser.h"
#include
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
+if (Flag.startswith("!march=") || Flag.startswith("-march="))
+ continue;
+
+NewFlags.push_back(Flag.str());
+ }
+
+ llvm::StringSet<> AllArchExts;
+ // Reconstruct multi-lib list, and break march option into seperated
+ // extension. e.g. march=rv32im -> +i +m
+ for (auto M : RISCVMultilibSet) {
+bool Skip = false;
+
+MultilibBuilder NewMultilib =
+MultilibBuilder(M.gccSuffix(), M.osSuffix(), M.includeSuffix());
+for (StringRef Flag : M.flags()) {
+ // Add back the all option except -march.
+ if (!Flag.startswith("-march=")) {
+NewMultilib.flag(Flag);
+continue;
+ }
+
+ // Break down -march into individual extension.
+ auto MLConfigParseResult = llvm::RISCVISAInfo::parseArchString(
+ Flag.drop_front(7), /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!MLConfigParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+llvm::consumeError(MLConfigParseResult.takeError());
+
+// We might got parsing error if rv32e in the list, we could just skip
+// that and process the rest of multi-lib configs.
+Skip = true;
+continue;
+ }
+ auto &MLConfigISAInfo = *MLConfigParseResult;
+
+ auto MLConfigArchExts = MLConfigISAInfo->getExtensions();
+ for (auto MLConfigArchExt : MLConfigArchExts) {
+auto ExtName = MLConfigArchExt.first;
+NewMultilib.flag(Twine("-", ExtName).str());
+
+if (!AllArchExts.contains(ExtName)) {
+ AllArchExts.ins
[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/73765
>From 320061a69ed129947eab1097d6308af434134a35 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 29 Nov 2023 00:27:25 -0800
Subject: [PATCH 1/3] [RISCV] Implement multi-lib reuse rule for RISC-V
bare-metal toolchain
Extend the multi-lib re-use selection mechanism for RISC-V.
This function will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
is a subset of march=rv32imc.
- march that contains atomic extension can't reuse multi-lib that
doesn't have atomic, vice versa. e.g. multi-lib=march=rv32im and
march=rv32ima are not compatible, because software and hardware
atomic operation can't work together correctly.
---
clang/lib/Driver/ToolChains/Gnu.cpp | 127 +-
.../riscv-toolchain-gcc-multilib-reuse.c | 86
2 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index b875991844..c373a194ee4064 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -30,6 +30,7 @@
#include "llvm/Option/ArgList.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Path.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/TargetParser/TargetParser.h"
#include
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
+if (Flag.startswith("!march=") || Flag.startswith("-march="))
+ continue;
+
+NewFlags.push_back(Flag.str());
+ }
+
+ llvm::StringSet<> AllArchExts;
+ // Reconstruct multi-lib list, and break march option into seperated
+ // extension. e.g. march=rv32im -> +i +m
+ for (auto M : RISCVMultilibSet) {
+bool Skip = false;
+
+MultilibBuilder NewMultilib =
+MultilibBuilder(M.gccSuffix(), M.osSuffix(), M.includeSuffix());
+for (StringRef Flag : M.flags()) {
+ // Add back the all option except -march.
+ if (!Flag.startswith("-march=")) {
+NewMultilib.flag(Flag);
+continue;
+ }
+
+ // Break down -march into individual extension.
+ auto MLConfigParseResult = llvm::RISCVISAInfo::parseArchString(
+ Flag.drop_front(7), /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!MLConfigParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+llvm::consumeError(MLConfigParseResult.takeError());
+
+// We might got parsing error if rv32e in the list, we could just skip
+// that and process the rest of multi-lib configs.
+Skip = true;
+continue;
+ }
+ auto &MLConfigISAInfo = *MLConfigParseResult;
+
+ auto MLConfigArchExts = MLConfigISAInfo->getExtensions();
+ for (auto MLConfigArchExt : MLConfigArchExts) {
+auto ExtName = MLConfigArchExt.first;
+NewMultilib.flag(Twine("-", ExtName).str());
+
+if (!AllArchExts.contains(ExtName)) {
+ AllArchExts.ins
[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/73765 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Recommit [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (#73765) (PR #75890)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/75890
Extend the multi-lib re-use selection mechanism for RISC-V.
This funciton will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
is a subset of march=rv32imc.
- march that contains atomic extension can't reuse multi-lib that
doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
march=rv32ima are not compatible, because software and hardware
atomic operation can't work together correctly.
>From 43ecdfdc5d96d1b53ccfc851e3dce8547b2f6fe9 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Mon, 18 Dec 2023 15:52:14 +0800
Subject: [PATCH] Recommit [RISCV] Implement multi-lib reuse rule for RISC-V
bare-metal toolchain (#73765)
Extend the multi-lib re-use selection mechanism for RISC-V.
This funciton will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
is a subset of march=rv32imc.
- march that contains atomic extension can't reuse multi-lib that
doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
march=rv32ima are not compatible, because software and hardware
atomic operation can't work together correctly.
---
clang/lib/Driver/ToolChains/Gnu.cpp | 127 +-
.../riscv-toolchain-gcc-multilib-reuse.c | 81 +++
2 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 835215a83c4037..7e70626faf8cce 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -30,6 +30,7 @@
#include "llvm/Option/ArgList.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Path.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/TargetParser/TargetParser.h"
#include
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This function will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't have atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+selectRISCVMultilib(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVectorImpl &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ llvm::Expected> ParseResult =
+ llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will be handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+
+ auto &ISAInfo = *ParseResult;
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
+if (Flag.starts_with("!march=") || Flag.starts_with("-march="))
+ continue;
+
+NewFlags.push_back(Flag.str());
+ }
+
+ llvm::StringSet<> AllArchExts;
+ // Reconstruct multi-lib list, and break march option into separated
+ // extension. e.g. march=rv32im -> +i +m
+ for (const auto &M : RISCVMultilibSet) {
+bool Skip = false;
+
+MultilibBuilder NewMultilib =
+MultilibBuilder(M.gccSuffix(), M.osSuffix(), M.includeSuffix());
+for (StringRef Flag : M.flags()) {
+ // Add back all flags except -march.
+ if (!Flag.consume_front("-march=")) {
+NewMultilib.flag(Flag);
+continue;
+ }
+
+ // Break down -march into individual extension.
+ llvm::Expected> MLConfigParseResult =
+ llvm::RISCVISAInfo::parseArchString(
+ Flag, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!MLConfigParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+llvm::consumeError(MLConfigParseResult.takeError());
+
+
[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)
@@ -121,38 +121,36 @@ entry:
declare
@llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
,
,
- ,
+ ,
iXLen, iXLen);
-define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind {
+define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:vl8r.v v24, (a0)
-; CHECK-NEXT:vsetvli zero, a1, e8, m1, tu, ma
-; CHECK-NEXT:sf.vqmaccus.4x8x4 v8, v16, v24
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT:sf.vqmaccus.4x8x4 v8, v16, v20
; CHECK-NEXT:ret
entry:
%a = call
@llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
%0,
%1,
- %2,
+ %2,
iXLen %3, iXLen 2)
ret %a
}
-define @intrinsic_vqmaccus_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind {
+define @intrinsic_vqmaccus_4x8x4_ta_i32m8( %0, %1, %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:vl8r.v v24, (a0)
-; CHECK-NEXT:vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:sf.vqmaccus.4x8x4 v8, v16, v24
+; CHECK-NEXT:vsetvli zero, a0, e8, m1, ta, ma
4vtomat wrote:
Updated in this [commit](https://github.com/llvm/llvm-project/pull/76006)!
https://github.com/llvm/llvm-project/pull/75768
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Recommit [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (#73765) (PR #75890)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/75890
>From 3f4a4f10ed75cb0b0f937129b2372184ac34849d Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Mon, 18 Dec 2023 15:52:14 +0800
Subject: [PATCH 1/2] Recommit [RISCV] Implement multi-lib reuse rule for
RISC-V bare-metal toolchain (#73765)
Extend the multi-lib re-use selection mechanism for RISC-V.
This funciton will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
is a subset of march=rv32imc.
- march that contains atomic extension can't reuse multi-lib that
doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
march=rv32ima are not compatible, because software and hardware
atomic operation can't work together correctly.
---
clang/lib/Driver/ToolChains/Gnu.cpp | 127 +-
.../riscv-toolchain-gcc-multilib-reuse.c | 81 +++
2 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 835215a83c4037..7e70626faf8cce 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -30,6 +30,7 @@
#include "llvm/Option/ArgList.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Path.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/TargetParser/TargetParser.h"
#include
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This function will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't have atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+selectRISCVMultilib(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVectorImpl &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ llvm::Expected> ParseResult =
+ llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will be handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+
+ auto &ISAInfo = *ParseResult;
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
+if (Flag.starts_with("!march=") || Flag.starts_with("-march="))
+ continue;
+
+NewFlags.push_back(Flag.str());
+ }
+
+ llvm::StringSet<> AllArchExts;
+ // Reconstruct multi-lib list, and break march option into separated
+ // extension. e.g. march=rv32im -> +i +m
+ for (const auto &M : RISCVMultilibSet) {
+bool Skip = false;
+
+MultilibBuilder NewMultilib =
+MultilibBuilder(M.gccSuffix(), M.osSuffix(), M.includeSuffix());
+for (StringRef Flag : M.flags()) {
+ // Add back all flags except -march.
+ if (!Flag.consume_front("-march=")) {
+NewMultilib.flag(Flag);
+continue;
+ }
+
+ // Break down -march into individual extension.
+ llvm::Expected> MLConfigParseResult =
+ llvm::RISCVISAInfo::parseArchString(
+ Flag, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!MLConfigParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+llvm::consumeError(MLConfigParseResult.takeError());
+
+// We might get a parsing error if rv32e in the list, we could just
skip
+// that and process the rest of multi-lib configs.
+Skip = true;
+continue;
+ }
+ auto &MLConfigISAInfo = *MLConfigParseResult;
+
+ const llvm::RISCVISAInfo::OrderedExtensionMap &MLConfigArchExts =
+ MLConfigISAInfo->getExtensions();
+ for (auto MLConfigArchExt : MLConfigArchExts) {
+auto ExtName = MLConfigArchExt.first;
+NewMultilib.flag(Twine("-", ExtName).str());
+
+if (AllArch
[clang] Recommit [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (#73765) (PR #75890)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/75890 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/73765
Extend the multi-lib re-use selection mechanism for RISC-V.
This funciton will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
is a subset of march=rv32imc.
- march that contains atomic extension can't reuse multi-lib that
doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
march=rv32ima are not compatible, because software and hardware
atomic operation can't work together correctly.
>From 4f6500b9cc359522e399ef0965f01ff820d7cd54 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 29 Nov 2023 00:27:25 -0800
Subject: [PATCH] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal
toolchain
Extend the multi-lib re-use selection mechanism for RISC-V.
This funciton will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
is a subset of march=rv32imc.
- march that contains atomic extension can't reuse multi-lib that
doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
march=rv32ima are not compatible, because software and hardware
atomic operation can't work together correctly.
---
clang/lib/Driver/ToolChains/Gnu.cpp | 134 +-
.../8.2.0/rv32ic/ilp32/crtbegin.o | 0
.../8.2.0/rv32if/ilp32f/crtbegin.o| 0
.../8.2.0/rv32ifc/ilp32/crtbegin.o| 0
.../8.2.0/rv32ifc/ilp32f/crtbegin.o | 0
.../riscv-toolchain-gcc-multilib-reuse.c | 86 +++
6 files changed, 216 insertions(+), 4 deletions(-)
create mode 100644
clang/test/Driver/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv32ic/ilp32/crtbegin.o
create mode 100644
clang/test/Driver/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv32if/ilp32f/crtbegin.o
create mode 100644
clang/test/Driver/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv32ifc/ilp32/crtbegin.o
create mode 100644
clang/test/Driver/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv32ifc/ilp32f/crtbegin.o
create mode 100644 clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 16cf5707227264d..ffc53377d97bd02 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -30,6 +30,7 @@
#include "llvm/Option/ArgList.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Path.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/TargetParser/TargetParser.h"
#include
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
+if (Flag.startswith("!march=") || Flag.startswith("-march="))
+ continue;
+
+NewFlags.push_back(Flag.str());
+ }
+
+ llvm::StringSet<> AllArchExts;
+ // Reconstruct multi-lib list, and break march option into seperated
+ // extension. e.g. march=rv32im -> +i +m
+ for (auto M : RISCVMultilibSet) {
+bool Skip = false;
+
+Multil
[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/73765
>From c406872192d75c92dedd13d1afc36e7b5d71ccca Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 29 Nov 2023 00:27:25 -0800
Subject: [PATCH] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal
toolchain
Extend the multi-lib re-use selection mechanism for RISC-V.
This funciton will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
is a subset of march=rv32imc.
- march that contains atomic extension can't reuse multi-lib that
doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
march=rv32ima are not compatible, because software and hardware
atomic operation can't work together correctly.
---
clang/lib/Driver/ToolChains/Gnu.cpp | 127 +-
.../riscv-toolchain-gcc-multilib-reuse.c | 86
2 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 16cf5707227264d..5bb09101fef0038 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -30,6 +30,7 @@
#include "llvm/Option/ArgList.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Path.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/TargetParser/TargetParser.h"
#include
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
+if (Flag.startswith("!march=") || Flag.startswith("-march="))
+ continue;
+
+NewFlags.push_back(Flag.str());
+ }
+
+ llvm::StringSet<> AllArchExts;
+ // Reconstruct multi-lib list, and break march option into seperated
+ // extension. e.g. march=rv32im -> +i +m
+ for (auto M : RISCVMultilibSet) {
+bool Skip = false;
+
+MultilibBuilder NewMultilib =
+MultilibBuilder(M.gccSuffix(), M.osSuffix(), M.includeSuffix());
+for (StringRef Flag : M.flags()) {
+ // Add back the all option except -march.
+ if (!Flag.startswith("-march=")) {
+NewMultilib.flag(Flag);
+continue;
+ }
+
+ // Break down -march into individual extension.
+ auto MLConfigParseResult = llvm::RISCVISAInfo::parseArchString(
+ Flag.drop_front(7), /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!MLConfigParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+llvm::consumeError(MLConfigParseResult.takeError());
+
+// We might got parsing error if rv32e in the list, we could just skip
+// that and process the rest of multi-lib configs.
+Skip = true;
+continue;
+ }
+ auto &MLConfigISAInfo = *MLConfigParseResult;
+
+ auto MLConfigArchExts = MLConfigISAInfo->getExtensions();
+ for (auto MLConfigArchExt : MLConfigArchExts) {
+auto ExtName = MLConfigArchExt.first;
+NewMultilib.flag(Twine("-", ExtName).str());
+
+if (!AllArchExts.contains(ExtName)) {
+ AllArchExts.insert
[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
4vtomat wrote:
Since `RISCVMultilibSet.select` uses `SmallVector` reference, so this function
just aligned with it, otherwise, we need another `reinterpret_cast` when
calling `RISCVMultilibSet.select` in line 1734.
https://github.com/llvm/llvm-project/pull/73765
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[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
4vtomat wrote:
No we didn't use this variable.
https://github.com/llvm/llvm-project/pull/73765
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[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
4vtomat wrote:
It's a good idea, thanks!
https://github.com/llvm/llvm-project/pull/73765
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[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
4vtomat wrote:
I think `StringRef` is already a Reference and don't need a `&`, unless `Flags`
is a vector of `StringRef`, but it's a vector of `string`~
https://github.com/llvm/llvm-project/pull/73765
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[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
@@ -0,0 +1,86 @@ +// Test case for scanning input of GCC output as multilib config 4vtomat wrote: No we don't use gcc, it's a copy mistake from downstream lol~ https://github.com/llvm/llvm-project/pull/73765 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/73765
>From 0c5f7497a8ce41695cba8f16a9402d74e4f798ea Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 29 Nov 2023 00:27:25 -0800
Subject: [PATCH 1/2] [RISCV] Implement multi-lib reuse rule for RISC-V
bare-metal toolchain
Extend the multi-lib re-use selection mechanism for RISC-V.
This function will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
is a subset of march=rv32imc.
- march that contains atomic extension can't reuse multi-lib that
doesn't have atomic, vice versa. e.g. multi-lib=march=rv32im and
march=rv32ima are not compatible, because software and hardware
atomic operation can't work together correctly.
---
clang/lib/Driver/ToolChains/Gnu.cpp | 127 +-
.../riscv-toolchain-gcc-multilib-reuse.c | 86
2 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 16cf570722726..5bb09101fef00 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -30,6 +30,7 @@
#include "llvm/Option/ArgList.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Path.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/VirtualFileSystem.h"
#include "llvm/TargetParser/TargetParser.h"
#include
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
+if (Flag.startswith("!march=") || Flag.startswith("-march="))
+ continue;
+
+NewFlags.push_back(Flag.str());
+ }
+
+ llvm::StringSet<> AllArchExts;
+ // Reconstruct multi-lib list, and break march option into seperated
+ // extension. e.g. march=rv32im -> +i +m
+ for (auto M : RISCVMultilibSet) {
+bool Skip = false;
+
+MultilibBuilder NewMultilib =
+MultilibBuilder(M.gccSuffix(), M.osSuffix(), M.includeSuffix());
+for (StringRef Flag : M.flags()) {
+ // Add back the all option except -march.
+ if (!Flag.startswith("-march=")) {
+NewMultilib.flag(Flag);
+continue;
+ }
+
+ // Break down -march into individual extension.
+ auto MLConfigParseResult = llvm::RISCVISAInfo::parseArchString(
+ Flag.drop_front(7), /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!MLConfigParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+llvm::consumeError(MLConfigParseResult.takeError());
+
+// We might got parsing error if rv32e in the list, we could just skip
+// that and process the rest of multi-lib configs.
+Skip = true;
+continue;
+ }
+ auto &MLConfigISAInfo = *MLConfigParseResult;
+
+ auto MLConfigArchExts = MLConfigISAInfo->getExtensions();
+ for (auto MLConfigArchExt : MLConfigArchExts) {
+auto ExtName = MLConfigArchExt.first;
+NewMultilib.flag(Twine("-", ExtName).str());
+
+if (!AllArchExts.contains(ExtName)) {
+ AllArchExts.inser
[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
4vtomat wrote: Resolved the comments and also modified the commit messages. https://github.com/llvm/llvm-project/pull/73765 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)
@@ -349,16 +349,24 @@ multiclass VPseudoSiFiveVMACC;
}
-multiclass VPseudoSiFiveVQMACC {
+multiclass VPseudoSiFiveVQMACCDOD {
foreach m = MxListVF8 in
let VLMul = m.value in
defm NAME : VPseudoSiFiveVMACC;
}
+multiclass VPseudoSiFiveVQMACCQOQ {
+ foreach i = [0, 1, 2, 3] in
+let VLMul = MxListVF4[i].value in
+defm NAME : VPseudoSiFiveVMACChttps://github.com/llvm/llvm-project/pull/75768
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[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)
@@ -349,16 +349,24 @@ multiclass VPseudoSiFiveVMACC;
}
-multiclass VPseudoSiFiveVQMACC {
+multiclass VPseudoSiFiveVQMACCDOD {
foreach m = MxListVF8 in
let VLMul = m.value in
defm NAME : VPseudoSiFiveVMACC;
}
+multiclass VPseudoSiFiveVQMACCQOQ {
+ foreach i = [0, 1, 2, 3] in
+let VLMul = MxListVF4[i].value in
+defm NAME : VPseudoSiFiveVMACC;
+}
+
multiclass VPseudoSiFiveVFWMACC {
- foreach m = MxListFW in
-let VLMul = m.value in
-defm NAME : VPseudoSiFiveVMACC;
+ foreach i = [0, 1, 2, 3, 4] in
+let VLMul = MxListVF2[i].value in
+defm NAME : VPseudoSiFiveVMACC;
4vtomat wrote:
Yes, it's the same lol~
https://github.com/llvm/llvm-project/pull/75768
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[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)
@@ -553,29 +560,40 @@ class GetFTypeInfo {
}
multiclass VPatVMACC info_pairs, ValueType vec_m1> {
+ list info_pairs, ValueType vec_m1,
+ bit lmul_follows_vd = 0> {
4vtomat wrote:
Oh, that's right.
https://github.com/llvm/llvm-project/pull/75768
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[llvm] [clang] Recommit [RISCV] Update the interface of sifive vqmaccqoq (#74284) (PR #75768)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/75768 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/77487
This patch optimize:
1. Reduce string size of RVVIntrinsicDef.
2. Reduce the type size of the index of intrinsics.
I use valgrind --tool=massif to analyze a simple program:
```
#include
vint32m1_t test(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
```
and before optimization, the peak memory usage is 15.68MB,
after optimization, the peak memory usage is 13.69MB.
>From 84ea759c43d8e9cb450d95d00fd802be622153a2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
This patch optimize:
1. Reduce string size of RVVIntrinsicDef.
2. Reduce the type size of the index of intrinsics.
I use valgrind --tool=massif to analyze a simple program:
```
#include
vint32m1_t test(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
```
and before optimization, the peak memory usage is 15.68MB,
after optimization, the peak memory usage is 13.69MB.
---
clang/include/clang/Support/RISCVVIntrinsicUtils.h | 6 --
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 13 +++--
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 5 -
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index c525d3443331e0..7e20f022c28b55 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes &getInputTypes() const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
+ llvm::StringRef getOverloadedName() const {
+return "__riscv_" + OverloadedName;
+ }
bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
bool hasVL() const { return HasVL; }
bool hasPolicy() const { return Scheme != PolicyScheme::SchemeNone; }
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 3ed3e619544189..e9523871e9cd1f 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -43,7 +43,7 @@ struct RVVIntrinsicDef {
struct RVVOverloadIntrinsicDef {
// Indexes of RISCVIntrinsicManagerImpl::IntrinsicList.
- SmallVector Indexes;
+ SmallVector Indexes;
};
} // namespace
@@ -162,7 +162,7 @@ class RISCVIntrinsicManagerImpl : public
sema::RISCVIntrinsicManager {
// List of all RVV intrinsic.
std::vector IntrinsicList;
// Mapping function name to index of IntrinsicList.
- StringMap Intrinsics;
+ StringMap Intrinsics;
// Mapping function name to RVVOverloadIntrinsicDef.
StringMap OverloadIntrinsics;
@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
OverloadedName += "_" + OverloadedSuffixStr.str();
// clang built-in function name, e.g. __builtin_rvv_vadd.
- std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
+ std::string BuiltinName = std::string(Record.Name);
RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName,
OverloadedName, PolicyAttrs,
Record.HasFRMRoundModeOp);
// Put into IntrinsicList.
- uint32_t Index = IntrinsicList.size();
+ uint16_t Index = IntrinsicList.size();
IntrinsicList.push_back({BuiltinName, Signature});
// Creating mapping to Intrinsics.
@@ -452,7 +452,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
RVVIntrinsicDecl->addAttr(OverloadableAttr::CreateImplicit(Context));
// Setup alias to __builtin_rvv_*
- IdentifierInfo &IntrinsicII = PP.getIdentifierTable().get(IDef.BuiltinName);
+ IdentifierInfo &IntrinsicII =
+ PP.getIdentifierTable().get("__builtin_rvv_" + IDef.BuiltinName);
RVVIntrinsicDecl->addAttr(
BuiltinAliasAttr::CreateImplicit(S.Context, &IntrinsicII));
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR,
IdentifierInfo *II,
Preprocessor &PP) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
// Lookup the function name from the overload intrinsics first.
auto OvIItr = OverloadIntrinsics.find(Name);
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 2de977a3dc72
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
4vtomat wrote:
Very minor too, if you use std::pair, could you add the comments describing
what the fields represent?
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+const auto *FoundProfile =
+llvm::find_if(SupportedProfiles, [&](const RISCVProfile &Profile) {
+ return Arch.starts_with(Profile.Name);
+});
+
+if (FoundProfile == std::end(SupportedProfiles))
+ return createStringError(errc::invalid_argument, "unsupported profile");
+
+NewArch = FoundProfile->MArch;
+StringRef ArchWithoutProfile = Arch.substr(strlen(FoundProfile->Name));
+if (!ArchWithoutProfile.empty()) {
+ if (!ArchWithoutProfile.starts_with("_"))
+return createStringError(
+errc::invalid_argument,
+"additional extensions must be after separator '_'");
+ NewArch = NewArch + ArchWithoutProfile.str();
4vtomat wrote:
Maybe `NewArch += ArchWithoutProfile.str()` to reduce 1 redundant copy?
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
4vtomat wrote:
`NewArch` might be assigned twice, I'm wondering whether we can pre-reserve a
chunk of memory beforehand to prevent 1 more memory allocation?
https://github.com/llvm/llvm-project/pull/76357
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
However, if we can do something like that, we can get about 5x speedup with my
rough measurement lol~
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
@topperc I'm not sure why we also need "-" for features that are not enabled,
is there any use case?
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
> @4vtomat if the MCPU has a feature but the function explicitly disables it
> then I think we want the `-`
Why don't we just remove it from feature map?
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
> > But we don't have the FunctionDecl info in the
> > RISCVTargetInfo::initFeatureMap call.
>
> What about keeping this map in ASTContext instead?
I guess it might be a feasible solution, however the memory usage might
increase since it has to keep the map for each function during the lifetime of
the ASTContext.
@topperc Do you think we can do this? Or we can leave it in TODO until it
becomes a problem in some real cases.
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
@lukel97 Got it, thanks!
https://github.com/llvm/llvm-project/pull/83674
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[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
4vtomat wrote: Rebase and squash https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77560
>From 08371002a08d8958cd23eecb5ff3c5f2f2661c0e Mon Sep 17 00:00:00 2001
From: 4vtomat
Date: Wed, 22 Mar 2023 22:58:35 -0700
Subject: [PATCH] [RISCV] RISCV vector calling convention (1/2)
This is the vector calling convention based on
https://github.com/riscv-non-isa/riscv-elf-psabi-doc,
the idea is to split between "scalar" callee-saved registers
and "vector" callee-saved registers. "scalar" ones remain the
original strategy, however, "vector" ones are handled together
with RVV objects.
The stack layout would be:
|--| <-- FP
| callee-allocated save|
| area for register varargs|
|--|
| callee-saved registers | <-- scalar callee-saved
|(scalar) |
|--|
| RVV alignment padding|
|--|
| callee-saved registers | <-- vector callee-saved
|(vector) |
|--|
| RVV objects |
|--|
| padding before RVV |
|--|
| scalar local variables |
|--| <-- BP
| variable size objects|
|--| <-- SP
Note: This patch doesn't contain "tuple" type, e.g. vint32m1x2.
It will be handled in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc (2/2).
Differential Revision: https://reviews.llvm.org/D154576
---
clang/include/clang-c/Index.h | 1 +
clang/include/clang/Basic/Attr.td | 7 ++
clang/include/clang/Basic/AttrDocs.td | 11 +++
clang/include/clang/Basic/Specifiers.h| 43
clang/lib/AST/ItaniumMangle.cpp | 1 +
clang/lib/AST/Type.cpp| 4 +
clang/lib/AST/TypePrinter.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.cpp | 11 +++
clang/lib/Basic/Targets/RISCV.h | 2 +
clang/lib/CodeGen/CGCall.cpp | 6 ++
clang/lib/CodeGen/CGDebugInfo.cpp | 2 +
clang/lib/Sema/SemaDeclAttr.cpp | 7 ++
clang/lib/Sema/SemaType.cpp | 5 +-
.../RISCV/riscv-vector-callingconv-llvm-ir.c | 34 +++
.../riscv-vector-callingconv-llvm-ir.cpp | 32 ++
.../CodeGen/RISCV/riscv-vector-callingconv.c | 17
.../RISCV/riscv-vector-callingconv.cpp| 35 +++
clang/tools/libclang/CXType.cpp | 1 +
llvm/include/llvm/AsmParser/LLToken.h | 1 +
llvm/include/llvm/BinaryFormat/Dwarf.def | 1 +
llvm/include/llvm/IR/CallingConv.h| 3 +
llvm/lib/AsmParser/LLLexer.cpp| 1 +
llvm/lib/AsmParser/LLParser.cpp | 4 +
llvm/lib/IR/AsmWriter.cpp | 3 +
llvm/lib/Target/RISCV/RISCVCallingConv.td | 13 +++
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 97 +--
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 15 +++
.../CodeGen/RISCV/rvv/callee-saved-regs.ll| 95 ++
29 files changed, 409 insertions(+), 50 deletions(-)
create mode 100644 clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
create mode 100644
clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
create mode 100644 clang/test/CodeGen/RISCV/riscv-vector-callingconv.c
create mode 100644 clang/test/CodeGen/RISCV/riscv-vector-callingconv.cpp
create mode 100644 llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index 60db3cf0966c02..7a8bd985a91fc0 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -2991,6 +2991,7 @@ enum CXCallingConv {
CXCallingConv_AArch64SVEPCS = 18,
CXCallingConv_M68kRTD = 19,
CXCallingConv_PreserveNone = 20,
+ CXCallingConv_RISCVVectorCall = 21,
CXCallingConv_Invalid = 100,
CXCallingConv_Unexposed = 200
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 318d4e5ac5ba44..80e607525a0a37 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -3011,6 +3011,13 @@ def PreserveNone : DeclOrTypeAttr,
TargetSpecificAttr {
let Documentation = [PreserveNoneDocs];
}
+def RISCVVectorCC: DeclOrTypeAttr, TargetSpecificAttr {
+ let Spellings = [CXX11<"riscv", "vector_cc">,
+ C23<"riscv", "vector_cc">,
+ Clang<"riscv_vector_cc">];
+ let Documentation = [RISCVVectorCCDocs];
+}
+
def Target : InheritableAttr {
let Spellings = [GCC<"target">];
let Args = [StringArgument<"featuresStr">];
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index 384aebbdf2e32a..3ea4d676b4f89d 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5494,6 +5494,17 @@ for clang builtin functio
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From 10ab0fa16e62e44b8d04b372f20b95018f065048 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
__attribute__((target("arch=+v")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 5ecd2f9eb2881f..3a1abd4c7892b8 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -2234,7 +2234,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap &FeatureMap);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index f3d705e1551fe2..d597309905b4cf 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index b55f433a8be76f..72393bea620526 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2065,8 +2065,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 08449581330934..447e73686b4f3f 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5760,57 +5760,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
&TI, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Check if each required feature is included
- for (StringRef F : ReqFeatures) {
-SmallVector ReqOpFeatures;
-F.split(ReqOpFeatures, '|');
-
-if (llvm::none_of(ReqOpFeatures,
- [&TI](StringRef OF) { return TI.hasFeature(OF); })) {
- std::string FeatureStrs;
- bool IsExtension = true;
- for (StringRef OF : ReqOpFeatures) {
-// If the feature is 64bit, alter the string so it will print better in
-// the diagnostic.
-if (OF == "64bit") {
-
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
4vtomat wrote: Rebase https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
4vtomat wrote: The latest fixup commit add [[riscv::riscv_vector]] supports for C23 and C++11. https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/83553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Improve error message when the extension is not supported (PR #83989)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83989
>From 764c861931fd8013df5b144c2d789614bc952126 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 5 Mar 2024 02:28:10 -0800
Subject: [PATCH 1/2] [RISCV] Improve error message when the extension is not
supported
If the "march" has some extension with version that is not supported, it
returns the error message like: "error: invalid arch name 'some_arch',
unsupported version number 2.0 for extension 'some_arch'", which is not
precise enough, it should return the message that only tells users "the
extension is not supported".
---
clang/test/Driver/riscv-arch.c| 4 ++--
llvm/lib/Support/RISCVISAInfo.cpp | 26 --
2 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index c9e984e07cbea9..8399b4e97f86d5 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -306,7 +306,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ist2p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s
// RV32-SMINOR0: error: invalid arch name 'rv32ist2p0',
-// RV32-SMINOR0: unsupported version number 2.0 for extension 'st'
+// RV32-SMINOR0: unsupported standard supervisor-level extension 'st'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_ -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
@@ -397,7 +397,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izbb1p0zbs1p0
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE: error: invalid arch name
'rv32izbb1p0zbs1p0', unsupported version number 1.0 for extension 'zbb1p0zbs'
+// RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE: error: invalid arch name
'rv32izbb1p0zbs1p0', unsupported standard user-level extension 'zbb1p0zbs'
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izba1p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBA %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 54b4dcb22de8e0..6eec03fd6f7082 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -531,6 +531,17 @@ std::vector RISCVISAInfo::toFeatures(bool
AddAllExtensions,
return Features;
}
+static Error getStringErrorForInvalidExt(std::string_view ExtName) {
+ if (ExtName.size() == 1) {
+return createStringError(errc::invalid_argument,
+ "unsupported standard user-level extension '" +
+ ExtName + "'");
+ }
+ return createStringError(errc::invalid_argument,
+ "unsupported " + getExtensionTypeDesc(ExtName) +
+ " '" + ExtName + "'");
+}
+
// Extensions may have a version number, and may be separated by
// an underscore '_' e.g.: rv32i2_m2.
// Version number is divided into major and minor version numbers,
@@ -629,6 +640,9 @@ static Error getExtensionVersion(StringRef Ext, StringRef
In, unsigned &Major,
if (RISCVISAInfo::isSupportedExtension(Ext, Major, Minor))
return Error::success();
+ if (!RISCVISAInfo::isSupportedExtension(Ext))
+return getStringErrorForInvalidExt(Ext);
+
std::string Error = "unsupported version number " + std::string(MajorStr);
if (!MinorStr.empty())
Error += "." + MinorStr.str();
@@ -965,16 +979,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
const std::string &ExtName = SeenExtAndVers.first;
RISCVISAInfo::ExtensionVersion ExtVers = SeenExtAndVers.second;
-if (!RISCVISAInfo::isSupportedExtension(ExtName)) {
- if (ExtName.size() == 1) {
-return createStringError(errc::invalid_argument,
- "unsupported standard user-level extension '"
+
- ExtName + "'");
- }
- return createStringError(errc::invalid_argument,
- "unsupported " + getExtensionTypeDesc(ExtName) +
- " '" + ExtName + "'");
-}
+if (!RISCVISAInfo::isSupportedExtension(ExtName))
+ return getStringErrorForInvalidExt(ExtName);
ISAInfo->addExtension(ExtName, ExtVers);
}
>From 0eb84049821dc6f71c185215b16696508cd46261 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 5 Mar 2024 17:20:09 -0800
Subject: [PATCH 2/2] fixup! [RISCV] Improve error message when the extension
is not supported
---
llvm/unittests/Support/RISCVISAInfoTest.cpp | 15 +++
1 file changed, 15 insertions(+)
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp
b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 8a627eca05cb4b..82cf4c639b6160 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RIS
[clang] [llvm] [RISCV] Improve error message when the extension is not supported (PR #83989)
4vtomat wrote: > perhaps the llvm libSupport prats of this change should be unit tested in > LLVM, rather than only tested indirectly in clang? Good point, thanks! I've added for unites. https://github.com/llvm/llvm-project/pull/83989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Improve error message when the extension is not supported (PR #83989)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/83989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From faab3d0d9163e99185fb6a2d3efd21549ed33e00 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
__attribute__((target("arch=+v")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 25c4c58ad4ae43..229ae7c1050cd6 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -14081,7 +14081,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap &FeatureMap);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..6991caa21d23b4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index cfb653e665ea03..41c7bfb25a7921 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,8 +2077,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 561764edd08100..2a6aceaefa9b19 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5429,57 +5429,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
&TI, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Check if each required feature is included
- for (StringRef F : ReqFeatures) {
-SmallVector ReqOpFeatures;
-F.split(ReqOpFeatures, '|');
-
-if (llvm::none_of(ReqOpFeatures,
- [&TI](StringRef OF) { return TI.hasFeature(OF); })) {
- std::string FeatureStrs;
- bool IsExtension = true;
- for (StringRef OF : ReqOpFeatures) {
-// If the feature is 64bit, alter the string so it will print better in
-// the diagnostic.
-if (OF == "64bit") {
-
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
4vtomat wrote: Rebase. https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
@@ -3439,6 +3439,8 @@ StringRef FunctionType::getNameForCallConv(CallingConv
CC) {
case CC_PreserveAll: return "preserve_all";
case CC_M68kRTD: return "m68k_rtd";
case CC_PreserveNone: return "preserve_none";
+ case CC_RISCVVectorCall:
4vtomat wrote:
Sure~
https://github.com/llvm/llvm-project/pull/77560
___
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
Yes, it does.
With 100k RVV type declarations,
This pr's compile time is approximately 8 times slower than original one.(0.56
seconds vs 0.07 seconds on the server)
https://github.com/llvm/llvm-project/pull/83674
___
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
Mostly costed by `llvm::RISCVISAInfo::parseFeatures` in
`RISCVTargetInfo::initFeatureMap`.
https://github.com/llvm/llvm-project/pull/83674
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[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
4vtomat wrote: ping https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83553
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
'zve64x' extension"
which is supposed to be "RISC-V type 'vfloat64m1_t' ... requires the 'zve64d'
extension".
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH] [clang][RISCV] Reorder sema check for RVV type
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
'zve64x' extension"
which is supposed to be "RISC-V type 'vfloat64m1_t' ... requires the 'zve64d'
extension".
---
clang/lib/Sema/SemaChecking.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 979b63884359fc..27ed6f2da05254 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6332,9 +6332,12 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned EltSize = Context.getTypeSize(Info.ElementType);
unsigned MinElts = Info.EC.getKnownMinValue();
+ if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
+ !TI.hasFeature("zve64d"))
+Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
@@ -6347,9 +6350,6 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
- else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
-Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// Given that caller already checked isRVVType() before calling this
function,
// if we don't have at least zve32x supported, then we need to emit error.
else if (!TI.hasFeature("zve32x"))
___
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[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83553
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH 1/2] [clang][RISCV] Reorder sema check for RVV type
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
'zve64x' extension"
which is supposed to be "RISC-V type 'vfloat64m1_t' ... requires the 'zve64d'
extension".
---
clang/lib/Sema/SemaChecking.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 979b63884359fc..27ed6f2da05254 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6332,9 +6332,12 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned EltSize = Context.getTypeSize(Info.ElementType);
unsigned MinElts = Info.EC.getKnownMinValue();
+ if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
+ !TI.hasFeature("zve64d"))
+Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
@@ -6347,9 +6350,6 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
- else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
-Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// Given that caller already checked isRVVType() before calling this
function,
// if we don't have at least zve32x supported, then we need to emit error.
else if (!TI.hasFeature("zve32x"))
>From 779aebac10d2128d4507f74c2c929ab0924a80b6 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 02:57:00 -0800
Subject: [PATCH 2/2] fixup! [clang][RISCV] Reorder sema check for RVV type
---
clang/lib/Sema/SemaChecking.cpp | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 27ed6f2da05254..ae011806eec629 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6333,12 +6333,13 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned MinElts = Info.EC.getKnownMinValue();
if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
+ !TI.hasFeature("zve64d"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
- !TI.hasFeature("zve64x"))
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) ||
+MinElts == 1) &&
+ !TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
!TI.hasFeature("zvfhmin"))
___
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[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83553
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH 1/3] [clang][RISCV] Reorder sema check for RVV type
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
'zve64x' extension"
which is supposed to be "RISC-V type 'vfloat64m1_t' ... requires the 'zve64d'
extension".
---
clang/lib/Sema/SemaChecking.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 979b63884359fc..27ed6f2da05254 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6332,9 +6332,12 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned EltSize = Context.getTypeSize(Info.ElementType);
unsigned MinElts = Info.EC.getKnownMinValue();
+ if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
+ !TI.hasFeature("zve64d"))
+Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
@@ -6347,9 +6350,6 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
- else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
-Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// Given that caller already checked isRVVType() before calling this
function,
// if we don't have at least zve32x supported, then we need to emit error.
else if (!TI.hasFeature("zve32x"))
>From 779aebac10d2128d4507f74c2c929ab0924a80b6 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 02:57:00 -0800
Subject: [PATCH 2/3] fixup! [clang][RISCV] Reorder sema check for RVV type
---
clang/lib/Sema/SemaChecking.cpp | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 27ed6f2da05254..ae011806eec629 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6333,12 +6333,13 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned MinElts = Info.EC.getKnownMinValue();
if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
+ !TI.hasFeature("zve64d"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
- !TI.hasFeature("zve64x"))
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) ||
+MinElts == 1) &&
+ !TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
!TI.hasFeature("zvfhmin"))
>From ee33c7d12c307835b5f999eef9f3db6f0d0071f7 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 2 Mar 2024 02:58:12 -0800
Subject: [PATCH 3/3] fixup! [clang][RISCV] Reorder sema check for RVV type
---
clang/test/Sema/riscv-vector-float64-check.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/clang/test/Sema/riscv-vector-float64-check.c
b/clang/test/Sema/riscv-vector-float64-check.c
index ee7db32663959e..f21ae5c0c70405 100644
--- a/clang/test/Sema/riscv-vector-float64-check.c
+++ b/clang/test/Sema/riscv-vector-float64-check.c
@@ -1,5 +1,4 @@
-// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64f -target-feature +zfh \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zve32x \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// REQUIRES: riscv-registered-target
#include
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[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
4vtomat wrote: Maybe we can modify the current test case, it would get the error message "RISC-V type 'vfloat64m1_t' ... requires the 'zve64x' extension", but should be 'zve64d' instead. https://github.com/llvm/llvm-project/pull/83553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Support function attribute __attribute__((target("+attr"))) (PR #83674)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83674
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
>From 51c523397008dd307bfbc190fd8966fbc4fa4331 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH] [clang][RISCV] Support function attribute
__attribute__((target("+attr")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index ef4b93fac95ce5..932b76c82af0ee 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -14067,7 +14067,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap &FeatureMap);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..6991caa21d23b4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index cfb653e665ea03..41c7bfb25a7921 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,8 +2077,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 0d4d57db01c93a..50afb56ae09eac 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5415,57 +5415,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
&TI, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Ch
[clang] [clang][RISCV] Support function attribute __attribute__((target("+attr"))) (PR #83674)
4vtomat wrote: Related request: https://github.com/riscv-non-isa/riscv-c-api-doc/issues/69 https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
4vtomat wrote:
> I tried compiling it and then got two warnings.
>
> ```
> llvm-project/clang/lib/CodeGen/CGDebugInfo.cpp:1408:11: warning: enumeration
> value 'CC_RISCVVectorCall' not handled in switch [-Wswitch]
> 1408 | switch (CC) {
> | ^~
> 1 warning generated.
> [3629/3776] Building CXX object
> tools/clang/tools/libclang/CMakeFiles/libclang.dir/CXType.cpp.o
> llvm-project/clang/tools/libclang/CXType.cpp:662:13: warning: enumeration
> value 'CC_RISCVVectorCall' not handled in switch [-Wswitch]
> 662 | switch (FD->getCallConv()) {
> | ^
> 1 warning generated.
> ```
I forgot to add these cases for `CC_RISCVVectorCall` lol, thanks~
https://github.com/llvm/llvm-project/pull/77560
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[clang] [clang][RISCV] Support function attribute __attribute__((target("+attr"))) (PR #83674)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From f14c54cb7c3c31e84a78ddf33b932c4c74e20365 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/2] [clang][RISCV] Enable RVV with function attribute
__attribute__((target("arch=+v")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index ef4b93fac95ce5..932b76c82af0ee 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -14067,7 +14067,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap &FeatureMap);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..6991caa21d23b4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index cfb653e665ea03..41c7bfb25a7921 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,8 +2077,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 0d4d57db01c93a..50afb56ae09eac 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5415,57 +5415,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
&TI, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Check if each required feature is included
- for (StringRef F : ReqFeatures) {
-SmallVector ReqOpFeatures;
-F.split(ReqOpFeatures, '|');
-
-if (llvm::none_of(ReqOpFeatures,
- [&TI](StringRef OF) { return TI.hasFeature(OF); })) {
- std::string FeatureStrs;
- bool IsExtension = true;
- for (StringRef OF : ReqOpFeatures) {
-// If the feature is 64bit, alter the string so it will print better in
-// the diagnostic.
-if (OF == "64bit") {
-
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("+attr"))) (PR #83674)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -S -verify %s
+
+// REQUIRES: riscv-registered-target
+#include
+
+void test_builtin() {
+ __riscv_vsetvl_e8m8(1); // expected-error {{'__builtin_rvv_vsetvli' needs
target feature zve32x}}
+}
+
+__attribute__((target("+zve32x")))
4vtomat wrote:
Updated thanks!
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
4vtomat wrote:
Updated!
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From f14c54cb7c3c31e84a78ddf33b932c4c74e20365 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
__attribute__((target("arch=+v")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index ef4b93fac95ce5..932b76c82af0ee 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -14067,7 +14067,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap &FeatureMap);
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..6991caa21d23b4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index cfb653e665ea03..41c7bfb25a7921 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,8 +2077,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 0d4d57db01c93a..50afb56ae09eac 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5415,57 +5415,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
&TI, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Check if each required feature is included
- for (StringRef F : ReqFeatures) {
-SmallVector ReqOpFeatures;
-F.split(ReqOpFeatures, '|');
-
-if (llvm::none_of(ReqOpFeatures,
- [&TI](StringRef OF) { return TI.hasFeature(OF); })) {
- std::string FeatureStrs;
- bool IsExtension = true;
- for (StringRef OF : ReqOpFeatures) {
-// If the feature is 64bit, alter the string so it will print better in
-// the diagnostic.
-if (OF == "64bit") {
-
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
4vtomat wrote: Move the test cases to existing files. https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Improve error message when the extension is not supported (PR #83989)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83989
If the "march" has some extension with version that is not supported, it
returns the error message like: "error: invalid arch name 'some_arch',
unsupported version number 2.0 for extension 'some_arch'", which is not
precise enough, it should return the message that only tells users "the
extension is not supported".
>From 764c861931fd8013df5b144c2d789614bc952126 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 5 Mar 2024 02:28:10 -0800
Subject: [PATCH] [RISCV] Improve error message when the extension is not
supported
If the "march" has some extension with version that is not supported, it
returns the error message like: "error: invalid arch name 'some_arch',
unsupported version number 2.0 for extension 'some_arch'", which is not
precise enough, it should return the message that only tells users "the
extension is not supported".
---
clang/test/Driver/riscv-arch.c| 4 ++--
llvm/lib/Support/RISCVISAInfo.cpp | 26 --
2 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index c9e984e07cbea9..8399b4e97f86d5 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -306,7 +306,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ist2p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s
// RV32-SMINOR0: error: invalid arch name 'rv32ist2p0',
-// RV32-SMINOR0: unsupported version number 2.0 for extension 'st'
+// RV32-SMINOR0: unsupported standard supervisor-level extension 'st'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_ -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
@@ -397,7 +397,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izbb1p0zbs1p0
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE: error: invalid arch name
'rv32izbb1p0zbs1p0', unsupported version number 1.0 for extension 'zbb1p0zbs'
+// RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE: error: invalid arch name
'rv32izbb1p0zbs1p0', unsupported standard user-level extension 'zbb1p0zbs'
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izba1p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBA %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 54b4dcb22de8e0..6eec03fd6f7082 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -531,6 +531,17 @@ std::vector RISCVISAInfo::toFeatures(bool
AddAllExtensions,
return Features;
}
+static Error getStringErrorForInvalidExt(std::string_view ExtName) {
+ if (ExtName.size() == 1) {
+return createStringError(errc::invalid_argument,
+ "unsupported standard user-level extension '" +
+ ExtName + "'");
+ }
+ return createStringError(errc::invalid_argument,
+ "unsupported " + getExtensionTypeDesc(ExtName) +
+ " '" + ExtName + "'");
+}
+
// Extensions may have a version number, and may be separated by
// an underscore '_' e.g.: rv32i2_m2.
// Version number is divided into major and minor version numbers,
@@ -629,6 +640,9 @@ static Error getExtensionVersion(StringRef Ext, StringRef
In, unsigned &Major,
if (RISCVISAInfo::isSupportedExtension(Ext, Major, Minor))
return Error::success();
+ if (!RISCVISAInfo::isSupportedExtension(Ext))
+return getStringErrorForInvalidExt(Ext);
+
std::string Error = "unsupported version number " + std::string(MajorStr);
if (!MinorStr.empty())
Error += "." + MinorStr.str();
@@ -965,16 +979,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
const std::string &ExtName = SeenExtAndVers.first;
RISCVISAInfo::ExtensionVersion ExtVers = SeenExtAndVers.second;
-if (!RISCVISAInfo::isSupportedExtension(ExtName)) {
- if (ExtName.size() == 1) {
-return createStringError(errc::invalid_argument,
- "unsupported standard user-level extension '"
+
- ExtName + "'");
- }
- return createStringError(errc::invalid_argument,
- "unsupported " + getExtensionTypeDesc(ExtName) +
- " '" + ExtName + "'");
-}
+if (!RISCVISAInfo::isSupportedExtension(ExtName))
+ return getStringErrorForInvalidExt(ExtName);
ISAInfo->addExtension(ExtName, ExtVers);
}
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[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/79618 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/79615 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (PR #79407)
@@ -10,7 +10,8 @@ // CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT:call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT:[[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32 4vtomat wrote: I guess it's because I just use "i" for `sf_vc_x` in `riscv_sifive_vector.td`. Maybe I should also add ["c", "s", "l"] back~ https://github.com/llvm/llvm-project/pull/79407 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77487
>From 84ea759c43d8e9cb450d95d00fd802be622153a2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/2] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
This patch optimize:
1. Reduce string size of RVVIntrinsicDef.
2. Reduce the type size of the index of intrinsics.
I use valgrind --tool=massif to analyze a simple program:
```
#include
vint32m1_t test(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
```
and before optimization, the peak memory usage is 15.68MB,
after optimization, the peak memory usage is 13.69MB.
---
clang/include/clang/Support/RISCVVIntrinsicUtils.h | 6 --
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 13 +++--
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 5 -
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index c525d3443331e0b..7e20f022c28b551 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes &getInputTypes() const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
+ llvm::StringRef getOverloadedName() const {
+return "__riscv_" + OverloadedName;
+ }
bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
bool hasVL() const { return HasVL; }
bool hasPolicy() const { return Scheme != PolicyScheme::SchemeNone; }
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 3ed3e6195441893..e9523871e9cd1fb 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -43,7 +43,7 @@ struct RVVIntrinsicDef {
struct RVVOverloadIntrinsicDef {
// Indexes of RISCVIntrinsicManagerImpl::IntrinsicList.
- SmallVector Indexes;
+ SmallVector Indexes;
};
} // namespace
@@ -162,7 +162,7 @@ class RISCVIntrinsicManagerImpl : public
sema::RISCVIntrinsicManager {
// List of all RVV intrinsic.
std::vector IntrinsicList;
// Mapping function name to index of IntrinsicList.
- StringMap Intrinsics;
+ StringMap Intrinsics;
// Mapping function name to RVVOverloadIntrinsicDef.
StringMap OverloadIntrinsics;
@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
OverloadedName += "_" + OverloadedSuffixStr.str();
// clang built-in function name, e.g. __builtin_rvv_vadd.
- std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
+ std::string BuiltinName = std::string(Record.Name);
RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName,
OverloadedName, PolicyAttrs,
Record.HasFRMRoundModeOp);
// Put into IntrinsicList.
- uint32_t Index = IntrinsicList.size();
+ uint16_t Index = IntrinsicList.size();
IntrinsicList.push_back({BuiltinName, Signature});
// Creating mapping to Intrinsics.
@@ -452,7 +452,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
RVVIntrinsicDecl->addAttr(OverloadableAttr::CreateImplicit(Context));
// Setup alias to __builtin_rvv_*
- IdentifierInfo &IntrinsicII = PP.getIdentifierTable().get(IDef.BuiltinName);
+ IdentifierInfo &IntrinsicII =
+ PP.getIdentifierTable().get("__builtin_rvv_" + IDef.BuiltinName);
RVVIntrinsicDecl->addAttr(
BuiltinAliasAttr::CreateImplicit(S.Context, &IntrinsicII));
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR,
IdentifierInfo *II,
Preprocessor &PP) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
// Lookup the function name from the overload intrinsics first.
auto OvIItr = OverloadIntrinsics.find(Name);
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 2de977a3dc720bd..7d2a2d7e826f9cd 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -1150,11 +1150,6 @@ void RVVIntrinsic::updateNamesAndPolicy(
OverloadedName += suffix;
};
- // This follows the naming guideline under riscv-c-api-doc to add the
- // `__riscv_` suffix for all RVV intrinsics.
- Name = "__riscv_" + Name;
- OverloadedName =
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic( OverloadedName += "_" + OverloadedSuffixStr.str(); // clang built-in function name, e.g. __builtin_rvv_vadd. - std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name); + std::string BuiltinName = std::string(Record.Name); RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName, OverloadedName, PolicyAttrs, Record.HasFRMRoundModeOp); // Put into IntrinsicList. - uint32_t Index = IntrinsicList.size(); + uint16_t Index = IntrinsicList.size(); 4vtomat wrote: I've added an assertion for checking whether intrinsics overflow. https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV][RVV Intrinsic] Fix codegen redundant intrinsic names (PR #77889)
https://github.com/4vtomat approved this pull request. Thanks, LGTM~ https://github.com/llvm/llvm-project/pull/77889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add missing dependency check for Zvkb (PR #79467)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/79467
None
>From 61dd60b6172df5a73daa403d1fc5b5e39169df40 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 25 Jan 2024 08:13:31 -0800
Subject: [PATCH] [RISCV] Add missing dependency check for Zvkb
---
clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
index 1f8a5a8821edfa..ac70fb2631a590 100644
--- a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
+++ b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
@@ -66,7 +66,7 @@
// RUN: -target riscv64-unknown-elf \
// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \
// RUN: --print-multi-directory \
-// RUN: -march=rv32i_zvkb -mabi=ilp32 \
+// RUN: -march=rv32iv_zvkb -mabi=ilp32 \
// RUN: | FileCheck -check-prefix=GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32 %s
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32: rv32i/ilp32
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32-NOT: {{^.+$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 32b4ff5de86f1e..a359e6eefa8f1d 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -976,8 +976,8 @@ Error RISCVISAInfo::checkDependency() {
errc::invalid_argument,
"'zvbc' requires 'v' or 'zve64*' extension to also be specified");
- if ((Exts.count("zvkg") || Exts.count("zvkned") || Exts.count("zvknha") ||
- Exts.count("zvksed") || Exts.count("zvksh")) &&
+ if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkned") ||
+ Exts.count("zvknha") || Exts.count("zvksed") || Exts.count("zvksh")) &&
!HasVector)
return createStringError(
errc::invalid_argument,
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -464,7 +466,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR,
IdentifierInfo *II,
Preprocessor &PP) {
- StringRef Name = II->getName().substr(8);
+ StringRef Name = II->getName();
+ Name.consume_front("__riscv_");
4vtomat wrote:
Sure~
https://github.com/llvm/llvm-project/pull/77487
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77487
>From 84ea759c43d8e9cb450d95d00fd802be622153a2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/3] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
This patch optimize:
1. Reduce string size of RVVIntrinsicDef.
2. Reduce the type size of the index of intrinsics.
I use valgrind --tool=massif to analyze a simple program:
```
#include
vint32m1_t test(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
```
and before optimization, the peak memory usage is 15.68MB,
after optimization, the peak memory usage is 13.69MB.
---
clang/include/clang/Support/RISCVVIntrinsicUtils.h | 6 --
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 13 +++--
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 5 -
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index c525d3443331e0b..7e20f022c28b551 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes &getInputTypes() const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
+ llvm::StringRef getOverloadedName() const {
+return "__riscv_" + OverloadedName;
+ }
bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
bool hasVL() const { return HasVL; }
bool hasPolicy() const { return Scheme != PolicyScheme::SchemeNone; }
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 3ed3e6195441893..e9523871e9cd1fb 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -43,7 +43,7 @@ struct RVVIntrinsicDef {
struct RVVOverloadIntrinsicDef {
// Indexes of RISCVIntrinsicManagerImpl::IntrinsicList.
- SmallVector Indexes;
+ SmallVector Indexes;
};
} // namespace
@@ -162,7 +162,7 @@ class RISCVIntrinsicManagerImpl : public
sema::RISCVIntrinsicManager {
// List of all RVV intrinsic.
std::vector IntrinsicList;
// Mapping function name to index of IntrinsicList.
- StringMap Intrinsics;
+ StringMap Intrinsics;
// Mapping function name to RVVOverloadIntrinsicDef.
StringMap OverloadIntrinsics;
@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
OverloadedName += "_" + OverloadedSuffixStr.str();
// clang built-in function name, e.g. __builtin_rvv_vadd.
- std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
+ std::string BuiltinName = std::string(Record.Name);
RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName,
OverloadedName, PolicyAttrs,
Record.HasFRMRoundModeOp);
// Put into IntrinsicList.
- uint32_t Index = IntrinsicList.size();
+ uint16_t Index = IntrinsicList.size();
IntrinsicList.push_back({BuiltinName, Signature});
// Creating mapping to Intrinsics.
@@ -452,7 +452,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
RVVIntrinsicDecl->addAttr(OverloadableAttr::CreateImplicit(Context));
// Setup alias to __builtin_rvv_*
- IdentifierInfo &IntrinsicII = PP.getIdentifierTable().get(IDef.BuiltinName);
+ IdentifierInfo &IntrinsicII =
+ PP.getIdentifierTable().get("__builtin_rvv_" + IDef.BuiltinName);
RVVIntrinsicDecl->addAttr(
BuiltinAliasAttr::CreateImplicit(S.Context, &IntrinsicII));
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR,
IdentifierInfo *II,
Preprocessor &PP) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
// Lookup the function name from the overload intrinsics first.
auto OvIItr = OverloadIntrinsics.find(Name);
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 2de977a3dc720bd..7d2a2d7e826f9cd 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -1150,11 +1150,6 @@ void RVVIntrinsic::updateNamesAndPolicy(
OverloadedName += suffix;
};
- // This follows the naming guideline under riscv-c-api-doc to add the
- // `__riscv_` suffix for all RVV intrinsics.
- Name = "__riscv_" + Name;
- OverloadedName =
[clang] [llvm] [RISCV] Add missing dependency check for Zvkb (PR #79467)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/79467
>From d451e89a2bf650d3af638a2d22582135ad53cc27 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 25 Jan 2024 08:13:31 -0800
Subject: [PATCH] [RISCV] Add missing dependency check for Zvkb
---
clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
index 1f8a5a8821edfa..ac70fb2631a590 100644
--- a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
+++ b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
@@ -66,7 +66,7 @@
// RUN: -target riscv64-unknown-elf \
// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \
// RUN: --print-multi-directory \
-// RUN: -march=rv32i_zvkb -mabi=ilp32 \
+// RUN: -march=rv32iv_zvkb -mabi=ilp32 \
// RUN: | FileCheck -check-prefix=GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32 %s
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32: rv32i/ilp32
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32-NOT: {{^.+$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 32b4ff5de86f1e..a359e6eefa8f1d 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -976,8 +976,8 @@ Error RISCVISAInfo::checkDependency() {
errc::invalid_argument,
"'zvbc' requires 'v' or 'zve64*' extension to also be specified");
- if ((Exts.count("zvkg") || Exts.count("zvkned") || Exts.count("zvknha") ||
- Exts.count("zvksed") || Exts.count("zvksh")) &&
+ if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkned") ||
+ Exts.count("zvknha") || Exts.count("zvksed") || Exts.count("zvksh")) &&
!HasVector)
return createStringError(
errc::invalid_argument,
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[llvm] [clang] [RISCV] Add missing dependency check for Zvkb (PR #79467)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/79467
>From 6f16a5b2807e1cab5edae90f92cf0145474f4f23 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 25 Jan 2024 08:13:31 -0800
Subject: [PATCH] [RISCV] Add missing dependency check for Zvkb
---
clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
index 1f8a5a8821edfad..ac70fb2631a590c 100644
--- a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
+++ b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
@@ -66,7 +66,7 @@
// RUN: -target riscv64-unknown-elf \
// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \
// RUN: --print-multi-directory \
-// RUN: -march=rv32i_zvkb -mabi=ilp32 \
+// RUN: -march=rv32iv_zvkb -mabi=ilp32 \
// RUN: | FileCheck -check-prefix=GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32 %s
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32: rv32i/ilp32
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32-NOT: {{^.+$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 32b4ff5de86f1ea..a359e6eefa8f1d1 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -976,8 +976,8 @@ Error RISCVISAInfo::checkDependency() {
errc::invalid_argument,
"'zvbc' requires 'v' or 'zve64*' extension to also be specified");
- if ((Exts.count("zvkg") || Exts.count("zvkned") || Exts.count("zvknha") ||
- Exts.count("zvksed") || Exts.count("zvksh")) &&
+ if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkned") ||
+ Exts.count("zvknha") || Exts.count("zvksed") || Exts.count("zvksh")) &&
!HasVector)
return createStringError(
errc::invalid_argument,
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[llvm] [clang] [RISCV] Add missing dependency check for Zvkb (PR #79467)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/79467 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (PR #79407)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/79407 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77487
>From d52f1e4652f7791413c61cfb075755a46fca8cfa Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/3] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
This patch optimize:
1. Reduce string size of RVVIntrinsicDef.
2. Reduce the type size of the index of intrinsics.
I use valgrind --tool=massif to analyze a simple program:
```
#include
vint32m1_t test(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
```
and before optimization, the peak memory usage is 15.68MB,
after optimization, the peak memory usage is 13.69MB.
---
clang/include/clang/Support/RISCVVIntrinsicUtils.h | 6 --
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 13 +++--
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 5 -
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 05a5e02e1390054..a0b70d1c4155039 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes &getInputTypes() const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
+ llvm::StringRef getOverloadedName() const {
+return "__riscv_" + OverloadedName;
+ }
bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
bool hasVL() const { return HasVL; }
bool hasPolicy() const { return Scheme != PolicyScheme::SchemeNone; }
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 00a5ea65f3f4e7d..0f8c3e99f0c84e9 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -43,7 +43,7 @@ struct RVVIntrinsicDef {
struct RVVOverloadIntrinsicDef {
// Indexes of RISCVIntrinsicManagerImpl::IntrinsicList.
- SmallVector Indexes;
+ SmallVector Indexes;
};
} // namespace
@@ -162,7 +162,7 @@ class RISCVIntrinsicManagerImpl : public
sema::RISCVIntrinsicManager {
// List of all RVV intrinsic.
std::vector IntrinsicList;
// Mapping function name to index of IntrinsicList.
- StringMap Intrinsics;
+ StringMap Intrinsics;
// Mapping function name to RVVOverloadIntrinsicDef.
StringMap OverloadIntrinsics;
@@ -379,14 +379,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
OverloadedName += "_" + OverloadedSuffixStr.str();
// clang built-in function name, e.g. __builtin_rvv_vadd.
- std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
+ std::string BuiltinName = std::string(Record.Name);
RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName,
OverloadedName, PolicyAttrs,
Record.HasFRMRoundModeOp);
// Put into IntrinsicList.
- uint32_t Index = IntrinsicList.size();
+ uint16_t Index = IntrinsicList.size();
IntrinsicList.push_back({BuiltinName, Signature});
// Creating mapping to Intrinsics.
@@ -451,7 +451,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
RVVIntrinsicDecl->addAttr(OverloadableAttr::CreateImplicit(Context));
// Setup alias to __builtin_rvv_*
- IdentifierInfo &IntrinsicII = PP.getIdentifierTable().get(IDef.BuiltinName);
+ IdentifierInfo &IntrinsicII =
+ PP.getIdentifierTable().get("__builtin_rvv_" + IDef.BuiltinName);
RVVIntrinsicDecl->addAttr(
BuiltinAliasAttr::CreateImplicit(S.Context, &IntrinsicII));
@@ -462,7 +463,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR,
IdentifierInfo *II,
Preprocessor &PP) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
// Lookup the function name from the overload intrinsics first.
auto OvIItr = OverloadIntrinsics.find(Name);
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 2de977a3dc720bd..7d2a2d7e826f9cd 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -1150,11 +1150,6 @@ void RVVIntrinsic::updateNamesAndPolicy(
OverloadedName += suffix;
};
- // This follows the naming guideline under riscv-c-api-doc to add the
- // `__riscv_` suffix for all RVV intrinsics.
- Name = "__riscv_" + Name;
- OverloadedName =
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-2, -1, 0, 1, 2],
+OverloadedName = "vfwcvtbf16_f" in
+defm : RVVConvBuiltinSet<"vfwcvtbf16_f_f_v", "y", [["Fw", "Fwv"]]>;
4vtomat wrote:
There are two same definitions in this scope, one has `HasFRMRoundModeOp` and
the other doesn't. If we define the name then it causes the redefinition error.
https://github.com/llvm/llvm-project/pull/79618
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[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)
@@ -0,0 +1,479 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ +// RUN: -target-feature +zvfh -target-feature +experimental-zvfbfwma -disable-O0-optnone \ 4vtomat wrote: No, it doesn't, I just copied the test cases from [this](https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/293) lol. I will remove it though. https://github.com/llvm/llvm-project/pull/79615 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)
@@ -1730,12 +1730,26 @@ let ManualCodegen = [{
defm vfwnmacc : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
+
+// Vector BF16 widening multiply-accumulate
+let Log2LMUL = [-2, -1, 0, 1, 2],
4vtomat wrote:
Yes, we do.
https://github.com/llvm/llvm-project/pull/79615
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[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)
https://github.com/4vtomat deleted https://github.com/llvm/llvm-project/pull/79618 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-2, -1, 0, 1, 2],
+OverloadedName = "vfwcvtbf16_f" in
+defm : RVVConvBuiltinSet<"vfwcvtbf16_f_f_v", "y", [["Fw", "Fwv"]]>;
4vtomat wrote:
Yes, we can just define like this~
https://github.com/llvm/llvm-project/pull/79618
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[llvm] [clang] riscv vector cc (PR #77560)
@@ -24,6 +24,19 @@ def CSR_ILP32D_LP64D : CalleeSavedRegs<(add CSR_ILP32_LP64, F8_D, F9_D, (sequence "F%u_D", 18, 27))>; +defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31), + V2M2, V4M2, V6M2, V24M2, V26M2, V28M2, V30M2, 4vtomat wrote: If I don't list all of LMUL variations, it would use LMUL 1 for all saved/restored registers, I'm not sure if we have any mechanism to auto-combine them? https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
