================ @@ -0,0 +1,479 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ +// RUN: -target-feature +zvfh -target-feature +experimental-zvfbfwma -disable-O0-optnone \ ---------------- 4vtomat wrote:
No, it doesn't, I just copied the test cases from [this](https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/293) lol. I will remove it though. https://github.com/llvm/llvm-project/pull/79615 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
