RE: [PATCH 6.10 090/263] drm/amdgpu/pm: Fix the param type of set_power_profile_mode
[Public]
> -Original Message-
> From: Jiri Slaby
> Sent: Monday, August 19, 2024 3:54 AM
> To: Greg Kroah-Hartman ;
> sta...@vger.kernel.org
> Cc: patc...@lists.linux.dev; Deucher, Alexander
> ; Sasha Levin ; Koenig,
> Christian ; Pan, Xinhui ;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 6.10 090/263] drm/amdgpu/pm: Fix the param type of
> set_power_profile_mode
>
> FTR:
> Delivery has failed to these recipients or groups:
> Ma Jun (jun@amd.com)
> The email address you entered couldn't be found
>
> So the author of the patch CANNOT respond. Anyone else?
This was a Coverity fix. As to why it was pulled into stable, I think Sasha's
scripts picked it up.
Alex
>
> On 19. 08. 24, 9:49, Jiri Slaby wrote:
> > On 12. 08. 24, 18:01, Greg Kroah-Hartman wrote:
> >> 6.10-stable review patch. If anyone has any objections, please let
> >> me know.
> >>
> >> --
> >>
> >> From: Ma Jun
> >>
> >> [ Upstream commit f683f24093dd94a831085fe0ea8e9dc4c6c1a2d1 ]
> >>
> >> Function .set_power_profile_mode need an array as input parameter.
> >
> > Which one and why?
> >
> > static int smu_bump_power_profile_mode(struct smu_context *smu,
> > long *param,
> > uint32_t param_size)
> >
> >int (*set_power_profile_mode)(struct smu_context *smu, long *input,
> > uint32_t size);
> >
> > static int pp_set_power_profile_mode(void *handle, long *input,
> > uint32_t
> > size)
> >
> >int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input,
> > uint32_t size);
> >
> > static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long
> > *input, uint32_t size) {
> > int workload_type = 0;
> > int result = 0;
> >
> > if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
> >
> >
> > There is absolutely no problem doing input[0] when a pointer to a
> > local non-array variable is passed, is it?
> >
> >> So define variable workload as an array to fix the below coverity
> >> warning.
> >
> > This very much looks like one of many Coverity false positives.
> >
> >> "Passing &workload to function
> >> hwmgr->hwmgr_func->set_power_profile_mode
> >> which uses it as an array. This might corrupt or misinterpret
> >> adjacent memory locations"
> >
> > Care to explain how this fixes anything but a Coverity false positive?
> > Why was this included in a stable tree at all?
> >
> >> Signed-off-by: Ma Jun
> >> Acked-by: Alex Deucher
> >> Signed-off-by: Alex Deucher
> >> Signed-off-by: Sasha Levin
> > ...
> >> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> >> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> >> @@ -929,7 +929,7 @@ static int pp_dpm_switch_power_profile(void
> >> *handle,
> >> enum PP_SMC_POWER_PROFILE type, bool en)
> >> {
> >> struct pp_hwmgr *hwmgr = handle;
> >> -long workload;
> >> +long workload[1];
> >
> > This only obfuscates the code. So please revert this if you cannot
> > explain what real issue this actually fixes.
> >
> >> uint32_t index;
> >> if (!hwmgr || !hwmgr->pm_en)
> >> @@ -947,12 +947,12 @@ static int pp_dpm_switch_power_profile(void
> >> *handle,
> >> hwmgr->workload_mask &= ~(1 <<
> >> hwmgr->workload_prority[type]);
> >> index = fls(hwmgr->workload_mask);
> >> index = index > 0 && index <= Workload_Policy_Max ? index -
> >> 1 : 0;
> >> -workload = hwmgr->workload_setting[index];
> >> +workload[0] = hwmgr->workload_setting[index];
> >> } else {
> >> hwmgr->workload_mask |= (1 <<
> >> hwmgr->workload_prority[type]);
> >> index = fls(hwmgr->workload_mask);
> >> index = index <= Workload_Policy_Max ? index - 1 : 0;
> >> -workload = hwmgr->workload_setting[index];
> >> +workload[0] = hwmgr->workload_setting[index];
> >> }
> >> if (type == PP_SMC_POWER_PROFILE_COMPUTE && @@ -962,7
> +962,7 @@
> >> static int pp_dpm_switch_power_profile(void *handle,
> >> }
> >> if (hwmgr->
RE: [PATCH 6.10 090/263] drm/amdgpu/pm: Fix the param type of set_power_profile_mode
[Public] > -Original Message- > From: Jiri Slaby > Sent: Tuesday, August 20, 2024 12:39 AM > To: Deucher, Alexander ; Greg Kroah-Hartman > ; sta...@vger.kernel.org > Cc: patc...@lists.linux.dev; Sasha Levin ; Koenig, > Christian ; Pan, Xinhui ; > amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 6.10 090/263] drm/amdgpu/pm: Fix the param type of > set_power_profile_mode > > On 19. 08. 24, 22:12, Deucher, Alexander wrote: > > [Public] > > > >> -Original Message- > >> From: Jiri Slaby > >> Sent: Monday, August 19, 2024 3:54 AM > >> To: Greg Kroah-Hartman ; > >> sta...@vger.kernel.org > >> Cc: patc...@lists.linux.dev; Deucher, Alexander > >> ; Sasha Levin ; Koenig, > >> Christian ; Pan, Xinhui > >> ; amd-gfx@lists.freedesktop.org > >> Subject: Re: [PATCH 6.10 090/263] drm/amdgpu/pm: Fix the param type > >> of set_power_profile_mode > >> > >> FTR: > >> Delivery has failed to these recipients or groups: > >> Ma Jun (jun@amd.com) > >> The email address you entered couldn't be found > >> > >> So the author of the patch CANNOT respond. Anyone else? > > > > This was a Coverity fix. As to why it was pulled into stable, I think > > Sasha's > scripts picked it up. > > Sorry, but again, why do we change the kernel to _silence_ Coverity? We do > not do this even for compilers. > > I am asking, why do you call this a fix at all? What does it fixes? I don't think this is stable material. As I said, it got picked up by a script that nominates patches for stable. I guess more people need to review the patches that get nominated for stable. I personally can't keep up with all of them. Alex > > And finally, Coverity has a "False positive" selection box to dismiss a > warning > for good. One needs not changing the code. > > thanks, > -- > js > suse labs
Re: [PATCH v4 2/2] drm/amdgpu: Do core dump immediately when job tmo
[AMD Official Use Only - AMD Internal Distribution Only]
Series is:
Reviewed-by: Alex Deucher
From: Huang, Trigger
Sent: Wednesday, August 21, 2024 4:38 AM
To: amd-gfx@lists.freedesktop.org
Cc: Khatri, Sunil ; Deucher, Alexander
; Huang, Trigger
Subject: [PATCH v4 2/2] drm/amdgpu: Do core dump immediately when job tmo
From: Trigger Huang
Do the coredump immediately after a job timeout to get a closer
representation of GPU's error status.
V2: This will skip printing vram_lost as the GPU reset is not
happened yet (Alex)
V3: Unconditionally call the core dump as we care about all the reset
functions(soft-recovery and queue reset and full adapter reset, Alex)
V4: Do the dump after adev->job_hang = true (Sunil)
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 68 -
1 file changed, 67 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index c6a1783fc9ef..3000a49b3e5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -30,6 +30,61 @@
#include "amdgpu.h"
#include "amdgpu_trace.h"
#include "amdgpu_reset.h"
+#include "amdgpu_dev_coredump.h"
+#include "amdgpu_xgmi.h"
+
+static void amdgpu_job_do_core_dump(struct amdgpu_device *adev,
+ struct amdgpu_job *job)
+{
+ int i;
+
+ dev_info(adev->dev, "Dumping IP State\n");
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (adev->ip_blocks[i].version->funcs->dump_ip_state)
+ adev->ip_blocks[i].version->funcs
+ ->dump_ip_state((void *)adev);
+ dev_info(adev->dev, "Dumping IP State Completed\n");
+ }
+
+ amdgpu_coredump(adev, true, false, job);
+}
+
+static void amdgpu_job_core_dump(struct amdgpu_device *adev,
+struct amdgpu_job *job)
+{
+ struct list_head device_list, *device_list_handle = NULL;
+ struct amdgpu_device *tmp_adev = NULL;
+ struct amdgpu_hive_info *hive = NULL;
+
+ if (!amdgpu_sriov_vf(adev))
+ hive = amdgpu_get_xgmi_hive(adev);
+ if (hive)
+ mutex_lock(&hive->hive_lock);
+ /*
+* Reuse the logic in amdgpu_device_gpu_recover() to build list of
+* devices for code dump
+*/
+ INIT_LIST_HEAD(&device_list);
+ if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)
&& hive) {
+ list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head)
+ list_add_tail(&tmp_adev->reset_list, &device_list);
+ if (!list_is_first(&adev->reset_list, &device_list))
+ list_rotate_to_front(&adev->reset_list, &device_list);
+ device_list_handle = &device_list;
+ } else {
+ list_add_tail(&adev->reset_list, &device_list);
+ device_list_handle = &device_list;
+ }
+
+ /* Do the coredump for each device */
+ list_for_each_entry(tmp_adev, device_list_handle, reset_list)
+ amdgpu_job_do_core_dump(tmp_adev, job);
+
+ if (hive) {
+ mutex_unlock(&hive->hive_lock);
+ amdgpu_put_xgmi_hive(hive);
+ }
+}
static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
{
@@ -48,9 +103,14 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct
drm_sched_job *s_job)
return DRM_GPU_SCHED_STAT_ENODEV;
}
-
adev->job_hang = true;
+ /*
+* Do the coredump immediately after a job timeout to get a very
+* close dump/snapshot/representation of GPU's current error status
+*/
+ amdgpu_job_core_dump(adev, job);
+
if (amdgpu_gpu_recovery &&
amdgpu_ring_soft_recovery(ring, job->vmid,
s_job->s_fence->parent)) {
dev_err(adev->dev, "ring %s timeout, but soft recovered\n",
@@ -101,6 +161,12 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct
drm_sched_job *s_job)
reset_context.src = AMDGPU_RESET_SRC_JOB;
clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
+ /*
+* To avoid an unnecessary extra coredump, as we have already
+* got the very close representation of GPU's error status
+*/
+ set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags);
+
r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
if (r)
dev_err(adev->dev, "GPU Recovery Failed: %d\n", r);
--
2.34.1
Re: [PATCH] drm/amd/pm: Add support for new P2S table revision
[AMD Official Use Only - AMD Internal Distribution Only]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Lijo Lazar
Sent: Thursday, August 22, 2024 12:20 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal, Asad ; Kamal, Asad
Subject: [PATCH] drm/amd/pm: Add support for new P2S table revision
Add p2s table support for a new revision of SMUv13.0.6.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 7cea0862dcbb..ece1ffc1e56d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -121,6 +121,7 @@ struct mca_ras_info {
#define P2S_TABLE_ID_A 0x50325341
#define P2S_TABLE_ID_X 0x50325358
+#define P2S_TABLE_ID_3 0x50325303
// clang-format off
static const struct cmn2asic_msg_mapping
smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
@@ -279,14 +280,18 @@ static int smu_v13_0_6_init_microcode(struct smu_context
*smu)
struct amdgpu_device *adev = smu->adev;
uint32_t p2s_table_id = P2S_TABLE_ID_A;
int ret = 0, i, p2stable_count;
+ int var = (adev->pdev->device & 0xF);
char ucode_prefix[15];
/* No need to load P2S tables in IOV mode */
if (amdgpu_sriov_vf(adev))
return 0;
- if (!(adev->flags & AMD_IS_APU))
+ if (!(adev->flags & AMD_IS_APU)) {
p2s_table_id = P2S_TABLE_ID_X;
+ if (var == 0x5)
+ p2s_table_id = P2S_TABLE_ID_3;
+ }
amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
sizeof(ucode_prefix));
--
2.25.1
Re: [PATCH v2] drm/amdgpu/gfx9: Convert `//` to `/* ... */` in cleaner shader code
[AMD Official Use Only - AMD Internal Distribution Only]
I think you can drop this patch. This code is not compiled, it's just for
reference, and changing all of the comments will just make it harder to keep in
sync with the internal version.
Alex
From: SHANMUGAM, SRINIVASAN
Sent: Wednesday, September 4, 2024 5:51 AM
To: Koenig, Christian ; Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org ; SHANMUGAM,
SRINIVASAN
Subject: [PATCH v2] drm/amdgpu/gfx9: Convert `//` to `/* ... */` in cleaner
shader code
This commit updates the comment style in the cleaner shader code from
`//` to `/* ... */` to adhere to the Linux kernel coding style.
The comments describe the operation of the cleaner shader, which is used
to clean LDS, SGPRs, and VGPRs. The shader uses two kernels launched
separately to clean VGPRs, LDS, and lower SGPRs, and to clean remaining
SGPRs.
Fixes: 3b721dfb2c95 ("drm/amdgpu/gfx9: Add cleaner shader for GFX9.4.3")
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
v2:
- Corrected typo for iteraions
- Added fixes tag
.../amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm | 139 +-
1 file changed, 72 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm
index d5325ef80ab0..8951b5a87ae1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm
@@ -21,47 +21,52 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-// This shader is to clean LDS, SGPRs and VGPRs. It is first 64 Dwords or 256
bytes of 192 Dwords cleaner shader.
-//To turn this shader program on for complitaion change this to main and lower
shader main to main_1
-
-// MI300 : Clear SGPRs, VGPRs and LDS
-// Uses two kernels launched separately:
-// 1. Clean VGPRs, LDS, and lower SGPRs
-//Launches one workgroup per CU, each workgroup with 4x wave64 per
SIMD in the CU
-//Waves are "wave64" and have 128 VGPRs each, which uses all 512 VGPRs
per SIMD
-//Waves in the workgroup share the 64KB of LDS
-//Each wave clears SGPRs 0 - 95. Because there are 4 waves/SIMD, this
is physical SGPRs 0-383
-//Each wave clears 128 VGPRs, so all 512 in the SIMD
-//The first wave of the workgroup clears its 64KB of LDS
-//The shader starts with "S_BARRIER" to ensure SPI has launched all
waves of the workgroup
-// before any wave in the workgroup could end. Without this, it is
possible not all SGPRs get cleared.
-//2. Clean remaining SGPRs
-//Launches a workgroup with 24 waves per workgroup, yielding 6 waves
per SIMD in each CU
-//Waves are allocating 96 SGPRs
-// CP sets up SPI_RESOURCE_RESERVE_* registers to prevent these waves
from allocating SGPRs 0-223.
-// As such, these 6 waves per SIMD are allocated physical SGPRs
224-799
-//Barriers do not work for >16 waves per workgroup, so we cannot start
with S_BARRIER
-// Instead, the shader starts with an S_SETHALT 1. Once all waves are
launched CP will send unhalt command
-//The shader then clears all SGPRs allocated to it, cleaning out
physical SGPRs 224-799
+/*
+ * This shader is to clean LDS, SGPRs and VGPRs. It is first 64 Dwords or 256
bytes of 192 Dwords cleaner shader.
+ * To turn this shader program on for complitaion change this to main and
lower shader main to main_1
+ *
+ * MI300 : Clear SGPRs, VGPRs and LDS
+ * Uses two kernels launched separately:
+ * 1. Clean VGPRs, LDS, and lower SGPRs
+ *Launches one workgroup per CU, each workgroup with 4x wave64 per
SIMD in the CU
+ *Waves are "wave64" and have 128 VGPRs each, which uses all 512 VGPRs
per SIMD
+ *Waves in the workgroup share the 64KB of LDS
+ *Each wave clears SGPRs 0 - 95. Because there are 4 waves/SIMD, this
is physical SGPRs 0-383
+ *Each wave clears 128 VGPRs, so all 512 in the SIMD
+ *The first wave of the workgroup clears its 64KB of LDS
+ *The shader starts with "S_BARRIER" to ensure SPI has launched all
waves of the workgroup
+ * before any wave in the workgroup could end. Without this, it is
possible not all SGPRs get cleared.
+ *2. Clean remaining SGPRs
+ *Launches a workgroup with 24 waves per workgroup, yielding 6 waves
per SIMD in each CU
+ *Waves are allocating 96 SGPRs
+ * CP sets up SPI_RESOURCE_RESERVE_* registers to prevent these waves
from allocating SGPRs 0-223.
+ * As such, these 6 waves per SIMD are allocated physical SGPRs
224-799
+ * Barriers do not work for >16 waves per workgroup, so we cannot start
with S_BARRIER
+ * Instead, the shader starts with an S_SETHALT 1. Once all waves are
launched CP will send unhalt command
+ *
Re: [PATCH] drm/amdgpu: update suspend status for aborting from deeper suspend
[AMD Official Use Only - AMD Internal Distribution Only]
Can you elaborate on how this fails? Seems like maybe we should just get rid
of adev->suspend_complete and just check the MP0 SOL register to determine
whether or not we need to reset the GPU on resume.
Alex
From: Liang, Prike
Sent: Thursday, September 5, 2024 3:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH] drm/amdgpu: update suspend status for aborting from deeper
suspend
[AMD Official Use Only - AMD Internal Distribution Only]
According to the ChromeOS team test, this patch can resolve the S3 suspend
abort from deeper sleep, which occurs when suspension aborts after calling the
noirq suspend and before executing the _S3 and turning off the power rail.
Could this patch get a review or acknowledgment?
Thanks,
Prike
> -Original Message-
> From: Liang, Prike
> Sent: Monday, September 2, 2024 4:13 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
>
> Subject: [PATCH] drm/amdgpu: update suspend status for aborting from
> deeper suspend
>
> There're some other suspend abort cases which can call the noirq suspend
> except for executing _S3 method. In those cases need to process as
> incomplete suspendsion.
>
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 8d16dacdc172..cf701bb8fc79 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -587,11 +587,13 @@ static bool soc15_need_reset_on_resume(struct
> amdgpu_device *adev)
>* 2) S3 suspend abort and TOS already launched.
>*/
> if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> - !adev->suspend_complete &&
> - sol_reg)
> + sol_reg) {
> + adev->suspend_complete = false;
> return true;
> -
> - return false;
> + } else {
> + adev->suspend_complete = true;
> + return false;
> + }
> }
>
> static int soc15_asic_reset(struct amdgpu_device *adev)
> --
> 2.34.1
Re: [PATCH] drm/amdgpu: remove golden setting for gfx 11.5.0
[AMD Official Use Only - General]
Acked-by: Alex Deucher
From: Zhang, Yifan
Sent: Monday, January 29, 2024 4:06 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Huang, Tim ; Yu, Lang
; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: remove golden setting for gfx 11.5.0
No need to set golden settings in driver from gfx 11.5.0 onwards
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 32 ++
1 file changed, 2 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index c1e10760..4e99af904e04 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -90,10 +90,6 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
-static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x2000, 0x2000)
-};
-
static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff,
0x0010),
@@ -104,24 +100,8 @@ static const struct soc15_reg_golden
golden_settings_gc_11_0_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffd,
0x0008),
SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff,
0x55480100),
SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7, 0x0103),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcff, 0x000a)
-};
-
-static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = {
- SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0x, 0x0800),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff,
0x0242),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1,
0x0500),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK, 0x,
0xfff3),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0x,
0xfff3),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0x, 0xf37fff3f),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffb, 0x00f40188),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ff, 0x80009007),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ff, 0x00880007),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0x,
0x0001),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7, 0x0103),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f, 0x),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcf, 0x200a),
- SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0x, 0x048f)
+ SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcff, 0x000a),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x2000, 0x2000)
};
#define DEFAULT_SH_MEM_CONFIG \
@@ -304,17 +284,9 @@ static void gfx_v11_0_init_golden_registers(struct
amdgpu_device *adev)
golden_settings_gc_11_0_1,
(const
u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
break;
- case IP_VERSION(11, 5, 0):
- soc15_program_register_sequence(adev,
- golden_settings_gc_11_5_0,
- (const
u32)ARRAY_SIZE(golden_settings_gc_11_5_0));
- break;
default:
break;
}
- soc15_program_register_sequence(adev,
- golden_settings_gc_11_0,
- (const
u32)ARRAY_SIZE(golden_settings_gc_11_0));
}
--
2.37.3
RE: [PATCH] drm/amdgpu: Clear the hotplug interrupt ack bit before hpd initialization
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Qiang
> Ma
> Sent: Tuesday, January 30, 2024 4:35 AM
> To: lexander.deuc...@amd.com; Koenig, Christian
> ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch; sunran...@208suo.com;
> SHANMUGAM, SRINIVASAN
> Cc: Qiang Ma ; dri-de...@lists.freedesktop.org;
> amd-gfx@lists.freedesktop.org; linux-ker...@vger.kernel.org
> Subject: [PATCH] drm/amdgpu: Clear the hotplug interrupt ack bit before hpd
> initialization
>
> Problem:
> The computer in the bios initialization process, unplug the HDMI display, wait
> until the system up, plug in the HDMI display, did not enter the hotplug
> interrupt function, the display is not bright.
>
> Fix:
> After the above problem occurs, and the hpd ack interrupt bit is 1, the
> interrupt should be cleared during hpd_init initialization so that when the
> driver is ready, it can respond to the hpd interrupt normally.
>
> Signed-off-by: Qiang Ma
> ---
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 20 +---
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 20 +---
> 4 files changed, 38 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index bb666cb7522e..11859059fd10 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -51,6 +51,7 @@
>
> static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
> static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
> +static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
>
> static const u32 crtc_offsets[] = {
> CRTC0_REGISTER_OFFSET,
> @@ -363,6 +364,7 @@ static void dce_v10_0_hpd_init(struct
> amdgpu_device *adev)
>
> AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
> WREG32(mmDC_HPD_TOGGLE_FILT_CNTL +
> hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
>
> + dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
Should be dce_v10_0_hpd_int_ack().
> dce_v10_0_hpd_set_polarity(adev, amdgpu_connector-
> >hpd.hpd);
> amdgpu_irq_get(adev, &adev->hpd_irq,
> amdgpu_connector->hpd.hpd);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 7af277f61cca..745e4fdffade 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -51,6 +51,7 @@
>
> static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
> static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
> +static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
>
> static const u32 crtc_offsets[] =
> {
> @@ -387,6 +388,7 @@ static void dce_v11_0_hpd_init(struct
> amdgpu_device *adev)
>
> AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
> WREG32(mmDC_HPD_TOGGLE_FILT_CNTL +
> hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
>
> + dce_v11_0_hpd_int_ack(adev, amdgpu_connector-
> >hpd.hpd);
> dce_v11_0_hpd_set_polarity(adev, amdgpu_connector-
> >hpd.hpd);
> amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector-
> >hpd.hpd);
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 143efc37a17f..f8e15ebf74b4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -272,6 +272,21 @@ static void dce_v6_0_hpd_set_polarity(struct
> amdgpu_device *adev,
> WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); }
>
> +static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev,
> + int hpd)
> +{
> + u32 tmp;
> +
> + if (hpd >= adev->mode_info.num_hpd) {
> + DRM_DEBUG("invalid hdp %d\n", hpd);
> + return;
> + }
> +
> + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
> + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
> + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); }
> +
> /**
> * dce_v6_0_hpd_init - hpd setup callback.
> *
> @@ -311,6 +326,7 @@ static void dce_v6_0_hpd_init(struct amdgpu_device
> *adev)
> continue;
> }
>
> + dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
> dce_v6_0_hpd_set_polarity(adev, amdgpu_connector-
> >hpd.hpd);
> amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector-
> >hpd.hpd);
> }
> @@ -3101,9 +3117,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device
> *adev,
> mask = interrupt_status_offsets[hpd].hpd;
>
> if (disp_int & mask) {
> - tmp = RREG32(mmDC_HPD1_INT_CONTROL +
> hpd_offsets[hpd]);
> - tmp |=
> DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
> - WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd],
> tmp);
> + dce_v6_0
RE: [PATCH] drm/amdgpu: Fix potential out-of-bounds access in 'amdgpu_discovery_reg_base_init()'
[Public]
> -Original Message-
> From: SHANMUGAM, SRINIVASAN
> Sent: Thursday, February 1, 2024 12:36 PM
> To: Deucher, Alexander ; Koenig, Christian
>
> Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN
>
> Subject: [PATCH] drm/amdgpu: Fix potential out-of-bounds access in
> 'amdgpu_discovery_reg_base_init()'
>
> The issue arises when the array 'adev->vcn.vcn_config' is accessed before
> checking if the index 'adev->vcn.num_vcn_inst' is within the bounds of the
> array.
>
> The fix involves moving the bounds check before the array access. This ensures
> that 'adev->vcn.num_vcn_inst' is within the bounds of the array before it is
> used as an index.
>
> Fixes the below:
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1289
> amdgpu_discovery_reg_base_init() error: testing array offset 'adev-
> >vcn.num_vcn_inst' after use.
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index ef800590c1ab..83da46d73f70 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1282,11 +1282,11 @@ static int
> amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
>* 0b10 : encode is disabled
>* 0b01 : decode is disabled
>*/
> - adev->vcn.vcn_config[adev-
> >vcn.num_vcn_inst] =
> - ip->revision & 0xc0;
> - ip->revision &= ~0xc0;
> if (adev->vcn.num_vcn_inst <
> AMDGPU_MAX_VCN_INSTANCES) {
> + adev->vcn.vcn_config[adev-
> >vcn.num_vcn_inst] =
> + ip->revision & 0xc0;
> + ip->revision &= ~0xc0;
I have vague recollections of this being this way for a reason, but I can't
recall why at this time. That said, the ` ip->revision &= ~0xc0;` should
always be executed, not just if the number of instances < MAX_VCN_INSTANCES. So
I would move that line after the if/else block.
Alex
> adev->vcn.num_vcn_inst++;
> adev->vcn.inst_mask |=
> (1U << ip->instance_number);
> --
> 2.34.1
RE: [PATCH 1/2] drm/amdgpu: skip to program GFXDEC registers for suspend abort
[AMD Official Use Only - General]
> -Original Message-
> From: Liang, Prike
> Sent: Thursday, February 1, 2024 3:58 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Sharma, Deepak
> ; Liang, Prike
> Subject: [PATCH 1/2] drm/amdgpu: skip to program GFXDEC registers for
> suspend abort
>
> In the suspend abort cases, the gfx power rail doesn't turn off so some
> GFXDEC registers/CSB can't reset to default value and at this moment
> reinitialize GFXDEC/CSB will result in an unexpected error.
> So let skip those program sequence for the suspend abort case.
>
> Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8
> 3 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index c5f3859fd682..312dfaec7b4a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1079,6 +1079,8 @@ struct amdgpu_device {
> boolin_s3;
> boolin_s4;
> boolin_s0ix;
> + /* indicate amdgpu suspension status */
> + boolsuspend_complete;
>
> enum pp_mp1_state mp1_state;
> struct amdgpu_doorbell_index doorbell_index; diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 475bd59c9ac2..59254144916c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2472,6 +2472,7 @@ static int amdgpu_pmops_suspend(struct device
> *dev)
> struct drm_device *drm_dev = dev_get_drvdata(dev);
> struct amdgpu_device *adev = drm_to_adev(drm_dev);
>
> + adev->suspend_complete = false;
> if (amdgpu_acpi_is_s0ix_active(adev))
> adev->in_s0ix = true;
> else if (amdgpu_acpi_is_s3_active(adev)) @@ -2486,6 +2487,7 @@
> static int amdgpu_pmops_suspend_noirq(struct device *dev)
> struct drm_device *drm_dev = dev_get_drvdata(dev);
> struct amdgpu_device *adev = drm_to_adev(drm_dev);
>
> + adev->suspend_complete = true;
> if (amdgpu_acpi_should_gpu_reset(adev))
> return amdgpu_asic_reset(adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 57808be6e3ec..169d45268ef6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3034,6 +3034,14 @@ static int gfx_v9_0_cp_gfx_start(struct
> amdgpu_device *adev)
>
> gfx_v9_0_cp_gfx_enable(adev, true);
>
> + /* Now only limit the quirk on the APU gfx9 series and already
> + * confirmed that the APU gfx10/gfx11 needn't such update.
> + */
> + if (adev->flags & AMD_IS_APU &&
> + adev->in_s3 && !adev->suspend_complete) {
> + DRM_INFO(" Will skip the CSB packet resubmit\n");
> + return 0;
> + }
> r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
> if (r) {
> DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
> --
> 2.34.1
RE: [PATCH 2/2] drm/amdgpu: reset gpu for s3 suspend abort case
[Public]
> -Original Message-
> From: Liang, Prike
> Sent: Thursday, February 1, 2024 3:58 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Sharma, Deepak
> ; Liang, Prike
> Subject: [PATCH 2/2] drm/amdgpu: reset gpu for s3 suspend abort case
>
> In the s3 suspend abort case some type of gfx9 power rail not turn off from
> FCH side and this will put the GPU in an unknown power status, so let's reset
> the gpu to a known good power state before reinitialize gpu device.
>
> Signed-off-by: Prike Liang
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 15033efec2ba..c64c01e2944a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1298,10 +1298,32 @@ static int soc15_common_suspend(void
> *handle)
> return soc15_common_hw_fini(adev);
> }
>
> +static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) {
> + u32 sol_reg;
> +
> + sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
> +
> + /* Will reset for the following suspend abort cases.
> + * 1) Only reset limit on APU side, dGPU hasn't checked yet.
> + * 2) S3 suspend abort and TOS already launched.
> + */
> + if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> + !adev->suspend_complete &&
> + sol_reg)
> + return true;
> +
> + return false;
> +}
> +
> static int soc15_common_resume(void *handle) {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + if (soc15_need_reset_on_resume(adev)) {
> + dev_info(adev->dev, "S3 suspend abort case, let's reset
> ASIC.\n");
> + soc15_asic_reset(adev);
> + }
> return soc15_common_hw_init(adev);
> }
>
> --
> 2.34.1
Re: [PATCH] drm/amd/display: Clear phantom stream count and plane count
[Public]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Mario
Limonciello
Sent: Friday, February 2, 2024 7:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Limonciello, Mario
Subject: [PATCH] drm/amd/display: Clear phantom stream count and plane count
When dc_state_destruct() was refactored the new phantom_stream_count
and phantom_plane_count members weren't cleared.
Fixes: 012a04b1d6af ("drm/amd/display: Refactor phantom resource allocation")
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 88c6436b28b6..180ac47868c2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -291,11 +291,14 @@ void dc_state_destruct(struct dc_state *state)
dc_stream_release(state->phantom_streams[i]);
state->phantom_streams[i] = NULL;
}
+ state->phantom_stream_count = 0;
for (i = 0; i < state->phantom_plane_count; i++) {
dc_plane_state_release(state->phantom_planes[i]);
state->phantom_planes[i] = NULL;
}
+ state->phantom_plane_count = 0;
+
state->stream_mask = 0;
memset(&state->res_ctx, 0, sizeof(state->res_ctx));
memset(&state->pp_display_cfg, 0, sizeof(state->pp_display_cfg));
--
2.34.1
RE: drm/amdkfd: Relocate TBA/TMA to opposite side of VM hole (v2)
[Public] > -Original Message- > From: amd-gfx On Behalf Of > Shengyu Qu > Sent: Saturday, February 3, 2024 8:05 AM > To: Kuehling, Felix ; amd-gfx@lists.freedesktop.org > Cc: wiagn...@outlook.com; Cornwall, Jay ; > Koenig, Christian ; Paneer Selvam, Arunpravin > > Subject: Re: drm/amdkfd: Relocate TBA/TMA to opposite side of VM hole (v2) > > Hi Felix, > Sorry for my late reply. I was busy this week. > I just did some more tests using next-20240202 branch. Testing using blender > 4.0.2, when only one HIP render task is running, there's no problem. > However, when two tasks run together, software always crashes, but not > crashes the whole system. Dmesg reports gpu reset in most cases, for > example: > > [ 176.071823] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring > gfx_0.0.0 timeout, signaled seq=32608, emitted seq=32610 [ 176.072000] > [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process > information: process blender pid 4256 thread blender:cs0 pid 4297 > [ 176.072143] amdgpu :03:00.0: amdgpu: GPU reset begin! > [ 176.073571] amdgpu :03:00.0: amdgpu: Guilty job already signaled, > skipping HW reset [ 176.073593] amdgpu :03:00.0: amdgpu: GPU > reset(4) succeeded! > > And in some rare cases, there would be a page fault report, see dmesg.log. > Do you have any idea? Can I make it print more detailed diagnostic > information? Are you only seeing the problem with this patch applied or in general? If you are seeing it in general, it likely related to a firmware issue that was recently fixed that will be resolved with an update CP firmware image. Driver side changes: https://gitlab.freedesktop.org/agd5f/linux/-/commit/0eb6c664b780dd1b4080e047ad51b100cd7840a3 https://gitlab.freedesktop.org/agd5f/linux/-/commit/40970e60070ed3d1390ec65e38e819f6d81b8f0c Alex > > Best regards, > Shengyu > > > 在 2024/1/30 01:47, Felix Kuehling 写道: > > On 2024-01-29 10:24, Shengyu Qu wrote: > >> Hello Felix, > >> I think you are right. This problem has existed for years(just look > >> at the issue creation time in my link), and is thought caused by > >> OpenGL-ROCM interop(that's why I think this patch might help). It is > >> very easy to trigger this problem in blender(method is also mentioned > >> in the link). > > > > This doesn't help you, but it's unlikely that this has been the same > > issue for two years for everybody who chimed into this bug report. > > Different kernel versions, GPUs, user mode ROCm and Mesa versions etc. > > > > Case in point, it's possible that you're seeing an issue specific to > > RDNA3, which hasn't even been around for that long. > > > > > >> Do > >> you have any idea about this? > > > > Not without seeing a lot more diagnostic information. A full backtrace > > from your kernel log would be a good start. > > > > Regards, > > Felix > > > > > >> Best regards, > >> Shengyu > >> 在 2024/1/29 22:51, Felix Kuehling 写道: > >>> On 2024-01-29 8:58, Shengyu Qu wrote: > Hi, > Seems rocm-opengl interop hang problem still exists[1]. Btw have > you discovered into this problem? > Best regards, > Shengyu > [1] > https://projects.blender.org/blender/blender/issues/100353#issuecom > ment-599 > >>> > >>> Maybe you're having a different problem. Do you see this issue also > >>> without any version of the "Relocate TBA/TMA ..." patch? > >>> > >>> Regards, > >>> Felix > >>> > >>> > > 在 2024/1/27 03:15, Shengyu Qu 写道: > > Hello Felix, > > This patch seems working on my system, also it seems fixes the > > ROCM/OpenGL interop problem. > > Is this intended to happen or not? Maybe we need more users to > > test it. > > Besides, > > Tested-by: Shengyu Qu Best Regards, > Shengyu > > > > 在 2024/1/26 06:27, Felix Kuehling 写道: > >> The TBA and TMA, along with an unused IB allocation, reside at > >> low addresses in the VM address space. A stray VM fault which > >> hits these pages must be serviced by making their page table entries > invalid. > >> The scheduler depends upon these pages being resident and fails, > >> preventing a debugger from inspecting the failure state. > >> > >> By relocating these pages above 47 bits in the VM address space > >> they can only be reached when bits [63:48] are set to 1. This > >> makes it much less likely for a misbehaving program to generate > >> accesses to them. > >> The current placement at VA (PAGE_SIZE*2) is readily hit by a > >> NULL access with a small offset. > >> > >> v2: > >> - Move it to the reserved space to avoid concflicts with Mesa > >> - Add macros to make reserved space management easier > >> > >> Cc: Arunpravin Paneer Selvam > >> Cc: Christian Koenig > >> Signed-off-by: Jay Cornwall > >> Signed-off-by: Felix Kuehling > >> --- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 4 +-- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c| 7 ++--- > >>
Re: [PATCH v2] amdkfd: pass debug exceptions to second-level trap handler
[AMD Official Use Only - General]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Laurent
Morichetti
Sent: Thursday, February 1, 2024 4:33 PM
To: amd-gfx@lists.freedesktop.org
Cc: jay.cornwall@amd.com ; Morichetti, Laurent
; Six, Lancelot ; Cornwall,
Jay
Subject: [PATCH v2] amdkfd: pass debug exceptions to second-level trap handler
Call the 2nd level trap handler if the cwsr handler is entered with any
one of wave_start, wave_end, or trap_after_inst exceptions.
Signed-off-by: Laurent Morichetti
Tested-by: Lancelot Six
Reviewed-by: Jay Cornwall
---
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2 +-
.../drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 17 -
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index d1caaf0e6a7c..2e9b64edb8d2 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -2518,7 +2518,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
0x8b6eff7b, 0x0400,
0xbfa20045, 0xbf830010,
0xb8fbf803, 0xbfa0fffa,
- 0x8b6eff7b, 0x0900,
+ 0x8b6eff7b, 0x00160900,
0xbfa20015, 0x8b6eff7b,
0x71ff, 0xbfa10008,
0x8b6fff7b, 0x7080,
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
index 71b3dc0c7363..7568ff3af978 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
@@ -81,6 +81,11 @@ var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11
var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21
var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800
var SQ_WAVE_TRAPSTS_EXCP_HI_MASK= 0x7000
+#if ASIC_FAMILY >= CHIP_PLUM_BONITO
+var SQ_WAVE_TRAPSTS_WAVE_START_MASK= 0x2
+var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x4
+var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x10
+#endif
var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12
var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19
@@ -92,6 +97,16 @@ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK= 0x003F8000
var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800
+#if ASIC_FAMILY < CHIP_PLUM_BONITO
+var S_TRAPSTS_NON_MASKABLE_EXCP_MASK =
SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK
+#else
+var S_TRAPSTS_NON_MASKABLE_EXCP_MASK = SQ_WAVE_TRAPSTS_MEM_VIOL_MASK
|\
+
SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK |\
+
SQ_WAVE_TRAPSTS_WAVE_START_MASK|\
+ SQ_WAVE_TRAPSTS_WAVE_END_MASK
|\
+
SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK
+#endif
+
// bits [31:24] unused by SPI debug data
var TTMP11_SAVE_REPLAY_W64H_SHIFT = 31
var TTMP11_SAVE_REPLAY_W64H_MASK= 0x8000
@@ -224,7 +239,7 @@ L_NOT_HALTED:
// Check non-maskable exceptions. memory_violation, illegal_instruction
// and xnack_error exceptions always cause the wave to enter the trap
// handler.
- s_and_b32 ttmp2, s_save_trapsts,
SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK
+ s_and_b32 ttmp2, s_save_trapsts, S_TRAPSTS_NON_MASKABLE_EXCP_MASK
s_cbranch_scc1 L_FETCH_2ND_TRAP
// Check for maskable exceptions in trapsts.excp and trapsts.excp_hi.
base-commit: c4b562a17829454713e45219fa754be1bfda9004
--
2.25.1
Re: drm/amdkfd: Relocate TBA/TMA to opposite side of VM hole (v2)
[AMD Official Use Only - General] The firmware has not been released yet, It's still undergoing regression testing. Alex From: Shengyu Qu Sent: Tuesday, February 6, 2024 5:08 AM To: Deucher, Alexander; Kuehling, Felix; amd-gfx@lists.freedesktop.org Cc: wiagn...@outlook.com; Cornwall, Jay; Koenig, Christian; Paneer Selvam, Arunpravin Subject: Re: drm/amdkfd: Relocate TBA/TMA to opposite side of VM hole (v2) Hi Alexander, 在 2024/2/6 1:12, Deucher, Alexander 写道: Are you only seeing the problem with this patch applied or in general? If you are seeing it in general, it likely related to a firmware issue that was recently fixed that will be resolved with an update CP firmware image. Driver side changes: https://gitlab.freedesktop.org/agd5f/linux/-/commit/0eb6c664b780dd1b4080e047ad51b100cd7840a3 https://gitlab.freedesktop.org/agd5f/linux/-/commit/40970e60070ed3d1390ec65e38e819f6d81b8f0c Alex This problem is not affected by this patch, so possible the firmware issue. Where can I get the newest firmware image? Or is it already pushed to linux-firmware repo? Best regards, Shengyu
RE: [PATCH] drm/amdkfd: Initialize kfd_gpu_cache_info for KFD topology
[AMD Official Use Only - General]
> -Original Message-
> From: Kuehling, Felix
> Sent: Tuesday, February 6, 2024 4:15 PM
> To: Greathouse, Joseph ; amd-
> g...@lists.freedesktop.org; Deucher, Alexander
>
> Subject: Re: [PATCH] drm/amdkfd: Initialize kfd_gpu_cache_info for KFD
> topology
>
>
> On 2024-02-06 15:55, Joseph Greathouse wrote:
> > The current kfd_gpu_cache_info structure is only partially filled in
> > for some architectures. This means that for devices where we do not
> > fill in some fields, we can returned uninitialized values through the
> > KFD topology.
> > Zero out the kfd_gpu_cache_info before asking the remaining fields to
> > be filled in by lower-level functions.
> >
> > Signed-off-by: Joseph Greathouse
>
> This fixes your previous patch "drm/amdkfd: Add cache line sizes to KFD
> topology". Alex, I think the previous patch hasn't gone upstream yet. Do you
> want a Fixes: tag or is is possible to squash this with Joe's previous patch
> before upstreaming?
Either way. I can fix up the tag when we upstream or squash it.
Alex
>
> One nit-pick below.
>
>
> > ---
> > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > index 3df2a8ad86fb..67c1e7f84750 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > @@ -1707,6 +1707,7 @@ static void kfd_fill_cache_non_crat_info(struct
> > kfd_topology_device *dev, struct
> >
> > gpu_processor_id = dev->node_props.simd_id_base;
> >
> > + memset(cache_info, 0, sizeof(struct kfd_gpu_cache_info) *
> > +KFD_MAX_CACHE_TYPES);
>
> Just use sizeof(cache_info). No need to calculate the size of the array and
> risk
> getting it wrong.
>
> Regards,
>Felix
>
>
> > pcache_info = cache_info;
> > num_of_cache_types = kfd_get_gpu_cache_info(kdev, &pcache_info);
> > if (!num_of_cache_types) {
RE: [PATCH] drm/amd: Set s0i3/s3 in prepare() callback instead of suspend() callback
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of Mario
> Limonciello
> Sent: Tuesday, February 6, 2024 4:32 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario ; Jürg Billeter
>
> Subject: [PATCH] drm/amd: Set s0i3/s3 in prepare() callback instead of
> suspend() callback
>
> commit 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
> callback") intentionally moved the eviction of resources to earlier in the
> suspend process, but this introduced a subtle change that it occurs before
> adev->in_s0ix or adev->in_s3 are set. This meant that APUs actually started to
> evict resources at suspend time as well.
>
> Move the s0i3/s3 setting flags into prepare() to ensure that they're set
> during
> eviction. Drop the existing call to return 1 in this case because the
> suspend()
> callback looks for the flags too.
>
> Reported-by: Jürg Billeter
> Closes: https://gitlab.freedesktop.org/drm/amd/-
> /issues/3132#note_2271038
> Fixes: 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
> callback")
> Signed-off-by: Mario Limonciello
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 --
> 1 file changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index b74f68a15802..190b2ee9e36b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2464,12 +2464,10 @@ static int amdgpu_pmops_prepare(struct device
> *dev)
> pm_runtime_suspended(dev))
> return 1;
>
> - /* if we will not support s3 or s2i for the device
> - * then skip suspend
> - */
> - if (!amdgpu_acpi_is_s0ix_active(adev) &&
> - !amdgpu_acpi_is_s3_active(adev))
> - return 1;
> + if (amdgpu_acpi_is_s0ix_active(adev))
> + adev->in_s0ix = true;
> + else if (amdgpu_acpi_is_s3_active(adev))
> + adev->in_s3 = true;
>
Will resume always get called to clear these after after prepare? Will these
ever get set and then not unset?
Alex
> return amdgpu_device_prepare(drm_dev); } @@ -2484,10 +2482,6
> @@ static int amdgpu_pmops_suspend(struct device *dev)
> struct drm_device *drm_dev = dev_get_drvdata(dev);
> struct amdgpu_device *adev = drm_to_adev(drm_dev);
>
> - if (amdgpu_acpi_is_s0ix_active(adev))
> - adev->in_s0ix = true;
> - else if (amdgpu_acpi_is_s3_active(adev))
> - adev->in_s3 = true;
> if (!adev->in_s0ix && !adev->in_s3)
> return 0;
> return amdgpu_device_suspend(drm_dev, true);
> --
> 2.34.1
RE: [PATCH] drm/amdgpu/soc21: update VCN 4 max HEVC encoding resolution
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of Thong
> Sent: Tuesday, February 6, 2024 6:28 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Thai, Thong
> Subject: [PATCH] drm/amdgpu/soc21: update VCN 4 max HEVC encoding
> resolution
>
> Update the maximum resolution reported for HEVC encoding on VCN 4 devices
> to reflect its 8K encoding capability.
>
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3159
With that added,
Acked-by: Alex Deucher
> Signed-off-by: Thong
> ---
> drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
> b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index 48c6efcdeac9..4d7188912edf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -50,13 +50,13 @@ static const struct amd_ip_funcs
> soc21_common_ip_funcs;
> /* SOC21 */
> static const struct amdgpu_video_codec_info
> vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
>
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4
> _AVC, 4096, 2304, 0)},
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
> 4096, 2304, 0)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
> 8192, 4352,
> +0)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
> 8192, 4352, 0)}, };
>
> static const struct amdgpu_video_codec_info
> vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
>
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4
> _AVC, 4096, 2304, 0)},
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
> 4096, 2304, 0)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
> 8192, 4352,
> +0)},
> };
>
> static const struct amdgpu_video_codecs
> vcn_4_0_0_video_codecs_encode_vcn0 = {
> --
> 2.34.1
RE: [PATCH] drm/amdgpu: bail on INFO IOCTL if the GPU is in reset
[AMD Official Use Only - General] Ping? > -Original Message- > From: Deucher, Alexander > Sent: Monday, January 29, 2024 10:56 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH] drm/amdgpu: bail on INFO IOCTL if the GPU is in reset > > This avoids queries to read registers or query the SMU for telemetry data > while > the GPU is in reset. This mirrors what we already do for sysfs. > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > index a2df3025a754..d522e99c6f81 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > @@ -607,6 +607,9 @@ int amdgpu_info_ioctl(struct drm_device *dev, void > *data, struct drm_file *filp) > int i, found, ret; > int ui32_size = sizeof(ui32); > > + if (amdgpu_in_reset(adev)) > + return -EPERM; > + > if (!info->return_size || !info->return_pointer) > return -EINVAL; > > -- > 2.42.0
RE: [PATCH 1/3] drm/radeon: Use RMW accessors for changing LNKCTL2
[Public] > -Original Message- > From: Ilpo Järvinen > Sent: Thursday, February 15, 2024 8:32 AM > To: Deucher, Alexander ; amd- > g...@lists.freedesktop.org; Daniel Vetter ; David Airlie > ; Dennis Dalessandro > ; dri- > de...@lists.freedesktop.org; Jason Gunthorpe ; Leon > Romanovsky ; linux-ker...@vger.kernel.org; linux- > r...@vger.kernel.org; Pan, Xinhui ; Koenig, Christian > > Cc: Ilpo Järvinen ; Lukas Wunner > > Subject: [PATCH 1/3] drm/radeon: Use RMW accessors for changing LNKCTL2 > > Convert open coded RMW accesses for LNKCTL2 to use > pcie_capability_clear_and_set_word() which makes its easier to understand > what the code tries to do. > > LNKCTL2 is not really owned by any driver because it is a collection of > control > bits that PCI core might need to touch. RMW accessors already have support > for proper locking for a selected set of registers > (LNKCTL2 is not yet among them but likely will be in the future) to avoid > losing > concurrent updates. > > Suggested-by: Lukas Wunner > Signed-off-by: Ilpo Järvinen The radeon and amdgpu patches are: Acked-by: Alex Deucher Are you looking for me to pick them up or do you want to land them as part of some larger change? Either way is fine with me. Alex > --- > drivers/gpu/drm/radeon/cik.c | 40 ++-- > drivers/gpu/drm/radeon/si.c | 40 ++-- > 2 files changed, 30 insertions(+), 50 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index 10be30366c2b..b5e96a8fc2c1 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -9592,28 +9592,18 @@ static void cik_pcie_gen3_enable(struct > radeon_device *rdev) > > PCI_EXP_LNKCTL_HAWD); > > /* linkctl2 */ > - pcie_capability_read_word(root, > PCI_EXP_LNKCTL2, > - &tmp16); > - tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP > | > -PCI_EXP_LNKCTL2_TX_MARGIN); > - tmp16 |= (bridge_cfg2 & > - (PCI_EXP_LNKCTL2_ENTER_COMP | > -PCI_EXP_LNKCTL2_TX_MARGIN)); > - pcie_capability_write_word(root, > -PCI_EXP_LNKCTL2, > -tmp16); > - > - pcie_capability_read_word(rdev->pdev, > - PCI_EXP_LNKCTL2, > - &tmp16); > - tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP > | > -PCI_EXP_LNKCTL2_TX_MARGIN); > - tmp16 |= (gpu_cfg2 & > - (PCI_EXP_LNKCTL2_ENTER_COMP | > -PCI_EXP_LNKCTL2_TX_MARGIN)); > - pcie_capability_write_word(rdev->pdev, > -PCI_EXP_LNKCTL2, > -tmp16); > + pcie_capability_clear_and_set_word(root, > PCI_EXP_LNKCTL2, > + > PCI_EXP_LNKCTL2_ENTER_COMP | > + > PCI_EXP_LNKCTL2_TX_MARGIN, > +bridge_cfg2 > | > + > (PCI_EXP_LNKCTL2_ENTER_COMP | > + > PCI_EXP_LNKCTL2_TX_MARGIN)); > + pcie_capability_clear_and_set_word(rdev- > >pdev, PCI_EXP_LNKCTL2, > + > PCI_EXP_LNKCTL2_ENTER_COMP | > + > PCI_EXP_LNKCTL2_TX_MARGIN, > +gpu_cfg2 | > + > (PCI_EXP_LNKCTL2_ENTER_COMP | > + > PCI_EXP_LNKCTL2_TX_MARGIN)); > > tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); > tmp &= ~LC_SET_QUIESCE; > @@ -9627,15 +9617,15 @@ static void cik_pcie_gen3_enable(struct > radeon_device *rdev) > speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; > WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); > > - pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); > - tmp16 &= ~PCI_EXP_LNKCTL2_TLS; > + tmp16 = 0; > if (speed_cap == PCIE_SPEED_8_0GT) > tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ > else if (speed_cap == PCIE_SPEED_5_0GT) > tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 *
Re: [PATCH] drm/amdgpu: Drop redundant parameter in amdgpu_gfx_kiq_init_ring
[Public]
Reviewed-by: Alex Deucher
From: Ma, Jun
Sent: Monday, February 19, 2024 1:40 AM
To: amd-gfx@lists.freedesktop.org ; Koenig,
Christian ; Deucher, Alexander
Cc: Ma, Jun
Subject: [PATCH] drm/amdgpu: Drop redundant parameter in
amdgpu_gfx_kiq_init_ring
Drop redundant parameters in function amdgpu_gfx_kiq_init_ring
to simplify the code
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 +---
7 files changed, 13 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index e114694d1131..4835d6d899e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -304,11 +304,11 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device
*adev,
return -EINVAL;
}
-int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
-struct amdgpu_ring *ring,
-struct amdgpu_irq_src *irq, int xcc_id)
+int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id)
{
struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
+ struct amdgpu_irq_src *irq = &kiq->irq;
+ struct amdgpu_ring *ring = &kiq->ring;
int r = 0;
spin_lock_init(&kiq->ring_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index f23bafec71c5..8fcf889ddce9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -471,9 +471,7 @@ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
unsigned max_sh);
-int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
-struct amdgpu_ring *ring,
-struct amdgpu_irq_src *irq, int xcc_id);
+int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id);
void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index b02d63328f1c..691fa40e4e01 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4490,7 +4490,7 @@ static int gfx_v10_0_compute_ring_init(struct
amdgpu_device *adev, int ring_id,
static int gfx_v10_0_sw_init(void *handle)
{
int i, j, k, r, ring_id = 0;
- struct amdgpu_kiq *kiq;
+ int xcc_id = 0;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
@@ -4619,8 +4619,7 @@ static int gfx_v10_0_sw_init(void *handle)
return r;
}
- kiq = &adev->gfx.kiq[0];
- r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
+ r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
if (r)
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 2fb1342d5bd9..9d8ec709cd52 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1329,7 +1329,7 @@ static int gfx_v11_0_rlc_backdoor_autoload_enable(struct
amdgpu_device *adev)
static int gfx_v11_0_sw_init(void *handle)
{
int i, j, k, r, ring_id = 0;
- struct amdgpu_kiq *kiq;
+ int xcc_id = 0;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
@@ -1454,8 +1454,7 @@ static int gfx_v11_0_sw_init(void *handle)
return r;
}
- kiq = &adev->gfx.kiq[0];
- r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
+ r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
if (r)
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index ea174b76ee70..b97ea62212b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1900,8 +1900,8 @@ static void gfx_v8_0_sq_irq_work_func(struct work_struct
*work);
static int gfx_v8_0_sw_init(void *handle)
{
int i, j, k, r, ring_id;
+ int xcc_id = 0;
struct amdgpu_ring *ring;
- struct amdgpu_kiq *kiq;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
switch (adev->asic_type) {
@@ -2022,8 +2022
RE: [PATCH] drm/amd: Only allow one entity to control ABM
[Public] > -Original Message- > From: amd-gfx On Behalf Of > Christian König > Sent: Tuesday, February 20, 2024 9:10 AM > To: Alex Deucher > Cc: Limonciello, Mario ; Wentland, Harry > ; amd-gfx@lists.freedesktop.org; dri- > de...@lists.freedesktop.org; Mahfooz, Hamza ; > Li, Sun peng (Leo) > Subject: Re: [PATCH] drm/amd: Only allow one entity to control ABM > > Am 19.02.24 um 16:28 schrieb Alex Deucher: > > On Mon, Feb 19, 2024 at 10:19 AM Christian König > > wrote: > >> Am 16.02.24 um 19:37 schrieb Alex Deucher: > >>> On Fri, Feb 16, 2024 at 10:42 AM Christian König > >>> wrote: > Am 16.02.24 um 16:12 schrieb Mario Limonciello: > > On 2/16/2024 09:05, Harry Wentland wrote: > >> On 2024-02-16 09:47, Christian König wrote: > >>> Am 16.02.24 um 15:42 schrieb Mario Limonciello: > On 2/16/2024 08:38, Christian König wrote: > > Am 16.02.24 um 15:07 schrieb Mario Limonciello: > >> By exporting ABM to sysfs it's possible that DRM master and > >> software controlling the sysfs file fight over the value programmed > for ABM. > >> > >> Adjust the module parameter behavior to control who control > ABM: > >> -2: DRM > >> -1: sysfs (IE via software like power-profiles-daemon) > > Well that sounds extremely awkward. Why should a > > power-profiles-deamon has control over the panel power saving > > features? > > > > I mean we are talking about things like reducing backlight > > level when the is inactivity, don't we? > We're talking about activating the ABM algorithm when the > system is in power saving mode; not from inactivity. This > allows the user to squeeze out some extra power "just" in that > situation. > > But given the comments on the other patch, I tend to agree with > Harry's proposal instead that we just drop the DRM property > entirely as there are no consumers of it. > >>> Yeah, but even then the design to let this be controlled by an > >>> userspace deamon is questionable. Stuff like that is handled > >>> inside the kernel and not exposed to userspace usually. > >>> > > Regarding the "how" and "why" of PPD; besides this panel power > > savings sysfs file there are two other things that are nominally > > changed. > > > > ACPI platform profile: > > https://www.kernel.org/doc/html/latest/userspace-api/sysfs-platfor > > m_profile.html > > > > AMD-Pstate EPP value: > > https://www.kernel.org/doc/html//latest/admin-guide/pm/amd- > pstate. > > html > > > > When a user goes into "power saving" mode both of those are tweaked. > > Before we introduced the EPP tweaking in PPD we did discuss a > > callback within the kernel so that userspace could change "just" > > the ACPI platform profile and everything else would react. There > > was pushback on this, and so instead knobs are offered for things > > that should be tweaked and the userspace daemon can set up policy > > for what to do when a a user uses a userspace client (such as > > GNOME or KDE) to change the desired system profile. > Ok, well who came up with the idea of the userspace deamon? Cause I > think there will be even more push back on this approach. > > Basically when we go from AC to battery (or whatever) the drivers > usually handle that all inside the kernel today. Involving > userspace is only done when there is a need for that, e.g. > inactivity detection or similar. > >>> Well, we don't want policy in the kernel unless it's a platform or > >>> hardware requirement. Kernel should provide the knobs and then > >>> userspace can set them however they want depending on user preference. > >> Well, you not have the policy itself but usually the handling inside > >> the kernel. > >> > >> In other words when I connect/disconnect AC from my laptop I can hear > >> the fan changing, which is a switch in power state. Only the beep > >> which comes out of the speakers as conformation is handled in userspace I > think. > >> > >> And IIRC changing background light is also handled completely inside > >> the kernel and when I close the lid the display turns off on its own > >> and not because of some userspace deamon. > >> > >> So why is for this suddenly a userspace deamon involved? > > It's a user preference. Some people won't like ABM, some will. They > > set the policy from user space. It's similar to the backlight level. > > Some users always prefer a bright backlight regardless of AC/DC state, > > others want the backlight to get brighter when on AC power. The > > kernel provides the knobs to set the ABM level and then user space can > > specify the level and also device when they want it enabled (never, > > only on DC, etc.). The kernel driver for the backlight doesn't change > > the backlight at AC/DC switch, userspa
Re: [PATCH] drm/amdgpu: Fix missing break in ATOM_ARG_IMM Case of atom_get_src_int()
[Public]
Reviewed-by: Alex Deucher
From: SHANMUGAM, SRINIVASAN
Sent: Saturday, February 24, 2024 1:38 AM
To: Koenig, Christian ; Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org ; SHANMUGAM,
SRINIVASAN ; Jammy Zhou
Subject: [PATCH] drm/amdgpu: Fix missing break in ATOM_ARG_IMM Case of
atom_get_src_int()
Missing break statement in the ATOM_ARG_IMM case of a switch statement,
adds the missing break statement, ensuring that the program's control
flow is as intended.
Fixes the below:
drivers/gpu/drm/amd/amdgpu/atom.c:323 atom_get_src_int() warn: ignoring
unreachable code.
Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
Cc: Jammy Zhou
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/atom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
b/drivers/gpu/drm/amd/amdgpu/atom.c
index b888613f653f..72362df352f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -320,7 +320,7 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx,
uint8_t attr,
DEBUG("IMM 0x%02X\n", val);
return val;
}
- return 0;
+ break;
case ATOM_ARG_PLL:
idx = U8(*ptr);
(*ptr)++;
--
2.34.1
Re: Re:RE: Why has to offer "/dev/drv/render128" fd when running ROCm demo?
[Public] No such situation exists. there is always a rendernode. Alex From: 曹子龙 Sent: Wednesday, March 6, 2024 12:25 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Yat Sin, David ; Kuehling, Felix Subject: Re:RE: Why has to offer "/dev/drv/render128" fd when running ROCm demo? Hi felix: Thanks for your kindly help. i still has a question, if on a pure-compute platform, which has no /dev/dri/render node, but only with a single /dev/kfd node, how the compue scenario works since that wei have no "render" fd exists? is such platfom(without render node) exists? thanks for your kindly help.! BRs zlcao. At 2024-03-06 04:43:30, "Kuehling, Felix" wrote: [AMD Official Use Only - General] I already answered this question in a reply to another email that was addressed to me: The render nodes are used for CPU mapping of VRAM with mmap calls and an offset that identifies the BO. The render node also creates the GPU virtual address space that is used by KFD to create the GPU memory mappings. Applications that use both graphics and compute can share the same GPU virtual address space in this way. Zlcao, in the future, this type of question may be better addressed to a mailing list such as amd-gfx@lists.freedesktop.org, instead of writing separately to different maintainers. Regards, Felix From: Deucher, Alexander Sent: Tuesday, March 5, 2024 3:17 PM To: 曹子龙 ; Kuehling, Felix ; Yat Sin, David Subject: Re: Why has to offer "/dev/drv/render128" fd when running ROCm demo? [AMD Official Use Only - General] + Felix, David to comment. From: 曹子龙 mailto:gainery...@163.com>> Sent: Tuesday, March 5, 2024 8:46 AM To: Deucher, Alexander mailto:alexander.deuc...@amd.com>> Subject: Why has to offer "/dev/drv/render128" fd when running ROCm demo? Hi alexander.: sorry for bother. but i really need some help to deal with my puzzle. i am a freshman to AMD GPU Driver, NOW i am trying to write a simple demo to use "/dev/kfd" and do some vram alloc/free tests, but i found you must do the right "AMDKFD_IOC_ACQUIRE_VM" ioctl comamnd before you try GPU to do vram allocation and other things. from the kfd driver code,the pre-condition to do the right "AMDKFD_IOC_ACQUIRE_VM" is to offer a "/dev/drv/render128" fd to the parameters. so, why need to do this? kfd is used for compute, but "/dev/dri/render128" is specify to gfx usaged, why must open the "/dev/dri/render128" during the KFD compute scenario? thanks for your kindly help! BRs zlcao.
RE: [PATCH] drm/amdgpu: add vm fault information to devcoredump
[Public]
> -Original Message-
> From: Sunil Khatri
> Sent: Wednesday, March 6, 2024 1:20 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Sharma, Shashank
>
> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org; Joshi, Mukul ; Paneer
> Selvam, Arunpravin ; Khatri, Sunil
>
> Subject: [PATCH] drm/amdgpu: add vm fault information to devcoredump
>
> Add page fault information to the devcoredump.
>
> Output of devcoredump:
> AMDGPU Device Coredump
> version: 1
> kernel: 6.7.0-amd-staging-drm-next
> module: amdgpu
> time: 29.725011811
> process_name: soft_recovery_p PID: 1720
>
> Ring timed out details
> IP Type: 0 Ring Name: gfx_0.0.0
>
> [gfxhub] Page fault observed for GPU family:143 Faulty page starting at
I think we should add a separate section for the GPU identification information
(family, PCI ids, IP versions, etc.). For this patch, I think fine to just
print the fault address and status.
Alex
> address 0x Protection fault status register:0x301031
>
> VRAM is lost due to GPU reset!
>
> Signed-off-by: Sunil Khatri
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 15 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 +
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> index 147100c27c2d..d7fea6cdf2f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> @@ -203,8 +203,20 @@ amdgpu_devcoredump_read(char *buffer, loff_t
> offset, size_t count,
> coredump->ring->name);
> }
>
> + if (coredump->fault_info.status) {
> + struct amdgpu_vm_fault_info *fault_info = &coredump-
> >fault_info;
> +
> + drm_printf(&p, "\n[%s] Page fault observed for GPU
> family:%d\n",
> +fault_info->vmhub ? "mmhub" : "gfxhub",
> +coredump->adev->family);
> + drm_printf(&p, "Faulty page starting at address 0x%016llx\n",
> +fault_info->addr);
> + drm_printf(&p, "Protection fault status register:0x%x\n",
> +fault_info->status);
> + }
> +
> if (coredump->reset_vram_lost)
> - drm_printf(&p, "VRAM is lost due to GPU reset!\n");
> + drm_printf(&p, "\nVRAM is lost due to GPU reset!\n");
> if (coredump->adev->reset_info.num_regs) {
> drm_printf(&p, "AMDGPU register dumps:\nOffset:
> Value:\n");
>
> @@ -253,6 +265,7 @@ void amdgpu_coredump(struct amdgpu_device
> *adev, bool vram_lost,
> if (job) {
> s_job = &job->base;
> coredump->ring = to_amdgpu_ring(s_job->sched);
> + coredump->fault_info = job->vm->fault_info;
> }
>
> coredump->adev = adev;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> index 60522963aaca..3197955264f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> @@ -98,6 +98,7 @@ struct amdgpu_coredump_info {
> struct timespec64 reset_time;
> boolreset_vram_lost;
> struct amdgpu_ring *ring;
> + struct amdgpu_vm_fault_info fault_info;
> };
> #endif
>
> --
> 2.34.1
RE: [PATCH v2] drm/amdgpu: Clear the hotplug interrupt ack bit before hpd initialization
[Public]
> -Original Message-
> From: Qiang Ma
> Sent: Wednesday, March 13, 2024 2:18 AM
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch; SHANMUGAM, SRINIVASAN
> ; sunran...@208suo.com
> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v2] drm/amdgpu: Clear the hotplug interrupt ack bit
> before hpd initialization
>
> On Wed, 31 Jan 2024 15:57:03 +0800
> Qiang Ma wrote:
>
> Hello everyone, please help review this patch.
This was applied back in January, sorry if I forget to reply.
Alex
>
> Qiang Ma
>
> > Problem:
> > The computer in the bios initialization process, unplug the HDMI
> > display, wait until the system up, plug in the HDMI display, did not
> > enter the hotplug interrupt function, the display is not bright.
> >
> > Fix:
> > After the above problem occurs, and the hpd ack interrupt bit is 1,
> > the interrupt should be cleared during hpd_init initialization so that
> > when the driver is ready, it can respond to the hpd interrupt
> > normally.
> >
> > Signed-off-by: Qiang Ma
> > ---
> > v2:
> > - Remove unused variable 'tmp'
> > - Fixed function spelling errors
> >
> > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 ++
> > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 ++
> > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 22 ++---
> -
> > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 22 ++---
> -
> > 4 files changed, 40 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index
> > bb666cb7522e..12a8ba929a72 100644 ---
> > a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++
> > b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -51,6 +51,7 @@
> >
> > static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
> > static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
> > +static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int
> > hpd);
> > static const u32 crtc_offsets[] = {
> > CRTC0_REGISTER_OFFSET,
> > @@ -363,6 +364,7 @@ static void dce_v10_0_hpd_init(struct
> > amdgpu_device *adev) AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
> > WREG32(mmDC_HPD_TOGGLE_FILT_CNTL +
> > hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
> > + dce_v10_0_hpd_int_ack(adev,
> > amdgpu_connector->hpd.hpd); dce_v10_0_hpd_set_polarity(adev,
> > amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq,
> >amdgpu_connector->hpd.hpd); diff --git
> > a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> > b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index
> > 7af277f61cca..745e4fdffade 100644 ---
> > a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++
> > b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -51,6 +51,7 @@
> >
> > static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
> > static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
> > +static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int
> > hpd);
> > static const u32 crtc_offsets[] =
> > {
> > @@ -387,6 +388,7 @@ static void dce_v11_0_hpd_init(struct
> > amdgpu_device *adev) AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
> > WREG32(mmDC_HPD_TOGGLE_FILT_CNTL +
> > hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
> > + dce_v11_0_hpd_int_ack(adev,
> > amdgpu_connector->hpd.hpd); dce_v11_0_hpd_set_polarity(adev,
> > amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq,
> > amdgpu_connector->hpd.hpd); } diff --git
> > a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index
> > 143efc37a17f..28c4a735716b 100644 ---
> > a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++
> > b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -272,6 +272,21 @@
> static
> > void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
> > WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); }
> >
> > +static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev,
> > +int hpd)
> > +{
> > + u32 tmp;
> > +
> > + if (hpd >= adev->mode_info.num_hpd) {
> > + DRM_DEBUG("invalid hdp %d\n", hpd);
> > + return;
> > + }
> > +
> > + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
> > + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
> > +
Re: [PATCH] drm/amdgpu: correct the KGQ fallback message
[Public]
Reviewed-by: Alex Deucher
From: Liang, Prike
Sent: Wednesday, March 13, 2024 5:29 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Liang, Prike
Subject: [PATCH] drm/amdgpu: correct the KGQ fallback message
Fix the KGQ fallback function name, as this will
help differentiate the failure in the KCQ enablement.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 4835d6d899e7..d9dc5485 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -686,7 +686,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int
xcc_id)
r = amdgpu_ring_test_helper(kiq_ring);
spin_unlock(&kiq->ring_lock);
if (r)
- DRM_ERROR("KCQ enable failed\n");
+ DRM_ERROR("KGQ enable failed\n");
return r;
}
--
2.34.1
RE: [PATCH v2 1/9] drm/amd/pm: Add support for DPM policies
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Thursday, March 14, 2024 7:56 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Liu, Shuzhou (Bill)
>
> Subject: [PATCH v2 1/9] drm/amd/pm: Add support for DPM policies
>
> Add support to set/get information about different DPM policies. The support
> is only available on SOCs which use swsmu architecture.
>
> A DPM policy type may be defined with different levels. For example, a policy
> may be defined to select Pstate preference and then later a pstate preference
> may be chosen.
>
> Signed-off-by: Lijo Lazar
> Reviewed-by: Hawking Zhang
> ---
> v2: Add NULL checks before accessing smu_dpm_policy_ctxt
>
> .../gpu/drm/amd/include/kgd_pp_interface.h| 16
> drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 29 ++
> drivers/gpu/drm/amd/pm/amdgpu_pm.c| 92 ++
> drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 4 +
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 95
> +++
> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 29 ++
> 6 files changed, 265 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index afb930b70615..84dd819ccc06 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -273,6 +273,22 @@ enum pp_xgmi_plpd_mode {
> XGMI_PLPD_COUNT,
> };
>
> +enum pp_pm_policy {
> + PP_PM_POLICY_NONE = -1,
> + PP_PM_POLICY_SOC_PSTATE = 0,
> + PP_PM_POLICY_NUM,
> +};
> +
> +enum pp_policy_soc_pstate {
> + SOC_PSTATE_DEFAULT = 0,
> + SOC_PSTATE_0,
> + SOC_PSTATE_1,
> + SOC_PSTATE_2,
> + SOC_PSTAT_COUNT,
> +};
> +
> +#define PP_POLICY_MAX_LEVELS 5
> +
> #define PP_GROUP_MASK0xF000
> #define PP_GROUP_SHIFT 28
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> index f84bfed50681..db3addd07120 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> @@ -411,6 +411,35 @@ int amdgpu_dpm_set_xgmi_plpd_mode(struct
> amdgpu_device *adev, int mode)
> return ret;
> }
>
> +ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, char
> +*buf) {
> + struct smu_context *smu = adev->powerplay.pp_handle;
> + int ret = -EOPNOTSUPP;
> +
> + if (is_support_sw_smu(adev)) {
> + mutex_lock(&adev->pm.mutex);
> + ret = smu_get_pm_policy_info(smu, buf);
> + mutex_unlock(&adev->pm.mutex);
> + }
> +
> + return ret;
> +}
> +
> +int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int
> policy_type,
> + int policy_level)
> +{
> + struct smu_context *smu = adev->powerplay.pp_handle;
> + int ret = -EOPNOTSUPP;
> +
> + if (is_support_sw_smu(adev)) {
> + mutex_lock(&adev->pm.mutex);
> + ret = smu_set_pm_policy(smu, policy_type, policy_level);
> + mutex_unlock(&adev->pm.mutex);
> + }
> +
> + return ret;
> +}
> +
> int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) {
> void *pp_handle = adev->powerplay.pp_handle; diff --git
> a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index efc631bddf4a..7ee11c2e3c61 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2179,6 +2179,96 @@ static ssize_t
> amdgpu_set_xgmi_plpd_policy(struct device *dev,
> return count;
> }
>
> +static ssize_t amdgpu_get_pm_policy(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = drm_to_adev(ddev);
> +
> + if (amdgpu_in_reset(adev))
> + return -EPERM;
> + if (adev->in_suspend && !adev->in_runpm)
> + return -EPERM;
> +
> + return amdgpu_dpm_get_pm_policy_info(adev, buf); }
> +
> +static ssize_t amdgpu_set_pm_policy(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = drm_to_adev(ddev);
> + int policy_type, ret, num_params = 0;
> + char delimiter[] = " \n\t";
> + char tmp_buf[128];
> + char *tmp, *param;
> + long val;
> +
> +
Re: [PATCH 2/2] drm/amdgpu: enable UMSCH 4.0.6
[AMD Official Use Only - General]
Series is:
Acked-by: Alex Deucher
From: amd-gfx on behalf of Lang Yu
Sent: Thursday, March 21, 2024 10:53 PM
To: amd-gfx@lists.freedesktop.org
Cc: Yu, Lang ; Gopalakrishnan, Veerabadhran (Veera)
Subject: [PATCH 2/2] drm/amdgpu: enable UMSCH 4.0.6
Share same codes with 4.0.5 and enable collaborate mode for VPE.
Signed-off-by: Lang Yu
Reviewed-by: Veerabadhran Gopalakrishnan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 12 ++--
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c| 7 +--
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 3c407164837b..07c5fca06178 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2247,6 +2247,7 @@ static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct
amdgpu_device *adev)
{
switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
case IP_VERSION(4, 0, 5):
+ case IP_VERSION(4, 0, 6):
if (amdgpu_umsch_mm & 0x1) {
amdgpu_device_ip_block_add(adev,
&umsch_mm_v4_0_ip_block);
adev->enable_umsch_mm = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 99210a3b1044..95f80b9131a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -189,10 +189,13 @@ static void setup_vpe_queue(struct amdgpu_device *adev,
mqd->rptr_val = 0;
mqd->unmapped = 1;
+ if (adev->vpe.collaborate_mode)
+ memcpy(++mqd, test->mqd_data_cpu_addr, sizeof(struct MQD_INFO));
+
qinfo->mqd_addr = test->mqd_data_gpu_addr;
qinfo->csa_addr = test->ctx_data_gpu_addr +
offsetof(struct umsch_mm_test_ctx_data, vpe_ctx_csa);
- qinfo->doorbell_offset_0 = (adev->doorbell_index.vpe_ring + 1) << 1;
+ qinfo->doorbell_offset_0 = 0;
qinfo->doorbell_offset_1 = 0;
}
@@ -287,7 +290,10 @@ static int submit_vpe_queue(struct amdgpu_device *adev,
struct umsch_mm_test *te
ring[5] = 0;
mqd->wptr_val = (6 << 2);
- //
WDOORBELL32(adev->umsch_mm.agdb_index[CONTEXT_PRIORITY_LEVEL_NORMAL],
mqd->wptr_val);
+ if (adev->vpe.collaborate_mode)
+ (++mqd)->wptr_val = (6 << 2);
+
+ WDOORBELL32(adev->umsch_mm.agdb_index[CONTEXT_PRIORITY_LEVEL_NORMAL],
mqd->wptr_val);
for (i = 0; i < adev->usec_timeout; i++) {
if (*fence == test_pattern)
@@ -571,6 +577,7 @@ int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm
*umsch)
switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
case IP_VERSION(4, 0, 5):
+ case IP_VERSION(4, 0, 6):
fw_name = "amdgpu/umsch_mm_4_0_0.bin";
break;
default:
@@ -750,6 +757,7 @@ static int umsch_mm_early_init(void *handle)
switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
case IP_VERSION(4, 0, 5):
+ case IP_VERSION(4, 0, 6):
umsch_mm_v4_0_set_funcs(&adev->umsch_mm);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index 8e7b763cfdb7..84368cf1e175 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -60,7 +60,7 @@ static int umsch_mm_v4_0_load_microcode(struct
amdgpu_umsch_mm *umsch)
umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
- if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) {
+ if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) {
WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
1 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
@@ -248,7 +248,7 @@ static int umsch_mm_v4_0_ring_stop(struct amdgpu_umsch_mm
*umsch)
data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
- if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) {
+ if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) {
WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
2 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
@@ -271,6 +271,8 @@ static int umsch_mm_v4_0_set_hw_resources(struct
amdgpu_umsch_mm *umsch)
set_hw_resources.vmid_mask_mm_vcn = umsch->vmid_mask_mm_vcn;
set_hw_resources.vmid_mask_mm_vpe = umsch->vmid_mask_mm_vpe;
+ set_hw_resources.collaboration_mask_vpe =
+ adev->vpe.collaborate_mode ? 0x3 : 0x0
RE: [PATCH 10/28] drm: amdgpu: Use PCI_IRQ_INTX
[Public] > -Original Message- > From: amd-gfx On Behalf Of > Damien Le Moal > Sent: Monday, March 25, 2024 3:09 AM > To: linux-...@vger.kernel.org; Bjorn Helgaas ; > Manivannan Sadhasivami ; linux- > s...@vger.kernel.org; Martin K . Petersen ; > Jaroslav Kysela ; linux-so...@vger.kernel.org; Greg Kroah- > Hartman ; linux-...@vger.kernel.org; linux- > ser...@vger.kernel.org; Hans de Goede ; platform- > driver-...@vger.kernel.org; n...@lists.linux.dev; Lee Jones ; > David Airlie ; amd-gfx@lists.freedesktop.org; Jason > Gunthorpe ; linux-r...@vger.kernel.org; David S . Miller > ; Eric Dumazet ; > net...@vger.kernel.org; linux-ker...@vger.kernel.org > Subject: [PATCH 10/28] drm: amdgpu: Use PCI_IRQ_INTX > > Use the macro PCI_IRQ_INTX instead of the deprecated PCI_IRQ_LEGACY > macro. > > Signed-off-by: Damien Le Moal Feel free to take it through whatever tree makes sense. If you want me to pick it up, let me know. Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c > index 7e6d09730e6d..d18113017ee7 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c > @@ -279,7 +279,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) > adev->irq.msi_enabled = false; > > if (!amdgpu_msi_ok(adev)) > - flags = PCI_IRQ_LEGACY; > + flags = PCI_IRQ_INTX; > else > flags = PCI_IRQ_ALL_TYPES; > > -- > 2.44.0
Re: [PATCH] drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
[AMD Official Use Only - General]
Acked-by: Alex Deucher
From: Huang, Tim
Sent: Thursday, March 28, 2024 12:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim
Subject: [PATCH] drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
From: Tim Huang
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state resulting into hard hangs.
Adding a GFX reset as workaround just before sending the
MP1_UNLOAD message avoids this failure.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index e8119918ef6b..88f1a0d878f3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -226,8 +226,18 @@ static int smu_v13_0_4_system_features_control(struct
smu_context *smu, bool en)
struct amdgpu_device *adev = smu->adev;
int ret = 0;
- if (!en && !adev->in_s0ix)
+ if (!en && !adev->in_s0ix) {
+ /* Adds a GFX reset as workaround just before sending the
+* MP1_UNLOAD message to prevent GC/RLC/PMFW from entering
+* an invalid state.
+*/
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GfxDeviceDriverReset,
+ SMU_RESET_MODE_2, NULL);
+ if (ret)
+ return ret;
+
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload,
NULL);
+ }
return ret;
}
--
2.39.2
RE: [PATCH v2] drm/amdgpu: Reset dGPU if suspend got aborted
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Lijo
> Lazar
> Sent: Thursday, March 28, 2024 12:20 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Wang, Yang(Kevin)
>
> Subject: [PATCH v2] drm/amdgpu: Reset dGPU if suspend got aborted
>
> For SOC21 ASICs, there is an issue in re-enabling PM features if a suspend got
> aborted. In such cases, reset the device during resume phase. This is a
> workaround till a proper solution is finalized.
>
> Signed-off-by: Lijo Lazar
Reviewed-by: Alex Deucher
> ---
> v2: Read TOS status only if required (Kevin).
> Refine log message.
>
> drivers/gpu/drm/amd/amdgpu/soc21.c | 25
> +
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
> b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index 8526282f4da1..abe319b0f063 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -867,10 +867,35 @@ static int soc21_common_suspend(void *handle)
> return soc21_common_hw_fini(adev);
> }
>
> +static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) {
> + u32 sol_reg1, sol_reg2;
> +
> + /* Will reset for the following suspend abort cases.
> + * 1) Only reset dGPU side.
> + * 2) S3 suspend got aborted and TOS is active.
> + */
> + if (!(adev->flags & AMD_IS_APU) && adev->in_s3 &&
> + !adev->suspend_complete) {
> + sol_reg1 = RREG32_SOC15(MP0, 0,
> regMP0_SMN_C2PMSG_81);
> + msleep(100);
> + sol_reg2 = RREG32_SOC15(MP0, 0,
> regMP0_SMN_C2PMSG_81);
> +
> + return (sol_reg1 != sol_reg2);
> + }
> +
> + return false;
> +}
> +
> static int soc21_common_resume(void *handle) {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + if (soc21_need_reset_on_resume(adev)) {
> + dev_info(adev->dev, "S3 suspend aborted, resetting...");
> + soc21_asic_reset(adev);
> + }
> +
> return soc21_common_hw_init(adev);
> }
>
> --
> 2.25.1
Re: [PATCH] drm/amdgpu: Fix VCN allocation in CPX partition
[AMD Official Use Only - General]
Acked-by: Alex Deucher
From: Lazar, Lijo
Sent: Wednesday, March 27, 2024 10:05 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Zhu, James ; Kamal, Asad
Subject: [PATCH] drm/amdgpu: Fix VCN allocation in CPX partition
VCN need not be shared in CPX mode always for all GFX 9.4.3 SOC SKUs. In
certain configs, VCN instance can be exclusively allocated to a
partition even under CPX mode.
Signed-off-by: Lijo Lazar
Reviewed-by: James Zhu
Reviewed-by: Asad Kamal
---
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index d6f808acfb17..fbb43ae7624f 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -62,6 +62,11 @@ void aqua_vanjaram_doorbell_index_init(struct amdgpu_device
*adev)
adev->doorbell_index.max_assignment =
AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1;
}
+static bool aqua_vanjaram_xcp_vcn_shared(struct amdgpu_device *adev)
+{
+ return (adev->xcp_mgr->num_xcps > adev->vcn.num_vcn_inst);
+}
+
static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,
uint32_t inst_idx, struct amdgpu_ring *ring)
{
@@ -87,7 +92,7 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device
*adev,
case AMDGPU_RING_TYPE_VCN_ENC:
case AMDGPU_RING_TYPE_VCN_JPEG:
ip_blk = AMDGPU_XCP_VCN;
- if (adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)
+ if (aqua_vanjaram_xcp_vcn_shared(adev))
inst_mask = 1 << (inst_idx * 2);
break;
default:
@@ -140,10 +145,12 @@ static int aqua_vanjaram_xcp_sched_list_update(
aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id);
- /* VCN is shared by two partitions under CPX MODE */
+ /* VCN may be shared by two partitions under CPX MODE in certain
+* configs.
+*/
if ((ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
- ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&
- adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)
+ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&
+ aqua_vanjaram_xcp_vcn_shared(adev))
aqua_vanjaram_xcp_gpu_sched_update(adev, ring,
ring->xcp_id + 1);
}
--
2.25.1
Re: [PATCH] drm/amd/amdgpu: Update PF2VF Header
[AMD Official Use Only - General]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Luqmaan
Irshad
Sent: Tuesday, April 2, 2024 6:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Irshad, Luqmaan
Subject: [PATCH] drm/amd/amdgpu: Update PF2VF Header
Adding a new field for GPU Capacity to align the header with the host.
Signed-off-by: Luqmaan Irshad
---
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
index 0de78d6a83fe..fb2b394bb9c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
@@ -158,7 +158,7 @@ struct amd_sriov_msg_pf2vf_info_header {
uint32_t reserved[2];
};
-#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (48)
+#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (49)
struct amd_sriov_msg_pf2vf_info {
/* header contains size and version */
struct amd_sriov_msg_pf2vf_info_header header;
@@ -209,6 +209,8 @@ struct amd_sriov_msg_pf2vf_info {
struct amd_sriov_msg_uuid_info uuid_info;
/* PCIE atomic ops support flag */
uint32_t pcie_atomic_ops_support_flags;
+ /* Portion of GPU memory occupied by VF. MAX value is 65535, but set
to uint32_t to maintain alignment with reserved size */
+ uint32_t gpu_capacity;
/* reserved */
uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
};
--
2.44.0
Re: [PATCH] drm/amdgpu: increase mes submission timeout
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: Kim, Jonathan
Sent: Thursday, April 11, 2024 3:03 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Joshi, Mukul
; Kim, Jonathan ; Kim, Jonathan
Subject: [PATCH] drm/amdgpu: increase mes submission timeout
MES internally has a timeout allowance of 2 seconds.
Increase driver timeout to 3 seconds to be safe.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index e5230078a4cd..81833395324a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -111,7 +111,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct
amdgpu_mes *mes,
struct amdgpu_device *adev = mes->adev;
struct amdgpu_ring *ring = &mes->ring;
unsigned long flags;
- signed long timeout = adev->usec_timeout;
+ signed long timeout = 300; /* 3000 ms */
if (amdgpu_emu_mode) {
timeout *= 100;
--
2.34.1
Re: [PATCH] drm/amdgpu: replace tmz flag into buffer flag
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: Min, Frank
Sent: Friday, April 12, 2024 8:06 AM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun ; Zhang, Hawking ;
Deucher, Alexander ; Koenig, Christian
Subject: [PATCH] drm/amdgpu: replace tmz flag into buffer flag
[AMD Official Use Only - General]
From: Frank Min
Replace tmz flag into buffer flag to make it easier to understand and extend
Signed-off-by: Likun Gao
Signed-off-by: Frank Min
---
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 +++-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c| 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c| 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c| 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c| 5 +++--
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 4 ++--
15 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index edc6377ec5ff..199693369c7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -39,7 +39,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device
*adev, unsigned size,
for (i = 0; i < n; i++) {
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence,
- false, false, false);
+ false, false, 0);
if (r)
goto exit_do_move;
r = dma_fence_wait(fence, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 38742ff0ff49..abb1505c82ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -791,7 +791,7 @@ int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
struct dma_fence **fence)
return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
amdgpu_bo_size(shadow), NULL, fence,
- true, false, false);
+ true, false, 0);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index a22c6446817b..b5bde6652838 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -136,7 +136,7 @@ struct amdgpu_buffer_funcs {
uint64_t dst_offset,
/* number of byte to transfer */
uint32_t byte_count,
-bool tmz);
+uint32_t copy_flags);
/* maximum bytes in a single operation */
uint32_tfill_max_bytes;
@@ -154,7 +154,7 @@ struct amdgpu_buffer_funcs {
uint32_t byte_count);
};
-#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t)
(adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
+#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, f)
+(adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (f))
#define amdgpu_emit_fill_buffer(adev, ib, s, d, b)
(adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
struct amdgpu_sdma_instance *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f0fffbf2bdd5..d58ab879e125 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -267,7 +267,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object
*bo,
dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
- dst_addr, num_bytes, false);
+ dst_addr, num_bytes, 0);
amdgpu_ring_pad_ib(ring, &job->ibs[0]);
WARN_ON(job->ibs[0].length_dw > num_dw); @@ -327,6 +327,8 @@ int
amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
struct dma_fence *fence = NULL;
int r = 0;
+ uint32_t copy_flags = 0;
+
if (!adev->mman.buffer_funcs_enabled) {
DRM_ERROR("Trying to move memory with ring
RE: [syzbot] [mm?] general protection fault in dequeue_hugetlb_folio_nodemask
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Limonciello, Mario
> Sent: Thursday, June 6, 2024 10:56 AM
> To: Deucher, Alexander
> Cc: syzbot ;
> Huang, Tim ; Pan, Xinhui ;
> airl...@gmail.com; a...@linux-foundation.org; Deucher, Alexander
> ; amd-gfx@lists.freedesktop.org; Koenig,
> Christian ; dan...@ffwll.ch; dri-
> de...@lists.freedesktop.org; evan.q...@amd.com; Lazar, Lijo
> ; linux-ker...@vger.kernel.org; linux...@kvack.org;
> muchun.s...@linux.dev; syzkaller-b...@googlegroups.com; Zhang, Yifan
>
> Subject: Re: [syzbot] [mm?] general protection fault in
> dequeue_hugetlb_folio_nodemask
>
> On 6/6/2024 09:39, syzbot wrote:
> > Hello,
> >
> > syzbot found the following issue on:
> >
> > HEAD commit:0e1980c40b6e Add linux-next specific files for 20240531
> > git tree: linux-next
> > console+strace:
> > console+https://syzkaller.appspot.com/x/log.txt?x=166086f298
> > kernel config:
> > https://syzkaller.appspot.com/x/.config?x=d9c3ca4e54577b88
> > dashboard link:
> https://syzkaller.appspot.com/bug?extid=c019f68a83ef9b456444
> > compiler: Debian clang version 15.0.6, GNU ld (GNU Binutils for
> > Debian)
> 2.40
> > syz repro:
> https://syzkaller.appspot.com/x/repro.syz?x=12f4094a98
> > C reproducer:
> https://syzkaller.appspot.com/x/repro.c?x=15e1e43298
> >
> > Downloadable assets:
> > disk image:
> > https://storage.googleapis.com/syzbot-assets/44fb1d8b5978/disk-
> 0e1980c
> > 4.raw.xz
> > vmlinux:
> > https://storage.googleapis.com/syzbot-assets/a66ce5caf0b2/vmlinux-0e19
> > 80c4.xz kernel image:
> > https://storage.googleapis.com/syzbot-assets/8992fc8fe046/bzImage-
> 0e19
> > 80c4.xz
> >
> > The issue was bisected to:
> >
> > commit cd94d1b182d2986378550c9087571991bfee01d4
> > Author: Mario Limonciello
> > Date: Thu May 2 18:32:17 2024 +
> >
> > dm/amd/pm: Fix problems with reboot/shutdown for some SMU
> > 13.0.4/13.0.11 users
> >
> > bisection log:
> > https://syzkaller.appspot.com/x/bisect.txt?x=176121c298
> > console output:
> > https://syzkaller.appspot.com/x/log.txt?x=10e121c298
> >
> > IMPORTANT: if you fix the issue, please add the following tag to the commit:
> > Reported-by: syzbot+c019f68a83ef9b456...@syzkaller.appspotmail.com
> > Fixes: cd94d1b182d2 ("dm/amd/pm: Fix problems with reboot/shutdown
> for
> > some SMU 13.0.4/13.0.11 users")
> >
> > Oops: general protection fault, probably for non-canonical address
> > 0xdc000489: [#1] PREEMPT SMP KASAN PTI
> > KASAN: probably user-memory-access in range
> > [0x2448-0x244f]
> > CPU: 1 PID: 5089 Comm: syz-executor257 Not tainted
> > 6.10.0-rc1-next-20240531-syzkaller #0 Hardware name: Google Google
> > Compute Engine/Google Compute Engine, BIOS Google 04/02/2024
> > RIP: 0010:zonelist_zone_idx include/linux/mmzone.h:1613 [inline]
> > RIP: 0010:next_zones_zonelist include/linux/mmzone.h:1644 [inline]
> > RIP: 0010:first_zones_zonelist include/linux/mmzone.h:1670 [inline]
> > RIP: 0010:dequeue_hugetlb_folio_nodemask+0x193/0xe40
> mm/hugetlb.c:1362
> > Code: 13 9b a0 ff c7 44 24 14 00 00 00 00 83 7c 24 40 00 0f 85 97 0c
> > 00 00 48 83 7c 24 20 00 0f 85 45 09 00 00 48 89 d8 48 c1 e8 03 <42> 0f
> > b6 04 28 84 c0 0f 85 58 09 00 00 44 8b 33 44 89 f7 8b 5c 24
> > RSP: 0018:c900035ef720 EFLAGS: 00010002
> > RAX: 0489 RBX: 2448 RCX:
> 888026ef
> > RDX: RSI: RDI:
>
> > RBP: c900035ef858 R08: 81f5e070 R09: f520006bdee8
> > R10: dc00 R11: f520006bdee8 R12:
> > R13: dc00 R14: R15:
>
> > FS: 64010380() GS:8880b950()
> > knlGS:
> > CS: 0010 DS: ES: CR0: 80050033
> > CR2: 005fdeb8 CR3: 7bd96000 CR4:
> 003506f0
> > DR0: DR1: DR2:
>
> > DR3: DR6: fffe0ff0 DR7:
> 0400 Call
> > Trace:
> >
> > alloc_hugetlb_folio_nodemask+0xae/0x3f0 mm/hugetlb.c:2603
> > memfd_alloc_folio+0x15e/0x390 mm/memfd.c:75
> > memfd_pin_folios+0x1066/0x1720 mm/gup.c:3864
> > udmabuf_create+0x658/0x11c0 drivers/dma-buf/udmabuf.c:353
> > udmabuf_ioctl_create drivers/dma-buf/udmabuf.c:420 [inline]
> > udmabuf_ioctl+0x304/
RE: [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off.
[Public] > -Original Message- > From: Thomas Glanzmann > Sent: Friday, June 7, 2024 12:53 AM > To: Deucher, Alexander ; Koenig, Christian > ; p...@glanzmann.de; Pan, Xinhui > > Cc: amd-gfx@lists.freedesktop.org > Subject: [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory > with ring turned off. > > Hello, > starting with 6.10.0-rc1 I get the following in dmesg: Should be fixed with this patch: https://patchwork.freedesktop.org/patch/597421/ Alex > > [ 11.025935] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear > memory with ring turned off. > [ 11.026037] [ cut here ] > [ 11.026038] WARNING: CPU: 10 PID: 659 at > drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:1382 > amdgpu_bo_release_notify+0x1f5/0x210 [amdgpu] > [ 11.026114] Modules linked in: rtl2832_sdr videobuf2_vmalloc > videobuf2_memops videobuf2_v4l2 videodev videobuf2_common r820t > intel_rapl_msr amd_atl intel_rapl_common rtl2832 amdgpu(+) i2c_mux > edac_mce_amd kvm_amd kvm ghash_clmulni_intel snd_hda_codec_realtek > sha512_ssse3 snd_hda_codec_generic sha256_ssse3 > snd_hda_scodec_component sha1_ssse3 snd_hda_codec_hdmi > dvb_usb_rtl28xxu snd_hda_intel dvb_usb_v2 snd_intel_dspcfg > snd_intel_sdw_acpi dvb_core snd_hda_codec drm_exec mc amdxcp > eeepc_wmi drm_buddy asus_wmi rc_core snd_hda_core aesni_intel > gpu_sched battery drm_suballoc_helper sparse_keymap snd_hwdep > platform_profile crypto_simd drm_display_helper cryptd snd_pcm rfkill > wmi_bmof drm_ttm_helper snd_timer joydev rapl ttm sp5100_tco snd pcspkr > watchdog drm_kms_helper k10temp ccp soundcore i2c_algo_bit rng_core > button evdev nfsd auth_rpcgss nfs_acl lockd parport_pc grace ppdev lp > parport drm fuse loop efi_pstore dm_mod configfs sunrpc ip_tables x_tables > autofs4 ext4 crc16 mbcache jbd2 btrfs blake2b_generic efivarfs raid10 > [ 11.026138] raid456 async_raid6_recov async_memcpy async_pq > async_xor async_tx raid1 raid0 md_mod hid_lenovo hid_generic usbhid hid > ahci nvme libahci xhci_pci mpt3sas nvme_core libata xhci_hcd t10_pi r8169 > raid_class scsi_transport_sas realtek crc64_rocksoft mdio_devres > crc32_pclmul scsi_mod usbcore crc_t10dif crc32c_intel libphy > crct10dif_generic i2c_piix4 video crct10dif_pclmul usb_common scsi_common > crct10dif_common gpio_amdpt wmi gpio_generic > [ 11.026158] CPU: 10 PID: 659 Comm: (udev-worker) Not tainted 6.10.0-rc2 > #7 > [ 11.026160] Hardware name: ASUS System Product Name/TUF GAMING > B650M-PLUS, BIOS 2412 01/26/2024 > [ 11.026162] RIP: 0010:amdgpu_bo_release_notify+0x1f5/0x210 [amdgpu] > [ 11.026231] Code: 0b e9 b3 fe ff ff 48 ba ff ff ff ff ff ff ff 7f 31 f6 4c > 89 e7 e8 > 6b 72 3c fa eb 98 e8 f4 6b 3c fa eb b2 0f 0b e9 60 fe ff ff <0f> 0b eb a7 be > 03 > 00 00 00 e8 8d 71 14 fa eb 9b e8 c6 5f 6b fa 66 > [ 11.026233] RSP: 0018:bff4412ab370 EFLAGS: 00010282 > [ 11.026234] RAX: ffea RBX: 9e9dd60d4448 RCX: > > [ 11.026236] RDX: RSI: bc628da6 RDI: > > [ 11.026237] RBP: 9e9dc9c0ef58 R08: R09: > 0003 > [ 11.026238] R10: bff4412ab0f0 R11: 9ead1de35fe8 R12: > 9e9dd60d4400 > [ 11.026239] R13: 9e9dd60d4548 R14: 9e9dc9c0ef58 R15: > 0258 > [ 11.026240] FS: 7fc9121948c0() GS:9eacddb0() > knlGS: > [ 11.026241] CS: 0010 DS: ES: CR0: 80050033 > [ 11.026242] CR2: 7f11564d0790 CR3: 0001072db000 CR4: > 00750ef0 > [ 11.026243] PKRU: 5554 > [ 11.026244] Call Trace: > [ 11.026246] > [ 11.026247] ? __warn+0x7c/0x120 > [ 11.026251] ? amdgpu_bo_release_notify+0x1f5/0x210 [amdgpu] > [ 11.026329] ? report_bug+0x189/0x1c0 > [ 11.026332] ? handle_bug+0x41/0x70 > [ 11.026334] ? exc_invalid_op+0x13/0x60 > [ 11.026336] ? asm_exc_invalid_op+0x16/0x20 > [ 11.026338] ? amdgpu_bo_release_notify+0x1f5/0x210 [amdgpu] > [ 11.026410] ttm_bo_release+0xfb/0x2e0 [ttm] > [ 11.026413] ? amdgpu_ttm_debugfs_init+0xf0/0xf0 [amdgpu] > [ 11.026484] ? ttm_resource_move_to_lru_tail+0x138/0x1d0 [ttm] > [ 11.026486] amdgpu_bo_free_kernel+0xc7/0x120 [amdgpu] > [ 11.026556] dm_helpers_free_gpu_mem+0x3d/0x80 [amdgpu] > [ 11.026663] dcn315_clk_mgr_construct+0x190/0x7e0 [amdgpu] > [ 11.026764] dc_clk_mgr_create+0x31c/0x500 [amdgpu] > [ 11.026843] dc_create+0x286/0x630 [amdgpu] > [ 11.026938] amdgpu_dm_init.isra.0+0x2e9/0x1f10 [amdgpu] > [ 11.027022] ? __irq_work_queue_local+0x3c/0xe0 > [ 11.027025] ? irq_work_queue+0x31/0x50 > [ 11.027027] ? vprintk_emit+0x17f/0x2b0 > [ 11.027029] ? dev_printk_emit+0xa1/0xd0 > [ 11.02703
Re: [PATCH 2/2] drm/amdgpu: reject gang submit on reserved VMIDs
[AMD Official Use Only - AMD Internal Distribution Only]
Series is:
Reviewed-by: Alex Deucher
From: Christian König
Sent: Tuesday, June 11, 2024 7:43 AM
To: Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org
Subject: [PATCH 2/2] drm/amdgpu: reject gang submit on reserved VMIDs
A gang submit won't work if the VMID is reserved and we can't flush out
VM changes from multiple engines at the same time.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 15 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 1 +
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ec888fc6ead8..916b6b8cf7d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1093,6 +1093,21 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser
*p)
unsigned int i;
int r;
+ /*
+* We can't use gang submit on with reserved VMIDs when the VM changes
+* can't be invalidated by more than one engine at the same time.
+*/
+ if (p->gang_size > 1 && !p->adev->vm_manager.concurrent_flush) {
+ for (i = 0; i < p->gang_size; ++i) {
+ struct drm_sched_entity *entity = p->entities[i];
+ struct drm_gpu_scheduler *sched = entity->rq->sched;
+ struct amdgpu_ring *ring = to_amdgpu_ring(sched);
+
+ if (amdgpu_vmid_uses_reserved(vm, ring->vm_hub))
+ return -EINVAL;
+ }
+ }
+
r = amdgpu_vm_clear_freed(adev, vm, NULL);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index b5b9d4f40f53..b6a8bddada4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -424,7 +424,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
if (r || !idle)
goto error;
- if (vm->reserved_vmid[vmhub] || (enforce_isolation && (vmhub ==
AMDGPU_GFXHUB(0 {
+ if (amdgpu_vmid_uses_reserved(vm, vmhub)) {
r = amdgpu_vmid_grab_reserved(vm, ring, job, &id, fence);
if (r || !id)
goto error;
@@ -474,6 +474,19 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
return r;
}
+/*
+ * amdgpu_vmid_uses_reserved - check if a VM will use a reserved VMID
+ * @vm: the VM to check
+ * @vmhub: the VMHUB which will be used
+ *
+ * Returns: True if the VM will use a reserved VMID.
+ */
+bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub)
+{
+ return vm->reserved_vmid[vmhub] ||
+ (enforce_isolation && (vmhub == AMDGPU_GFXHUB(0)));
+}
+
int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
unsigned vmhub)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
index fa8c42c83d5d..240fa6751260 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -78,6 +78,7 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv,
bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
struct amdgpu_vmid *id);
+bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub);
int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
unsigned vmhub);
void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
--
2.34.1
RE: [PATCH 1/2] drm/amdgpu/pptable: Fix __counted_by attribute
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Mario
> Limonciello
> Sent: Friday, June 14, 2024 1:06 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario ; Tasos Sahanidis
>
> Subject: [PATCH 1/2] drm/amdgpu/pptable: Fix __counted_by attribute
>
> The attribute is not helpful if commented out.
It's commented out on purpose because it breaks clang 19. See:
https://lists.freedesktop.org/archives/amd-gfx/2024-May/109223.html
Alex
>
> Cc: Tasos Sahanidis
> Fixes: c6c4dd540125 ("drm/amdgpu/pptable: Fix UBSAN array-index-out-of-
> bounds")
> Signed-off-by: Mario Limonciello
> ---
> drivers/gpu/drm/amd/include/pptable.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/include/pptable.h
> b/drivers/gpu/drm/amd/include/pptable.h
> index f83ace2d7ec3..984770d0eb4c 100644
> --- a/drivers/gpu/drm/amd/include/pptable.h
> +++ b/drivers/gpu/drm/amd/include/pptable.h
> @@ -480,7 +480,7 @@ typedef struct _StateArray{
> //how many states we have
> UCHAR ucNumEntries;
>
> - ATOM_PPLIB_STATE_V2 states[] /* __counted_by(ucNumEntries) */;
> + ATOM_PPLIB_STATE_V2 states[] __counted_by(ucNumEntries);
> }StateArray;
>
>
> --
> 2.43.0
Re: [PATCH] drm/amdgpu/vcn: port mmsch ctx table size fix from jpeg v4
[Public] Acked-by: Alex Deucher From: amd-gfx on behalf of Jane Jian Sent: Tuesday, June 11, 2024 6:06 AM To: Chen, JingWen (Wayne) Cc: amd-gfx@lists.freedesktop.org ; Jian, Jane Subject: [PATCH] drm/amdgpu/vcn: port mmsch ctx table size fix from jpeg v4 add jpeg table size to ctx table size rather than override it Signed-off-by: Jane Jian --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 04d8966423de..0edfb7754768 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -202,7 +202,7 @@ static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); header.version = MMSCH_VERSION; - header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; + header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE); table_loc = (uint32_t *)table->cpu_addr; table_loc += header.total_size; -- 2.34.1
RE: quadbuffer stereo
[Public] Quadbuffer stereo is not supported on Linux. Alex From: amd-gfx On Behalf Of adblover Sent: Monday, June 24, 2024 6:53 AM To: intel-...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org Subject: quadbuffer stereo I have no idea how to enable quadbuffer stereo (hdmi-3d) on linux for intel and amdgpu. I tried using Option Stereo 12 with this result (WW) AMDGPU(0): Option "Stereo" is not used Hoping for solutions for both cards (intel arc,renoir) thanks -- #xorg.conf that I used Section "ServerLayout" Identifier "xserver" Screen 0 "screen" 0 0 InputDevice"keyb" "CoreKeyboard" InputDevice"mouse" "CorePointer" EndSection Section "ServerFlags" Option "AllowMouseOpenFail" "true" # allows the server to start up even if the mouse does not work #Option "DontVTSwitch""false" # allow switching between virtual terminal # Option "DontZoom""true" # disable / (resolution switching) EndSection Section "Files" #RgbPath "/usr/X11R6/lib/X11/rgb" #ModulePath "/usr/X11R6/lib/modules" # More information: http://ftp.x.org/pub/X11R7.0/doc/html/fonts.html FontPath "/usr/share/fonts/X11/misc" FontPath "/usr/share/fonts/X11/100dpi/:unscaled" FontPath "/usr/share/fonts/X11/75dpi/:unscaled" FontPath "/usr/share/fonts/X11/Type1" FontPath "/usr/share/fonts/X11/100dpi" FontPath "/usr/share/fonts/X11/75dpi" FontPath "/usr/X11R6/lib/X11/fonts/misc:unscaled" FontPath "/usr/X11R6/lib/X11/fonts/misc" FontPath "/usr/X11R6/lib/X11/fonts/75dpi:unscaled" FontPath "/usr/X11R6/lib/X11/fonts/75dpi" FontPath "/usr/X11R6/lib/X11/fonts/100dpi:unscaled" FontPath "/usr/X11R6/lib/X11/fonts/100dpi" # True type and type1 fonts are also handled via xftlib, see /etc/X11/XftConfig! FontPath "/usr/X11R6/lib/X11/fonts/Type1" FontPath "/usr/share/fonts/ttf/western" FontPath "/usr/share/fonts/ttf/decoratives" FontPath "/usr/share/fonts/truetype/ttf-bitstream-vera" FontPath "/usr/share/fonts/latex-ttf-fonts" FontPath "/var/lib/defoma/x-ttcidfont-conf.d/dirs/TrueType" EndSection Section "Module" Load "dbe" # double buffer extension Load "dri" # direct rendering Load "glx" # 3D layer Load "amdgpu" Load "modesetting" Load "glamoregl" Load "extmod"# some commonly used server extensions (e.g. shape extension) Load "record"# recording extension Load "evdev" # generic input handling driver on Linux Load "bitmap"# bitmap fonts Load "ddc" # ddc probing of monitor Load "freetype" # font rendering EndSection Section "InputDevice" Identifier "keyb" Option "CoreKeyboard" Driver "evdev" Option "XkbRules" "xorg" Option "XkbModel" "pc105" Option "XkbLayout" "de" #Option "XkbOptions" "u" EndSection Section "InputDevice" Identifier "mouse" Driver "evdev" #Option "Device" "/dev/input/mice" #Option "ZAxisMapping" "4 5" #Option "Buttons" "5" #Option "SendCoreEvents""true" EndSection Section "Monitor" Identifier "sony" Option "DPMS" "true" #HorizSync31.0 - 61.0 #VertRefresh 50.0 - 90.0 EndSection Section "Device" Identifier "card" Driver "amdgpu" Option "Stereo" "12" EndSection Section "Screen" Identifier "screen" Device "card" Monitor"sony" SubSection "Display" Depth 24 Modes "1920x1080" EndSubSection SubSection "Display" Depth 32 Modes "1920x1080" EndSubSection SubSection "Extensions" Option "Composite" "Disable" EndSubSection EndSection # Make sure you have the relevant Debian packages on your system # to be able to use DRI (libgl1-mesa-dri for example) Section "DRI" Mode 0666 EndSection
Re: [PATCH] drm/amdgpu: Set no_hw_access when VF request full GPU fails
[Public]
Acked-by: Alex Deucher
From: Yifan Zha
Sent: Friday, June 28, 2024 4:42 AM
To: amd-gfx@lists.freedesktop.org ; Deucher,
Alexander ; Zhang, Hawking
Cc: Chen, Horace ; Chang, HaiJun ;
Zha, YiFan(Even)
Subject: [PATCH] drm/amdgpu: Set no_hw_access when VF request full GPU fails
[Why]
If VF request full GPU access and the request failed,
the VF driver can get stuck accessing registers for an extended period during
the unload of KMS.
[How]
Set no_hw_access flag when VF request for full GPU access fails
This prevents further hardware access attempts, avoiding the prolonged
stuck state.
Signed-off-by: Yifan Zha
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index ccb3d041c2b2..111c380f929b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -86,8 +86,10 @@ int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev,
bool init)
if (virt->ops && virt->ops->req_full_gpu) {
r = virt->ops->req_full_gpu(adev, init);
- if (r)
+ if (r) {
+ adev->no_hw_access = true;
return r;
+ }
adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
}
--
2.25.1
Re: [PATCH 7/7] drm/amdgpu: add firmware for GC IP v11.5.2
[Public]
Series is:
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 10:38 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim ; Zhang, Yifan
Subject: [PATCH 7/7] drm/amdgpu: add firmware for GC IP v11.5.2
This patch is to add firmware for GC 11.5.2.
Signed-off-by: Tim Huang
Reviewed-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 ++
3 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 9acdabd7719a..38150398a31b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -93,6 +93,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin");
static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {
SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index a9f5d9e4610d..6c1891889c4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -38,6 +38,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_3_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_4_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_0_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_imu.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_imu.bin");
static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 3b1f6ad99100..1376b6ff1b77 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -51,6 +51,8 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin");
static int mes_v11_0_hw_init(void *handle);
static int mes_v11_0_hw_fini(void *handle);
--
2.43.0
Re: [PATCH 2/2] drm/amdgpu: Add NBIO IP v7.11.3 support
[Public] Series is: Reviewed-by: Alex Deucher From: Huang, Tim Sent: Sunday, June 30, 2024 10:48 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Zhang, Yifan ; Huang, Tim ; Zhang, Yifan Subject: [PATCH 2/2] drm/amdgpu: Add NBIO IP v7.11.3 support Enable setting soc21 common clockgating for NBIO 7.11.3. Signed-off-by: Tim Huang Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/soc21.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index b04c763015d3..b43c50f1c7ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -953,6 +953,7 @@ static int soc21_common_set_clockgating_state(void *handle, case IP_VERSION(7, 7, 1): case IP_VERSION(7, 11, 0): case IP_VERSION(7, 11, 1): + case IP_VERSION(7, 11, 3): adev->nbio.funcs->update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); adev->nbio.funcs->update_medium_grain_light_sleep(adev, -- 2.43.0
Re: [PATCH 3/3] drm/amdgpu: add firmware for VPE IP v6.1.3
[Public]
Series is:
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 10:50 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim ; Zhang, Yifan
Subject: [PATCH 3/3] drm/amdgpu: add firmware for VPE IP v6.1.3
This patch is to add firmware for VPE 6.1.3.
Signed-off-by: Tim Huang
Reviewed-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
index 09315dd5a1ec..45876883bbf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
@@ -34,6 +34,7 @@
MODULE_FIRMWARE("amdgpu/vpe_6_1_0.bin");
MODULE_FIRMWARE("amdgpu/vpe_6_1_1.bin");
+MODULE_FIRMWARE("amdgpu/vpe_6_1_3.bin");
#define VPE_THREAD1_UCODE_OFFSET0x8000
--
2.43.0
Re: [PATCH 7/7] drm/amdgpu: add firmware for PSP IP v14.0.4
[AMD Official Use Only - AMD Internal Distribution Only]
Series is:
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 10:58 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim ; Zhang, Yifan
Subject: [PATCH 7/7] drm/amdgpu: add firmware for PSP IP v14.0.4
This patch is to add firmware for PSP 14.0.4.
Signed-off-by: Tim Huang
Reviewed-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 407477b895d1..1251ee38a676 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -57,6 +57,8 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin");
+MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin");
+MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin");
/* For large FW files the time to complete can be very long */
#define USBC_PD_POLLING_LIMIT_S 240
--
2.43.0
Re: [PATCH] drm/amd/pm: avoid to load smu firmware for APUs
[Public]
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 11:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim
Subject: [PATCH] drm/amd/pm: avoid to load smu firmware for APUs
Certain call paths still load the SMU firmware for APUs,
which needs to be skipped.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 +++-
drivers/gpu/drm/amd/pm/amdgpu_dpm.c| 2 +-
4 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 18488c02d1cf..c55518fe542c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7324,11 +7324,9 @@ static int gfx_v10_0_hw_init(void *handle)
* loaded firstly, so in direct type, it has to load smc ucode
* here before rlc.
*/
- if (!(adev->flags & AMD_IS_APU)) {
- r = amdgpu_pm_load_smu_firmware(adev, NULL);
- if (r)
- return r;
- }
+ r = amdgpu_pm_load_smu_firmware(adev, NULL);
+ if (r)
+ return r;
gfx_v10_0_disable_gpa_mode(adev);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 38150398a31b..0ad35e96d2b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4558,11 +4558,9 @@ static int gfx_v11_0_hw_init(void *handle)
* loaded firstly, so in direct type, it has to load smc ucode
* here before rlc.
*/
- if (!(adev->flags & AMD_IS_APU)) {
- r = amdgpu_pm_load_smu_firmware(adev, NULL);
- if (r)
- return r;
- }
+ r = amdgpu_pm_load_smu_firmware(adev, NULL);
+ if (r)
+ return r;
}
gfx_v11_0_constants_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index ccb26f78252a..40edda2c3003 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3306,11 +3306,9 @@ static int gfx_v12_0_hw_init(void *handle)
* loaded firstly, so in direct type, it has to load smc ucode
* here before rlc.
*/
- if (!(adev->flags & AMD_IS_APU)) {
- r = amdgpu_pm_load_smu_firmware(adev, NULL);
- if (r)
- return r;
- }
+ r = amdgpu_pm_load_smu_firmware(adev, NULL);
+ if (r)
+ return r;
}
gfx_v12_0_constants_init(adev);
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index b3b5e7b74c85..a1b8a82d77cf 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -618,7 +618,7 @@ int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
uint32_t *smu_versio
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int r = 0;
- if (!pp_funcs || !pp_funcs->load_firmware)
+ if (!pp_funcs || !pp_funcs->load_firmware || adev->flags & AMD_IS_APU)
return 0;
mutex_lock(&adev->pm.mutex);
--
2.43.0
Re: [PATCH 3/3] drm/amdgpu: add firmware for SDMA IP v6.1.2
[Public]
Series is:
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 10:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim ; Zhang, Yifan
Subject: [PATCH 3/3] drm/amdgpu: add firmware for SDMA IP v6.1.2
This patch is to add firmware for SDMA 6.1.2.
Signed-off-by: Tim Huang
Reviewed-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index c833b6b8373b..dab4c2db8c9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -50,6 +50,7 @@ MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin");
+MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin");
#define SDMA1_REG_OFFSET 0x600
#define SDMA0_HYP_DEC_REG_START 0x5880
--
2.43.0
Re: [PATCH] drm/amdgpu: restore dcc bo tilling configs while moving
[Public]
Reviewed-by: Alex Deucher
From: Min, Frank
Sent: Sunday, June 30, 2024 11:17 PM
To: Deucher, Alexander ; Olsak, Marek
; Koenig, Christian ; Zhang,
Hawking ; Gao, Likun ;
amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: restore dcc bo tilling configs while moving
[AMD Official Use Only - AMD Internal Distribution Only]
From: Frank Min
While moving buffer which as dcc tiling config, it is needed to restore its
original dcc tiling.
1. extend copy flag to cover tiling bits
2. add logic to restore original dcc tiling config
Signed-off-by: Frank Min
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 17 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 11 +++
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 10 --
3 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 9a92dd3c9fb8..dd4aed47af1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -308,7 +308,8 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
mutex_lock(&adev->mman.gtt_window_lock);
while (src_mm.remaining) {
- uint64_t from, to, cur_size;
+ uint64_t from, to, cur_size, tiling_flags;
+ uint32_t num_type, data_format, max_com;
struct dma_fence *next;
/* Never copy more than 256MiB at once to avoid a timeout */ @@
-329,10 +330,20 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
abo_dst = ttm_to_amdgpu_bo(dst->bo);
if (tmz)
copy_flags |= AMDGPU_COPY_FLAGS_TMZ;
- if (abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
+ if ((abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
+ (abo_src->tbo.resource->mem_type == TTM_PL_VRAM))
copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED;
- if (abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
+ if ((abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
+ (dst->mem->mem_type == TTM_PL_VRAM)) {
copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED;
+ amdgpu_bo_get_tiling_flags(abo_dst, &tiling_flags);
+ max_com = AMDGPU_TILING_GET(tiling_flags,
GFX12_DCC_MAX_COMPRESSED_BLOCK);
+ num_type = AMDGPU_TILING_GET(tiling_flags,
GFX12_DCC_NUMBER_TYPE);
+ data_format = AMDGPU_TILING_GET(tiling_flags,
GFX12_DCC_DATA_FORMAT);
+ copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED,
max_com) |
+ AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE,
num_type) |
+ AMDGPU_COPY_FLAGS_SET(DATA_FORMAT,
data_format));
+ }
r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
&next, false, true, copy_flags); diff
--git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 7c903a6c9ddb..8d34e8588dc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -114,6 +114,17 @@ struct amdgpu_copy_mem {
#define AMDGPU_COPY_FLAGS_TMZ (1 << 0)
#define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED(1 << 1)
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED (1 << 2)
+#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT 3
+#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK 0x03
+#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT5
+#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07
+#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT8
+#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f
+
+#define AMDGPU_COPY_FLAGS_SET(field, value) \
+ (((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) <<
+AMDGPU_COPY_FLAGS_##field##_SHIFT)
+#define AMDGPU_COPY_FLAGS_GET(value, field) \
+ (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) &
+AMDGPU_COPY_FLAGS_##field##_MASK)
int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); void
amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); diff --git
a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 96514fd77e35..41b5e45697dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1566,6 +1566,12 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib
*ib,
uint32_t byte_count,
uint32_t copy_flags)
{
+ uint32_t num_type, data_format, max_com;
+
+ max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);
+ data_format =
Re: [PATCH] drm/amd/display: fix doc entry for bb_from_dmub
[Public]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Aurabindo
Pillai
Sent: Monday, July 15, 2024 3:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: alexdeuc...@gmail.com ; Siqueira, Rodrigo
; Hung, Alex ; Pillai, Aurabindo
Subject: [PATCH] drm/amd/display: fix doc entry for bb_from_dmub
Fixes the warning:
Function parameter or struct member 'bb_from_dmub' not described in
'amdgpu_display_manager'
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 5fd1b6b44577..369159c29bbe 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -587,7 +587,9 @@ struct amdgpu_display_manager {
*/
struct mutex dpia_aux_lock;
- /*
+ /**
+* @bb_from_dmub:
+*
* Bounding box data read from dmub during early initialization for
DCN4+
*/
struct dml2_soc_bb *bb_from_dmub;
--
2.45.2
Re: [PATCH v1 6/6] drm/amdgpu: add print support for sdma_v_4_4_2 ip_dump
[Public]
Series is:
Reviewed-by: Alex Deucher
From: Sunil Khatri
Sent: Thursday, July 18, 2024 12:42 AM
To: Deucher, Alexander ; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org ; Khatri,
Sunil
Subject: [PATCH v1 6/6] drm/amdgpu: add print support for sdma_v_4_4_2 ip_dump
Add print support for ip dump for sdma_v_4_4_2 in
devcoredump.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 917a767ebaf2..9d4091175d29 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1857,6 +1857,27 @@ static void sdma_v4_4_2_get_clockgating_state(void
*handle, u64 *flags)
*flags |= AMD_CG_SUPPORT_SDMA_LS;
}
+static void sdma_v4_4_2_print_ip_state(void *handle, struct drm_printer *p)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i, j;
+ uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
+ uint32_t instance_offset;
+
+ if (!adev->sdma.ip_dump)
+ return;
+
+ drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ instance_offset = i * reg_count;
+ drm_printf(p, "\nInstance:%d\n", i);
+
+ for (j = 0; j < reg_count; j++)
+ drm_printf(p, "%-50s \t 0x%08x\n",
sdma_reg_list_4_4_2[j].reg_name,
+ adev->sdma.ip_dump[instance_offset + j]);
+ }
+}
+
static void sdma_v4_4_2_dump_ip_state(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1895,6 +1916,7 @@ const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
.set_powergating_state = sdma_v4_4_2_set_powergating_state,
.get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
.dump_ip_state = sdma_v4_4_2_dump_ip_state,
+ .print_ip_state = sdma_v4_4_2_print_ip_state,
};
static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
--
2.34.1
Re: [PATCH] drm/amdgpu: skip kfd init if GFX is not ready.
[Public]
Acked-by: Alex Deucher
From: Zhang, Yifan
Sent: Sunday, July 21, 2024 10:25 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: skip kfd init if GFX is not ready.
avoid kfd init crash in that case.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index bcacf2e35eba..730dae77570c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2471,6 +2471,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
*/
static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
{
+ struct amdgpu_ip_block *ip_block;
struct pci_dev *parent;
int i, r;
bool total;
@@ -2608,7 +2609,10 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
if (!total)
return -ENODEV;
- amdgpu_amdkfd_device_probe(adev);
+ ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
+ if (ip_block->status.valid != false)
+ amdgpu_amdkfd_device_probe(adev);
+
adev->cg_flags &= amdgpu_cg_mask;
adev->pg_flags &= amdgpu_pg_mask;
--
2.37.3
RE: [PATCH 1/2] drm/amdgpu: properly handle vbios fake edid sizing
[Public]
> -Original Message-
> From: Thomas Weißschuh
> Sent: Tuesday, July 23, 2024 1:58 PM
> To: Deucher, Alexander
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/amdgpu: properly handle vbios fake edid sizing
>
> On 2024-07-23 13:33:56+, Alex Deucher wrote:
> > The comment in the vbios structure says:
> > // = 128 means EDID length is 128 bytes, otherwise the EDID length =
> > ucFakeEDIDLength*128
> >
> > This fake edid struct has not been used in a long time, so I'm not
> > sure if there were actually any boards out there with a non-128 byte
> > EDID, but align the code with the comment.
> >
> > Reported-by: Thomas Weißschuh
>
> Afaik Reported-by: should also have a Link:.
>
> And IMO a Fixes: would also be fitting.
I can add those.
>
> > Signed-off-by: Alex Deucher
> > ---
> > .../gpu/drm/amd/amdgpu/atombios_encoders.c| 24 +++--
> --
> > 1 file changed, 14 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
> > b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
> > index 25feab188dfe..a8751a5901c6 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
> > @@ -2065,12 +2065,16 @@
> amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)
> > fake_edid_record =
> (ATOM_FAKE_EDID_PATCH_RECORD *)record;
> > if (fake_edid_record-
> >ucFakeEDIDLength) {
> > struct edid *edid;
> > - int edid_size =
> > -
> max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
> > - edid = kmalloc(edid_size,
> GFP_KERNEL);
> > + int edid_size;
> > +
> > + if (fake_edid_record-
> >ucFakeEDIDLength == 128)
> > + edid_size =
> fake_edid_record->ucFakeEDIDLength;
> > + else
> > + edid_size =
> fake_edid_record->ucFakeEDIDLength * 128;
> > + edid =
> kmalloc(max(EDID_LENGTH, edid_size), GFP_KERNEL);
>
> This looks wrong, but it was similar before.
> If the EDID contains extensions and the code tries to access those, it will
> be an
> out of bounds memory access, because the extensions were not actually
> copied.
> (And this seems to already happen in drm_edid_is_valid())
>
> This code will go away soon with my patch, but at least we can now figure out
> what to do on EDIDs with extensions instead of changing the behaviour just as
> a side-effect.
>
> Is there any issue with just dropping the max() and keeping the full EDID?
Yes, we can drop the max(). Although I'm not entirely sure what the problem is
that you are getting at. We always copy the entire EDID from the vbios. The
EDID from the bios is either 128 bytes or a multiple of 128 bytes. The max was
only there to make sure we allocated a minimum of EDID_LENGTH bytes.
>
> Also if this is touched anyways, it could become kmemdup().
Will fix that up.
Thanks,
Alex
>
> > if (edid) {
> > memcpy((u8 *)edid,
> (u8 *)&fake_edid_record->ucFakeEDIDString[0],
> > - fake_edid_record-
> >ucFakeEDIDLength);
> > + edid_size);
> >
> > if
> (drm_edid_is_valid(edid)) {
> > adev-
> >mode_info.bios_hardcoded_edid = edid; @@ -2078,13
> > +2082,13 @@ amdgpu_atombios_encoder_get_lcd_info(struct
> amdgpu_encoder *encoder)
> > } else
> > kfree(edid);
> > }
> > + record +=
> struct_size(fake_edid_record,
> > +
> ucFakeEDIDString,
> > +
> > edid_size);
> > + } else {
> > + /* empty fake edid record
> must be 3 bytes
RE: [PATCH 6.10] drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()
[Public]
> -Original Message-
> From: Kevin Holm
> Sent: Tuesday, July 30, 2024 2:54 PM
> To: sta...@vger.kernel.org
> Cc: regressi...@lists.linux.dev; amd-gfx@lists.freedesktop.org; ML dri-devel
> ; LKML ; Lin,
> Wayne ; Zuo, Jerry ;
> Mohamed, Zaeem ; Wheeler, Daniel
> ; Deucher, Alexander
> ; Kevin Holm
> Subject: [PATCH 6.10] drm/amd/display: Refactor function
> dm_dp_mst_is_port_support_mode()
>
> From: Wayne Lin
>
> [ Upstream commit fa57924c76d995e87ca3533ec60d1d5e55769a27 ]
>
> [Why]
> dm_dp_mst_is_port_support_mode() is a bit not following the original design
> rule and cause light up issue with multiple 4k monitors after mst dsc hub.
>
> [How]
> Refactor function dm_dp_mst_is_port_support_mode() a bit to solve the light
> up issue.
>
> Reviewed-by: Jerry Zuo
> Acked-by: Zaeem Mohamed
> Signed-off-by: Wayne Lin
> Tested-by: Daniel Wheeler
> Signed-off-by: Alex Deucher
> [ke...@holm.dev: Resolved merge conflict in .../amdgpu_dm_mst_types.c]
> Fixes: 4df96ba6676034 ("drm/amd/display: Add timing pixel encoding for
> mst mode validation")
> Link:
> https://lore.kernel.org/stable/d74a7768e957e6ce88c27a5bece0c64dff132e
> 2...@holm.dev/T/#u
> Signed-off-by: Kevin Holm
Acked-by: Alex Deucher
> ---
> I resolved the merge conflict so that, after this patch is applied to the
> linux-
> 6.10.y branch of the stable git repository, the resulting function
> dm_dp_mst_is_port_support_mode (and also the new function
> dp_get_link_current_set_bw) is identical to the original commit.
>
> I've confirmed that it fixes the regression I reported for my use case.
> ---
> .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 232 +++-
> --
> 1 file changed, 147 insertions(+), 85 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index a5e1a93ddaea..e90f9d697511 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -1595,109 +1595,171 @@ static bool
> is_dsc_common_config_possible(struct dc_stream_state *stream,
> return bw_range->max_target_bpp_x16 && bw_range-
> >min_target_bpp_x16; }
>
> +#if defined(CONFIG_DRM_AMD_DC_FP)
> +static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t
> +*cur_link_bw) {
> + uint32_t total_data_bw_efficiency_x1 = 0;
> + uint32_t link_rate_per_lane_kbps = 0;
> + enum dc_link_rate link_rate;
> + union lane_count_set lane_count;
> + u8 dp_link_encoding;
> + u8 link_bw_set = 0;
> +
> + *cur_link_bw = 0;
> +
> + if (drm_dp_dpcd_read(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
> &dp_link_encoding, 1) != 1 ||
> + drm_dp_dpcd_read(aux, DP_LANE_COUNT_SET,
> &lane_count.raw, 1) != 1 ||
> + drm_dp_dpcd_read(aux, DP_LINK_BW_SET, &link_bw_set, 1)
> != 1)
> + return false;
> +
> + switch (dp_link_encoding) {
> + case DP_8b_10b_ENCODING:
> + link_rate = link_bw_set;
> + link_rate_per_lane_kbps = link_rate *
> LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
> + total_data_bw_efficiency_x1 =
> DATA_EFFICIENCY_8b_10b_x1;
> + total_data_bw_efficiency_x1 /= 100;
> + total_data_bw_efficiency_x1 *=
> DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
> + break;
> + case DP_128b_132b_ENCODING:
> + switch (link_bw_set) {
> + case DP_LINK_BW_10:
> + link_rate = LINK_RATE_UHBR10;
> + break;
> + case DP_LINK_BW_13_5:
> + link_rate = LINK_RATE_UHBR13_5;
> + break;
> + case DP_LINK_BW_20:
> + link_rate = LINK_RATE_UHBR20;
> + break;
> + default:
> + return false;
> + }
> +
> + link_rate_per_lane_kbps = link_rate * 1;
> + total_data_bw_efficiency_x1 =
> DATA_EFFICIENCY_128b_132b_x1;
> + break;
> + default:
> + return false;
> + }
> +
> + *cur_link_bw = link_rate_per_lane_kbps *
> lane_count.bits.LANE_COUNT_SET / 1 *
> total_data_bw_efficiency_x1;
> + return true;
> +}
> +#endif
> +
> enum dc_status dm_dp_mst_is_port_support_mode(
> struct amdgpu_dm_connector *aconnector,
> struct dc_stream_state *stream)
> {
> - int pbn, branch_max_throughput_mps = 0;
> +#if defined(CONFIG_DRM
RE: [PATCH 1/9] drm/amdgpu: Use backlight power constants
[Public]
> -Original Message-
> From: Thomas Zimmermann
> Sent: Wednesday, July 31, 2024 8:17 AM
> To: maarten.lankho...@linux.intel.com; mrip...@kernel.org;
> airl...@gmail.com; dan...@ffwll.ch
> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; intel...@lists.freedesktop.org; Thomas
> Zimmermann ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui
> Subject: [PATCH 1/9] drm/amdgpu: Use backlight power constants
>
> Replace FB_BLANK_ constants with their counterparts from the backlight
> subsystem. The values are identical, so there's no change in functionality or
> semantics.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: Xinhui Pan
This patch and the radeon patch are:
Acked-by: Alex Deucher
Feel free to take them via whatever tree makes sense if you are trying to keep
the patches together, or let me know if you want me to pick them up.
Thanks,
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
> b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
> index 25feab188dfe..650ec95bb40a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
> +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
> @@ -215,7 +215,7 @@ void
> amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder
> *amdgpu_encode
> dig->bl_dev = bd;
>
> bd->props.brightness =
> amdgpu_atombios_encoder_get_backlight_brightness(bd);
> - bd->props.power = FB_BLANK_UNBLANK;
> + bd->props.power = BACKLIGHT_POWER_ON;
> backlight_update_status(bd);
>
> DRM_INFO("amdgpu atom DIG backlight initialized\n");
> --
> 2.45.2
RE: [PATCH] drm/amdgpu/mes: refine for maximum packet execution
[Public] > -Original Message- > From: Xiao, Jack > Sent: Tuesday, July 23, 2024 4:28 AM > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander > ; ckoenig.leichtzumer...@gmail.com > Cc: Xiao, Jack > Subject: [PATCH] drm/amdgpu/mes: refine for maximum packet execution > > Only allow API_NUMBER_OF_COMMAND_MAX packet in mes ring buffer, > refine the code for maximum packet execution. > > Signed-off-by: Jack Xiao Any updates on this patch? Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 2 +- > 3 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > index ad49cecb20b8..dfe487521a4a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > @@ -212,6 +212,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, > struct amdgpu_ring *ring, >*/ > if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) > sched_hw_submission = max(sched_hw_submission, 256); > + else if (ring->funcs->type == AMDGPU_RING_TYPE_MES) > + sched_hw_submission = 32; > else if (ring == &adev->sdma.instance[0].page) > sched_hw_submission = 256; > > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > index 68c74adf79f1..951f13e01ee9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > @@ -198,7 +198,7 @@ static int > mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, > > seq = ++ring->fence_drv.sync_seq; > r = amdgpu_fence_wait_polling(ring, > - seq - ring->fence_drv.num_fences_mask, > + seq - > (API_NUMBER_OF_COMMAND_MAX/2 - 1), > timeout); > if (r < 1) > goto error_undo; > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c > b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c > index 48e01206bcc4..dc65f28d1795 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c > @@ -184,7 +184,7 @@ static int > mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, > > seq = ++ring->fence_drv.sync_seq; > r = amdgpu_fence_wait_polling(ring, > - seq - ring->fence_drv.num_fences_mask, > + seq - > (API_NUMBER_OF_COMMAND_MAX/2 - 1), > timeout); > if (r < 1) > goto error_undo; > -- > 2.41.0
RE: [PATCH] amd/gpu: drm/hisilicon: Remove unused declarations
[Public]
> -Original Message-
> From: Zhang Zekun
> Sent: Monday, August 12, 2024 8:24 AM
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch; amd-gfx@lists.freedesktop.org
> Cc: zhangzeku...@huawei.com
> Subject: [PATCH] amd/gpu: drm/hisilicon: Remove unused declarations
Applied with patch title fixed up.
Thanks,
Alex
>
> amdgpu_gart_table_vram_pin() and amdgpu_gart_table_vram_unpin() has
> been removed since commit 575e55ee4fbc ("drm/amdgpu: recover gart table
> at resume") remain the declarations untouched in the header files.
>
> Besides, amdgpu_dm_display_resume() has also beed removed since commit
> a80aa93de1a0 ("drm/amd/display: Unify dm resume sequence into a single
> call"). So, let's remove this unused declarations.
>
> Signed-off-by: Zhang Zekun
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 --
> 2 files changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 137a88b8de45..f0feb199b6e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1588,13 +1588,6 @@ static inline bool
> amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return static inline
> void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
> #endif
>
> -#if defined(CONFIG_DRM_AMD_DC)
> -int amdgpu_dm_display_resume(struct amdgpu_device *adev ); -#else -static
> inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return
> 0; } -#endif
> -
> -
> void amdgpu_register_gpu_instance(struct amdgpu_device *adev); void
> amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> index 8283d682f543..7cc980bf4725 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> @@ -55,8 +55,6 @@ int amdgpu_gart_table_ram_alloc(struct
> amdgpu_device *adev); void amdgpu_gart_table_ram_free(struct
> amdgpu_device *adev); int amdgpu_gart_table_vram_alloc(struct
> amdgpu_device *adev); void amdgpu_gart_table_vram_free(struct
> amdgpu_device *adev); -int amdgpu_gart_table_vram_pin(struct
> amdgpu_device *adev); -void amdgpu_gart_table_vram_unpin(struct
> amdgpu_device *adev); int amdgpu_gart_init(struct amdgpu_device *adev);
> void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev); void
> amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
> --
> 2.17.1
RE: [PATCH v2] drm/radeon/evergreen_cs: fix int overflow errors in cs track offsets
[Public]
> -Original Message-
> From: Nikita Zhandarovich
> Sent: Tuesday, August 6, 2024 1:19 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ; David
> Airlie ; Daniel Vetter
> Cc: Nikita Zhandarovich ; Jerome Glisse
> ; Dave Airlie ; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org; lvc-proj...@linuxtesting.org
> Subject: [PATCH v2] drm/radeon/evergreen_cs: fix int overflow errors in cs
> track offsets
>
> Several cs track offsets (such as 'track->db_s_read_offset') either are
> initialized
> with or plainly take big enough values that, once shifted 8 bits left, may be
> hit
> with integer overflow if the resulting values end up going over u32 limit.
>
> Same goes for a few instances of 'surf.layer_size * mslice'
> multiplications that are added to 'offset' variable - they may potentially
> overflow as well and need to be validated properly.
>
> While some debug prints in this code section take possible overflow issues
> into
> account, simply casting to (unsigned long) may be erroneous in its own way,
> as depending on CPU architecture one is liable to get different results.
>
> Fix said problems by:
> - casting 'offset' to fixed u64 data type instead of ambiguous unsigned
> long.
> - casting one of the operands in vulnerable to integer overflow cases to
> u64.
> - adjust format specifiers in debug prints to properly represent 'offset'
> values.
>
> Found by Linux Verification Center (linuxtesting.org) with static analysis
> tool
> SVACE.
>
> Fixes: 285484e2d55e ("drm/radeon: add support for evergreen/ni tiling
> informations v11")
> Signed-off-by: Nikita Zhandarovich
Applied. Thanks!
Alex
> ---
> v2:
> - change data type to cast from unsigned long to u64 per Alex's and
> Christian's
> suggestion:
> https://lore.kernel.org/all/CADnq5_NaMr+vpqwqhsMoSeGrto2Lw5v0KXWEp
> 2HRK=++ors...@mail.gmail.com/
> - include validation of surf.layer_size * mslice per Christian's
> approval:
> https://lore.kernel.org/all/1914cfcb-9700-4274-8120-
> 9746e241c...@amd.com/
> - change format specifiers when printing 'offset' value.
> - fix commit description to reflect patch changes.
>
> v1:
> https://lore.kernel.org/all/20240725180950.15820-1-
> n.zhandarov...@fintech.ru/
>
> drivers/gpu/drm/radeon/evergreen_cs.c | 62 +---
> ---
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c
> b/drivers/gpu/drm/radeon/evergreen_cs.c
> index e5577d2a19ef..a46613283393 100644
> --- a/drivers/gpu/drm/radeon/evergreen_cs.c
> +++ b/drivers/gpu/drm/radeon/evergreen_cs.c
> @@ -397,7 +397,7 @@ static int evergreen_cs_track_validate_cb(struct
> radeon_cs_parser *p, unsigned i
> struct evergreen_cs_track *track = p->track;
> struct eg_surface surf;
> unsigned pitch, slice, mslice;
> - unsigned long offset;
> + u64 offset;
> int r;
>
> mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1; @@ -
> 435,14 +435,14 @@ static int evergreen_cs_track_validate_cb(struct
> radeon_cs_parser *p, unsigned i
> return r;
> }
>
> - offset = track->cb_color_bo_offset[id] << 8;
> + offset = (u64)track->cb_color_bo_offset[id] << 8;
> if (offset & (surf.base_align - 1)) {
> - dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned
> with %ld\n",
> + dev_warn(p->dev, "%s:%d cb[%d] bo base %llu not aligned
> with %ld\n",
>__func__, __LINE__, id, offset, surf.base_align);
> return -EINVAL;
> }
>
> - offset += surf.layer_size * mslice;
> + offset += (u64)surf.layer_size * mslice;
> if (offset > radeon_bo_size(track->cb_color_bo[id])) {
> /* old ddx are broken they allocate bo with w*h*bpp but
>* program slice with ALIGN(h, 8), catch this and patch @@ -
> 450,14 +450,14 @@ static int evergreen_cs_track_validate_cb(struct
> radeon_cs_parser *p, unsigned i
>*/
> if (!surf.mode) {
> uint32_t *ib = p->ib.ptr;
> - unsigned long tmp, nby, bsize, size, min = 0;
> + u64 tmp, nby, bsize, size, min = 0;
>
> /* find the height the ddx wants */
> if (surf.nby > 8) {
> min = surf.nby - 8;
> }
> bsize = rade
Re: [PATCH] drm/amdgpu: Use driver mode reset for data poison handling
[Public]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Hawking
Zhang
Sent: Tuesday, April 16, 2024 1:56 AM
To: amd-gfx@lists.freedesktop.org ; Zhou1, Tao
Cc: Zhang, Hawking
Subject: [PATCH] drm/amdgpu: Use driver mode reset for data poison handling
mode-2 reset is the only reliable method that can get
GC/SDMA back when poison is consumed. mmhub requires
mode-1 reset.
Signed-off-by: Hawking Zhang
---
.../gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 22 +++
1 file changed, 3 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
index c368c70df3f4a..94eb2493103ef 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
@@ -144,7 +144,7 @@ static void event_interrupt_poison_consumption_v9(struct
kfd_node *dev,
uint16_t pasid, uint16_t client_id)
{
enum amdgpu_ras_block block = 0;
- int old_poison, ret = -EINVAL;
+ int old_poison;
uint32_t reset = 0;
struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
@@ -163,17 +163,13 @@ static void event_interrupt_poison_consumption_v9(struct
kfd_node *dev,
case SOC15_IH_CLIENTID_SE2SH:
case SOC15_IH_CLIENTID_SE3SH:
case SOC15_IH_CLIENTID_UTCL2:
- ret = kfd_dqm_evict_pasid(dev->dqm, pasid);
block = AMDGPU_RAS_BLOCK__GFX;
- if (ret)
- reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
+ reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
break;
case SOC15_IH_CLIENTID_VMC:
case SOC15_IH_CLIENTID_VMC1:
- ret = kfd_dqm_evict_pasid(dev->dqm, pasid);
block = AMDGPU_RAS_BLOCK__MMHUB;
- if (ret)
- reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+ reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
break;
case SOC15_IH_CLIENTID_SDMA0:
case SOC15_IH_CLIENTID_SDMA1:
@@ -189,18 +185,6 @@ static void event_interrupt_poison_consumption_v9(struct
kfd_node *dev,
kfd_signal_poison_consumed_event(dev, pasid);
- /* resetting queue passes, do page retirement without gpu reset
-* resetting queue fails, fallback to gpu reset solution
-*/
- if (!ret)
- dev_warn(dev->adev->dev,
- "RAS poison consumption, unmap queue flow succeeded:
client id %d\n",
- client_id);
- else
- dev_warn(dev->adev->dev,
- "RAS poison consumption, fall back to gpu reset flow:
client id %d\n",
- client_id);
-
amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, reset);
}
--
2.17.1
Re: [PATCH] drm/amdgpu: Fix leak when GPU memory allocation fails
[Public] Reviewed-by: Alex Deucher From: amd-gfx on behalf of Mukul Joshi Sent: Thursday, April 18, 2024 12:17 PM To: amd-gfx@lists.freedesktop.org Cc: Kuehling, Felix ; Joshi, Mukul Subject: [PATCH] drm/amdgpu: Fix leak when GPU memory allocation fails Free the sync object if the memory allocation fails for any reason. Signed-off-by: Mukul Joshi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 0ae9fd844623..bcf4a9e82075 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1854,6 +1854,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( err_bo_create: amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id); err_reserve_limit: + amdgpu_sync_free(&(*mem)->sync); mutex_destroy(&(*mem)->lock); if (gobj) drm_gem_object_put(gobj); -- 2.35.1
Re: [PATCH] drm/amdgpu/vpe: fix vpe dpm setup failed
[AMD Official Use Only - General] Acked-by: Alex Deucher From: Lee, Peyton Sent: Thursday, April 18, 2024 1:12 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Liu, HaoPing (Alan) ; Yu, Lang ; Lee, Peyton Subject: [PATCH] drm/amdgpu/vpe: fix vpe dpm setup failed The vpe dpm settings should be done before firmware is loaded. Otherwise, the frequency cannot be successfully raised. Signed-off-by: Peyton Lee --- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 2 +- drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c | 14 +++--- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 6695481f870f..c23d97d34b7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -205,7 +205,7 @@ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe) dpm_ctl &= 0xfffe; /* Disable DPM */ WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__); - return 0; + return -EINVAL; } int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c index 769eb8f7bb3c..09315dd5a1ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c @@ -144,6 +144,12 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe) WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL), ret); } + /* setup collaborate mode */ + vpe_v6_1_set_collaborate_mode(vpe, true); + /* setup DPM */ + if (amdgpu_vpe_configure_dpm(vpe)) + dev_warn(adev->dev, "VPE failed to enable DPM\n"); + /* * For VPE 6.1.1, still only need to add master's offset, and psp will apply it to slave as well. * Here use instance 0 as master. @@ -159,11 +165,7 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe) adev->vpe.cmdbuf_cpu_addr[0] = f32_offset; adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl; - amdgpu_vpe_psp_update_sram(adev); - vpe_v6_1_set_collaborate_mode(vpe, true); - amdgpu_vpe_configure_dpm(vpe); - - return 0; + return amdgpu_vpe_psp_update_sram(adev); } vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data; @@ -196,8 +198,6 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe) } vpe_v6_1_halt(vpe, false); - vpe_v6_1_set_collaborate_mode(vpe, true); - amdgpu_vpe_configure_dpm(vpe); return 0; } -- 2.34.1
Re: [PATCH 1/2] drm/amdgpu: fix double free err_addr pointer warnings
[AMD Official Use Only - General] Acked-by: Alex Deucher From: Bob Zhou Sent: Tuesday, April 23, 2024 1:32 AM To: amd-gfx@lists.freedesktop.org ; Deucher, Alexander ; Koenig, Christian Cc: Zhou, Bob Subject: [PATCH 1/2] drm/amdgpu: fix double free err_addr pointer warnings In amdgpu_umc_bad_page_polling_timeout, the amdgpu_umc_handle_bad_pages will be run many times so that double free err_addr in some special case. So set the err_addr to NULL to avoid the warnings. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index f486510fc94c..32e818d182fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -170,6 +170,7 @@ static void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, } kfree(err_data->err_addr); + err_data->err_addr = NULL; mutex_unlock(&con->page_retirement_lock); } -- 2.34.1
RE: [PATCH 1/3] drm/amdgpu: Fix uninitialized variable warning in amdgpu_afmt_acr
[AMD Official Use Only - General]
> -Original Message-
> From: Ma, Jun
> Sent: Wednesday, April 24, 2024 6:04 AM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian
> ; Deucher, Alexander
>
> Cc: Ma, Jun
> Subject: [PATCH 1/3] drm/amdgpu: Fix uninitialized variable warning in
> amdgpu_afmt_acr
>
> Assign value to clock to fix the warning below:
> "Using uninitialized value res. Field res.clock is uninitialized"
>
> Signed-off-by: Ma Jun
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c
> index a4d65973bf7c..9e3442b2d2ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c
> @@ -87,7 +87,7 @@ static void amdgpu_afmt_calc_cts(uint32_t clock, int
> *CTS, int *N, int freq)
>
> struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) {
> - struct amdgpu_afmt_acr res;
> + struct amdgpu_afmt_acr res = {0};
I think you can drop this hunk since all of the fields are initialized below.
Alex
> u8 i;
>
> /* Precalculated values for common clocks */ @@ -100,6 +100,7 @@
> struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock)
> amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
> amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz,
> 44100);
> amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
> + res.clock = clock;
>
> return res;
> }
> --
> 2.34.1
RE: [PATCH 3/3] drm/amdgpu: Fix the uninitialized variable warning
[AMD Official Use Only - General] > -Original Message- > From: Ma, Jun > Sent: Wednesday, April 24, 2024 6:04 AM > To: amd-gfx@lists.freedesktop.org; Koenig, Christian > ; Deucher, Alexander > > Cc: Ma, Jun > Subject: [PATCH 3/3] drm/amdgpu: Fix the uninitialized variable warning > > Initialize the phy_id to 0 to fix the warning of "Using uninitialized value > phy_id" > > Signed-off-by: Ma Jun > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c > index 8ed0e073656f..df81078aa26d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c > @@ -95,7 +95,7 @@ static ssize_t > amdgpu_securedisplay_debugfs_write(struct file *f, const char __u > struct psp_context *psp = &adev->psp; > struct ta_securedisplay_cmd *securedisplay_cmd; > struct drm_device *dev = adev_to_drm(adev); > - uint32_t phy_id; > + uint32_t phy_id = 0; Would be better to return an error in case 2: below if size < 3. Otherwise we are just blindly using 0 for phy id. Alex > uint32_t op; > char str[64]; > int ret; > -- > 2.34.1
RE: [PATCH 1/2] drm/print: drop include debugfs.h and include where needed
[Public] > -Original Message- > From: Jani Nikula > Sent: Wednesday, April 24, 2024 9:55 AM > To: dri-de...@lists.freedesktop.org > Cc: Andrzej Hajda ; Maxime Ripard > ; Jacek Lawrynowicz > ; Stanislaw Gruszka > ; Oded Gabbay ; > Russell King ; David Airlie ; Daniel > Vetter ; Neil Armstrong ; Robert > Foss ; Laurent Pinchart > ; Jonas Karlman ; > Jernej Skrabec ; Maarten Lankhorst > ; Thomas Zimmermann > ; Rodrigo Vivi ; Joonas > Lahtinen ; Tvrtko Ursulin > ; Frank Binns ; Matt Coster > ; Rob Clark ; Abhinav > Kumar ; Dmitry Baryshkov > ; Sean Paul ; Marijn Suijten > ; Karol Herbst ; Lyude > Paul ; Danilo Krummrich ; Deucher, > Alexander ; Koenig, Christian > ; Pan, Xinhui ; Alain > Volmat ; Huang, Ray ; > Zack Rusin ; Broadcom internal kernel review list > ; Lucas De Marchi > ; Thomas Hellström > ; intel-...@lists.freedesktop.org; intel- > x...@lists.freedesktop.org; linux-arm-...@vger.kernel.org; > freedr...@lists.freedesktop.org; nouv...@lists.freedesktop.org; amd- > g...@lists.freedesktop.org > Subject: Re: [PATCH 1/2] drm/print: drop include debugfs.h and include where > needed > > On Mon, 22 Apr 2024, Jani Nikula wrote: > > Surprisingly many places depend on debugfs.h to be included via > > drm_print.h. Fix them. > > > > v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe > > > > v2: Also fix ivpu and vmwgfx > > > > Reviewed-by: Andrzej Hajda > > Acked-by: Maxime Ripard > > Link: > > > https://patchwork.freedesktop.org/patch/msgid/20240410141434.157908 > -1- > > jani.nik...@intel.com > > Signed-off-by: Jani Nikula > > While the changes all over the place are small, mostly just adding the > debugfs.h include, please consider acking. I've sent this a few times already. > For radeon: Acked-by: Alex Deucher > Otherwise, I'll merge this by the end of the week, acks or not. > > Thanks, > Jani. > > > > > > > --- > > > > Cc: Jacek Lawrynowicz > > Cc: Stanislaw Gruszka > > Cc: Oded Gabbay > > Cc: Russell King > > Cc: David Airlie > > Cc: Daniel Vetter > > Cc: Andrzej Hajda > > Cc: Neil Armstrong > > Cc: Robert Foss > > Cc: Laurent Pinchart > > Cc: Jonas Karlman > > Cc: Jernej Skrabec > > Cc: Maarten Lankhorst > > Cc: Maxime Ripard > > Cc: Thomas Zimmermann > > Cc: Jani Nikula > > Cc: Rodrigo Vivi > > Cc: Joonas Lahtinen > > Cc: Tvrtko Ursulin > > Cc: Frank Binns > > Cc: Matt Coster > > Cc: Rob Clark > > Cc: Abhinav Kumar > > Cc: Dmitry Baryshkov > > Cc: Sean Paul > > Cc: Marijn Suijten > > Cc: Karol Herbst > > Cc: Lyude Paul > > Cc: Danilo Krummrich > > Cc: Alex Deucher > > Cc: "Christian König" > > Cc: "Pan, Xinhui" > > Cc: Alain Volmat > > Cc: Huang Rui > > Cc: Zack Rusin > > Cc: Broadcom internal kernel review list > > > > Cc: Lucas De Marchi > > Cc: "Thomas Hellström" > > Cc: dri-de...@lists.freedesktop.org > > Cc: intel-...@lists.freedesktop.org > > Cc: intel...@lists.freedesktop.org > > Cc: linux-arm-...@vger.kernel.org > > Cc: freedr...@lists.freedesktop.org > > Cc: nouv...@lists.freedesktop.org > > Cc: amd-gfx@lists.freedesktop.org > > --- > > drivers/accel/ivpu/ivpu_debugfs.c | 2 ++ > > drivers/gpu/drm/armada/armada_debugfs.c | 1 + > > drivers/gpu/drm/bridge/ite-it6505.c | 1 + > > drivers/gpu/drm/bridge/panel.c | 2 ++ > > drivers/gpu/drm/drm_print.c | 6 +++--- > > drivers/gpu/drm/i915/display/intel_dmc.c| 1 + > > drivers/gpu/drm/imagination/pvr_fw_trace.c | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 ++ > > drivers/gpu/drm/nouveau/dispnv50/crc.c | 2 ++ > > drivers/gpu/drm/radeon/r100.c | 1 + > > drivers/gpu/drm/radeon/r300.c | 1 + > > drivers/gpu/drm/radeon/r420.c | 1 + > > drivers/gpu/drm/radeon/r600.c | 3 ++- > > drivers/gpu/drm/radeon/radeon_fence.c | 1 + > > drivers/gpu/drm/radeon/radeon_gem.c | 1 + > > drivers/gpu/drm/radeon/radeon_ib.c | 2 ++ > > drivers/gpu/drm/radeon/radeon_pm.c | 1 + > > drivers/gpu/drm/radeon/radeon_ring.c| 2 ++ > > drivers/gpu/drm/radeon/radeon_ttm.c | 1 + > > drivers/gpu/drm/radeon/rs400.c | 1 + > > drivers/gpu/drm/radeon/rv515.c | 1 + > > drivers/gpu/drm/sti/sti_drv.c | 1 + &g
Re: [PATCH] drm/amdgpu: add function descripion of new functions
[Public] Reviewed-by: Alex Deucher From: Sunil Khatri Sent: Friday, April 26, 2024 3:18 AM To: Deucher, Alexander ; Koenig, Christian Cc: amd-gfx@lists.freedesktop.org ; Khatri, Sunil Subject: [PATCH] drm/amdgpu: add function descripion of new functions Add function description of the new functions added in amd_ip_funcs. new functions added are: a. dump_ip_state b. print_ip_state Signed-off-by: Sunil Khatri --- drivers/gpu/drm/amd/include/amd_shared.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 7536c173a546..36ee9d3d6d9c 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -291,6 +291,8 @@ enum amd_dpm_forced_level; * @set_clockgating_state: enable/disable cg for the IP block * @set_powergating_state: enable/disable pg for the IP block * @get_clockgating_state: get current clockgating status + * @dump_ip_state: dump the IP state of the ASIC during a gpu hang + * @print_ip_state: print the IP state in devcoredump for each IP of the ASIC * * These hooks provide an interface for controlling the operational state * of IP blocks. After acquiring a list of IP blocks for the GPU in use, -- 2.34.1
Re: [PATCH v2 2/2] drm/amdgpu/pm: Fix uninitialized variable warning
[AMD Official Use Only - General]
Series is:
Acked-by: Alex Deucher
From: Ma, Jun
Sent: Monday, April 29, 2024 3:58 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Deucher, Alexander
; Wang, Yang(Kevin) ;
Koenig, Christian ; Ma, Jun
Subject: [PATCH v2 2/2] drm/amdgpu/pm: Fix uninitialized variable warning
Check return value of smum_send_msg_to_smc to fix
uninitialized variable varning
Signed-off-by: Ma Jun
---
.../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 21 +
.../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 20
.../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 23 ++-
3 files changed, 48 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 38d5605117ff..a8c732e07006 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1558,7 +1558,10 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr
*hwmgr,
}
if (input[0] == 0) {
- smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
+ ret = smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
+ if (ret)
+ return ret;
+
if (input[1] < min_freq) {
pr_err("Fine grain setting minimum sclk (%ld)
MHz is less than the minimum allowed (%d) MHz\n",
input[1], min_freq);
@@ -1566,7 +1569,10 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr
*hwmgr,
}
smu10_data->gfx_actual_soft_min_freq = input[1];
} else if (input[0] == 1) {
- smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
+ ret = smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
+ if (ret)
+ return ret;
+
if (input[1] > max_freq) {
pr_err("Fine grain setting maximum sclk (%ld)
MHz is greater than the maximum allowed (%d) MHz\n",
input[1], max_freq);
@@ -1581,10 +1587,15 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr
*hwmgr,
pr_err("Input parameter number not correct\n");
return -EINVAL;
}
- smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency,
&min_freq);
- smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency,
&max_freq);
-
+ ret = smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
+ if (ret)
+ return ret;
smu10_data->gfx_actual_soft_min_freq = min_freq;
+
+ ret = smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
+ if (ret)
+ return ret;
+
smu10_data->gfx_actual_soft_max_freq = max_freq;
} else if (type == PP_OD_COMMIT_DPM_TABLE) {
if (size != 0) {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
index c223e3a6bfca..10fd4e9f016c 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
@@ -293,12 +293,12 @@ static int vega12_set_features_platform_caps(struct
pp_hwmgr *hwmgr)
return 0;
}
-static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
+static int vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
{
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
struct amdgpu_device *adev = hwmgr->adev;
uint32_t top32, bottom32;
- int i;
+ int i, ret;
data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
FEATURE_DPM_PREFETCHER_BIT;
@@ -364,10 +364,16 @@ static void vega12_init_dpm_defaults(struct pp_hwmgr
*hwmgr)
}
/* Get the SN to turn into a Unique ID */
- smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
- smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
+ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
+ if (ret)
+ return ret;
+ ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32,
&bottom32);
+ if (ret)
+ return ret;
adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
+
+ return 0;
RE: [PATCH v3 10/10] Documentation/amdgpu: Add PM policy documentation
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Monday, May 13, 2024 5:21 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Kamal, Asad ; Ma,
> Le
> Subject: [PATCH v3 10/10] Documentation/amdgpu: Add PM policy
> documentation
>
> Add documentation about the newly added pm_policy node in sysfs.
>
> Signed-off-by: Lijo Lazar
> ---
> Documentation/gpu/amdgpu/thermal.rst | 6
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 48
>
> 2 files changed, 54 insertions(+)
>
> diff --git a/Documentation/gpu/amdgpu/thermal.rst
> b/Documentation/gpu/amdgpu/thermal.rst
> index 2f6166f81e6a..6d942b5c58f0 100644
> --- a/Documentation/gpu/amdgpu/thermal.rst
> +++ b/Documentation/gpu/amdgpu/thermal.rst
> @@ -49,6 +49,12 @@ pp_power_profile_mode .. kernel-doc::
> drivers/gpu/drm/amd/pm/amdgpu_pm.c
> :doc: pp_power_profile_mode
>
> +pm_policy
> +-
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> + :doc: pm_policy
> +
> \*_busy_percent
> ---
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 9cca4716ec43..45766d49f1f2 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2214,6 +2214,54 @@ static int pp_dpm_clk_default_attr_update(struct
> amdgpu_device *adev, struct amd
> return 0;
> }
>
> +/**
> + * DOC: pm_policy
> + *
> + * Certain SOCs can support different power policies to optimize
> +application
> + * performance. However, this policy is provided only at SOC level and
> +not at a
> + * per-process level. This is useful especially when entire SOC is
> +utilized for
> + * dedicated workload.
> + *
> + * The amdgpu driver provides a sysfs API for selecting the policy.
> +Presently,
> + * only two types of policies are supported through this interface.
> + *
> + * Pstate Policy Selection - This is to select different Pstate
> +profiles which
> + * decides clock/throttling preferences.
> + *
> + * XGMI PLPD Policy Selection - When multiple devices are connected
> +over XGMI,
> + * this helps to select policy to be applied for per link power down.
> + *
> + * The list of available policies and policy levels vary between SOCs.
> +They can
> + * be viewed by reading the file. The policy level which is applied
> +presently is
> + * denoted by * (asterisk). E.g.,
> + *
> + * .. code-block:: console
> + *
> + * cat /sys/bus/pci/devices/.../pm_policy
> + * soc pstate
> + * 0 : soc_pstate_default
> + * 1 : soc_pstate_0
> + * 2 : soc_pstate_1*
> + * 3 : soc_pstate_2
> + * xgmi plpd
> + * 0 : plpd_disallow
> + * 1 : plpd_default
> + * 2 : plpd_optimized*
> + *
> + * To apply a specific policy
> + *
> + * "echo > /sys/bus/pci/devices/.../pm_policy"
> + *
> + * For the levels listed in the example above, to select
> +"plpd_optimized" for
> + * XGMI and "soc_pstate_2" for soc pstate policy -
> + *
> + * .. code-block:: console
> + *
> + * echo "xgmi 2" > /sys/bus/pci/devices/.../pm_policy
> + * echo "soc_pstate 3" > /sys/bus/pci/devices/.../pm_policy
The naming should be consistent between what is printed when you read the file
and what you write to it. E.g., policy_type should be soc_pstate and xgmi_plpd
in both cases.
Alex
> + *
> + */
> +
> static ssize_t amdgpu_get_pm_policy(struct device *dev,
> struct device_attribute *attr, char *buf) {
> --
> 2.25.1
RE: [PATCH] drm/amdgpu: Add documentation for AMD_IP_BLOCK_TYPE_ISP
[Public]
+ Pratap
> -Original Message-
> From: Deucher, Alexander
> Sent: Tuesday, May 14, 2024 11:14 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Stephen Rothwell
>
> Subject: [PATCH] drm/amdgpu: Add documentation for
> AMD_IP_BLOCK_TYPE_ISP
>
> Add missing documentation for the IP block.
>
> Fixes: a83048bfa402 ("drm/amd/amdgpu: Add ISP support to
> amdgpu_discovery")
> Reported-by: Stephen Rothwell
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/include/amd_shared.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
> b/drivers/gpu/drm/amd/include/amd_shared.h
> index 8bc2134cdd6b8..f5b725f10a7ce 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -86,6 +86,7 @@ enum amd_apu_flags {
> * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
> * @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine
> * @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Schduler for Multimedia
> +* @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor
> * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types */ enum
> amd_ip_block_type {
> --
> 2.45.0
RE: [PATCH v4 10/10] Documentation/amdgpu: Add PM policy documentation
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Lazar, Lijo
> Sent: Tuesday, May 14, 2024 7:06 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Kamal, Asad ; Ma,
> Le
> Subject: [PATCH v4 10/10] Documentation/amdgpu: Add PM policy
> documentation
>
> Add documentation about the newly added pm_policy node in sysfs.
>
> Signed-off-by: Lijo Lazar
> ---
> Documentation/gpu/amdgpu/thermal.rst | 6
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 48
>
> 2 files changed, 54 insertions(+)
>
> diff --git a/Documentation/gpu/amdgpu/thermal.rst
> b/Documentation/gpu/amdgpu/thermal.rst
> index 2f6166f81e6a..6d942b5c58f0 100644
> --- a/Documentation/gpu/amdgpu/thermal.rst
> +++ b/Documentation/gpu/amdgpu/thermal.rst
> @@ -49,6 +49,12 @@ pp_power_profile_mode .. kernel-doc::
> drivers/gpu/drm/amd/pm/amdgpu_pm.c
> :doc: pp_power_profile_mode
>
> +pm_policy
> +-
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> + :doc: pm_policy
> +
> \*_busy_percent
> ---
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 5c92c041d0bc..be39276181a1 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2214,6 +2214,54 @@ static int pp_dpm_clk_default_attr_update(struct
> amdgpu_device *adev, struct amd
> return 0;
> }
>
> +/**
> + * DOC: pm_policy
> + *
> + * Certain SOCs can support different power policies to optimize
> +application
> + * performance. However, this policy is provided only at SOC level and
> +not at a
> + * per-process level. This is useful especially when entire SOC is
> +utilized for
> + * dedicated workload.
> + *
> + * The amdgpu driver provides a sysfs API for selecting the policy.
> +Presently,
> + * only two types of policies are supported through this interface.
> + *
> + * Pstate Policy Selection - This is to select different Pstate
> +profiles which
> + * decides clock/throttling preferences.
> + *
> + * XGMI PLPD Policy Selection - When multiple devices are connected
> +over XGMI,
> + * this helps to select policy to be applied for per link power down.
> + *
> + * The list of available policies and policy levels vary between SOCs.
> +They can
> + * be viewed by reading the file. The policy level which is applied
> +presently is
> + * denoted by * (asterisk). E.g.,
> + *
> + * .. code-block:: console
> + *
> + * cat /sys/bus/pci/devices/.../pm_policy
> + * soc_pstate
> + * 0 : soc_pstate_default
> + * 1 : soc_pstate_0
> + * 2 : soc_pstate_1*
> + * 3 : soc_pstate_2
> + * xgmi_plpd
> + * 0 : plpd_disallow
> + * 1 : plpd_default
> + * 2 : plpd_optimized*
I think it would be cleaner to have a pm_policy directory and then have
soc_pstate and xgmi_plpd has nodes within that directory. That aligns better
with the sysfs model and makes it easier to expose different policy options for
different SoCs.
Alex
> + *
> + * To apply a specific policy
> + *
> + * "echo > /sys/bus/pci/devices/.../pm_policy"
> + *
> + * For the levels listed in the example above, to select
> +"plpd_optimized" for
> + * XGMI and "soc_pstate_2" for soc pstate policy -
> + *
> + * .. code-block:: console
> + *
> + * echo "xgmi_plpd 2" > /sys/bus/pci/devices/.../pm_policy
> + * echo "soc_pstate 3" > /sys/bus/pci/devices/.../pm_policy
> + *
> + */
> +
> static ssize_t amdgpu_get_pm_policy(struct device *dev,
> struct device_attribute *attr, char *buf) {
> --
> 2.25.1
RE: [PATCH v3 1/4] drm/amdgpu: update the ip_dump to ipdump_core
[Public]
> -Original Message-
> From: Sunil Khatri
> Sent: Wednesday, May 15, 2024 8:18 AM
> To: Deucher, Alexander ; Koenig, Christian
>
> Cc: amd-gfx@lists.freedesktop.org; Khatri, Sunil
> Subject: [PATCH v3 1/4] drm/amdgpu: update the ip_dump to ipdump_core
>
> Update the memory pointer from ip_dump to ipdump_core to make it specific
> to core registers and rest other registers to be dumped in their respective
> memories.
>
> Signed-off-by: Sunil Khatri
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 +++---
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 109f471ff315..30d7f9c29478 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -435,7 +435,7 @@ struct amdgpu_gfx {
> boolmcbp; /* mid command buffer
> preemption */
>
> /* IP reg dump */
> - uint32_t*ip_dump;
> + uint32_t*ipdump_core;
I think this looks cleaner as ip_dump_core.
Alex
> };
>
> struct amdgpu_gfx_ras_reg_entry {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 953df202953a..f6d6a4b9802d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4603,9 +4603,9 @@ static void gfx_v10_0_alloc_dump_mem(struct
> amdgpu_device *adev)
> ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
> if (ptr == NULL) {
> DRM_ERROR("Failed to allocate memory for IP Dump\n");
> - adev->gfx.ip_dump = NULL;
> + adev->gfx.ipdump_core = NULL;
> } else {
> - adev->gfx.ip_dump = ptr;
> + adev->gfx.ipdump_core = ptr;
> }
> }
>
> @@ -4815,7 +4815,7 @@ static int gfx_v10_0_sw_fini(void *handle)
>
> gfx_v10_0_free_microcode(adev);
>
> - kfree(adev->gfx.ip_dump);
> + kfree(adev->gfx.ipdump_core);
>
> return 0;
> }
> @@ -9283,13 +9283,13 @@ static void gfx_v10_ip_print(void *handle, struct
> drm_printer *p)
> uint32_t i;
> uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>
> - if (!adev->gfx.ip_dump)
> + if (!adev->gfx.ipdump_core)
> return;
>
> for (i = 0; i < reg_count; i++)
> drm_printf(p, "%-50s \t 0x%08x\n",
> gc_reg_list_10_1[i].reg_name,
> -adev->gfx.ip_dump[i]);
> +adev->gfx.ipdump_core[i]);
> }
>
> static void gfx_v10_ip_dump(void *handle) @@ -9298,12 +9298,12 @@
> static void gfx_v10_ip_dump(void *handle)
> uint32_t i;
> uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>
> - if (!adev->gfx.ip_dump)
> + if (!adev->gfx.ipdump_core)
> return;
>
> amdgpu_gfx_off_ctrl(adev, false);
> for (i = 0; i < reg_count; i++)
> - adev->gfx.ip_dump[i] =
> RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
> + adev->gfx.ipdump_core[i] =
> +RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
> amdgpu_gfx_off_ctrl(adev, true);
> }
>
> --
> 2.34.1
RE: [PATCH v3 2/4] drm/amdgpu: Add support to dump gfx10 cp registers
[Public]
> -Original Message-
> From: Sunil Khatri
> Sent: Wednesday, May 15, 2024 8:18 AM
> To: Deucher, Alexander ; Koenig, Christian
>
> Cc: amd-gfx@lists.freedesktop.org; Khatri, Sunil
> Subject: [PATCH v3 2/4] drm/amdgpu: Add support to dump gfx10 cp
> registers
>
> add support to dump registers of all instances of cp registers in gfx10
>
> Signed-off-by: Sunil Khatri
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 117
> +++-
> 2 files changed, 114 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 30d7f9c29478..d96873c154ed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -436,6 +436,7 @@ struct amdgpu_gfx {
>
> /* IP reg dump */
> uint32_t*ipdump_core;
> + uint32_t*ipdump_cp;
I'd call this ip_dump_compute or ip_dump_compute_queues to align with that the
registers represent.
Alex
> };
>
> struct amdgpu_gfx_ras_reg_entry {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index f6d6a4b9802d..daf9a3571183 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -381,6 +381,49 @@ static const struct amdgpu_hwip_reg_entry
> gc_reg_list_10_1[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3) };
>
> +static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
> + /* compute registers */
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_HQD_PQ_DOORBELL_CONTROL),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS) };
> +
> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4,
> 0x, 0x00400014),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL,
> 0xfcff8fff, 0xf8000100), @@ -4595,10 +4638,11 @@ static int
> gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
>hw_prio, NULL);
> }
>
> -static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
> +static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
> {
> uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
> uint32_t *ptr;
> + uint32_t inst;
>
>
RE: [PATCH v3 3/4] drm/amdgpu: add support to dump gfx10 queue registers
[Public]
> -Original Message-
> From: Sunil Khatri
> Sent: Wednesday, May 15, 2024 8:18 AM
> To: Deucher, Alexander ; Koenig, Christian
>
> Cc: amd-gfx@lists.freedesktop.org; Khatri, Sunil
> Subject: [PATCH v3 3/4] drm/amdgpu: add support to dump gfx10 queue
> registers
>
> Add gfx queue register for all instances in ip dump for gfx10.
>
> Signed-off-by: Sunil Khatri
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 86
> +
> 2 files changed, 87 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index d96873c154ed..54232066cd3b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -437,6 +437,7 @@ struct amdgpu_gfx {
> /* IP reg dump */
> uint32_t*ipdump_core;
> uint32_t*ipdump_cp;
> + uint32_t*ipdump_gfx_queue;
I'd call this ip_dump_gfx or ip_dump_gfx_queues to better align with that it
stores.
> };
>
> struct amdgpu_gfx_ras_reg_entry {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index daf9a3571183..5b8132ecc039 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -424,6 +424,33 @@ static const struct amdgpu_hwip_reg_entry
> gc_cp_reg_list_10[] = {
> SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS) };
>
> +static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
> + /* gfx queue registers */
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_GFX_HQD_DEQUEUE_REQUEST),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_GFX_HQD_QUE_MGR_CONTROL),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
> + SOC15_REG_ENTRY_STR(GC, 0,
> mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI) };
> +
> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4,
> 0x, 0x00400014),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL,
> 0xfcff8fff, 0xf8000100), @@ -4664,6 +4691,19 @@ static void
> gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
> } else {
> adev->gfx.ipdump_cp = ptr;
> }
> +
> + /* Allocate memory for gfx cp queue registers for all the instances */
> + reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
> + inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
> + adev->gfx.me.num_queue_per_pipe;
> +
> + ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
> + if (ptr == NULL) {
> + DRM_ERROR("Failed to allocate memory for GFX CP IP
> Dump\n");
> + adev->gfx.ipdump_gfx_queue = NULL;
> + } else {
> + adev->gfx.ipdump_gfx_queue = ptr;
> + }
> }
>
> static int gfx_v10_0_sw_init(void *handle) @@ -4874,6 +4914,7 @@ static
> int gfx_v10_0_sw_fini(void *handle)
>
> kfree(adev->gfx.ipdump_core);
> kfree(adev->gfx.ipdump_cp);
> + kfree(adev->gfx.ipdump_gfx_queue);
>
> return 0;
> }
> @@ -9368,6 +9409,26 @@ static void gfx_v10_ip_print(void *handle, struct
> drm_printer *p)
> }
> }
> }
> +
> + /* print gfx queue registers for all instances */
> + if (!adev->gfx.ipdump_gfx_queue)
> + return;
> +
> + reg_
Re: [PATCH v5 10/10] Documentation/amdgpu: Add PM policy documentation
[AMD Official Use Only - AMD Internal Distribution Only]
I didn't have time to go through every patch in detail, but overall it looks
good to me. The series is:
Acked-by: Alex Deucher
From: Lazar, Lijo
Sent: Thursday, May 16, 2024 8:43 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal, Asad ; Ma, Le
Subject: [PATCH v5 10/10] Documentation/amdgpu: Add PM policy documentation
Add documentation about the newly added pm_policy node in sysfs.
Signed-off-by: Lijo Lazar
---
v5: Update documentation to reflect pm_policy nodes and sub nodes for each
policy type
Documentation/gpu/amdgpu/thermal.rst | 6
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 53
2 files changed, 59 insertions(+)
diff --git a/Documentation/gpu/amdgpu/thermal.rst
b/Documentation/gpu/amdgpu/thermal.rst
index 2f6166f81e6a..6d942b5c58f0 100644
--- a/Documentation/gpu/amdgpu/thermal.rst
+++ b/Documentation/gpu/amdgpu/thermal.rst
@@ -49,6 +49,12 @@ pp_power_profile_mode
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
:doc: pp_power_profile_mode
+pm_policy
+-
+
+.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
+ :doc: pm_policy
+
\*_busy_percent
---
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 5ff7783dfc43..3e5ffb83f398 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2220,6 +2220,59 @@ struct amdgpu_pm_policy_attr {
enum pp_pm_policy id;
};
+/**
+ * DOC: pm_policy
+ *
+ * Certain SOCs can support different power policies to optimize application
+ * performance. However, this policy is provided only at SOC level and not at a
+ * per-process level. This is useful especially when entire SOC is utilized for
+ * dedicated workload.
+ *
+ * The amdgpu driver provides a sysfs API for selecting the policy. Presently,
+ * only two types of policies are supported through this interface.
+ *
+ * Pstate Policy Selection - This is to select different Pstate profiles which
+ * decides clock/throttling preferences.
+ *
+ * XGMI PLPD Policy Selection - When multiple devices are connected over XGMI,
+ * this helps to select policy to be applied for per link power down.
+ *
+ * The list of available policies and policy levels vary between SOCs. They can
+ * be viewed under pm_policy node directory. If SOC doesn't support any policy,
+ * this node won't be available. The different policies supported will be
+ * available as separate nodes under pm_policy.
+ *
+ * cat /sys/bus/pci/devices/.../pm_policy/
+ *
+ * Reading the policy file shows the different levels supported. The level
which
+ * is applied presently is denoted by * (asterisk). E.g.,
+ *
+ * .. code-block:: console
+ *
+ * cat /sys/bus/pci/devices/.../pm_policy/soc_pstate
+ * 0 : soc_pstate_default
+ * 1 : soc_pstate_0
+ * 2 : soc_pstate_1*
+ * 3 : soc_pstate_2
+ *
+ * cat /sys/bus/pci/devices/.../pm_policy/xgmi_plpd
+ * 0 : plpd_disallow
+ * 1 : plpd_default
+ * 2 : plpd_optimized*
+ *
+ * To apply a specific policy
+ *
+ * "echo > /sys/bus/pci/devices/.../pm_policy/"
+ *
+ * For the levels listed in the example above, to select "plpd_optimized" for
+ * XGMI and "soc_pstate_2" for soc pstate policy -
+ *
+ * .. code-block:: console
+ *
+ * echo "2" > /sys/bus/pci/devices/.../pm_policy/xgmi_plpd
+ * echo "3" > /sys/bus/pci/devices/.../pm_policy/soc_pstate
+ *
+ */
static ssize_t amdgpu_get_pm_policy_attr(struct device *dev,
struct device_attribute *attr,
char *buf)
--
2.25.1
RE: Request for Information on the current drm radeon Atomic Mode Settings
[Public] The radeon driver does not support atomic modesetting. It was largely written before atomic existed. Converting it to atomic would be a substantial undertaking that would potentially regress a lot of really old chips. Radeon supports hardware that is 25+ years old at this point. Alex From: Mauro Rossi Sent: Friday, May 17, 2024 7:28 AM To: amd-gfx list Cc: Deucher, Alexander ; l...@kernel.org; Michael Goffioul ; Jon West ; youling 257 Subject: Re: Request for Information on the current drm radeon Atomic Mode Settings Cc: correct email address of Lee Jones, just For Your Information Updated [2] link URL because HWC3 in Celadon was moved to project Celadon drm-hwcomposer local branch on yesterday The request for information on drm radeon atomic modesettings is confirmed Mauro On Fri, May 17, 2024 at 8:31 AM Mauro Rossi mailto:issor.or...@gmail.com>> wrote: Hi all, with Android 14 QPR2 there were substantial changes in graphic stack's Android HAL (Hardware Abstraction Layer), essentially it became mandatory that hwcomposer HAL module supports AIDL Android Interface Definition Language, at the moment drm_hwcomposer does not support AIDL [1] Project Celadon has an HWC3 AIDL implemented [2], as a patch on top of hardware/interface AOSP project, there is an opportunity to use it also for non Intel GPUs. drm amdpu in kernel already supports ADF Atomic Display Framework, I would like to ask the current status of Atomic Display Framework in drm radeon, because Atomic Mode Settings seems partially implemented since 2010-2012, but ADF capabilities are not exposed to user space. Please, I also need some basic (high level) information about the outstanding changes that would be required to support it, in order to be able to use HWC3 -> drm_hwcomposer with r600, r300 chipsets. Thanks for your informations Mauro android-x86 team/Bliss-OS community [1] https://gitlab.freedesktop.org/drm-hwcomposer/drm-hwcomposer/-/issues/80 [2] https://github.com/projectceladon/vendor-intel-utils/blob/master/aosp_diff/preliminary/hardware/interfaces/11_0001-Enable-graphics.composer3-AIDL-HAL-service.patch [2] https://github.com/projectceladon/drm-hwcomposer/commit/1160cdfb53daebf59f3704ec9586c66385e63747
Re: [PATCH 2/4 V2] drm/amd/pm: fix unsigned value asic_type compared against
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Alex Deucher
From: Jesse Zhang
Sent: Tuesday, May 21, 2024 3:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Huang, Tim ; Zhang, Jesse(Jie)
; Zhang, Jesse(Jie)
Subject: [PATCH 2/4 V2] drm/amd/pm: fix unsigned value asic_type compared
against
Enum asic_type always greater than or equal CHIP_TAHITI.
Signed-off-by: Jesse Zhang
Suggested-by: Tim Huang
---
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index f245fc0bc6d3..68ac01a8bc3a 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -7928,12 +7928,8 @@ static void si_dpm_print_power_state(void *handle,
DRM_INFO("\tuvdvclk: %d dclk: %d\n", rps->vclk, rps->dclk);
for (i = 0; i < ps->performance_level_count; i++) {
pl = &ps->performance_levels[i];
- if (adev->asic_type >= CHIP_TAHITI)
- DRM_INFO("\t\tpower level %dsclk: %u mclk: %u vddc:
%u vddci: %u pcie gen: %u\n",
-i, pl->sclk, pl->mclk, pl->vddc, pl->vddci,
pl->pcie_gen + 1);
- else
- DRM_INFO("\t\tpower level %dsclk: %u mclk: %u vddc:
%u vddci: %u\n",
-i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
+ DRM_INFO("\t\tpower level %dsclk: %u mclk: %u vddc: %u
vddci: %u pcie gen: %u\n",
+i, pl->sclk, pl->mclk, pl->vddc, pl->vddci,
pl->pcie_gen + 1);
}
amdgpu_dpm_print_ps_status(adev, rps);
}
--
2.25.1
Re: [PATCH 3/4 V3] drm/amdgpu: fix invadate operation for pg_flags
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Alex Deucher
From: Jesse Zhang
Sent: Tuesday, May 21, 2024 3:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Huang, Tim ; Zhang, Jesse(Jie)
; Zhang, Jesse(Jie)
Subject: [PATCH 3/4 V3] drm/amdgpu: fix invadate operation for pg_flags
Since the type of pg_flags is u32, adev->pg_flags >> 16 >> 16 is 0
regardless of the values of its operands.
So removing the operations upper_32_bits and lower_32_bits.
Signed-off-by: Jesse Zhang
Suggested-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index ac0ba8b8c1aa..0e1a11b6b989 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -918,7 +918,7 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file
*f, char __user *buf,
/* rev==1 */
config[no_regs++] = adev->rev_id;
- config[no_regs++] = lower_32_bits(adev->pg_flags);
+ config[no_regs++] = adev->pg_flags;
config[no_regs++] = lower_32_bits(adev->cg_flags);
/* rev==2 */
@@ -935,7 +935,7 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file
*f, char __user *buf,
config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;
/* rev==5 PG/CG flag upper 32bit */
- config[no_regs++] = upper_32_bits(adev->pg_flags);
+ config[no_regs++] = 0;
config[no_regs++] = upper_32_bits(adev->cg_flags);
while (size && (*pos < no_regs * 4)) {
--
2.25.1
RE: [PATCH] MAINTAINERS: update email for Evan Quan
[Public] > -Original Message- > From: amd-gfx On Behalf Of > Wolfram Sang > Sent: Wednesday, May 29, 2024 7:46 AM > To: linux-ker...@vger.kernel.org > Cc: Wolfram Sang ; Evan Quan > ; amd-gfx@lists.freedesktop.org > Subject: [PATCH] MAINTAINERS: update email for Evan Quan > > The old email address bounced. I found the newer one in recent git history, > update MAINTAINERS accordingly. > > Cc: Evan Quan > Signed-off-by: Wolfram Sang Evan no longer maintains the SWSMU code, it should be changed to Kenneth and Jun (CCed). Thanks! Alex > --- > > Against v6.10-rc1. Still needs ack from Evan Quan > > MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index d6c90161c7bf..b2fd2a19277e 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1092,7 +1092,7 @@ F: Documentation/ABI/testing/sysfs-amd-pmf > F: drivers/platform/x86/amd/pmf/ > > AMD POWERPLAY AND SWSMU > -M: Evan Quan > +M: Evan Quan > L: amd-gfx@lists.freedesktop.org > S: Supported > T: git https://gitlab.freedesktop.org/agd5f/linux.git > -- > 2.43.0
RE: [PATCH 04/18] drm/amdgpu: refine mes firmware loading
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Wang, Yang(Kevin)
> Sent: Friday, May 31, 2024 2:53 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
>
> Subject: [PATCH 04/18] drm/amdgpu: refine mes firmware loading
>
> refine mes firmware loading
>
> Signed-off-by: Yang Wang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 62edf6328566..9194a53b7c14 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -1528,11 +1528,9 @@ int amdgpu_mes_init_microcode(struct
> amdgpu_device *adev, int pipe)
>
> r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], fw_name);
> if (r && need_retry && pipe == AMDGPU_MES_SCHED_PIPE) {
> - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",
> - ucode_prefix);
> - DRM_INFO("try to fall back to %s\n", fw_name);
> + DRM_INFO("try to fall back to %s_mes.bin\n", ucode_prefix);
While you are here, can you convert the DRM_INFO() macros to dev_info() instead
so we can get better output on multi-GPU systems?
Alex
> r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe],
> - fw_name);
> + "amdgpu/%s_mes.bin",
> ucode_prefix);
> }
>
> if (r)
> --
> 2.34.1
RE: [PATCH] Revert "drm/amdgpu: init iommu after amdkfd device init"
[AMD Official Use Only - AMD Internal Distribution Only] > -Original Message- > From: Kuehling, Felix > Sent: Tuesday, June 4, 2024 2:25 PM > To: Armin Wolf ; Deucher, Alexander > ; Koenig, Christian > ; Pan, Xinhui ; > gre...@linuxfoundation.org; sas...@kernel.org > Cc: sta...@vger.kernel.org; bkau...@gmail.com; Zhang, Yifan > ; Liang, Prike ; dri- > de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH] Revert "drm/amdgpu: init iommu after amdkfd device > init" > > > On 2024-06-03 18:19, Armin Wolf wrote: > > Am 23.05.24 um 19:30 schrieb Armin Wolf: > > > >> This reverts commit 56b522f4668167096a50c39446d6263c96219f5f. > >> > >> A user reported that this commit breaks the integrated gpu of his > >> notebook, causing a black screen. He was able to bisect the > >> problematic commit and verified that by reverting it the notebook works > again. > >> He also confirmed that kernel 6.8.1 also works on his device, so the > >> upstream commit itself seems to be ok. > >> > >> An amdgpu developer (Alex Deucher) confirmed that this patch should > >> have never been ported to 5.15 in the first place, so revert this > >> commit from the 5.15 stable series. > > > > Hi, > > > > what is the status of this? > > Which branch is this for? This patch won't apply to anything after Linux 6.5. It's applicable to 5.15 stable only. The original patch caused a regression on 5.15 so probably should not have been applied there. Alex > Support for IOMMUv2 was removed from amdgpu in Linux 6.6 by: > > commit c99a2e7ae291e5b19b60443eb6397320ef9e8571 > Author: Alex Deucher > Date: Fri Jul 28 12:20:12 2023 -0400 > > drm/amdkfd: drop IOMMUv2 support > > Now that we use the dGPU path for all APUs, drop the > IOMMUv2 support. > > v2: drop the now unused queue manager functions for gfx7/8 APUs > > Reviewed-by: Felix Kuehling > Acked-by: Christian König > Tested-by: Mike Lothian > Signed-off-by: Alex Deucher > > Regards, >Felix > > > > > > Armin Wolf > > > >> > >> Reported-by: Barry Kauler > >> Signed-off-by: Armin Wolf > >> --- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 > >> 1 file changed, 4 insertions(+), 4 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > >> index 222a1d9ecf16..5f6c32ec674d 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > >> @@ -2487,6 +2487,10 @@ static int amdgpu_device_ip_init(struct > >> amdgpu_device *adev) > >> if (r) > >> goto init_failed; > >> > >> +r = amdgpu_amdkfd_resume_iommu(adev); > >> +if (r) > >> +goto init_failed; > >> + > >> r = amdgpu_device_ip_hw_init_phase1(adev); > >> if (r) > >> goto init_failed; > >> @@ -2525,10 +2529,6 @@ static int amdgpu_device_ip_init(struct > >> amdgpu_device *adev) > >> if (!adev->gmc.xgmi.pending_reset) > >> amdgpu_amdkfd_device_init(adev); > >> > >> -r = amdgpu_amdkfd_resume_iommu(adev); > >> -if (r) > >> -goto init_failed; > >> - > >> amdgpu_fru_get_product_info(adev); > >> > >> init_failed: > >> -- > >> 2.39.2 > >> > >>
RE: [PATCH 1/2] drm/amd/display: use pre-allocated temp structure for bounding box
[Public]
> -Original Message-
> From: Arnd Bergmann
> Sent: Tuesday, June 4, 2024 3:43 PM
> To: Deucher, Alexander ; amd-
> g...@lists.freedesktop.org
> Cc: Zhang, George ; Mahfooz, Hamza
> ; Wentland, Harry
> ; Li, Sun peng (Leo) ;
> Siqueira, Rodrigo ; Aberback, Joshua
>
> Subject: Re: [PATCH 1/2] drm/amd/display: use pre-allocated temp structure
> for bounding box
>
> On Tue, Jun 4, 2024, at 20:06, Alex Deucher wrote:
> > This mirrors what the driver does for older DCN generations.
> >
> > Should fix:
> >
> > BUG: sleeping function called from invalid context at
> > include/linux/sched/mm.h:306
> > in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 449, name:
> > kworker/u64:8
> > preempt_count: 2, expected: 0
> > RCU nest depth: 0, expected: 0
> > Preemption disabled at:
> > c0ce1580>] dc_fpu_begin+0x30/0xd0 [amdgpu]
> > CPU: 5 PID: 449 Comm: kworker/u64:8 Tainted: GW 6.8.0+
> > #35
> > Hardware name: System manufacturer System Product Name/ROG STRIX
> > X570-E GAMING WIFI II, BIOS 4204 02/24/2022
> > Workqueue: events_unbound async_run_entry_fn
> >
> > Fixes: 88c61827cedc ("drm/amd/display: dynamically allocate
> > dml2_configuration_options structures")
> > Tested-by: George Zhang
> > Suggested-by: Hamza Mahfooz
> > Signed-off-by: Alex Deucher
> > Cc: George Zhang
> > Cc: Arnd Bergmann
> > Cc: harry.wentl...@amd.com
> > Cc: sunpeng...@amd.com
> > Cc: rodrigo.sique...@amd.com
>
> That looks nicer than all the other suggestions, thanks!
>
> Acked-by: Arnd Bergmann
>
> One part sticks out though:
>
> > @@ -2027,7 +2025,7 @@ static void
> dcn32_update_bw_bounding_box(struct
> > dc *dc, struct clk_bw_params *bw
> >
> > DC_FP_END();
> >
> > - kfree(dml2_opt);
> > + memcpy(&dc->dml2_options, dml2_opt, sizeof(dc->dml2_options));
> > }
>
> The driver did not copy the data back before, so this is a change in
> behavior. Is
> that intentional or a mistake?
Yes, sorry, was on autopilot based on the patch Hamza had pointed me to. Will
drop in v2.
Thanks,
Alex
>
> If the intention is to have the data copied back into
> dc->dml2_options in the end, wouldn't it be easier to
> just pass a pointer as in the old version before commit
> e779f4587f61 ("drm/amd/display: Add handling for DC power mode")?
>
> Arnd
Re: [PATCH] drm/amd: Explicitly check for GFXOFF to be enabled for s0ix
[Public] Reviewed-by: Alex Deucher From: amd-gfx on behalf of Mario Limonciello Sent: Thursday, November 9, 2023 11:27 AM To: amd-gfx@lists.freedesktop.org Cc: Limonciello, Mario Subject: [PATCH] drm/amd: Explicitly check for GFXOFF to be enabled for s0ix If a user has disabled GFXOFF this may cause problems for the suspend sequence. Ensure that it is enabled in amdgpu_acpi_is_s0ix_active(). The system won't reach the deepest state but it also won't hang. Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index d62e49758635..e550067e5c5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -1497,6 +1497,9 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) if (adev->asic_type < CHIP_RAVEN) return false; + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) + return false; + /* * If ACPI_FADT_LOW_POWER_S0 is not set in the FADT, it is generally * risky to do any special firmware-related preparations for entering -- 2.34.1
RE: [PATCH 1/2] drm/amdgpu: correct the amdgpu runtime dereference usage count
[Public]
> -Original Message-
> From: Liang, Prike
> Sent: Thursday, November 9, 2023 2:37 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
>
> Subject: [PATCH 1/2] drm/amdgpu: correct the amdgpu runtime dereference
> usage count
>
> Fix the amdgpu runpm dereference usage count.
>
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> index a53f436fa9f1..f6e5d9f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> @@ -1992,7 +1992,7 @@ static int amdgpu_debugfs_sclk_set(void *data,
> u64 val)
>
> ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK,
> (uint32_t)val, (uint32_t)val);
> if (ret)
> - ret = -EINVAL;
> + goto out;
I think this hunk can be dropped. It doesn't really change anything. Or you
could just drop the whole ret check since we just return ret at the end anyway.
Not sure if changing the error code is important here or not.
>
> out:
> pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 0cacd0b9f8be..ff1f42ae6d8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -346,6 +346,7 @@ int amdgpu_display_crtc_set_config(struct
> drm_mode_set *set,
> if (!active && adev->have_disp_power_ref) {
> pm_runtime_put_autosuspend(dev->dev);
> adev->have_disp_power_ref = false;
> + return ret;
> }
I think it would be cleaner to just drop the runtime_put above and update the
comment. We'll just fall through to the end of the function.
Alex
>
> out:
> --
> 2.34.1
RE: [PATCH 2/2] drm/amdgpu: add amdgpu runpm usage trace for separate funcs
[Public]
> -Original Message-
> From: Liang, Prike
> Sent: Thursday, November 9, 2023 2:37 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
>
> Subject: [PATCH 2/2] drm/amdgpu: add amdgpu runpm usage trace for
> separate funcs
>
> Add trace for amdgpu runpm separate funcs usage and this will help
> debugging on the case of runpm usage missed to dereference.
> In the normal case the runpm usage count referred by one kind of
> functionality pairwise and usage should be changed from 1 to 0, otherwise
> there will be an issue in the amdgpu runpm usage dereference.
>
> Signed-off-by: Prike Liang
Looks good. Not sure if you want to add tracepoints to the other call sites as
well. These are probably the trickiest however.
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 4
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 7 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 15 +++
> 3 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> index e7e87a3b2601..decbbe3d4f06 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> @@ -42,6 +42,7 @@
> #include
> #include
> #include
> +#include "amdgpu_trace.h"
>
> /**
> * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation @@ -
> 63,6 +64,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
> attach->peer2peer = false;
>
> r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
> + trace_amdgpu_runpm_reference_dumps(1, __func__);
> if (r < 0)
> goto out;
>
> @@ -70,6 +72,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf
> *dmabuf,
>
> out:
> pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + trace_amdgpu_runpm_reference_dumps(0, __func__);
> return r;
> }
>
> @@ -90,6 +93,7 @@ static void amdgpu_dma_buf_detach(struct dma_buf
> *dmabuf,
>
> pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
> pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + trace_amdgpu_runpm_reference_dumps(0, __func__);
> }
>
> /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> index 709a2c1b9d63..1026a9fa0c0f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> @@ -183,6 +183,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring,
> struct dma_fence **f, struct amd
> amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
> seq, flags | AMDGPU_FENCE_FLAG_INT);
> pm_runtime_get_noresume(adev_to_drm(adev)->dev);
> + trace_amdgpu_runpm_reference_dumps(1, __func__);
> ptr = &ring->fence_drv.fences[seq & ring-
> >fence_drv.num_fences_mask];
> if (unlikely(rcu_dereference_protected(*ptr, 1))) {
> struct dma_fence *old;
> @@ -286,8 +287,11 @@ bool amdgpu_fence_process(struct amdgpu_ring
> *ring)
> seq != ring->fence_drv.sync_seq)
> amdgpu_fence_schedule_fallback(ring);
>
> - if (unlikely(seq == last_seq))
> + if (unlikely(seq == last_seq)) {
> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + trace_amdgpu_runpm_reference_dumps(0, __func__);
> return false;
> + }
>
> last_seq &= drv->num_fences_mask;
> seq &= drv->num_fences_mask;
> @@ -310,6 +314,7 @@ bool amdgpu_fence_process(struct amdgpu_ring
> *ring)
> dma_fence_put(fence);
> pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
> pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + trace_amdgpu_runpm_reference_dumps(0, __func__);
> } while (last_seq != seq);
>
> return true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> index 2fd1bfb35916..5d4792645540 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> @@ -554,6 +554,21 @@ TRACE_EVENT(amdgpu_reset_reg_dumps,
> __entry->value)
> );
>
> +TRACE_EVENT(amdgpu_runpm_reference_dumps,
> + TP_PROTO(uint32_t index, const char *func),
> + TP_ARGS(index, func),
> + TP_STRUCT__entry(
> + __field(uint32_t, index)
> + __string(func, func)
> + ),
> + TP_fast_assign(
> +__entry->index = index;
> +__assign_str(func, func);
> +),
> + TP_printk("amdgpu runpm reference dump 0x%d: 0x%s\n",
> + __entry->index,
> + __get_str(func))
> +);
> #undef AMDGPU_JOB_GET_TIMELINE_NAME
> #endif
>
> --
> 2.34.1
Re: [PATCH] drm/amdgpu: exclude domain start when calucales offset for AGP aperture BOs
[Public]
It happens in amdgpu_gmc_agp_addr() which is called from
amdgpu_ttm_alloc_gart().
Alex
From: Koenig, Christian
Sent: Friday, November 10, 2023 9:14 AM
To: Zhang, Yifan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Jesse(Jie)
Subject: Re: [PATCH] drm/amdgpu: exclude domain start when calucales offset for
AGP aperture BOs
Am 10.11.23 um 13:52 schrieb Yifan Zhang:
> For BOs in AGP aperture, tbo.resource->start includes AGP aperture start.
Well big NAK to that. tbo.resource->start should never ever include the
AGP aperture start in the first place.
How did that happen?
Regards,
Christian.
> Don't add it again in amdgpu_bo_gpu_offset. This issue was mitigated due to
> GART aperture start was 0 until this patch ("a013c94d5aca drm/amdgpu/gmc11:
> set gart placement GC11") changes GART start to a non-zero value.
>
> Reported-by: Jesse Zhang
> Signed-off-by: Yifan Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c| 7 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 --
> 3 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 5f71414190e9..00e940eb69ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -169,6 +169,13 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev,
> void *cpu_pt_addr,
>return 0;
> }
>
> +bool bo_in_agp_aperture(struct amdgpu_bo *bo)
> +{
> + struct ttm_buffer_object *tbo = &(bo->tbo);
> + struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
> +
> + return (tbo->resource->start << PAGE_SHIFT) > adev->gmc.agp_start;
> +}
> /**
>* amdgpu_gmc_agp_addr - return the address in the AGP address space
>*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index e699d1ca8deb..448dc08e83de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -393,6 +393,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev,
> void *cpu_pt_addr,
>uint64_t flags);
> uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
> uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
> +bool bo_in_agp_aperture(struct amdgpu_bo *bo);
> void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct
> amdgpu_gmc *mc);
> void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc
> *mc,
> u64 base);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index cef920a93924..91a011d63ab4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -39,6 +39,7 @@
> #include "amdgpu.h"
> #include "amdgpu_trace.h"
> #include "amdgpu_amdkfd.h"
> +#include "amdgpu_gmc.h"
>
> /**
>* DOC: amdgpu_object
> @@ -1529,8 +1530,13 @@ u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
>struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>uint64_t offset;
>
> - offset = (bo->tbo.resource->start << PAGE_SHIFT) +
> - amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
> + /* tbo.resource->start includes agp_start for AGP BOs */
> + if (bo_in_agp_aperture(bo)) {
> + offset = (bo->tbo.resource->start << PAGE_SHIFT);
> + } else {
> + offset = (bo->tbo.resource->start << PAGE_SHIFT) +
> + amdgpu_ttm_domain_start(adev,
> bo->tbo.resource->mem_type);
> + }
>
>return amdgpu_gmc_sign_extend(offset);
> }
Re: [PATCH] drm/amdgpu: exclude domain start when calucales offset for AGP aperture BOs
[Public]
I think the proper fix is probably to just drop the addition of agp_start in
amdgpu_gmc_agp_addr().
Alex
From: Deucher, Alexander
Sent: Friday, November 10, 2023 9:16 AM
To: Koenig, Christian ; Zhang, Yifan
; amd-gfx@lists.freedesktop.org
Cc: Zhang, Jesse(Jie)
Subject: Re: [PATCH] drm/amdgpu: exclude domain start when calucales offset for
AGP aperture BOs
It happens in amdgpu_gmc_agp_addr() which is called from
amdgpu_ttm_alloc_gart().
Alex
From: Koenig, Christian
Sent: Friday, November 10, 2023 9:14 AM
To: Zhang, Yifan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Jesse(Jie)
Subject: Re: [PATCH] drm/amdgpu: exclude domain start when calucales offset for
AGP aperture BOs
Am 10.11.23 um 13:52 schrieb Yifan Zhang:
> For BOs in AGP aperture, tbo.resource->start includes AGP aperture start.
Well big NAK to that. tbo.resource->start should never ever include the
AGP aperture start in the first place.
How did that happen?
Regards,
Christian.
> Don't add it again in amdgpu_bo_gpu_offset. This issue was mitigated due to
> GART aperture start was 0 until this patch ("a013c94d5aca drm/amdgpu/gmc11:
> set gart placement GC11") changes GART start to a non-zero value.
>
> Reported-by: Jesse Zhang
> Signed-off-by: Yifan Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c| 7 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 --
> 3 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 5f71414190e9..00e940eb69ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -169,6 +169,13 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev,
> void *cpu_pt_addr,
>return 0;
> }
>
> +bool bo_in_agp_aperture(struct amdgpu_bo *bo)
> +{
> + struct ttm_buffer_object *tbo = &(bo->tbo);
> + struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
> +
> + return (tbo->resource->start << PAGE_SHIFT) > adev->gmc.agp_start;
> +}
> /**
>* amdgpu_gmc_agp_addr - return the address in the AGP address space
>*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index e699d1ca8deb..448dc08e83de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -393,6 +393,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev,
> void *cpu_pt_addr,
>uint64_t flags);
> uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
> uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
> +bool bo_in_agp_aperture(struct amdgpu_bo *bo);
> void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct
> amdgpu_gmc *mc);
> void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc
> *mc,
> u64 base);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index cef920a93924..91a011d63ab4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -39,6 +39,7 @@
> #include "amdgpu.h"
> #include "amdgpu_trace.h"
> #include "amdgpu_amdkfd.h"
> +#include "amdgpu_gmc.h"
>
> /**
>* DOC: amdgpu_object
> @@ -1529,8 +1530,13 @@ u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
>struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>uint64_t offset;
>
> - offset = (bo->tbo.resource->start << PAGE_SHIFT) +
> - amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
> + /* tbo.resource->start includes agp_start for AGP BOs */
> + if (bo_in_agp_aperture(bo)) {
> + offset = (bo->tbo.resource->start << PAGE_SHIFT);
> + } else {
> + offset = (bo->tbo.resource->start << PAGE_SHIFT) +
> + amdgpu_ttm_domain_start(adev,
> bo->tbo.resource->mem_type);
> + }
>
>return amdgpu_gmc_sign_extend(offset);
> }
Re: [PATCH] drm/amdgpu: exclude domain start when calucales offset for AGP aperture BOs
[Public]
In that case, how do we know we can skip the gart setup in
amdgpu_ttm_alloc_gart()?
Alex
From: Koenig, Christian
Sent: Friday, November 10, 2023 9:20 AM
To: Deucher, Alexander ; Zhang, Yifan
; amd-gfx@lists.freedesktop.org
Cc: Zhang, Jesse(Jie)
Subject: Re: [PATCH] drm/amdgpu: exclude domain start when calucales offset for
AGP aperture BOs
No, that's broken as well.
The problem is in amdgpu_ttm_alloc_gart():
if (addr != AMDGPU_BO_INVALID_OFFSET) {
bo->resource->start = addr >> PAGE_SHIFT;
return 0;
}
bo->resource->start is relative to the GART address, so we can't assign the AGP
address here in the first place.
What we need to do is to drop this and call amdgpu_gmc_agp_addr() from
amdgpu_bo_gpu_offset_no_check().
Regards,
Christian.
Am 10.11.23 um 15:17 schrieb Deucher, Alexander:
[Public]
I think the proper fix is probably to just drop the addition of agp_start in
amdgpu_gmc_agp_addr().
Alex
____________
From: Deucher, Alexander
<mailto:alexander.deuc...@amd.com>
Sent: Friday, November 10, 2023 9:16 AM
To: Koenig, Christian
<mailto:christian.koe...@amd.com>; Zhang, Yifan
<mailto:yifan1.zh...@amd.com>;
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
<mailto:amd-gfx@lists.freedesktop.org>
Cc: Zhang, Jesse(Jie) <mailto:jesse.zh...@amd.com>
Subject: Re: [PATCH] drm/amdgpu: exclude domain start when calucales offset for
AGP aperture BOs
It happens in amdgpu_gmc_agp_addr() which is called from
amdgpu_ttm_alloc_gart().
Alex
From: Koenig, Christian
<mailto:christian.koe...@amd.com>
Sent: Friday, November 10, 2023 9:14 AM
To: Zhang, Yifan <mailto:yifan1.zh...@amd.com>;
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
<mailto:amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander
<mailto:alexander.deuc...@amd.com>; Zhang,
Jesse(Jie) <mailto:jesse.zh...@amd.com>
Subject: Re: [PATCH] drm/amdgpu: exclude domain start when calucales offset for
AGP aperture BOs
Am 10.11.23 um 13:52 schrieb Yifan Zhang:
> For BOs in AGP aperture, tbo.resource->start includes AGP aperture start.
Well big NAK to that. tbo.resource->start should never ever include the
AGP aperture start in the first place.
How did that happen?
Regards,
Christian.
> Don't add it again in amdgpu_bo_gpu_offset. This issue was mitigated due to
> GART aperture start was 0 until this patch ("a013c94d5aca drm/amdgpu/gmc11:
> set gart placement GC11") changes GART start to a non-zero value.
>
> Reported-by: Jesse Zhang <mailto:jesse.zh...@amd.com>
> Signed-off-by: Yifan Zhang <mailto:yifan1.zh...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c| 7 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 --
> 3 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 5f71414190e9..00e940eb69ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -169,6 +169,13 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev,
> void *cpu_pt_addr,
>return 0;
> }
>
> +bool bo_in_agp_aperture(struct amdgpu_bo *bo)
> +{
> + struct ttm_buffer_object *tbo = &(bo->tbo);
> + struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
> +
> + return (tbo->resource->start << PAGE_SHIFT) > adev->gmc.agp_start;
> +}
> /**
>* amdgpu_gmc_agp_addr - return the address in the AGP address space
>*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index e699d1ca8deb..448dc08e83de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -393,6 +393,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev,
> void *cpu_pt_addr,
>uint64_t flags);
> uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
> uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
> +bool bo_in_agp_aperture(struct amdgpu_bo *bo);
> void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct
> amdgpu_gmc *mc);
> void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc
> *mc,
> u64 base);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index cef920a93924..91a011d63ab4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgp
Re: [PATCH v2] drm/amdgpu: correct the amdgpu runtime dereference usage count
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: Liang, Prike
Sent: Thursday, November 16, 2023 10:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Li, Sun peng (Leo)
; Wentland, Harry ; Feng, Kenneth
; Liang, Prike
Subject: [PATCH v2] drm/amdgpu: correct the amdgpu runtime dereference usage
count
Fix the amdgpu runpm dereference usage count.
Signed-off-by: Prike Liang
---
v2: remove goto clause and return directly(Alex)
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 0cacd0b9f8be..b8fbe97efe1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -340,14 +340,11 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set
*set,
adev->have_disp_power_ref = true;
return ret;
}
- /* if we have no active crtcs, then drop the power ref
-* we got before
+ /* if we have no active crtcs, then go to
+* drop the power ref we got before
*/
- if (!active && adev->have_disp_power_ref) {
- pm_runtime_put_autosuspend(dev->dev);
+ if (!active && adev->have_disp_power_ref)
adev->have_disp_power_ref = false;
- }
-
out:
/* drop the power reference we got coming in here */
pm_runtime_put_autosuspend(dev->dev);
--
2.34.1
RE: [PATCH] drm/amd/swsmu: update smu v14_0_0 driver if version and metrics table
[Public]
> -Original Message-
> From: Ma, Li
> Sent: Thursday, November 23, 2023 5:07 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Zhang, Yifan ; Yu,
> Lang ; Ma, Li
> Subject: [PATCH] drm/amd/swsmu: update smu v14_0_0 driver if version and
> metrics table
>
> Increment the driver if version and add new mems to the mertics table.
>
> Signed-off-by: Li Ma
> ---
> .../gpu/drm/amd/include/kgd_pp_interface.h| 17
> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 10 +++
> .../inc/pmfw_if/smu14_driver_if_v14_0_0.h | 77 +++
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 46 ++-
> 4 files changed, 115 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 8ebba87f4289..eaea1c65e526 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -1086,6 +1086,10 @@ struct gpu_metrics_v3_0 {
> uint16_taverage_dram_reads;
> /* time filtered DRAM write bandwidth [MB/sec] */
> uint16_taverage_dram_writes;
> + /* time filtered IPU read bandwidth [MB/sec] */
> + uint16_taverage_ipu_reads;
> + /* time filtered IPU write bandwidth [MB/sec] */
> + uint16_taverage_ipu_writes;
>
> /* Driver attached timestamp (in ns) */
> uint64_tsystem_clock_counter;
> @@ -1105,6 +1109,8 @@ struct gpu_metrics_v3_0 {
> uint32_taverage_all_core_power;
> /* calculated core power [mW] */
> uint16_taverage_core_power[16];
> + /* time filtered total system power [mW] */
> + uint16_taverage_sys_power;
> /* maximum IRM defined STAPM power limit [mW] */
> uint16_tstapm_power_limit;
> /* time filtered STAPM power limit [mW] */ @@ -1117,6 +1123,8
> @@ struct gpu_metrics_v3_0 {
> uint16_taverage_ipuclk_frequency;
> uint16_taverage_fclk_frequency;
> uint16_taverage_vclk_frequency;
> + uint16_taverage_uclk_frequency;
> + uint16_taverage_mpipu_frequency;
>
> /* Current clocks */
> /* target core frequency [MHz] */
> @@ -1126,6 +1134,15 @@ struct gpu_metrics_v3_0 {
> /* GFXCLK frequency limit enforced on GFX [MHz] */
> uint16_tcurrent_gfx_maxfreq;
>
> + /* Throttle Residency (ASIC dependent) */
> + uint32_t throttle_residency_prochot;
> + uint32_t throttle_residency_spl;
> + uint32_t throttle_residency_fppt;
> + uint32_t throttle_residency_sppt;
> + uint32_t throttle_residency_thm_core;
> + uint32_t throttle_residency_thm_gfx;
> + uint32_t throttle_residency_thm_soc;
> +
> /* Metrics table alpha filter time constant [us] */
> uint32_ttime_filter_alphavalue;
> };
Is anything else besides smu14 using v3 of this struct? If so, we can't change
the layout otherwise it will break existing tools. If so, bump the version
minor and append the new items to the end.
Alex
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> index c125253df20b..c2265e027ca8 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> @@ -1418,6 +1418,16 @@ typedef enum {
> METRICS_PCIE_WIDTH,
> METRICS_CURR_FANPWM,
> METRICS_CURR_SOCKETPOWER,
> + METRICS_AVERAGE_VPECLK,
> + METRICS_AVERAGE_IPUCLK,
> + METRICS_AVERAGE_MPIPUCLK,
> + METRICS_THROTTLER_RESIDENCY_PROCHOT,
> + METRICS_THROTTLER_RESIDENCY_SPL,
> + METRICS_THROTTLER_RESIDENCY_FPPT,
> + METRICS_THROTTLER_RESIDENCY_SPPT,
> + METRICS_THROTTLER_RESIDENCY_THM_CORE,
> + METRICS_THROTTLER_RESIDENCY_THM_GFX,
> + METRICS_THROTTLER_RESIDENCY_THM_SOC,
> } MetricsMember_t;
>
> enum smu_cmn2asic_mapping_type {
> diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0
> .h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0
> .h
> index 22f88842a7fd..8f42771e1f0a 100644
> ---
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0
> .h
> +++
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0
> .h
> @@ -27,7 +27,7 @@
> // *** IMPORTANT ***
> // SMU TEAM: Always
Re: [PATCH] drm/amdgpu: disable MCBP by default
[Public] Acked-by: Alex Deucher From: amd-gfx on behalf of jiadong@amd.com Sent: Thursday, November 30, 2023 7:57 PM To: amd-gfx@lists.freedesktop.org Cc: Zhu, Jiadong Subject: [PATCH] drm/amdgpu: disable MCBP by default From: Jiadong Zhu Disable MCBP(mid command buffer preemption) by default as old Mesa hangs with it. We shall not enable the feature that breaks old usermode driver. Signed-off-by: Jiadong Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 21b8a8f2b622..280fcad9ce93 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3690,10 +3690,6 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device *adev) adev->gfx.mcbp = true; else if (amdgpu_mcbp == 0) adev->gfx.mcbp = false; - else if ((amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 0, 0)) && -(amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 0, 0)) && -adev->gfx.num_gfx_rings) - adev->gfx.mcbp = true; if (amdgpu_sriov_vf(adev)) adev->gfx.mcbp = true; -- 2.25.1
Re: [PATCH 3/3] drm/amdgpu: Avoid querying DRM MGCG status
[AMD Official Use Only - General]
For the series.
From: Alex Deucher
Sent: Friday, December 1, 2023 9:00 AM
To: Lazar, Lijo
Cc: amd-gfx@lists.freedesktop.org ; Deucher,
Alexander ; Zhang, Hawking
Subject: Re: [PATCH 3/3] drm/amdgpu: Avoid querying DRM MGCG status
Acked-by: Alex Deucher
On Fri, Dec 1, 2023 at 3:32 AM Lijo Lazar wrote:
>
> MP0 v13.0.6 SOCs don't support DRM MGCG.
>
> Signed-off-by: Lijo Lazar
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 9043ebf1e161..15033efec2ba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1430,7 +1430,8 @@ static void soc15_common_get_clockgating_state(void
> *handle, u64 *flags)
> if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)
> adev->hdp.funcs->get_clock_gating_state(adev, flags);
>
> - if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) {
> + if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&
> + (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) {
> /* AMD_CG_SUPPORT_DRM_MGCG */
> data = RREG32(SOC15_REG_OFFSET(MP0, 0,
> mmMP0_MISC_CGTT_CTRL0));
> if (!(data & 0x0100))
> --
> 2.25.1
>
RE: [PATCH] drm/amd/swsmu: update smu v14_0_0 driver if version and metrics table
[Public]
> -Original Message-
> From: Ma, Li
> Sent: Monday, December 4, 2023 3:52 AM
> To: Deucher, Alexander ; amd-
> g...@lists.freedesktop.org
> Cc: Koenig, Christian ; Zhang, Yifan
> ; Yu, Lang ; Wang,
> Yang(Kevin)
> Subject: RE: [PATCH] drm/amd/swsmu: update smu v14_0_0 driver if version
> and metrics table
>
> [Public]
>
> Hi Alex,
>
> Sorry for the late reply. Only smu14 used this gpu_metrics_v3_0 struct. And
> the patch has upstream. As far as l know, umr used gpu_metrics_v3_0 and I
> will submit a patch to umr.
> Does this struct need to be back compatible currently? If yes, I will revert
> this
> patch and add a new gpu_metrics_v3_1.
Ok. If we don't yet have a released kernel with v3_0 support we should be
fine. I'll just include the updates in 6.7.
Alex
>
> Best Regards,
> Li
>
> -Original Message-
> From: Deucher, Alexander
> Sent: Tuesday, November 28, 2023 4:47 AM
> To: Ma, Li ; amd-gfx@lists.freedesktop.org
> Cc: Koenig, Christian ; Zhang, Yifan
> ; Yu, Lang
> Subject: RE: [PATCH] drm/amd/swsmu: update smu v14_0_0 driver if version
> and metrics table
>
> [Public]
>
> > -Original Message-
> > From: Ma, Li
> > Sent: Thursday, November 23, 2023 5:07 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Koenig, Christian
> > ; Zhang, Yifan ; Yu,
> > Lang ; Ma, Li
> > Subject: [PATCH] drm/amd/swsmu: update smu v14_0_0 driver if version
> > and metrics table
> >
> > Increment the driver if version and add new mems to the mertics table.
> >
> > Signed-off-by: Li Ma
> > ---
> > .../gpu/drm/amd/include/kgd_pp_interface.h| 17
> > drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 10 +++
> > .../inc/pmfw_if/smu14_driver_if_v14_0_0.h | 77 +++
> > .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 46 ++-
> > 4 files changed, 115 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > index 8ebba87f4289..eaea1c65e526 100644
> > --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > @@ -1086,6 +1086,10 @@ struct gpu_metrics_v3_0 {
> > uint16_taverage_dram_reads;
> > /* time filtered DRAM write bandwidth [MB/sec] */
> > uint16_taverage_dram_writes;
> > + /* time filtered IPU read bandwidth [MB/sec] */
> > + uint16_taverage_ipu_reads;
> > + /* time filtered IPU write bandwidth [MB/sec] */
> > + uint16_taverage_ipu_writes;
> >
> > /* Driver attached timestamp (in ns) */
> > uint64_tsystem_clock_counter;
> > @@ -1105,6 +1109,8 @@ struct gpu_metrics_v3_0 {
> > uint32_taverage_all_core_power;
> > /* calculated core power [mW] */
> > uint16_taverage_core_power[16];
> > + /* time filtered total system power [mW] */
> > + uint16_taverage_sys_power;
> > /* maximum IRM defined STAPM power limit [mW] */
> > uint16_tstapm_power_limit;
> > /* time filtered STAPM power limit [mW] */ @@ -1117,6 +1123,8 @@
> > struct gpu_metrics_v3_0 {
> > uint16_taverage_ipuclk_frequency;
> > uint16_taverage_fclk_frequency;
> > uint16_taverage_vclk_frequency;
> > + uint16_taverage_uclk_frequency;
> > + uint16_taverage_mpipu_frequency;
> >
> > /* Current clocks */
> > /* target core frequency [MHz] */ @@ -1126,6 +1134,15 @@ struct
> > gpu_metrics_v3_0 {
> > /* GFXCLK frequency limit enforced on GFX [MHz] */
> > uint16_tcurrent_gfx_maxfreq;
> >
> > + /* Throttle Residency (ASIC dependent) */
> > + uint32_t throttle_residency_prochot;
> > + uint32_t throttle_residency_spl;
> > + uint32_t throttle_residency_fppt;
> > + uint32_t throttle_residency_sppt;
> > + uint32_t throttle_residency_thm_core;
> > + uint32_t throttle_residency_thm_gfx;
> > + uint32_t throttle_residency_thm_soc;
> > +
> > /* Metrics table alpha filter time constant [us] */
> > uint32_ttime_filter_alphavalue;
> > }
RE: [PATCH 1/6] Revert "drm/prime: Unexport helpers for fd/handle conversion"
[AMD Official Use Only - General]
> -Original Message-
> From: Kuehling, Felix
> Sent: Friday, December 1, 2023 6:40 PM
> To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Deucher,
> Alexander
> Cc: Daniel Vetter ; Koenig, Christian
> ; Thomas Zimmermann
>
> Subject: Re: [PATCH 1/6] Revert "drm/prime: Unexport helpers for fd/handle
> conversion"
>
> Hi Alex,
>
> I'm about to push patches 1-3 to the rebased amd-staging-drm-next. It would
> be good to get patch 1 into drm-fixes so that Linux 6.6 will be the only
> kernel
> without these prime helpers. That would minimize the hassle for DKMS driver
> installations on future distros.
Already done:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0514f63cfff38a0dcb7ba9c5f245827edc0c5107
Alex
>
> Thanks,
>Felix
>
>
> On 2023-12-01 18:34, Felix Kuehling wrote:
> > This reverts commit 71a7974ac7019afeec105a54447ae1dc7216cbb3.
> >
> > These helper functions are needed for KFD to export and import DMABufs
> > the right way without duplicating the tracking of DMABufs associated
> > with GEM objects while ensuring that move notifier callbacks are
> > working as intended.
> >
> > Acked-by: Christian König
> > Acked-by: Thomas Zimmermann
> > Acked-by: Daniel Vetter
> > Signed-off-by: Felix Kuehling
> > ---
> > drivers/gpu/drm/drm_prime.c | 33 ++---
> > include/drm/drm_prime.h | 7 +++
> > 2 files changed, 25 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
> > index 63b709a67471..834a5e28abbe 100644
> > --- a/drivers/gpu/drm/drm_prime.c
> > +++ b/drivers/gpu/drm/drm_prime.c
> > @@ -278,7 +278,7 @@ void drm_gem_dmabuf_release(struct dma_buf
> *dma_buf)
> > }
> > EXPORT_SYMBOL(drm_gem_dmabuf_release);
> >
> > -/*
> > +/**
> >* drm_gem_prime_fd_to_handle - PRIME import function for GEM drivers
> >* @dev: drm_device to import into
> >* @file_priv: drm file-private structure @@ -292,9 +292,9 @@
> > EXPORT_SYMBOL(drm_gem_dmabuf_release);
> >*
> >* Returns 0 on success or a negative error code on failure.
> >*/
> > -static int drm_gem_prime_fd_to_handle(struct drm_device *dev,
> > - struct drm_file *file_priv, int prime_fd,
> > - uint32_t *handle)
> > +int drm_gem_prime_fd_to_handle(struct drm_device *dev,
> > + struct drm_file *file_priv, int prime_fd,
> > + uint32_t *handle)
> > {
> > struct dma_buf *dma_buf;
> > struct drm_gem_object *obj;
> > @@ -360,6 +360,7 @@ static int drm_gem_prime_fd_to_handle(struct
> drm_device *dev,
> > dma_buf_put(dma_buf);
> > return ret;
> > }
> > +EXPORT_SYMBOL(drm_gem_prime_fd_to_handle);
> >
> > int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data,
> > struct drm_file *file_priv)
> > @@ -408,7 +409,7 @@ static struct dma_buf
> *export_and_register_object(struct drm_device *dev,
> > return dmabuf;
> > }
> >
> > -/*
> > +/**
> >* drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers
> >* @dev: dev to export the buffer from
> >* @file_priv: drm file-private structure @@ -421,10 +422,10 @@
> > static struct dma_buf *export_and_register_object(struct drm_device *dev,
> >* The actual exporting from GEM object to a dma-buf is done through the
> >* &drm_gem_object_funcs.export callback.
> >*/
> > -static int drm_gem_prime_handle_to_fd(struct drm_device *dev,
> > - struct drm_file *file_priv, uint32_t
> > handle,
> > - uint32_t flags,
> > - int *prime_fd)
> > +int drm_gem_prime_handle_to_fd(struct drm_device *dev,
> > + struct drm_file *file_priv, uint32_t handle,
> > + uint32_t flags,
> > + int *prime_fd)
> > {
> > struct drm_gem_object *obj;
> > int ret = 0;
> > @@ -506,6 +507,7 @@ static int drm_gem_prime_handle_to_fd(struct
> > drm_device *dev,
> >
> > return ret;
> > }
> > +EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
> >
> > int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,
> > stru
Re: [PATCH] drm/amd/pm: fix pp_*clk_od typo
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Dmitrii
Galantsev
Sent: Wednesday, December 6, 2023 2:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Galantsev, Dmitrii
Subject: [PATCH] drm/amd/pm: fix pp_*clk_od typo
Fix pp_dpm_sclk_od and pp_dpm_mclk_od typos.
Those were defined as pp_*clk_od but used as pp_dpm_*clk_od instead.
This change removes the _dpm part.
Signed-off-by: Dmitrii Galantsev
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e1497296afee..2cd995b0ceba 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2238,10 +2238,10 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) {
if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) ==
XGMI_PLPD_NONE)
*states = ATTR_STATE_UNSUPPORTED;
- } else if (DEVICE_ATTR_IS(pp_dpm_mclk_od)) {
+ } else if (DEVICE_ATTR_IS(pp_mclk_od)) {
if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP)
*states = ATTR_STATE_UNSUPPORTED;
- } else if (DEVICE_ATTR_IS(pp_dpm_sclk_od)) {
+ } else if (DEVICE_ATTR_IS(pp_sclk_od)) {
if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP)
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(apu_thermal_cap)) {
--
2.43.0
RE: [PATCH 2/3] drm/amdgpu/sdma5.0: add begin/end_use ring callbacks
[Public]
> -Original Message-
> From: Deucher, Alexander
> Sent: Friday, December 8, 2023 5:19 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 2/3] drm/amdgpu/sdma5.0: add begin/end_use ring
> callbacks
>
> Add begin/end_use ring callbacks to disallow GFXOFF when SDMA work is
> submitted and allow it again afterward.
>
> Signed-off-by: Alex Deucher
This one can probably be dropped. It's only needed if anyone on navi1x is
experiencing a similar issue.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 5c1bb6d07a76..1a68cd2de522 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -1790,6 +1790,8 @@ static const struct amdgpu_ring_funcs
> sdma_v5_0_ring_funcs = {
> .test_ib = sdma_v5_0_ring_test_ib,
> .insert_nop = sdma_v5_0_ring_insert_nop,
> .pad_ib = sdma_v5_0_ring_pad_ib,
> + .begin_use = amdgpu_sdma_ring_begin_use,
> + .end_use = amdgpu_sdma_ring_end_use,
> .emit_wreg = sdma_v5_0_ring_emit_wreg,
> .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
> .emit_reg_write_reg_wait =
> sdma_v5_0_ring_emit_reg_write_reg_wait,
> --
> 2.42.0
RE: [PATCH] drm/amd/display: fix documentation for dm_crtc_additional_color_mgmt()
[Public] > -Original Message- > From: Melissa Wen > Sent: Thursday, December 14, 2023 2:45 PM > To: Wentland, Harry ; Li, Sun peng (Leo) > ; Siqueira, Rodrigo ; > Deucher, Alexander ; Koenig, Christian > ; Pan, Xinhui ; > airl...@gmail.com; dan...@ffwll.ch > Cc: kernel test robot ; amd-gfx@lists.freedesktop.org; dri- > de...@lists.freedesktop.org; kernel-...@igalia.com > Subject: [PATCH] drm/amd/display: fix documentation for > dm_crtc_additional_color_mgmt() > > warning: expecting prototype for drm_crtc_additional_color_mgmt(). > Prototype was for dm_crtc_additional_color_mgmt() instead > > Reported-by: kernel test robot > Closes: https://lore.kernel.org/oe-kbuild-all/202312141801.o9eBCxt9- > l...@intel.com/ > Signed-off-by: Melissa Wen Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > index 8b3aa674741d..4439e5a27362 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c > @@ -292,7 +292,7 @@ static int amdgpu_dm_crtc_late_register(struct > drm_crtc *crtc) > > #ifdef AMD_PRIVATE_COLOR > /** > - * drm_crtc_additional_color_mgmt - enable additional color properties > + * dm_crtc_additional_color_mgmt - enable additional color properties > * @crtc: DRM CRTC > * > * This function lets the driver enable post-blending CRTC regamma transfer > -- > 2.42.0
RE: Crashes under Xen with Radeon graphics card
[Public] > -Original Message- > From: Juergen Gross > Sent: Friday, December 15, 2023 6:57 AM > To: lkml ; xen-de...@lists.xenproject.org; amd- > g...@lists.freedesktop.org > Cc: Deucher, Alexander ; Koenig, Christian > ; Pan, Xinhui > Subject: Crashes under Xen with Radeon graphics card > > Hi, > > I recently stumbled over a test system which showed crashes probably > resulting from memory being overwritten randomly. > > The problem is occurring only in Dom0 when running under Xen. It seems to > be present since at least kernel 6.3 (I didn't go back further yet), and it > seems > NOT to be present in kernel 5.14. > > I tracked the problem down to the initialization of the graphics card (the > problem might surface only later, but at least an early initialization > failure made > the problem go away). > > # lspci > 01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] > Caicos XTX [Radeon HD 8490 / R5 235X OEM] > 01:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Caicos HDMI > Audio [Radeon HD 6450 / 7450/8450/8490 OEM / R5 230/235/235X OEM] > > I had a working .config and one which did produce the crashes, so I narrowed > the problem down to detect that the important difference was in the area of > firmware loading (the working .config didn't have > CONFIG_FW_LOADER_COMPRESS_XZ set, causing firmware loading for the > card to fail). This was of course not the real problem, but it caused the card > initialization to fail. > > I manually decompressed the firmware files one by one to see whether the > problem would be in the decompressor or probably in the driver of the card. > > The last step without crash was: > > # dmesg | grep radeon > [ 10.106405] [drm] radeon kernel modesetting enabled. > [ 10.106455] radeon :01:00.0: vgaarb: deactivate vga console > [ 10.222944] radeon :01:00.0: VRAM: 1024M 0x > - > 0x3FFF (1024M used) > [ 10.252921] radeon :01:00.0: GTT: 1024M 0x4000 - > 0x7FFF > [ 10.278255] [drm] radeon: 1024M of VRAM memory ready > [ 10.295828] [drm] radeon: 1024M of GTT memory ready. > [ 10.295867] radeon :01:00.0: Direct firmware load for > radeon/CAICOS_pfp.bin succeeded > [ 10.330846] radeon :01:00.0: Direct firmware load for > radeon/CAICOS_me.bin succeeded > [ 10.330858] radeon :01:00.0: Direct firmware load for > radeon/BTC_rlc.bin > succeeded > [ 10.330870] radeon :01:00.0: Direct firmware load for > radeon/CAICOS_mc.bin failed with error -2 > [ 10.380979] ni_cp: Failed to load firmware "radeon/CAICOS_mc.bin" > [ 10.381006] [drm:evergreen_init [radeon]] *ERROR* Failed to load > firmware! > [ 10.405765] radeon :01:00.0: Fatal error during GPU init > [ 10.432107] [drm] radeon: finishing device. > [ 10.439179] [drm] radeon: ttm finalized > [ 10.463203] radeon: probe of :01:00.0 failed with error -2 > > And with decompressing radeon/CAICOS_mc.bin I got: > > # dmesg | grep radeon > [ 10.266491] [drm] radeon kernel modesetting enabled. > [ 10.266552] radeon :01:00.0: vgaarb: deactivate vga console > [ 10.456047] radeon :01:00.0: VRAM: 1024M 0x > - > 0x3FFF (1024M used) > [ 10.470270] radeon :01:00.0: GTT: 1024M 0x4000 - > 0x7FFF > [ 10.566946] [drm] radeon: 1024M of VRAM memory ready > [ 10.576891] [drm] radeon: 1024M of GTT memory ready. > [ 10.586971] radeon :01:00.0: Direct firmware load for > radeon/CAICOS_pfp.bin succeeded > [ 10.611886] radeon :01:00.0: Direct firmware load for > radeon/CAICOS_me.bin succeeded > [ 10.611909] radeon :01:00.0: Direct firmware load for > radeon/BTC_rlc.bin > succeeded > [ 10.611938] radeon :01:00.0: Direct firmware load for > radeon/CAICOS_mc.bin succeeded > [ 10.660599] radeon :01:00.0: Direct firmware load for > radeon/CAICOS_smc.bin failed with error -2 > [ 10.660601] smc: error loading firmware "radeon/CAICOS_smc.bin" You also need to make sure CAICOS_smc.bin is available. > [ 10.661676] [drm] radeon: power management initialized > [ 10.713666] radeon :01:00.0: Direct firmware load for > radeon/SUMO_uvd.bin > failed with error -2 > [ 10.713668] radeon :01:00.0: radeon_uvd: Can't load firmware > "radeon/SUMO_uvd.bin" > [ 10.713669] radeon :01:00.0: failed UVD (-2) init. And SUMO_uvd.bin. > [ 10.714787] [drm] enabling PCIE gen 2 link speeds, disable with > radeon.pcie_gen2=0 > [ 10.809213] radeon :01:00.0: WB enabled > [ 10.817528] radeon :01:00.0: fence driver on ring 0 use gpu addr > 0x4000
RE: Crashes under Xen with Radeon graphics card
[AMD Official Use Only - General] > -Original Message- > From: Juergen Gross > Sent: Friday, December 15, 2023 11:13 AM > To: Deucher, Alexander ; lkml ker...@vger.kernel.org>; xen-de...@lists.xenproject.org; amd- > g...@lists.freedesktop.org > Cc: Koenig, Christian ; Pan, Xinhui > > Subject: Re: Crashes under Xen with Radeon graphics card > > On 15.12.23 17:04, Deucher, Alexander wrote: > > [Public] > > > >> -Original Message- > >> From: Juergen Gross > >> Sent: Friday, December 15, 2023 6:57 AM > >> To: lkml ; > >> xen-de...@lists.xenproject.org; amd- g...@lists.freedesktop.org > >> Cc: Deucher, Alexander ; Koenig, Christian > >> ; Pan, Xinhui > >> Subject: Crashes under Xen with Radeon graphics card > >> > >> Hi, > >> > >> I recently stumbled over a test system which showed crashes probably > >> resulting from memory being overwritten randomly. > >> > >> The problem is occurring only in Dom0 when running under Xen. It > >> seems to be present since at least kernel 6.3 (I didn't go back > >> further yet), and it seems NOT to be present in kernel 5.14. > >> > >> I tracked the problem down to the initialization of the graphics card > >> (the problem might surface only later, but at least an early > >> initialization failure made the problem go away). > >> > >> # lspci > >> 01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. > >> [AMD/ATI] Caicos XTX [Radeon HD 8490 / R5 235X OEM] > >> 01:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Caicos > >> HDMI Audio [Radeon HD 6450 / 7450/8450/8490 OEM / R5 > 230/235/235X > >> OEM] > >> > >> I had a working .config and one which did produce the crashes, so I > >> narrowed the problem down to detect that the important difference was > >> in the area of firmware loading (the working .config didn't have > >> CONFIG_FW_LOADER_COMPRESS_XZ set, causing firmware loading for the > >> card to fail). This was of course not the real problem, but it caused > >> the card initialization to fail. > >> > >> I manually decompressed the firmware files one by one to see whether > >> the problem would be in the decompressor or probably in the driver of the > card. > >> > >> The last step without crash was: > >> > >> # dmesg | grep radeon > >> [ 10.106405] [drm] radeon kernel modesetting enabled. > >> [ 10.106455] radeon :01:00.0: vgaarb: deactivate vga console > >> [ 10.222944] radeon :01:00.0: VRAM: 1024M > 0x > >> - > >> 0x3FFF (1024M used) > >> [ 10.252921] radeon :01:00.0: GTT: 1024M 0x4000 > - > >> 0x7FFF > >> [ 10.278255] [drm] radeon: 1024M of VRAM memory ready > >> [ 10.295828] [drm] radeon: 1024M of GTT memory ready. > >> [ 10.295867] radeon :01:00.0: Direct firmware load for > >> radeon/CAICOS_pfp.bin succeeded > >> [ 10.330846] radeon :01:00.0: Direct firmware load for > >> radeon/CAICOS_me.bin succeeded > >> [ 10.330858] radeon :01:00.0: Direct firmware load for > >> radeon/BTC_rlc.bin > >> succeeded > >> [ 10.330870] radeon :01:00.0: Direct firmware load for > >> radeon/CAICOS_mc.bin failed with error -2 > >> [ 10.380979] ni_cp: Failed to load firmware "radeon/CAICOS_mc.bin" > >> [ 10.381006] [drm:evergreen_init [radeon]] *ERROR* Failed to load > >> firmware! > >> [ 10.405765] radeon :01:00.0: Fatal error during GPU init > >> [ 10.432107] [drm] radeon: finishing device. > >> [ 10.439179] [drm] radeon: ttm finalized > >> [ 10.463203] radeon: probe of :01:00.0 failed with error -2 > >> > >> And with decompressing radeon/CAICOS_mc.bin I got: > >> > >> # dmesg | grep radeon > >> [ 10.266491] [drm] radeon kernel modesetting enabled. > >> [ 10.266552] radeon :01:00.0: vgaarb: deactivate vga console > >> [ 10.456047] radeon :01:00.0: VRAM: 1024M > 0x > >> - > >> 0x3FFF (1024M used) > >> [ 10.470270] radeon :01:00.0: GTT: 1024M 0x4000 > - > >> 0x7FFF > >> [ 10.566946] [drm] radeon: 1024M of VRAM memory ready > >> [ 10.576891] [drm] radeon: 1024M of GTT memory ready. > >> [ 10.586971] radeon :01:00.0: Direct firmware load for > >> r
Re: [PATCH] drm/amd: Add missing definitions for `SMU_MAX_LEVELS_VDDGFX`
[Public]
VDDGFX should be matched to VDDC (e.g, SMU7_MAX_LEVELS_VDDC).
Alex
From: amd-gfx on behalf of Mario
Limonciello
Sent: Thursday, December 14, 2023 4:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Limonciello, Mario
Subject: [PATCH] drm/amd: Add missing definitions for `SMU_MAX_LEVELS_VDDGFX`
It is reported that on a Topaz dGPU the kernel emits:
amdgpu: can't get the mac of 5
This is because there is no definition for max levels of VDDGFX
declared for SMU71 or SMU7. There is however an unused definition of
VDDNB. Use this to return the max levels for VDDGFX.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3049
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c | 2 ++
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
index 9e4228232f02..c5bccd382196 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
@@ -2303,6 +2303,8 @@ static uint32_t ci_get_mac_definition(uint32_t value)
return SMU7_MAX_LEVELS_VDDCI;
case SMU_MAX_LEVELS_MVDD:
return SMU7_MAX_LEVELS_MVDD;
+ case SMU_MAX_LEVELS_VDDGFX:
+ return SMU7_MAX_LEVELS_VDDNB;
}
pr_debug("can't get the mac of %x\n", value);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
index 97d9802fe673..c9115eaa63c4 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
@@ -2268,6 +2268,8 @@ static uint32_t iceland_get_mac_definition(uint32_t value)
return SMU71_MAX_LEVELS_VDDCI;
case SMU_MAX_LEVELS_MVDD:
return SMU71_MAX_LEVELS_MVDD;
+ case SMU_MAX_LEVELS_VDDGFX:
+ return SMU71_MAX_LEVELS_VDDNB;
}
pr_warn("can't get the mac of %x\n", value);
--
2.34.1
