Re: [PATCH 2/3] drm: export gem dmabuf_ops for drivers to reuse
On Tue, Jan 09, 2018 at 01:13:08PM -0500, Alex Deucher wrote:
> On Tue, Jan 9, 2018 at 10:56 AM, Deucher, Alexander
> wrote:
> > I'll can push this and a few other misc patches today.
> >
>
> Pushed to drm-misc-next.
One thing I just noticed: Some kerneldoc for the newly exported functions
and maybe a small update to the intro section to explain what to do with
this would be neat.
-Daniel
>
> Thanks,
>
> Alex
>
>
> >
> > Alex
> >
> > From: amd-gfx on behalf of Li,
> > Samuel
> > Sent: Tuesday, January 9, 2018 10:20 AM
> > To: Daniel Vetter; Koenig, Christian
> > Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> > Subject: RE: [PATCH 2/3] drm: export gem dmabuf_ops for drivers to reuse
> >
> > Yes, please hush this for me.
> >
> > Regards,
> > Samuel Li
> >
> >
> >> -Original Message-
> >> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> >> Vetter
> >> Sent: Tuesday, January 09, 2018 4:22 AM
> >> To: Koenig, Christian
> >> Cc: Li, Samuel ; dri-de...@lists.freedesktop.org; amd-
> >> g...@lists.freedesktop.org
> >> Subject: Re: [PATCH 2/3] drm: export gem dmabuf_ops for drivers to reuse
> >>
> >> On Fri, Jan 05, 2018 at 10:16:04AM +0100, Christian König wrote:
> >> > Am 04.01.2018 um 22:12 schrieb Samuel Li:
> >> > > Change-Id: I03c22a890d2305f3243d88019d1a28bddd4ddda7
> >> > > Signed-off-by: Samuel Li
> >> >
> >> > Reviewed-by: Christian König
> >>
> >> Want to push to drm-misc or some other plan with this?
> >> -Daniel
> >>
> >> >
> >> > > ---
> >> > > drivers/gpu/drm/drm_prime.c | 53 ++---
> >>
> >> > > include/drm/drm_prime.h | 22 +++
> >> > > 2 files changed, 53 insertions(+), 22 deletions(-)
> >> > >
> >> > > diff --git a/drivers/gpu/drm/drm_prime.c
> >> > > b/drivers/gpu/drm/drm_prime.c index 8de93a2..68a69e9 100644
> >> > > --- a/drivers/gpu/drm/drm_prime.c
> >> > > +++ b/drivers/gpu/drm/drm_prime.c
> >> > > @@ -180,9 +180,8 @@ static int drm_prime_lookup_buf_handle(struct
> >> drm_prime_file_private *prime_fpri
> >> > >return -ENOENT;
> >> > > }
> >> > > -static int drm_gem_map_attach(struct dma_buf *dma_buf,
> >> > > - struct device *target_dev,
> >> > > - struct dma_buf_attachment *attach)
> >> > > +int drm_gem_map_attach(struct dma_buf *dma_buf, struct device
> >> *target_dev,
> >> > > +struct dma_buf_attachment *attach)
> >> > > {
> >> > >struct drm_prime_attachment *prime_attach;
> >> > >struct drm_gem_object *obj = dma_buf->priv; @@ -200,9 +199,10
> >> @@
> >> > > static int drm_gem_map_attach(struct dma_buf *dma_buf,
> >> > >return dev->driver->gem_prime_pin(obj);
> >> > > }
> >> > > +EXPORT_SYMBOL(drm_gem_map_attach);
> >> > > -static void drm_gem_map_detach(struct dma_buf *dma_buf,
> >> > > -struct dma_buf_attachment *attach)
> >> > > +void drm_gem_map_detach(struct dma_buf *dma_buf,
> >> > > + struct dma_buf_attachment *attach)
> >> > > {
> >> > >struct drm_prime_attachment *prime_attach = attach->priv;
> >> > >struct drm_gem_object *obj = dma_buf->priv; @@ -227,6 +227,7
> >> @@
> >> > > static void drm_gem_map_detach(struct dma_buf *dma_buf,
> >> > >kfree(prime_attach);
> >> > >attach->priv = NULL;
> >> > > }
> >> > > +EXPORT_SYMBOL(drm_gem_map_detach);
> >> > > void drm_prime_remove_buf_handle_locked(struct
> >> drm_prime_file_private *prime_fpriv,
> >> > >struct dma_buf *dma_buf)
> >> > > @@ -253,8 +254,8 @@ void
> >> drm_prime_remove_buf_handle_locked(struct drm_prime_file_private
> >> *prime_fpr
> >> > >}
> >> > > }
> >> > > -static struct sg_table *drm_gem_map_dma_buf(struct
> >> dma_buf_attachment *attach,
> >> > > - enum dma_data_direction dir)
> >> > > +struct sg_table *drm_gem_map_dma_buf(struct dma_buf_attachment
> >> *attach,
> >> > > + enum dma_data_direction dir)
> >> > > {
> >> > >struct drm_prime_attachment *prime_attach = attach->priv;
> >> > >struct drm_gem_object *obj = attach->dmabuf->priv; @@ -289,13
> >> > > +290,15 @@ static struct sg_table *drm_gem_map_dma_buf(struct
> >> dma_buf_attachment *attach,
> >> > >return sgt;
> >> > > }
> >> > > +EXPORT_SYMBOL(drm_gem_map_dma_buf);
> >> > > -static void drm_gem_unmap_dma_buf(struct dma_buf_attachment
> >> *attach,
> >> > > - struct sg_table *sgt,
> >> > > - enum dma_data_direction dir)
> >> > > +void drm_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
> >> > > +struct sg_table *sgt,
> >> > > +enum dma_data_direction dir)
> >> > > {
> >> > >/* nothing to be done here */
> >> > > }
> >> > > +EXPORT_SYMBOL(drm_gem_unmap_dma_buf);
> >> > > /**
> >> > >* drm_gem_dmabuf_export - dma_buf export imp
[PATCH] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory
Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..5f2ae77 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1069,7 +1069,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr += SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(0) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS | + PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory
Am 10.01.2018 um 09:18 schrieb Junwei Zhang: Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..5f2ae77 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1069,7 +1069,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr += SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE); Both the old and the new code looks strongly incorrect to me. SOC15_REG_OFFSET gives you the register offset, not the content of the register. So adding two register offsets or doesn't seem to make any sense at all. Regards, Christian. /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(0) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS | + PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory
On 01/10/2018 04:57 PM, Christian König wrote: Am 10.01.2018 um 09:18 schrieb Junwei Zhang: Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..5f2ae77 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1069,7 +1069,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); -adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; +adev->gfx.ngg.gds_reserve_addr += SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE); Both the old and the new code looks strongly incorrect to me. SOC15_REG_OFFSET gives you the register offset, not the content of the register. So adding two register offsets or doesn't seem to make any sense at all. Thanks to point it out. It's typo from the very beginning. Going to correct it with RREG32_SOC15(). Jerry Regards, Christian. /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | +PACKET3_DMA_DATA_DST_SEL(0) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); -amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - +amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS | +PACKET3_DMA_DATA_CMD_RAW_WAIT | +adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdkfd: avoid calling execute_queues_cpsch() when destroying an unactive queue
On Tue, Jan 2, 2018 at 8:10 PM, Yong Zhao wrote:
> Signed-off-by: Yong Zhao
> Reviewed-by: Oak Zeng
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index acfb121..b21285a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -1013,13 +1013,13 @@ static int destroy_queue_cpsch(struct
> device_queue_manager *dqm,
>
> list_del(&q->list);
> qpd->queue_count--;
> - if (q->properties.is_active)
> + if (q->properties.is_active) {
> dqm->queue_count--;
> -
> - retval = execute_queues_cpsch(dqm,
> + retval = execute_queues_cpsch(dqm,
> KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
> - if (retval == -ETIME)
> - qpd->reset_wavefronts = true;
> + if (retval == -ETIME)
> + qpd->reset_wavefronts = true;
> + }
>
> mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
>
> --
> 2.7.4
>
Both patches applied to next.
Thanks,
Oded.
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[PATCH] drm/amdkfd: use add ull suffix to 64bit defines
Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6a48d29ada47..0bedcf9cc08c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -41,9 +41,9 @@ #define KFD_SYSFS_FILE_MODE 0444 -#define KFD_MMAP_DOORBELL_MASK 0x8 -#define KFD_MMAP_EVENTS_MASK 0x4 -#define KFD_MMAP_RESERVED_MEM_MASK 0x2 +#define KFD_MMAP_DOORBELL_MASK 0x8ull +#define KFD_MMAP_EVENTS_MASK 0x4ull +#define KFD_MMAP_RESERVED_MEM_MASK 0x2ull /* * When working with cp scheduler we should assign the HIQ manually or via -- 2.14.3 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/pp: Add custom power profile mode support on Vega10
Change-Id: I0a554cb6a7a56db63a8fc5af60d5c63f65e021d1
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 39 +++
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 78 ++
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +
4 files changed, 121 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 8859b67..3493292 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1081,6 +1081,43 @@ static int pp_dpm_get_power_profile_state(void *handle,
return 0;
}
+static int pp_get_power_profile_mode(void *handle, char *buf)
+{
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle = (struct pp_instance *)handle;
+
+ if (!buf || pp_check(pp_handle))
+ return -EINVAL;
+
+ hwmgr = pp_handle->hwmgr;
+
+ if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return snprintf(buf, PAGE_SIZE, "\n");
+ }
+
+ return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
+}
+
+static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
+{
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle = (struct pp_instance *)handle;
+
+
+ if (pp_check(pp_handle))
+ return -EINVAL;
+
+ hwmgr = pp_handle->hwmgr;
+
+ if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return -EINVAL;
+ }
+
+ return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
+}
+
static int pp_dpm_set_power_profile_state(void *handle,
struct amd_pp_profile *request)
{
@@ -1464,6 +1501,8 @@ static int pp_get_display_mode_validation_clocks(void
*handle,
.switch_power_profile = pp_dpm_switch_power_profile,
.set_clockgating_by_smu = pp_set_clockgating_by_smu,
.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
+ .get_power_profile_mode = pp_get_power_profile_mode,
+ .set_power_profile_mode = pp_set_power_profile_mode,
/* export to DC */
.get_sclk = pp_dpm_get_sclk,
.get_mclk = pp_dpm_get_mclk,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 23b7239..e8b6c3d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -757,6 +757,8 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->backend = data;
+ hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
+
vega10_set_default_registry_data(hwmgr);
data->disable_dpm_mask = 0xff;
@@ -3950,6 +3952,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int
idx,
ret = -EINVAL;
break;
}
+
return ret;
}
@@ -5008,6 +5011,79 @@ static int vega10_register_thermal_interrupt(struct
pp_hwmgr *hwmgr,
return 0;
}
+static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
+{
+ struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
+ uint32_t i, size = 0;
+ uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
+ {90, 60, 0, 0,},
+ {70, 60, 0, 0,},
+ {70, 90, 0, 0,},
+ {30, 60, 0, 6,},
+ };
+ char *profile_name[6] = {"3D_FULL_SCREEN",
+ "POWER_SAVING",
+ "VIDEO",
+ "VR",
+ "COMPUTER",
+ "CUSTOM"};
+ char *title[6] = {"NUM",
+ "MODE_NAME",
+ "BUSY_SET_POINT",
+ "FPS",
+ "USE_RLC_BUSY",
+ "MIN_ACTIVE_LEVEL"};
+
+ if (!buf)
+ return -EINVAL;
+
+ size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
+ title[1], title[2], title[3], title[4], title[5]);
+
+ for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
+ size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
+ i, profile_name[i], (i == hwmgr->power_profile_mode) ?
"*" : " ",
+ profile_mode_setting[i][0], profile_mode_setting[i][1],
+ profile_mode_setting[i][2], profile_mode_setting[i][3]);
+ size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10
[PATCH 1/2] drm/amdgpu: add custom power policy support in sysfs
when cat pp_power_profile_mode on Vega10
NUMMODE_NAME BUSY_SET_POINT FPS USE_RLC_BUSY MIN_ACTIVE_LEVEL
0 3D_FULL_SCREEN : 70 60 1 3
1 POWER_SAVING : 90 60 0 0
2 VIDEO*: 70 60 0 0
3 VR : 70 90 0 0
4 COMPUTER : 30 60 0 6
5 CUSTOM : 0 0 0 0
the result show all the profile mode we can support and custom mode.
user can echo the num(0-4) to pp_power_profile_mode to select the profile
mode or can echo "5 value value value value" to enter CUSTOM mode.
the four parameter is set_point/FPS/USER_RLC_BUSY/MIN_ACTIVE_LEVEL.
Change-Id: I72634646a9a179ccd57f175b4c0b3f45e538a03f
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h| 8 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 81 +-
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 11 +++-
3 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 8a8d09dd..986f1d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -366,6 +366,14 @@ enum amdgpu_pcie_gen {
(adev)->powerplay.pp_handle, virtual_addr_low, \
virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
+#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
+ ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
+ (adev)->powerplay.pp_handle, buf))
+
+#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
+ ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
+ (adev)->powerplay.pp_handle, parameter, size))
+
struct amdgpu_dpm {
struct amdgpu_ps*ps;
/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index e5ee7cf..662edca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -584,6 +584,73 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
return count;
}
+static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+
+ if (adev->powerplay.pp_funcs->get_power_profile_mode)
+ return amdgpu_dpm_get_power_profile_mode(adev, buf);
+
+ return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+
+static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ int ret = 0xff;
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+ uint32_t parameter_size = 0;
+ long parameter[64];
+ char *sub_str, buf_cpy[128];
+ char *tmp_str;
+ uint32_t i = 0;
+ char tmp[2];
+ long int profile_mode = 0;
+ const char delimiter[3] = {' ', '\n', '\0'};
+
+ tmp[0] = *(buf);
+ tmp[1] = '\0';
+ ret = kstrtol(tmp, 0, &profile_mode);
+ if (ret)
+ goto fail;
+
+ if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
+ if (count < 2 || count > 127)
+ return -EINVAL;
+ while (isspace(*++buf))
+ i++;
+ memcpy(buf_cpy, buf, count-i);
+ tmp_str = buf_cpy;
+ while (tmp_str[0]) {
+ sub_str = strsep(&tmp_str, delimiter);
+ ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
+ if (ret) {
+ count = -EINVAL;
+ goto fail;
+ }
+ pr_info("value is %ld \n", parameter[parameter_size]);
+ parameter_size++;
+ while (isspace(*tmp_str))
+ tmp_str++;
+ }
+ }
+ parameter[parameter_size] = profile_mode;
+ if (adev->powerplay.pp_funcs->set_power_profile_mode)
+ ret = amdgpu_dpm_set_power_profile_mode(adev, parameter,
parameter_size);
+
+ if (!ret)
+ return count;
+fail:
+ return -EINVAL;
+}
+
static ssize_t amdgpu_get_pp_power_profile(struct device *dev,
char *buf, struct amd_pp_profile *query)
{
@@ -772,7 +839,9 @@ static DEVICE_ATTR(pp_gfx_power_profile, S_IRUGO | S_IWUSR,
static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
amdgpu_get_pp_compute_power_profile,
Re: [PATCH 2/2] drm/amd/pp: Add custom power profile mode support on Vega10
On Wed, Jan 10, 2018 at 1:01 PM, Rex Zhu wrote:
> Change-Id: I0a554cb6a7a56db63a8fc5af60d5c63f65e021d1
> Signed-off-by: Rex Zhu
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 39 +++
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 78
> ++
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 +
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +
> 4 files changed, 121 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 8859b67..3493292 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1081,6 +1081,43 @@ static int pp_dpm_get_power_profile_state(void *handle,
> return 0;
> }
>
> +static int pp_get_power_profile_mode(void *handle, char *buf)
> +{
> + struct pp_hwmgr *hwmgr;
> + struct pp_instance *pp_handle = (struct pp_instance *)handle;
> +
> + if (!buf || pp_check(pp_handle))
> + return -EINVAL;
> +
> + hwmgr = pp_handle->hwmgr;
> +
> + if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
> + pr_info("%s was not implemented.\n", __func__);
> + return snprintf(buf, PAGE_SIZE, "\n");
> + }
> +
> + return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
> +}
> +
> +static int pp_set_power_profile_mode(void *handle, long *input, uint32_t
> size)
> +{
> + struct pp_hwmgr *hwmgr;
> + struct pp_instance *pp_handle = (struct pp_instance *)handle;
> +
> +
Unnecessary blank line.
> + if (pp_check(pp_handle))
> + return -EINVAL;
> +
> + hwmgr = pp_handle->hwmgr;
> +
> + if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
> + pr_info("%s was not implemented.\n", __func__);
> + return -EINVAL;
> + }
> +
> + return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
> +}
> +
> static int pp_dpm_set_power_profile_state(void *handle,
> struct amd_pp_profile *request)
> {
> @@ -1464,6 +1501,8 @@ static int pp_get_display_mode_validation_clocks(void
> *handle,
> .switch_power_profile = pp_dpm_switch_power_profile,
> .set_clockgating_by_smu = pp_set_clockgating_by_smu,
> .notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
> + .get_power_profile_mode = pp_get_power_profile_mode,
> + .set_power_profile_mode = pp_set_power_profile_mode,
> /* export to DC */
> .get_sclk = pp_dpm_get_sclk,
> .get_mclk = pp_dpm_get_mclk,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 23b7239..e8b6c3d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -757,6 +757,8 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr
> *hwmgr)
>
> hwmgr->backend = data;
>
> + hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
> +
> vega10_set_default_registry_data(hwmgr);
>
> data->disable_dpm_mask = 0xff;
> @@ -3950,6 +3952,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr,
> int idx,
> ret = -EINVAL;
> break;
> }
> +
> return ret;
> }
>
> @@ -5008,6 +5011,79 @@ static int vega10_register_thermal_interrupt(struct
> pp_hwmgr *hwmgr,
> return 0;
> }
>
> +static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
> +{
> + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
> + uint32_t i, size = 0;
> + uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
static const, otherwise the compiler has to copy the table to stack on
every call.
> + {90, 60, 0, 0,},
> + {70, 60, 0, 0,},
> + {70, 90, 0, 0,},
> + {30, 60, 0, 6,},
> + };
> + char *profile_name[6] = {"3D_FULL_SCREEN",
static const char * const profile_name[6] = ...
Gražvydas
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[PATCH 05/21] drm/amdgpu: trace allocated PASIDs
Trace all allocated PASIDs.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 22 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 60e0f2dd87df..0948df366278 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -31,6 +31,7 @@
#include "amdgpu_sched.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
+#include "amdgpu_trace.h"
#include
#include
@@ -823,7 +824,10 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
if (pasid < 0) {
dev_info(adev->dev, "No more PASIDs available!");
pasid = 0;
+ } else {
+ trace_amdgpu_pasid_allocated(pasid);
}
+
r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
if (r)
goto error_pasid;
@@ -852,8 +856,10 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
amdgpu_vm_fini(adev, &fpriv->vm);
error_pasid:
- if (pasid)
+ if (pasid) {
amdgpu_pasid_free(pasid);
+ trace_amdgpu_pasid_freed(pasid);
+ }
kfree(fpriv);
@@ -908,8 +914,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
amdgpu_vm_fini(adev, &fpriv->vm);
- if (pasid)
+ if (pasid) {
amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
+ trace_amdgpu_pasid_freed(pasid);
+ }
amdgpu_bo_unref(&pd);
idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index cace7a93fc94..9890c39ee810 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -378,6 +378,28 @@ TRACE_EVENT(amdgpu_vm_flush,
__entry->vm_hub,__entry->pd_addr)
);
+DECLARE_EVENT_CLASS(amdgpu_pasid,
+ TP_PROTO(unsigned pasid),
+ TP_ARGS(pasid),
+ TP_STRUCT__entry(
+__field(unsigned, pasid)
+),
+ TP_fast_assign(
+ __entry->pasid = pasid;
+ ),
+ TP_printk("pasid=%u", __entry->pasid)
+);
+
+DEFINE_EVENT(amdgpu_pasid, amdgpu_pasid_allocated,
+ TP_PROTO(unsigned pasid),
+ TP_ARGS(pasid)
+);
+
+DEFINE_EVENT(amdgpu_pasid, amdgpu_pasid_freed,
+ TP_PROTO(unsigned pasid),
+ TP_ARGS(pasid)
+);
+
TRACE_EVENT(amdgpu_bo_list_set,
TP_PROTO(struct amdgpu_bo_list *list, struct amdgpu_bo *bo),
TP_ARGS(list, bo),
--
2.14.1
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[PATCH 04/21] drm/amdgpu: always allocate a pasid for each VM
Start to always allocate a pasid for each VM.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 43 ++---
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5773a581761b..60e0f2dd87df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -805,7 +805,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
{
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_fpriv *fpriv;
- int r;
+ int r, pasid;
file_priv->driver_priv = NULL;
@@ -819,28 +819,25 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto out_suspend;
}
- r = amdgpu_vm_init(adev, &fpriv->vm,
- AMDGPU_VM_CONTEXT_GFX, 0);
- if (r) {
- kfree(fpriv);
- goto out_suspend;
+ pasid = amdgpu_pasid_alloc(16);
+ if (pasid < 0) {
+ dev_info(adev->dev, "No more PASIDs available!");
+ pasid = 0;
}
+ r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
+ if (r)
+ goto error_pasid;
fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
if (!fpriv->prt_va) {
r = -ENOMEM;
- amdgpu_vm_fini(adev, &fpriv->vm);
- kfree(fpriv);
- goto out_suspend;
+ goto error_vm;
}
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
- if (r) {
- amdgpu_vm_fini(adev, &fpriv->vm);
- kfree(fpriv);
- goto out_suspend;
- }
+ if (r)
+ goto error_vm;
}
mutex_init(&fpriv->bo_list_lock);
@@ -849,6 +846,16 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
file_priv->driver_priv = fpriv;
+ goto out_suspend;
+
+error_vm:
+ amdgpu_vm_fini(adev, &fpriv->vm);
+
+error_pasid:
+ if (pasid)
+ amdgpu_pasid_free(pasid);
+
+ kfree(fpriv);
out_suspend:
pm_runtime_mark_last_busy(dev->dev);
@@ -871,6 +878,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
struct amdgpu_bo_list *list;
+ struct amdgpu_bo *pd;
+ unsigned int pasid;
int handle;
if (!fpriv)
@@ -895,7 +904,13 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
amdgpu_bo_unreserve(adev->virt.csa_obj);
}
+ pasid = fpriv->vm.pasid;
+ pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
+
amdgpu_vm_fini(adev, &fpriv->vm);
+ if (pasid)
+ amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
+ amdgpu_bo_unref(&pd);
idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
amdgpu_bo_list_free(list);
--
2.14.1
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[PATCH 06/21] drm/amdgpu: trace the PASID instead of the VM pointer
Makes more sense than tracing the kernel pointer.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 9890c39ee810..fc79c19917e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -217,7 +217,7 @@ TRACE_EVENT(amdgpu_vm_grab_id,
struct amdgpu_job *job),
TP_ARGS(vm, ring, job),
TP_STRUCT__entry(
-__field(struct amdgpu_vm *, vm)
+__field(u32, pasid)
__field(u32, ring)
__field(u32, vmid)
__field(u32, vm_hub)
@@ -226,15 +226,15 @@ TRACE_EVENT(amdgpu_vm_grab_id,
),
TP_fast_assign(
- __entry->vm = vm;
+ __entry->pasid = vm->pasid;
__entry->ring = ring->idx;
__entry->vmid = job->vmid;
__entry->vm_hub = ring->funcs->vmhub,
__entry->pd_addr = job->vm_pd_addr;
__entry->needs_flush = job->vm_needs_flush;
),
- TP_printk("vm=%p, ring=%u, id=%u, hub=%u, pd_addr=%010Lx
needs_flush=%u",
- __entry->vm, __entry->ring, __entry->vmid,
+ TP_printk("pasid=%d, ring=%u, id=%u, hub=%u, pd_addr=%010Lx
needs_flush=%u",
+ __entry->pasid, __entry->ring, __entry->vmid,
__entry->vm_hub, __entry->pd_addr, __entry->needs_flush)
);
--
2.14.1
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[PATCH 01/21] dma-buf: make returning the exclusive fence optional
Change reservation_object_get_fences_rcu to make the exclusive fence
pointer optional.
If not specified the exclusive fence is put into the fence array as
well.
This is helpful for a couple of cases where we need all fences in a
single array.
Signed-off-by: Christian König
---
drivers/dma-buf/reservation.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/dma-buf/reservation.c b/drivers/dma-buf/reservation.c
index b759a569b7b8..461afa9febd4 100644
--- a/drivers/dma-buf/reservation.c
+++ b/drivers/dma-buf/reservation.c
@@ -374,8 +374,9 @@ EXPORT_SYMBOL(reservation_object_copy_fences);
* @pshared: the array of shared fence ptrs returned (array is krealloc'd to
* the required size, and must be freed by caller)
*
- * RETURNS
- * Zero or -errno
+ * Retrieve all fences from the reservation object. If the pointer for the
+ * exclusive fence is not specified the fence is put into the array of the
+ * shared fences as well. Returns either zero or -ENOMEM.
*/
int reservation_object_get_fences_rcu(struct reservation_object *obj,
struct dma_fence **pfence_excl,
@@ -389,8 +390,8 @@ int reservation_object_get_fences_rcu(struct
reservation_object *obj,
do {
struct reservation_object_list *fobj;
- unsigned seq;
- unsigned int i;
+ unsigned int i, seq;
+ size_t sz = 0;
shared_count = i = 0;
@@ -402,9 +403,14 @@ int reservation_object_get_fences_rcu(struct
reservation_object *obj,
goto unlock;
fobj = rcu_dereference(obj->fence);
- if (fobj) {
+ if (fobj)
+ sz += sizeof(*shared) * fobj->shared_max;
+
+ if (!pfence_excl && fence_excl)
+ sz += sizeof(*shared);
+
+ if (sz) {
struct dma_fence **nshared;
- size_t sz = sizeof(*shared) * fobj->shared_max;
nshared = krealloc(shared, sz,
GFP_NOWAIT | __GFP_NOWARN);
@@ -420,13 +426,19 @@ int reservation_object_get_fences_rcu(struct
reservation_object *obj,
break;
}
shared = nshared;
- shared_count = fobj->shared_count;
-
+ shared_count = fobj ? fobj->shared_count : 0;
for (i = 0; i < shared_count; ++i) {
shared[i] = rcu_dereference(fobj->shared[i]);
if (!dma_fence_get_rcu(shared[i]))
break;
}
+
+ if (!pfence_excl && fence_excl) {
+ shared[i] = fence_excl;
+ fence_excl = NULL;
+ ++i;
+ ++shared_count;
+ }
}
if (i != shared_count || read_seqcount_retry(&obj->seq, seq)) {
@@ -448,7 +460,8 @@ int reservation_object_get_fences_rcu(struct
reservation_object *obj,
*pshared_count = shared_count;
*pshared = shared;
- *pfence_excl = fence_excl;
+ if (pfence_excl)
+ *pfence_excl = fence_excl;
return ret;
}
--
2.14.1
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[PATCH 17/21] drm/amdgpu: add PASID mapping for VCE v4
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 4e93dfe945f8..968f14a3cc0b 100755
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -35,6 +35,7 @@
#include "vce/vce_4_0_offset.h"
#include "vce/vce_4_0_default.h"
#include "vce/vce_4_0_sh_mask.h"
+#include "oss/osssys_4_0_offset.h"
#include "mmhub/mmhub_1_0_offset.h"
#include "mmhub/mmhub_1_0_sh_mask.h"
@@ -968,10 +969,12 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring
*ring,
unsigned int vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -984,6 +987,11 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring
*ring,
amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+ amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
+ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+ amdgpu_ring_write(ring, reg);
+ amdgpu_ring_write(ring, pasid);
+
amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, 0x);
@@ -1070,7 +1078,7 @@ static const struct amdgpu_ring_funcs
vce_v4_0_ring_vm_funcs = {
.set_wptr = vce_v4_0_ring_set_wptr,
.parse_cs = amdgpu_vce_ring_parse_cs_vm,
.emit_frame_size =
- 17 + /* vce_v4_0_emit_vm_flush */
+ 20 + /* vce_v4_0_emit_vm_flush */
5 + 5 + /* amdgpu_vce_ring_emit_fence x2 vm fence */
1, /* vce_v4_0_ring_insert_end */
.emit_ib_size = 5, /* vce_v4_0_ring_emit_ib */
--
2.14.1
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[PATCH 20/21] drm/amdgpu: print the PASID with VM faults on GMC v7
Print that extra information on GMC v7.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index b73599912b42..6b2896d057fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -746,21 +746,21 @@ static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
*
* Print human readable fault information (CIK).
*/
-static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
-u32 status, u32 addr, u32 mc_client)
+static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
+u32 addr, u32 mc_client, unsigned pasid)
{
- u32 mc_id;
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
VMID);
u32 protections = REG_GET_FIELD(status,
VM_CONTEXT1_PROTECTION_FAULT_STATUS,
PROTECTIONS);
char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
+ u32 mc_id;
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_ID);
- dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s'
(0x%08x) (%d)\n",
- protections, vmid, addr,
+ dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s
from '%s' (0x%08x) (%d)\n",
+ protections, vmid, pasid, addr,
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_RW) ?
"write" : "read", block, mc_client, mc_id);
@@ -1254,7 +1254,8 @@ static int gmc_v7_0_process_interrupt(struct
amdgpu_device *adev,
addr);
dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS
0x%08X\n",
status);
- gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
+ gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
+entry->pasid);
}
return 0;
--
2.14.1
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[PATCH 03/21] drm/amdgpu: add amdgpu_pasid_free_delayed
Free up a pasid after all fences signaled.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 73 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 2 +
2 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 5248a3232aff..63c9fb0361c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -40,6 +40,12 @@
*/
static DEFINE_IDA(amdgpu_pasid_ida);
+/* Helper to free pasid from a fence callback */
+struct amdgpu_pasid_cb {
+ struct dma_fence_cb cb;
+ unsigned int pasid;
+};
+
/**
* amdgpu_pasid_alloc - Allocate a PASID
* @bits: Maximum width of the PASID in bits, must be at least 1
@@ -75,6 +81,73 @@ void amdgpu_pasid_free(unsigned int pasid)
ida_simple_remove(&amdgpu_pasid_ida, pasid);
}
+static void amdgpu_pasid_free_cb(struct dma_fence *fence,
+struct dma_fence_cb *_cb)
+{
+ struct amdgpu_pasid_cb *cb =
+ container_of(_cb, struct amdgpu_pasid_cb, cb);
+
+ amdgpu_pasid_free(cb->pasid);
+ dma_fence_put(fence);
+ kfree(cb);
+}
+
+/**
+ * amdgpu_pasid_free_delayed - free pasid when fences signal
+ *
+ * @resv: reservation object with the fences to wait for
+ * @pasid: pasid to free
+ *
+ * Free the pasid only after all the fences in resv are signaled.
+ */
+void amdgpu_pasid_free_delayed(struct reservation_object *resv,
+ unsigned int pasid)
+{
+ struct dma_fence *fence, **fences;
+ struct amdgpu_pasid_cb *cb;
+ unsigned count;
+ int r;
+
+ r = reservation_object_get_fences_rcu(resv, NULL, &count, &fences);
+ if (r) {
+ /* Not enough memory to grab the fence list, as last resort
+* block for all the fences to complete.
+*/
+ reservation_object_wait_timeout_rcu(resv, true, false,
+ MAX_SCHEDULE_TIMEOUT);
+ amdgpu_pasid_free(pasid);
+ return;
+ }
+
+ if (count == 0) {
+ amdgpu_pasid_free(pasid);
+ return;
+ }
+
+ if (count == 1) {
+ fence = fences[0];
+ kfree(fences);
+ } else {
+ uint64_t context = dma_fence_context_alloc(1);
+
+ fence = &dma_fence_array_create(count, fences, context,
+ 1, false)->base;
+ }
+
+ cb = kmalloc(sizeof(*cb), GFP_KERNEL);
+ if (!cb) {
+ /* Last resort when we are OOM */
+ dma_fence_wait(fence, false);
+ dma_fence_put(fence);
+ amdgpu_pasid_free(pasid);
+ } else {
+ cb->pasid = pasid;
+ if (dma_fence_add_callback(fence, &cb->cb,
+ amdgpu_pasid_free_cb))
+ amdgpu_pasid_free_cb(fence, &cb->cb);
+ }
+}
+
/*
* VMID manager
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
index ad931fa570b3..38f37c16fc5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -69,6 +69,8 @@ struct amdgpu_vmid_mgr {
int amdgpu_pasid_alloc(unsigned int bits);
void amdgpu_pasid_free(unsigned int pasid);
+void amdgpu_pasid_free_delayed(struct reservation_object *resv,
+ unsigned int pasid);
bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
struct amdgpu_vmid *id);
--
2.14.1
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[PATCH 14/21] drm/amdgpu: add PASID mapping for GFX v9
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5a9cf6a8817f..baaa3ab9f268 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -32,6 +32,7 @@
#include "gc/gc_9_0_sh_mask.h"
#include "vega10_enum.h"
#include "hdp/hdp_4_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
#include "soc15_common.h"
#include "clearstate_gfx9.h"
@@ -3686,11 +3687,13 @@ static void gfx_v9_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -3703,6 +3706,9 @@ static void gfx_v9_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
hub->ctx0_ptb_addr_hi32 + (2 * vmid),
upper_32_bits(pd_addr));
+ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
+ gfx_v9_0_write_data_to_reg(ring, usepfp, true, reg, pasid);
+
gfx_v9_0_write_data_to_reg(ring, usepfp, true,
hub->vm_inv_eng0_req + eng, req);
@@ -4298,7 +4304,7 @@ static const struct amdgpu_ring_funcs
gfx_v9_0_ring_funcs_gfx = {
.emit_frame_size = /* totally 242 maximum if 16 IBs */
5 + /* COND_EXEC */
7 + /* PIPELINE_SYNC */
- 24 + /* VM_FLUSH */
+ 29 + /* VM_FLUSH */
8 + /* FENCE for VM_FLUSH */
20 + /* GDS switch */
4 + /* double SWITCH_BUFFER,
@@ -4346,7 +4352,7 @@ static const struct amdgpu_ring_funcs
gfx_v9_0_ring_funcs_compute = {
7 + /* gfx_v9_0_ring_emit_hdp_flush */
5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
- 24 + /* gfx_v9_0_ring_emit_vm_flush */
+ 29 + /* gfx_v9_0_ring_emit_vm_flush */
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm
fence */
.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
@@ -4377,7 +4383,7 @@ static const struct amdgpu_ring_funcs
gfx_v9_0_ring_funcs_kiq = {
7 + /* gfx_v9_0_ring_emit_hdp_flush */
5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
- 24 + /* gfx_v9_0_ring_emit_vm_flush */
+ 29 + /* gfx_v9_0_ring_emit_vm_flush */
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence,
vm fence */
.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
--
2.14.1
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[PATCH 07/21] drm/amdgpu: forward pasid to backend flush implementations
rd the pasid from the VM code to the emit_vm_flush function and update
all implementations with the new parameter.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 6 --
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c| 6 --
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c| 6 --
18 files changed, 42 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b7c181ebfe4e..e828f174bdef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1124,8 +1124,9 @@ struct amdgpu_job {
void*owner;
uint64_tfence_ctx; /* the fence_context this job uses */
boolvm_needs_flush;
- unsignedvmid;
uint64_tvm_pd_addr;
+ unsignedvmid;
+ unsignedpasid;
uint32_tgds_base, gds_size;
uint32_tgws_base, gws_size;
uint32_toa_base, oa_size;
@@ -1860,7 +1861,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib),
(vmid), (c))
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
-#define amdgpu_ring_emit_vm_flush(r, vmid, addr)
(r)->funcs->emit_vm_flush((r), (vmid), (addr))
+#define amdgpu_ring_emit_vm_flush(r, vmid, pasid, addr)
(r)->funcs->emit_vm_flush((r), (vmid), (pasid), (addr))
#define amdgpu_ring_emit_fence(r, addr, seq, flags)
(r)->funcs->emit_fence((r), (addr), (seq), (flags))
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as)
(r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 63c9fb0361c0..a0601fc5b653 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -224,6 +224,7 @@ static int amdgpu_vmid_grab_reserved_locked(struct
amdgpu_vm *vm,
id->last_flush = NULL;
}
job->vmid = id - id_mgr->ids;
+ job->pasid = vm->pasid;
trace_amdgpu_vm_grab_id(vm, ring, job);
out:
return r;
@@ -375,6 +376,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
list_move_tail(&id->list, &id_mgr->ids_lru);
job->vmid = id - id_mgr->ids;
+ job->pasid = vm->pasid;
trace_amdgpu_vm_grab_id(vm, ring, job);
error:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 102dad3edf6a..12b9a06f4d21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -126,7 +126,7 @@ struct amdgpu_ring_funcs {
uint64_t seq, unsigned flags);
void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
- uint64_t pd_addr);
+ unsigned pasid, uint64_t pd_addr);
void (*emit_hdp_flush)(struct amdgpu_ring *ring);
void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index ae54335ae426..69a9a1da1b25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -512,7 +512,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct
amdgpu_job *job, bool need_
struct dma_fence *fence;
trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
- amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
+ amdgpu_ring_emit_vm_flush(ring, job->vmid, job->pasid,
+ job->vm_pd_addr);
r = amdgpu_fence_emit(ring, &fence);
if (r)
diff --git a/drivers/gpu/drm/am
[PATCH 10/21] drm/amdgpu: add PASID mapping for SDMA v3
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index a17db3ff7e5c..f55f8bd68f17 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1137,6 +1137,11 @@ static void sdma_v3_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
}
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+ amdgpu_ring_write(ring, (mmIH_VMID_0_LUT + vmid));
+ amdgpu_ring_write(ring, pasid);
+
/* flush TLB */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
@@ -1640,7 +1645,7 @@ static const struct amdgpu_ring_funcs
sdma_v3_0_ring_funcs = {
6 + /* sdma_v3_0_ring_emit_hdp_flush */
3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
6 + /* sdma_v3_0_ring_emit_pipeline_sync */
- 12 + /* sdma_v3_0_ring_emit_vm_flush */
+ 15 + /* sdma_v3_0_ring_emit_vm_flush */
10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence,
vm fence */
.emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
.emit_ib = sdma_v3_0_ring_emit_ib,
--
2.14.1
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[PATCH 02/21] drm/amdgpu: fix amdgpu_vm_pasid_fault_credit
As soon as the lock is dropped the VM pointer can be invalid.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 7b1dae663bd0..ae54335ae426 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2478,17 +2478,21 @@ bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device
*adev,
spin_lock(&adev->vm_manager.pasid_lock);
vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
- spin_unlock(&adev->vm_manager.pasid_lock);
- if (!vm)
+ if (!vm) {
/* VM not found, can't track fault credit */
+ spin_unlock(&adev->vm_manager.pasid_lock);
return true;
+ }
/* No lock needed. only accessed by IRQ handler */
- if (!vm->fault_credit)
+ if (!vm->fault_credit) {
/* Too many faults in this VM */
+ spin_unlock(&adev->vm_manager.pasid_lock);
return false;
+ }
vm->fault_credit--;
+ spin_unlock(&adev->vm_manager.pasid_lock);
return true;
}
--
2.14.1
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[PATCH 16/21] drm/amdgpu: add PASID mapping for UVD v7
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 68e221ad0b15..4a1dd7b96766 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -31,6 +31,7 @@
#include "uvd/uvd_7_0_offset.h"
#include "uvd/uvd_7_0_sh_mask.h"
+#include "oss/osssys_4_0_offset.h"
#include "vce/vce_4_0_offset.h"
#include "vce/vce_4_0_default.h"
#include "vce/vce_4_0_sh_mask.h"
@@ -1294,8 +1295,9 @@ static void uvd_v7_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
uint32_t data0, data1, mask;
@@ -1311,6 +1313,10 @@ static void uvd_v7_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
data1 = lower_32_bits(pd_addr);
uvd_v7_0_vm_reg_write(ring, data0, data1);
+ data0 = (SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid) << 2;
+ data1 = pasid;
+ uvd_v7_0_vm_reg_write(ring, data0, data1);
+
data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
mask = 0x;
@@ -1347,10 +1353,11 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned int vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
- unsigned eng = ring->vm_inv_eng;
+ unsigned eng = ring->vm_inv_eng, reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -1363,6 +1370,11 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
+ reg = (SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid) << 2;
+ amdgpu_ring_write(ring, reg);
+ amdgpu_ring_write(ring, pasid);
+
amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, 0x);
@@ -1716,7 +1728,7 @@ static const struct amdgpu_ring_funcs
uvd_v7_0_ring_vm_funcs = {
.emit_frame_size =
2 + /* uvd_v7_0_ring_emit_hdp_flush */
2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
- 34 + /* uvd_v7_0_ring_emit_vm_flush */
+ 40 + /* uvd_v7_0_ring_emit_vm_flush */
14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
.emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
.emit_ib = uvd_v7_0_ring_emit_ib,
@@ -1742,7 +1754,7 @@ static const struct amdgpu_ring_funcs
uvd_v7_0_enc_ring_vm_funcs = {
.get_wptr = uvd_v7_0_enc_ring_get_wptr,
.set_wptr = uvd_v7_0_enc_ring_set_wptr,
.emit_frame_size =
- 17 + /* uvd_v7_0_enc_ring_emit_vm_flush */
+ 20 + /* uvd_v7_0_enc_ring_emit_vm_flush */
5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1, /* uvd_v7_0_enc_ring_insert_end */
.emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
--
2.14.1
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[PATCH 19/21] drm/amdgpu: rename pas_id to pasid
sed -i "s/pas_id/pasid/g" drivers/gpu/drm/amd/amdgpu/*.c
sed -i "s/pas_id/pasid/g" drivers/gpu/drm/amd/amdgpu/*.h
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 8
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cz_ih.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vega10_ih.c| 2 +-
8 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 29cf10927a92..b8a7dba69595 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -109,7 +109,7 @@ struct amdgpu_iv_entry {
unsigned vmid_src;
uint64_t timestamp;
unsigned timestamp_src;
- unsigned pas_id;
+ unsigned pasid;
unsigned pasid_src;
unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
const uint32_t *iv_entry;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index fc79c19917e6..532263ab6e16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -86,7 +86,7 @@ TRACE_EVENT(amdgpu_iv,
__field(unsigned, vmid_src)
__field(uint64_t, timestamp)
__field(unsigned, timestamp_src)
-__field(unsigned, pas_id)
+__field(unsigned, pasid)
__array(unsigned, src_data, 4)
),
TP_fast_assign(
@@ -97,16 +97,16 @@ TRACE_EVENT(amdgpu_iv,
__entry->vmid_src = iv->vmid_src;
__entry->timestamp = iv->timestamp;
__entry->timestamp_src = iv->timestamp_src;
- __entry->pas_id = iv->pas_id;
+ __entry->pasid = iv->pasid;
__entry->src_data[0] = iv->src_data[0];
__entry->src_data[1] = iv->src_data[1];
__entry->src_data[2] = iv->src_data[2];
__entry->src_data[3] = iv->src_data[3];
),
- TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu
pas_id:%u src_data: %08x %08x %08x %08x\n",
+ TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu
pasid:%u src_data: %08x %08x %08x %08x\n",
__entry->client_id, __entry->src_id,
__entry->ring_id, __entry->vmid,
- __entry->timestamp, __entry->pas_id,
+ __entry->timestamp, __entry->pasid,
__entry->src_data[0], __entry->src_data[1],
__entry->src_data[2], __entry->src_data[3])
);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index d5a05c19708f..07c7852180d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -281,7 +281,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
entry->src_data[0] = dw[1] & 0xfff;
entry->ring_id = dw[2] & 0xff;
entry->vmid = (dw[2] >> 8) & 0xff;
- entry->pas_id = (dw[2] >> 16) & 0x;
+ entry->pasid = (dw[2] >> 16) & 0x;
/* wptr/rptr are in bytes! */
adev->irq.ih.rptr += 16;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index f576e9cbbc61..cfd0ad03c938 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -260,7 +260,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
entry->src_data[0] = dw[1] & 0xfff;
entry->ring_id = dw[2] & 0xff;
entry->vmid = (dw[2] >> 8) & 0xff;
- entry->pas_id = (dw[2] >> 16) & 0x;
+ entry->pasid = (dw[2] >> 16) & 0x;
/* wptr/rptr are in bytes! */
adev->irq.ih.rptr += 16;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7ec54c23c07d..aca837c004c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -262,10 +262,10 @@ static int gmc_v9_0_process_interrupt(struct
amdgpu_device *adev,
if (printk_ratelimit()) {
dev_err(adev->dev,
- "[%s] VMC page fault (src_id:%u ring:%u vmid:%u
pas_id:%u)\n",
+ "[%s] VMC page fault (src_id:%u ring:%u vmid:%u
pasid:%u)\n",
entry->vmid_src ? "mmhub" : "gfxhub",
entry->src_id, entry->ring_id, entry->vmid,
- entry->pas_id);
+ e
[PATCH 21/21] drm/amdgpu: print the PASID with VM faults on GMC v8
Print that extra information on GMC v8.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 287228315b76..5b4f6c1f0993 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -962,21 +962,21 @@ static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
*
* Print human readable fault information (CIK).
*/
-static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
-u32 status, u32 addr, u32 mc_client)
+static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
+u32 addr, u32 mc_client, unsigned pasid)
{
- u32 mc_id;
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
VMID);
u32 protections = REG_GET_FIELD(status,
VM_CONTEXT1_PROTECTION_FAULT_STATUS,
PROTECTIONS);
char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
+ u32 mc_id;
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_ID);
- dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s'
(0x%08x) (%d)\n",
- protections, vmid, addr,
+ dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s
from '%s' (0x%08x) (%d)\n",
+ protections, vmid, pasid, addr,
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_RW) ?
"write" : "read", block, mc_client, mc_id);
@@ -1404,7 +1404,8 @@ static int gmc_v8_0_process_interrupt(struct
amdgpu_device *adev,
addr);
dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS
0x%08X\n",
status);
- gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
+ gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
+entry->pasid);
}
return 0;
--
2.14.1
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[PATCH 09/21] drm/amdgpu: add PASID mapping for SDMA v2.4
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index b843f5bc52c9..824390b83c87 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -871,6 +871,11 @@ static void sdma_v2_4_ring_emit_vm_flush(struct
amdgpu_ring *ring,
}
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+ amdgpu_ring_write(ring, (mmIH_VMID_0_LUT + vmid));
+ amdgpu_ring_write(ring, pasid);
+
/* flush TLB */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
@@ -1206,7 +1211,7 @@ static const struct amdgpu_ring_funcs
sdma_v2_4_ring_funcs = {
6 + /* sdma_v2_4_ring_emit_hdp_flush */
3 + /* sdma_v2_4_ring_emit_hdp_invalidate */
6 + /* sdma_v2_4_ring_emit_pipeline_sync */
- 12 + /* sdma_v2_4_ring_emit_vm_flush */
+ 15 + /* sdma_v2_4_ring_emit_vm_flush */
10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence,
vm fence */
.emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
.emit_ib = sdma_v2_4_ring_emit_ib,
--
2.14.1
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[PATCH 12/21] drm/amdgpu: add PASID mapping for GFX v7
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index ff9111656ad7..d260549b2848 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3255,6 +3255,13 @@ static void gfx_v7_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+WRITE_DATA_DST_SEL(0)));
+ amdgpu_ring_write(ring, mmIH_VMID_0_LUT + vmid);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, pasid);
+
/* bits 0-15 are the VM contexts0-15 */
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
@@ -5117,7 +5124,7 @@ static const struct amdgpu_ring_funcs
gfx_v7_0_ring_funcs_gfx = {
5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user
fence, vm fence */
7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
- 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
+ 22 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
@@ -5147,7 +5154,7 @@ static const struct amdgpu_ring_funcs
gfx_v7_0_ring_funcs_compute = {
7 + /* gfx_v7_0_ring_emit_hdp_flush */
5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
7 + /* gfx_v7_0_ring_emit_pipeline_sync */
- 17 + /* gfx_v7_0_ring_emit_vm_flush */
+ 22 + /* gfx_v7_0_ring_emit_vm_flush */
7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user
fence, vm fence */
.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
.emit_ib = gfx_v7_0_ring_emit_ib_compute,
--
2.14.1
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[PATCH 08/21] drm/amdgpu: add PASID mapping for CIK SDMA
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 985a6868b0a8..1d4787b78779 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -894,6 +894,10 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring
*ring,
}
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ amdgpu_ring_write(ring, (mmIH_VMID_0_LUT + vmid));
+ amdgpu_ring_write(ring, pasid);
+
/* flush TLB */
amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
@@ -1282,7 +1286,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs
= {
6 + /* cik_sdma_ring_emit_hdp_flush */
3 + /* cik_sdma_ring_emit_hdp_invalidate */
6 + /* cik_sdma_ring_emit_pipeline_sync */
- 12 + /* cik_sdma_ring_emit_vm_flush */
+ 15 + /* cik_sdma_ring_emit_vm_flush */
9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm
fence */
.emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
.emit_ib = cik_sdma_ring_emit_ib,
--
2.14.1
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[PATCH 18/21] drm/amdgpu: add PASID mapping for VCN v1
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 171e5e406b8b..05e5bed965c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -31,6 +31,7 @@
#include "vcn/vcn_1_0_offset.h"
#include "vcn/vcn_1_0_sh_mask.h"
#include "hdp/hdp_4_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
#include "mmhub/mmhub_9_1_offset.h"
#include "mmhub/mmhub_9_1_sh_mask.h"
@@ -891,8 +892,9 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
uint32_t data0, data1, mask;
@@ -908,6 +910,10 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct
amdgpu_ring *ring,
data1 = lower_32_bits(pd_addr);
vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
+ data0 = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+ data1 = pasid;
+ vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
+
data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
data1 = lower_32_bits(pd_addr);
mask = 0x;
@@ -1025,10 +1031,12 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned int vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -1043,6 +1051,11 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
(hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+ amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
+ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+ amdgpu_ring_write(ring, reg << 2);
+ amdgpu_ring_write(ring, pasid);
+
amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
amdgpu_ring_write(ring,
(hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
@@ -1136,7 +1149,7 @@ static const struct amdgpu_ring_funcs
vcn_v1_0_dec_ring_vm_funcs = {
.set_wptr = vcn_v1_0_dec_ring_set_wptr,
.emit_frame_size =
2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
- 34 + /* vcn_v1_0_dec_ring_emit_vm_flush */
+ 40 + /* vcn_v1_0_dec_ring_emit_vm_flush */
14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
6,
.emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
@@ -1164,7 +1177,7 @@ static const struct amdgpu_ring_funcs
vcn_v1_0_enc_ring_vm_funcs = {
.get_wptr = vcn_v1_0_enc_ring_get_wptr,
.set_wptr = vcn_v1_0_enc_ring_set_wptr,
.emit_frame_size =
- 17 + /* vcn_v1_0_enc_ring_emit_vm_flush */
+ 20 + /* vcn_v1_0_enc_ring_emit_vm_flush */
5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
1, /* vcn_v1_0_enc_ring_insert_end */
.emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
--
2.14.1
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[PATCH 13/21] drm/amdgpu: add PASID mapping for GFX v8
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4d1f9404d17e..70c517b5d012 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6347,6 +6347,14 @@ static void gfx_v8_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, pd_addr >> 12);
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+WRITE_DATA_DST_SEL(0)) |
+WR_CONFIRM);
+ amdgpu_ring_write(ring, mmIH_VMID_0_LUT + vmid);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, pasid);
+
/* bits 0-15 are the VM contexts0-15 */
/* invalidate the cache */
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -6872,7 +6880,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_gfx = {
.emit_frame_size = /* maximum 215dw if count 16 IBs in */
5 + /* COND_EXEC */
7 + /* PIPELINE_SYNC */
- 19 + /* VM_FLUSH */
+ 24 + /* VM_FLUSH */
8 + /* FENCE for VM_FLUSH */
20 + /* GDS switch */
4 + /* double SWITCH_BUFFER,
@@ -6918,7 +6926,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_compute = {
7 + /* gfx_v8_0_ring_emit_hdp_flush */
5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
7 + /* gfx_v8_0_ring_emit_pipeline_sync */
- 17 + /* gfx_v8_0_ring_emit_vm_flush */
+ 22 + /* gfx_v8_0_ring_emit_vm_flush */
7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user
fence, vm fence */
.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
.emit_ib = gfx_v8_0_ring_emit_ib_compute,
@@ -6948,7 +6956,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_kiq = {
7 + /* gfx_v8_0_ring_emit_hdp_flush */
5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
7 + /* gfx_v8_0_ring_emit_pipeline_sync */
- 17 + /* gfx_v8_0_ring_emit_vm_flush */
+ 22 + /* gfx_v8_0_ring_emit_vm_flush */
7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence,
vm fence */
.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
.emit_ib = gfx_v8_0_ring_emit_ib_compute,
--
2.14.1
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[PATCH 11/21] drm/amdgpu: add PASID mapping for SDMA v4
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 64926191edd7..c3f34d1a7169 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -35,6 +35,7 @@
#include "mmhub/mmhub_1_0_sh_mask.h"
#include "hdp/hdp_4_0_offset.h"
#include "sdma0/sdma0_4_1_default.h"
+#include "oss/osssys_4_0_offset.h"
#include "soc15_common.h"
#include "soc15.h"
@@ -1136,10 +1137,12 @@ static void sdma_v4_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
unsigned vmid, unsigned pasid,
uint64_t pd_addr)
{
- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = adev->gart.gart_funcs->get_invalidate_req(vmid);
uint64_t flags = AMDGPU_PTE_VALID;
unsigned eng = ring->vm_inv_eng;
+ uint32_t reg;
amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
pd_addr |= flags;
@@ -1154,6 +1157,12 @@ static void sdma_v4_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vmid * 2);
amdgpu_ring_write(ring, upper_32_bits(pd_addr));
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+ amdgpu_ring_write(ring, reg);
+ amdgpu_ring_write(ring, pasid);
+
/* flush TLB */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
--
2.14.1
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[PATCH 15/21] drm/amdgpu: add PASID mapping for UVD v6
This way we can see the PASID in VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index c6e22eff89e7..4122cca65785 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1077,6 +1077,13 @@ static void uvd_v6_0_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
amdgpu_ring_write(ring, 0x8);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+ amdgpu_ring_write(ring, (mmIH_VMID_0_LUT + vmid) << 2);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
+ amdgpu_ring_write(ring, pasid);
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
+ amdgpu_ring_write(ring, 0x8);
+
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
@@ -1135,6 +1142,8 @@ static void uvd_v6_0_enc_ring_emit_vm_flush(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, vmid);
amdgpu_ring_write(ring, pd_addr >> 12);
+ /* TODO: PASID handling. */
+
amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
amdgpu_ring_write(ring, vmid);
}
@@ -1580,7 +1589,7 @@ static const struct amdgpu_ring_funcs
uvd_v6_0_ring_vm_funcs = {
2 + /* uvd_v6_0_ring_emit_hdp_flush */
2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
10 + /* uvd_v6_0_ring_emit_pipeline_sync */
- 20 + /* uvd_v6_0_ring_emit_vm_flush */
+ 26 + /* uvd_v6_0_ring_emit_vm_flush */
14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
.emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
.emit_ib = uvd_v6_0_ring_emit_ib,
--
2.14.1
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Re: [PATCH] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory
Reviewed-by: Ken Wang From: Junwei Zhang Sent: Wednesday, January 10, 2018 4:18:30 PM To: amd-gfx@lists.freedesktop.org Cc: Wang, Ken; Zhang, Jerry Subject: [PATCH] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..5f2ae77 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1069,7 +1069,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr += SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(0) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS | + PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: AMD DC test results
On Thu, Dec 21, 2017 at 1:45 PM, Daniel Drake wrote: > Hi, Hi again, in Endless we are still actively working with DC on several laptops, so I just wanted to give you a quick update regarding the regressions indicated in Daniel's email. > 1. System hangs on S3 resume. > Bug can't be reproduced when booting with amdgpu.dc=0 > Also reproduced with DC on Linus master (4.15-rc), but appears fixed > on agd5f/amd-staging-drm-next > https://bugs.freedesktop.org/show_bug.cgi?id=104281 This keeps being an issue. Unfortunately (as stated in the bug report) this problem is still reproducible on the agd5f/amd-staging-drm-next branch (tested it today with HEAD at 95b5f44) even though the frequency is not high (maybe 1/10 suspends or less). In the bug report you can find the dmesg log if interested. > 2. Display corruption when using multiple displays > Bug can't be reproduced when booting with amdgpu.dc=0 > Also reproduced with DC on Linus master (4.15-rc), but appears fixed > on agd5f/amd-staging-drm-next > https://bugs.freedesktop.org/show_bug.cgi?id=104319 I was able to bisect this problem down to 1 specific commit (see [0]). > 3. HDMI audio device still shown as present and active even after > disconnecting HDMI cable > Bug can't be reproduced when booting with amdgpu.dc=0 > Appears fixed with DC on Linus master (4.15-rc). This was indeed fixed in on Linus master. Thank you very much for the DC work! Cheers, [0] https://www.spinics.net/lists/dri-devel/msg161258.html -- Carlo Caione | +44.7384.69.16.04 | Endless ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 2/3] drm: export gem dmabuf_ops for drivers to reuse
OK. I'll do it.
Samuel Li
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Wednesday, January 10, 2018 3:17 AM
> To: Alex Deucher
> Cc: Deucher, Alexander ; Li, Samuel
> ; Daniel Vetter ; Koenig, Christian
> ; dri-de...@lists.freedesktop.org; amd-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH 2/3] drm: export gem dmabuf_ops for drivers to reuse
>
> On Tue, Jan 09, 2018 at 01:13:08PM -0500, Alex Deucher wrote:
> > On Tue, Jan 9, 2018 at 10:56 AM, Deucher, Alexander
> > wrote:
> > > I'll can push this and a few other misc patches today.
> > >
> >
> > Pushed to drm-misc-next.
>
> One thing I just noticed: Some kerneldoc for the newly exported functions
> and maybe a small update to the intro section to explain what to do with this
> would be neat.
> -Daniel
>
> >
> > Thanks,
> >
> > Alex
> >
> >
> > >
> > > Alex
> > >
> > > From: amd-gfx on behalf of
> > > Li, Samuel
> > > Sent: Tuesday, January 9, 2018 10:20 AM
> > > To: Daniel Vetter; Koenig, Christian
> > > Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> > > Subject: RE: [PATCH 2/3] drm: export gem dmabuf_ops for drivers to
> > > reuse
> > >
> > > Yes, please hush this for me.
> > >
> > > Regards,
> > > Samuel Li
> > >
> > >
> > >> -Original Message-
> > >> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> > >> Daniel Vetter
> > >> Sent: Tuesday, January 09, 2018 4:22 AM
> > >> To: Koenig, Christian
> > >> Cc: Li, Samuel ;
> > >> dri-de...@lists.freedesktop.org; amd- g...@lists.freedesktop.org
> > >> Subject: Re: [PATCH 2/3] drm: export gem dmabuf_ops for drivers to
> > >> reuse
> > >>
> > >> On Fri, Jan 05, 2018 at 10:16:04AM +0100, Christian König wrote:
> > >> > Am 04.01.2018 um 22:12 schrieb Samuel Li:
> > >> > > Change-Id: I03c22a890d2305f3243d88019d1a28bddd4ddda7
> > >> > > Signed-off-by: Samuel Li
> > >> >
> > >> > Reviewed-by: Christian König
> > >>
> > >> Want to push to drm-misc or some other plan with this?
> > >> -Daniel
> > >>
> > >> >
> > >> > > ---
> > >> > > drivers/gpu/drm/drm_prime.c | 53
> > >> > > ++---
> > >>
> > >> > > include/drm/drm_prime.h | 22 +++
> > >> > > 2 files changed, 53 insertions(+), 22 deletions(-)
> > >> > >
> > >> > > diff --git a/drivers/gpu/drm/drm_prime.c
> > >> > > b/drivers/gpu/drm/drm_prime.c index 8de93a2..68a69e9 100644
> > >> > > --- a/drivers/gpu/drm/drm_prime.c
> > >> > > +++ b/drivers/gpu/drm/drm_prime.c
> > >> > > @@ -180,9 +180,8 @@ static int
> > >> > > drm_prime_lookup_buf_handle(struct
> > >> drm_prime_file_private *prime_fpri
> > >> > >return -ENOENT;
> > >> > > }
> > >> > > -static int drm_gem_map_attach(struct dma_buf *dma_buf,
> > >> > > - struct device *target_dev,
> > >> > > - struct dma_buf_attachment *attach)
> > >> > > +int drm_gem_map_attach(struct dma_buf *dma_buf, struct
> device
> > >> *target_dev,
> > >> > > +struct dma_buf_attachment *attach)
> > >> > > {
> > >> > >struct drm_prime_attachment *prime_attach;
> > >> > >struct drm_gem_object *obj = dma_buf->priv; @@ -200,9
> > >> > > +199,10
> > >> @@
> > >> > > static int drm_gem_map_attach(struct dma_buf *dma_buf,
> > >> > >return dev->driver->gem_prime_pin(obj);
> > >> > > }
> > >> > > +EXPORT_SYMBOL(drm_gem_map_attach);
> > >> > > -static void drm_gem_map_detach(struct dma_buf *dma_buf,
> > >> > > -struct dma_buf_attachment *attach)
> > >> > > +void drm_gem_map_detach(struct dma_buf *dma_buf,
> > >> > > + struct dma_buf_attachment *attach)
> > >> > > {
> > >> > >struct drm_prime_attachment *prime_attach = attach->priv;
> > >> > >struct drm_gem_object *obj = dma_buf->priv; @@ -227,6 +227,7
> > >> @@
> > >> > > static void drm_gem_map_detach(struct dma_buf *dma_buf,
> > >> > >kfree(prime_attach);
> > >> > >attach->priv = NULL;
> > >> > > }
> > >> > > +EXPORT_SYMBOL(drm_gem_map_detach);
> > >> > > void drm_prime_remove_buf_handle_locked(struct
> > >> drm_prime_file_private *prime_fpriv,
> > >> > >struct dma_buf *dma_buf) @@
> > >> > > -253,8 +254,8 @@ void
> > >> drm_prime_remove_buf_handle_locked(struct
> drm_prime_file_private
> > >> *prime_fpr
> > >> > >}
> > >> > > }
> > >> > > -static struct sg_table *drm_gem_map_dma_buf(struct
> > >> dma_buf_attachment *attach,
> > >> > > - enum dma_data_direction dir)
> > >> > > +struct sg_table *drm_gem_map_dma_buf(struct
> dma_buf_attachment
> > >> *attach,
> > >> > > + enum dma_data_direction dir)
> > >> > > {
> > >> > >struct drm_prime_attachment *prime_attach = attach->priv;
> > >> > >struct drm_gem_object *obj = attach->dmabuf->priv; @@
> > >> > > -289,13
> > >> > > +290,15 @@ static struct sg_table *drm_ge
Re: [PATCH] drm/amdgpu: fix 64bit BAR detection
Ping? Alex, David, anybody?
Am 08.01.2018 um 14:51 schrieb Christian König:
Windows added by the BIOS are not marked as 64bit because they are
usually not changeable anyway.
This fixes large BAR support on my new Ryzen build system.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e91575311646..7114f2527edc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -626,7 +626,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
root = root->parent;
pci_bus_for_each_resource(root, res, i) {
- if (res && res->flags & IORESOURCE_MEM_64 &&
+ if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
res->start > 0x1ull)
break;
}
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Re: [PATCH] drm/amdkfd: use add ull suffix to 64bit defines
Reviewed-by: Felix Kuehling On 2018-01-10 06:01 AM, Oded Gabbay wrote: > Signed-off-by: Oded Gabbay > --- > drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > index 6a48d29ada47..0bedcf9cc08c 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > @@ -41,9 +41,9 @@ > > #define KFD_SYSFS_FILE_MODE 0444 > > -#define KFD_MMAP_DOORBELL_MASK 0x8 > -#define KFD_MMAP_EVENTS_MASK 0x4 > -#define KFD_MMAP_RESERVED_MEM_MASK 0x2 > +#define KFD_MMAP_DOORBELL_MASK 0x8ull > +#define KFD_MMAP_EVENTS_MASK 0x4ull > +#define KFD_MMAP_RESERVED_MEM_MASK 0x2ull > > /* > * When working with cp scheduler we should assign the HIQ manually or via ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix 64bit BAR detection
On Mon, Jan 8, 2018 at 8:51 AM, Christian König
wrote:
> Windows added by the BIOS are not marked as 64bit because they are
> usually not changeable anyway.
>
> This fixes large BAR support on my new Ryzen build system.
>
> Signed-off-by: Christian König
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index e91575311646..7114f2527edc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -626,7 +626,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device
> *adev)
> root = root->parent;
>
> pci_bus_for_each_resource(root, res, i) {
> - if (res && res->flags & IORESOURCE_MEM_64 &&
> + if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64)
> &&
> res->start > 0x1ull)
> break;
> }
> --
> 2.14.1
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH] drm/amdkfd: Fix potential NULL pointer dereferences
In case kfd_get_process_device_data returns null, there are some
null pointer dereferences in functions kfd_bind_processes_to_device
and kfd_unbind_processes_from_device.
Fix this by null checking pdd before dereferencing it.
Addresses-Coverity-ID: 1463794 ("Dereference null return value")
Addresses-Coverity-ID: 1463772 ("Dereference null return value")
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index a22fb071..29d51d5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -461,6 +461,13 @@ int kfd_bind_processes_to_device(struct kfd_dev *dev)
hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
+
+ if (!pdd) {
+ pr_err("Process device data doesn't exist\n");
+ mutex_unlock(&p->mutex);
+ return -EFAULT;
+ }
+
if (pdd->bound != PDD_BOUND_SUSPENDED) {
mutex_unlock(&p->mutex);
continue;
@@ -501,6 +508,11 @@ void kfd_unbind_processes_from_device(struct kfd_dev *dev)
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
+ if (!pdd) {
+ mutex_unlock(&p->mutex);
+ return;
+ }
+
if (pdd->bound == PDD_BOUND)
pdd->bound = PDD_BOUND_SUSPENDED;
mutex_unlock(&p->mutex);
--
2.7.4
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Re: [PATCH] drm/amdkfd: Fix potential NULL pointer dereferences
Hi Gustavo,
Thanks for catching that. When returning a fault, I think you also need
to srcu_read_unlock(&kfd_processes_srcu, idx).
However, instead of returning an error, I think I'd prefer to skip PDDs
that can't be found with continue statements. That way others would
still suspend and resume successfully. Maybe just print a WARN_ON for
PDDs that aren't found, because that's an unexpected situation,
currently. Maybe in the future it could be normal thing if we ever
support GPU hotplug.
Regards,
Felix
On 2018-01-10 11:50 AM, Gustavo A. R. Silva wrote:
> In case kfd_get_process_device_data returns null, there are some
> null pointer dereferences in functions kfd_bind_processes_to_device
> and kfd_unbind_processes_from_device.
>
> Fix this by null checking pdd before dereferencing it.
>
> Addresses-Coverity-ID: 1463794 ("Dereference null return value")
> Addresses-Coverity-ID: 1463772 ("Dereference null return value")
> Signed-off-by: Gustavo A. R. Silva
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index a22fb071..29d51d5 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -461,6 +461,13 @@ int kfd_bind_processes_to_device(struct kfd_dev *dev)
> hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
> mutex_lock(&p->mutex);
> pdd = kfd_get_process_device_data(dev, p);
> +
> + if (!pdd) {
> + pr_err("Process device data doesn't exist\n");
> + mutex_unlock(&p->mutex);
> + return -EFAULT;
> + }
> +
> if (pdd->bound != PDD_BOUND_SUSPENDED) {
> mutex_unlock(&p->mutex);
> continue;
> @@ -501,6 +508,11 @@ void kfd_unbind_processes_from_device(struct kfd_dev
> *dev)
> mutex_lock(&p->mutex);
> pdd = kfd_get_process_device_data(dev, p);
>
> + if (!pdd) {
> + mutex_unlock(&p->mutex);
> + return;
> + }
> +
> if (pdd->bound == PDD_BOUND)
> pdd->bound = PDD_BOUND_SUSPENDED;
> mutex_unlock(&p->mutex);
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Re: [PATCH 1/2] drm/amdgpu: add custom power policy support in sysfs
On Wed, Jan 10, 2018 at 6:01 AM, Rex Zhu wrote:
> when cat pp_power_profile_mode on Vega10
> NUMMODE_NAME BUSY_SET_POINT FPS USE_RLC_BUSY MIN_ACTIVE_LEVEL
> 0 3D_FULL_SCREEN : 70 60 1 3
> 1 POWER_SAVING : 90 60 0 0
> 2 VIDEO*: 70 60 0 0
> 3 VR : 70 90 0 0
> 4 COMPUTER : 30 60 0 6
> 5 CUSTOM : 0 0 0 0
>
> the result show all the profile mode we can support and custom mode.
> user can echo the num(0-4) to pp_power_profile_mode to select the profile
> mode or can echo "5 value value value value" to enter CUSTOM mode.
> the four parameter is set_point/FPS/USER_RLC_BUSY/MIN_ACTIVE_LEVEL.
>
Is there any way we can unify this with profile stuff implemented for
smu7? I'd like to avoid lots of haphazard interfaces to support
specific use cases and asics. It becomes a maintenance nightmare.
Alex
> Change-Id: I72634646a9a179ccd57f175b4c0b3f45e538a03f
> Signed-off-by: Rex Zhu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h| 8 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 81
> +-
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 11 +++-
> 3 files changed, 98 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index 8a8d09dd..986f1d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -366,6 +366,14 @@ enum amdgpu_pcie_gen {
> (adev)->powerplay.pp_handle, virtual_addr_low, \
> virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
>
> +#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
> + ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
> + (adev)->powerplay.pp_handle, buf))
> +
> +#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
> + ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
> + (adev)->powerplay.pp_handle, parameter, size))
> +
> struct amdgpu_dpm {
> struct amdgpu_ps*ps;
> /* number of valid power states */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index e5ee7cf..662edca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -584,6 +584,73 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
> return count;
> }
>
> +static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = ddev->dev_private;
> +
> + if (adev->powerplay.pp_funcs->get_power_profile_mode)
> + return amdgpu_dpm_get_power_profile_mode(adev, buf);
> +
> + return snprintf(buf, PAGE_SIZE, "\n");
> +}
> +
> +
> +static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t count)
> +{
> + int ret = 0xff;
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = ddev->dev_private;
> + uint32_t parameter_size = 0;
> + long parameter[64];
> + char *sub_str, buf_cpy[128];
> + char *tmp_str;
> + uint32_t i = 0;
> + char tmp[2];
> + long int profile_mode = 0;
> + const char delimiter[3] = {' ', '\n', '\0'};
> +
> + tmp[0] = *(buf);
> + tmp[1] = '\0';
> + ret = kstrtol(tmp, 0, &profile_mode);
> + if (ret)
> + goto fail;
> +
> + if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
> + if (count < 2 || count > 127)
> + return -EINVAL;
> + while (isspace(*++buf))
> + i++;
> + memcpy(buf_cpy, buf, count-i);
> + tmp_str = buf_cpy;
> + while (tmp_str[0]) {
> + sub_str = strsep(&tmp_str, delimiter);
> + ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
> + if (ret) {
> + count = -EINVAL;
> + goto fail;
> + }
> + pr_info("value is %ld \n", parameter[parameter_size]);
> + parameter_size++;
> + while (isspace(*tmp_str))
> + tmp_str++;
> + }
> + }
> + parameter[parameter_size] = profile_mode;
> + if (adev->powerplay.pp_funcs->set_power_profile_mode)
> + ret = amdgpu_dpm_set
[pull] amdgpu, radeon, ttm drm-next-4.16
Hi Dave, A few fixes for 4.16: - Cleanup the the remains of ttm io_mem_pfn - A couple dpm quirks for SI - Add Chunming as another amdgpu maintainer - A few more huge page fixes - A few other misc fixes The following changes since commit fb8baefc7b2d7b93ad96abacbe63fa99e3d213d6: drm/amdgpu: use %pap format string for phys_addr_t (2018-01-09 10:59:28 +1000) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-next-4.16 for you to fetch changes up to ad8cec7df5d4bf3b1109fabbb1d61663857045ae: drm/amd/pp: Implement get_max_high_clocks for CI/VI (2018-01-10 15:44:55 -0500) Alex Deucher (4): drm/radeon: Add dpm quirk for Jet PRO (v2) drm/amdgpu: Add dpm quirk for Jet PRO (v2) drm/amdgpu: add atpx quirk handling (v2) drm/amdgpu/gfx9: only init the apertures used by KGD (v2) Christian König (8): drm/ttm: specify DMA_ATTR_NO_WARN for huge page pools drm/amdgpu: loosen the criteria for huge pages a bit drm/amdgpu: minor optimize VM moved handling v2 drm/amdgpu: update VM PDs after the PTs drm/amdgpu: simplify huge page handling drm/amdgpu: optimize moved handling only when vm_debug is inactive drm/amdgpu: fix 64bit BAR detection MAINTAINERS: add David (Chunming) Zhou as additional amdgpu maintainer Evan Quan (1): drm/amd/powerplay: set pp_num_states as 0 on error situation Rex Zhu (1): drm/amd/pp: Implement get_max_high_clocks for CI/VI Tan Xiaojun (2): staging: remove the default io_mem_pfn set drm/ttm: remove ttm_bo_default_io_mem_pfn Yintian Tao (1): drm/amd/powerplay: fix memory leakage when reload (v2) MAINTAINERS| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 57 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 8 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 8 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 78 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_dpm.c| 5 ++ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 2 + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 20 ++ drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 6 ++ drivers/gpu/drm/radeon/si_dpm.c| 5 ++ drivers/gpu/drm/ttm/ttm_bo_vm.c| 11 +-- drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 8 ++- drivers/staging/vboxvideo/vbox_ttm.c | 1 - include/drm/ttm/ttm_bo_api.h | 11 --- 16 files changed, 139 insertions(+), 86 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [pull] amdgpu, radeon, ttm drm-next-4.16
FWIW, Christian's "simplify huge page handling" broke CPU page table updates for KFD on large-BAR Vega10. It doesn't matter for Dave because KFD support on dGPUs isn't upstream yet. Regards, Felix On 2018-01-10 04:18 PM, Alex Deucher wrote: > Hi Dave, > > A few fixes for 4.16: > - Cleanup the the remains of ttm io_mem_pfn > - A couple dpm quirks for SI > - Add Chunming as another amdgpu maintainer > - A few more huge page fixes > - A few other misc fixes > > The following changes since commit fb8baefc7b2d7b93ad96abacbe63fa99e3d213d6: > > drm/amdgpu: use %pap format string for phys_addr_t (2018-01-09 10:59:28 > +1000) > > are available in the git repository at: > > git://people.freedesktop.org/~agd5f/linux drm-next-4.16 > > for you to fetch changes up to ad8cec7df5d4bf3b1109fabbb1d61663857045ae: > > drm/amd/pp: Implement get_max_high_clocks for CI/VI (2018-01-10 15:44:55 > -0500) > > > Alex Deucher (4): > drm/radeon: Add dpm quirk for Jet PRO (v2) > drm/amdgpu: Add dpm quirk for Jet PRO (v2) > drm/amdgpu: add atpx quirk handling (v2) > drm/amdgpu/gfx9: only init the apertures used by KGD (v2) > > Christian König (8): > drm/ttm: specify DMA_ATTR_NO_WARN for huge page pools > drm/amdgpu: loosen the criteria for huge pages a bit > drm/amdgpu: minor optimize VM moved handling v2 > drm/amdgpu: update VM PDs after the PTs > drm/amdgpu: simplify huge page handling > drm/amdgpu: optimize moved handling only when vm_debug is inactive > drm/amdgpu: fix 64bit BAR detection > MAINTAINERS: add David (Chunming) Zhou as additional amdgpu maintainer > > Evan Quan (1): > drm/amd/powerplay: set pp_num_states as 0 on error situation > > Rex Zhu (1): > drm/amd/pp: Implement get_max_high_clocks for CI/VI > > Tan Xiaojun (2): > staging: remove the default io_mem_pfn set > drm/ttm: remove ttm_bo_default_io_mem_pfn > > Yintian Tao (1): > drm/amd/powerplay: fix memory leakage when reload (v2) > > MAINTAINERS| 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 57 ++-- > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 8 +-- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 8 +-- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 78 > +- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/si_dpm.c| 5 ++ > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 2 + > drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 20 ++ > drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 6 ++ > drivers/gpu/drm/radeon/si_dpm.c| 5 ++ > drivers/gpu/drm/ttm/ttm_bo_vm.c| 11 +-- > drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 8 ++- > drivers/staging/vboxvideo/vbox_ttm.c | 1 - > include/drm/ttm/ttm_bo_api.h | 11 --- > 16 files changed, 139 insertions(+), 86 deletions(-) > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: BUG: KASAN: use-after-free in amdgpu_job_free_cb
On 01/09/2018 09:44 AM, Johannes Hirte wrote: On 2018 Jan 03, Johannes Hirte wrote: On 2018 Jan 03, Johannes Hirte wrote: This should be fixed already with https://lists.freedesktop.org/archives/amd-gfx/2017-October/014932.html but's still missing upstream. With this patch, the use-after-free in amdgpu_job_free_cb seems to be gone. But now I get an use-after-free in drm_atomic_helper_wait_for_flip_done: [89387.069387] == [89387.069407] BUG: KASAN: use-after-free in drm_atomic_helper_wait_for_flip_done+0x24f/0x270 [89387.069413] Read of size 8 at addr 880124df0688 by task kworker/u8:3/31426 [89387.069423] CPU: 1 PID: 31426 Comm: kworker/u8:3 Not tainted 4.15.0-rc6-1-ge0895ba8d88e #442 [89387.069427] Hardware name: HP HP ProBook 645 G2/80FE, BIOS N77 Ver. 01.10 10/12/2017 [89387.069435] Workqueue: events_unbound commit_work [89387.069440] Call Trace: [89387.069448] dump_stack+0x99/0x11e [89387.069453] ? _atomic_dec_and_lock+0x152/0x152 [89387.069460] print_address_description+0x65/0x270 [89387.069465] kasan_report+0x272/0x360 [89387.069470] ? drm_atomic_helper_wait_for_flip_done+0x24f/0x270 [89387.069475] drm_atomic_helper_wait_for_flip_done+0x24f/0x270 [89387.069483] amdgpu_dm_atomic_commit_tail+0x185e/0x2b90 [89387.069492] ? dm_crtc_duplicate_state+0x130/0x130 [89387.069498] ? drm_atomic_helper_wait_for_dependencies+0x3f2/0x800 [89387.069504] commit_tail+0x92/0xe0 [89387.069511] process_one_work+0x84b/0x1600 [89387.069517] ? tick_nohz_dep_clear_signal+0x20/0x20 [89387.069522] ? _raw_spin_unlock_irq+0xbe/0x120 [89387.069525] ? _raw_spin_unlock+0x120/0x120 [89387.069529] ? pwq_dec_nr_in_flight+0x3c0/0x3c0 [89387.069534] ? arch_vtime_task_switch+0xee/0x190 [89387.069539] ? finish_task_switch+0x27d/0x7f0 [89387.069542] ? wq_worker_waking_up+0xc0/0xc0 [89387.069547] ? copy_overflow+0x20/0x20 [89387.069550] ? sched_clock_cpu+0x18/0x1e0 [89387.069558] ? pci_mmcfg_check_reserved+0x100/0x100 [89387.069562] ? pci_mmcfg_check_reserved+0x100/0x100 [89387.069569] ? schedule+0xfb/0x3b0 [89387.069574] ? __schedule+0x19b0/0x19b0 [89387.069578] ? _raw_spin_unlock_irq+0xb9/0x120 [89387.069582] ? _raw_spin_unlock_irq+0xbe/0x120 [89387.069585] ? _raw_spin_unlock+0x120/0x120 [89387.069590] worker_thread+0x211/0x1790 [89387.069597] ? pick_next_task_fair+0x313/0x10f0 [89387.069601] ? trace_event_raw_event_workqueue_work+0x170/0x170 [89387.069606] ? __read_once_size_nocheck.constprop.6+0x10/0x10 [89387.069612] ? tick_nohz_dep_clear_signal+0x20/0x20 [89387.069616] ? account_idle_time+0x94/0x1f0 [89387.069620] ? _raw_spin_unlock_irq+0xbe/0x120 [89387.069623] ? _raw_spin_unlock+0x120/0x120 [89387.069628] ? finish_task_switch+0x27d/0x7f0 [89387.069633] ? sched_clock_cpu+0x18/0x1e0 [89387.069639] ? ret_from_fork+0x1f/0x30 [89387.069644] ? pci_mmcfg_check_reserved+0x100/0x100 [89387.069650] ? cyc2ns_read_end+0x20/0x20 [89387.069657] ? schedule+0xfb/0x3b0 [89387.069662] ? __schedule+0x19b0/0x19b0 [89387.069666] ? remove_wait_queue+0x2b0/0x2b0 [89387.069670] ? arch_vtime_task_switch+0xee/0x190 [89387.069675] ? _raw_spin_unlock_irqrestore+0xc2/0x130 [89387.069679] ? _raw_spin_unlock_irq+0x120/0x120 [89387.069683] ? trace_event_raw_event_workqueue_work+0x170/0x170 [89387.069688] kthread+0x2d4/0x390 [89387.069693] ? kthread_create_worker+0xd0/0xd0 [89387.069697] ret_from_fork+0x1f/0x30 [89387.069705] Allocated by task 2387: [89387.069712] kasan_kmalloc+0xa0/0xd0 [89387.069717] kmem_cache_alloc_trace+0xd1/0x1e0 [89387.069722] dm_crtc_duplicate_state+0x73/0x130 [89387.069726] drm_atomic_get_crtc_state+0x13c/0x400 [89387.069730] page_flip_common+0x52/0x230 [89387.069734] drm_atomic_helper_page_flip+0xa1/0x100 [89387.069739] drm_mode_page_flip_ioctl+0xc10/0x1030 [89387.069744] drm_ioctl_kernel+0x1b5/0x2c0 [89387.069748] drm_ioctl+0x709/0xa00 [89387.069752] amdgpu_drm_ioctl+0x118/0x280 [89387.069756] do_vfs_ioctl+0x18a/0x1260 [89387.069760] SyS_ioctl+0x6f/0x80 [89387.069764] do_syscall_64+0x220/0x670 [89387.069768] return_from_SYSCALL_64+0x0/0x65 [89387.069772] Freed by task 2533: [89387.069776] kasan_slab_free+0x71/0xc0 [89387.069780] kfree+0x88/0x1b0 [89387.069784] drm_atomic_state_default_clear+0x2c8/0xa00 [89387.069787] __drm_atomic_state_free+0x30/0xd0 [89387.069791] drm_atomic_helper_update_plane+0xb6/0x350 [89387.069794] __setplane_internal+0x5b4/0x9d0 [89387.069798] drm_mode_cursor_universal+0x412/0xc60 [89387.069801] drm_mode_cursor_common+0x4b6/0x890 [89387.069805] drm_mode_cursor_ioctl+0xd3/0x120 [89387.069809] drm_ioctl_kernel+0x1b5/0x2c0 [89387.069813] drm_ioctl+0x709/0xa00 [89387.069816] amdgpu_drm_ioctl+0x118/0x280 [89387.069819] do_vfs_ioctl+0x18a/0x1260 [89387.069822] SyS_ioctl+0x6f/0x80 [89387.069824] do_syscall_64+0x220/0x670 [89387.069828] return_from_SYSCALL_64+0x0/0x65 [89387.069834] The buggy address belongs to the object at 880124df0480 [89387.069839]
[PATCH] drm/amdgpu: Update MMHUB power gating register settings
The new register settings are needed to fix a tlb invalidation issue
when MMHUB power gating is turned on for Raven.
Change-Id: I846befbb2fcbddf40ca4ecbdc06da1cd442e3554
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 61 ++---
1 file changed, 33 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index ffd5b7e..bdf94c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -272,21 +272,21 @@ static const struct pctl_data pctl0_data[] = {
{0x11, 0x6a684},
{0x19, 0xea68e},
{0x29, 0xa69e},
- {0x2b, 0x34a6c0},
- {0x61, 0x83a707},
- {0xe6, 0x8a7a4},
- {0xf0, 0x1a7b8},
- {0xf3, 0xfa7cc},
- {0x104, 0x17a7dd},
- {0x11d, 0xa7dc},
- {0x11f, 0x12a7f5},
- {0x133, 0xa808},
- {0x135, 0x12a810},
- {0x149, 0x7a82c}
+ {0x2b, 0x0010a6c0},
+ {0x3d, 0x83a707},
+ {0xc2, 0x8a7a4},
+ {0xcc, 0x1a7b8},
+ {0xcf, 0xfa7cc},
+ {0xe0, 0x17a7dd},
+ {0xf9, 0xa7dc},
+ {0xfb, 0x12a7f5},
+ {0x10f, 0xa808},
+ {0x111, 0x12a810},
+ {0x125, 0x7a82c}
};
#define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data))
-#define PCTL0_RENG_EXEC_END_PTR 0x151
+#define PCTL0_RENG_EXEC_END_PTR 0x12d
#define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640
#define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
@@ -385,10 +385,9 @@ void mmhub_v1_0_initialize_power_gating(struct
amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
return;
+ /** pctl0 **/
pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC);
pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
- pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC);
- pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
/* Light sleep must be disabled before writing to pctl0 registers */
pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
@@ -402,12 +401,13 @@ void mmhub_v1_0_initialize_power_gating(struct
amdgpu_device *adev)
pctl0_data[i].data);
}
- /* Set the reng execute end ptr for pctl0 */
- pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
- PCTL0_RENG_EXECUTE,
- RENG_EXECUTE_END_PTR,
- PCTL0_RENG_EXEC_END_PTR);
- WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
+ /* Re-enable light sleep */
+ pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
+ WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
+
+ /** pctl1 **/
+ pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC);
+ pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
/* Light sleep must be disabled before writing to pctl1 registers */
pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
@@ -421,20 +421,25 @@ void mmhub_v1_0_initialize_power_gating(struct
amdgpu_device *adev)
pctl1_data[i].data);
}
+ /* Re-enable light sleep */
+ pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
+ WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
+
+ mmhub_v1_0_power_gating_write_save_ranges(adev);
+
+ /* Set the reng execute end ptr for pctl0 */
+ pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
+ PCTL0_RENG_EXECUTE,
+ RENG_EXECUTE_END_PTR,
+ PCTL0_RENG_EXEC_END_PTR);
+ WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
+
/* Set the reng execute end ptr for pctl1 */
pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
PCTL1_RENG_EXECUTE,
RENG_EXECUTE_END_PTR,
PCTL1_RENG_EXEC_END_PTR);
WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
-
- mmhub_v1_0_power_gating_write_save_ranges(adev);
-
- /* Re-enable light sleep */
- pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
- WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
- pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
- WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
}
void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
--
2.7.4
___
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Re: [PATCH] drm/amdgpu: Update MMHUB power gating register settings
On Wed, Jan 10, 2018 at 3:10 PM, Yong Zhao wrote:
> The new register settings are needed to fix a tlb invalidation issue
> when MMHUB power gating is turned on for Raven.
>
> Change-Id: I846befbb2fcbddf40ca4ecbdc06da1cd442e3554
> Signed-off-by: Yong Zhao
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 61
> ++---
> 1 file changed, 33 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index ffd5b7e..bdf94c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -272,21 +272,21 @@ static const struct pctl_data pctl0_data[] = {
> {0x11, 0x6a684},
> {0x19, 0xea68e},
> {0x29, 0xa69e},
> - {0x2b, 0x34a6c0},
> - {0x61, 0x83a707},
> - {0xe6, 0x8a7a4},
> - {0xf0, 0x1a7b8},
> - {0xf3, 0xfa7cc},
> - {0x104, 0x17a7dd},
> - {0x11d, 0xa7dc},
> - {0x11f, 0x12a7f5},
> - {0x133, 0xa808},
> - {0x135, 0x12a810},
> - {0x149, 0x7a82c}
> + {0x2b, 0x0010a6c0},
> + {0x3d, 0x83a707},
> + {0xc2, 0x8a7a4},
> + {0xcc, 0x1a7b8},
> + {0xcf, 0xfa7cc},
> + {0xe0, 0x17a7dd},
> + {0xf9, 0xa7dc},
> + {0xfb, 0x12a7f5},
> + {0x10f, 0xa808},
> + {0x111, 0x12a810},
> + {0x125, 0x7a82c}
> };
> #define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data))
>
> -#define PCTL0_RENG_EXEC_END_PTR 0x151
> +#define PCTL0_RENG_EXEC_END_PTR 0x12d
> #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640
> #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
>
> @@ -385,10 +385,9 @@ void mmhub_v1_0_initialize_power_gating(struct
> amdgpu_device *adev)
> if (amdgpu_sriov_vf(adev))
> return;
>
> + /** pctl0 **/
> pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC);
> pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
> - pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC);
> - pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
>
> /* Light sleep must be disabled before writing to pctl0 registers */
> pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
> @@ -402,12 +401,13 @@ void mmhub_v1_0_initialize_power_gating(struct
> amdgpu_device *adev)
> pctl0_data[i].data);
> }
>
> - /* Set the reng execute end ptr for pctl0 */
> - pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
> - PCTL0_RENG_EXECUTE,
> - RENG_EXECUTE_END_PTR,
> - PCTL0_RENG_EXEC_END_PTR);
> - WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
> + /* Re-enable light sleep */
> + pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
> + WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
> +
> + /** pctl1 **/
> + pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC);
> + pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
>
> /* Light sleep must be disabled before writing to pctl1 registers */
> pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
> @@ -421,20 +421,25 @@ void mmhub_v1_0_initialize_power_gating(struct
> amdgpu_device *adev)
> pctl1_data[i].data);
> }
>
> + /* Re-enable light sleep */
> + pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
> + WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
> +
> + mmhub_v1_0_power_gating_write_save_ranges(adev);
> +
> + /* Set the reng execute end ptr for pctl0 */
> + pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
> + PCTL0_RENG_EXECUTE,
> + RENG_EXECUTE_END_PTR,
> + PCTL0_RENG_EXEC_END_PTR);
> + WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
> +
> /* Set the reng execute end ptr for pctl1 */
> pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
> PCTL1_RENG_EXECUTE,
> RENG_EXECUTE_END_PTR,
> PCTL1_RENG_EXEC_END_PTR);
> WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
> -
> - mmhub_v1_0_power_gating_write_save_ranges(adev);
> -
> - /* Re-enable light sleep */
> - pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
> - WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
> - pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
> - WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
> }
>
> void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
> --
> 2.7.4
>
> ___
Re: [PATCH 1/2] drm/amdgpu: add custom power policy support in sysfs
Yes, this new interface is more common, I just save the input and send to hw
backend. Smu7 and Vega can share this interface.
Best Regards
Rex
From: Alex Deucher
Sent: Thursday, January 11, 2018 4:18:11 AM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 1/2] drm/amdgpu: add custom power policy support in sysfs
On Wed, Jan 10, 2018 at 6:01 AM, Rex Zhu wrote:
> when cat pp_power_profile_mode on Vega10
> NUMMODE_NAME BUSY_SET_POINT FPS USE_RLC_BUSY MIN_ACTIVE_LEVEL
> 0 3D_FULL_SCREEN : 70 60 1 3
> 1 POWER_SAVING : 90 60 0 0
> 2 VIDEO*: 70 60 0 0
> 3 VR : 70 90 0 0
> 4 COMPUTER : 30 60 0 6
> 5 CUSTOM : 0 0 0 0
>
> the result show all the profile mode we can support and custom mode.
> user can echo the num(0-4) to pp_power_profile_mode to select the profile
> mode or can echo "5 value value value value" to enter CUSTOM mode.
> the four parameter is set_point/FPS/USER_RLC_BUSY/MIN_ACTIVE_LEVEL.
>
Is there any way we can unify this with profile stuff implemented for
smu7? I'd like to avoid lots of haphazard interfaces to support
specific use cases and asics. It becomes a maintenance nightmare.
Alex
> Change-Id: I72634646a9a179ccd57f175b4c0b3f45e538a03f
> Signed-off-by: Rex Zhu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h| 8 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 81
> +-
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 11 +++-
> 3 files changed, 98 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index 8a8d09dd..986f1d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -366,6 +366,14 @@ enum amdgpu_pcie_gen {
> (adev)->powerplay.pp_handle, virtual_addr_low, \
> virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
>
> +#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
> + ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
> + (adev)->powerplay.pp_handle, buf))
> +
> +#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
> + ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
> + (adev)->powerplay.pp_handle, parameter, size))
> +
> struct amdgpu_dpm {
> struct amdgpu_ps*ps;
> /* number of valid power states */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index e5ee7cf..662edca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -584,6 +584,73 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
> return count;
> }
>
> +static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = ddev->dev_private;
> +
> + if (adev->powerplay.pp_funcs->get_power_profile_mode)
> + return amdgpu_dpm_get_power_profile_mode(adev, buf);
> +
> + return snprintf(buf, PAGE_SIZE, "\n");
> +}
> +
> +
> +static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t count)
> +{
> + int ret = 0xff;
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = ddev->dev_private;
> + uint32_t parameter_size = 0;
> + long parameter[64];
> + char *sub_str, buf_cpy[128];
> + char *tmp_str;
> + uint32_t i = 0;
> + char tmp[2];
> + long int profile_mode = 0;
> + const char delimiter[3] = {' ', '\n', '\0'};
> +
> + tmp[0] = *(buf);
> + tmp[1] = '\0';
> + ret = kstrtol(tmp, 0, &profile_mode);
> + if (ret)
> + goto fail;
> +
> + if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
> + if (count < 2 || count > 127)
> + return -EINVAL;
> + while (isspace(*++buf))
> + i++;
> + memcpy(buf_cpy, buf, count-i);
> + tmp_str = buf_cpy;
> + while (tmp_str[0]) {
> + sub_str = strsep(&tmp_str, delimiter);
> + ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
> + if (ret) {
> + count = -EINVAL;
> + goto fail;
> + }
> + pr_info("value is %ld \n", par
Re: [PATCH] drm/amdkfd: Fix potential NULL pointer dereferences
Yeah, this looks good to me.
Regards,
Felix
On 2018-01-10 04:58 PM, Gustavo A. R. Silva wrote:
> Hi Felix,
>
> Quoting Felix Kuehling :
>
>> Hi Gustavo,
>>
>> Thanks for catching that. When returning a fault, I think you also need
>> to srcu_read_unlock(&kfd_processes_srcu, idx).
>>
>> However, instead of returning an error, I think I'd prefer to skip PDDs
>> that can't be found with continue statements. That way others would
>> still suspend and resume successfully. Maybe just print a WARN_ON for
>> PDDs that aren't found, because that's an unexpected situation,
>> currently. Maybe in the future it could be normal thing if we ever
>> support GPU hotplug.
>>
>
> I got it. In that case, what do you think about the following patch
> instead?
>
> index a22fb071..4ff5f0f 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -461,7 +461,8 @@ int kfd_bind_processes_to_device(struct kfd_dev *dev)
> hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
> mutex_lock(&p->mutex);
> pdd = kfd_get_process_device_data(dev, p);
> - if (pdd->bound != PDD_BOUND_SUSPENDED) {
> +
> + if (WARN_ON(!pdd) || pdd->bound != PDD_BOUND_SUSPENDED) {
> mutex_unlock(&p->mutex);
> continue;
> }
> @@ -501,6 +502,11 @@ void kfd_unbind_processes_from_device(struct
> kfd_dev *dev)
> mutex_lock(&p->mutex);
> pdd = kfd_get_process_device_data(dev, p);
>
> + if (WARN_ON(!pdd)) {
> + mutex_unlock(&p->mutex);
> + continue;
> + }
> +
> if (pdd->bound == PDD_BOUND)
> pdd->bound = PDD_BOUND_SUSPENDED;
> mutex_unlock(&p->mutex);
>
>
> Thank you for the feedback.
> --
> Gustavo
>
>> Regards,
>> Felix
>>
>>
>> On 2018-01-10 11:50 AM, Gustavo A. R. Silva wrote:
>>> In case kfd_get_process_device_data returns null, there are some
>>> null pointer dereferences in functions kfd_bind_processes_to_device
>>> and kfd_unbind_processes_from_device.
>>>
>>> Fix this by null checking pdd before dereferencing it.
>>>
>>> Addresses-Coverity-ID: 1463794 ("Dereference null return value")
>>> Addresses-Coverity-ID: 1463772 ("Dereference null return value")
>>> Signed-off-by: Gustavo A. R. Silva
>>> ---
>>> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 12
>>> 1 file changed, 12 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
>>> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
>>> index a22fb071..29d51d5 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
>>> @@ -461,6 +461,13 @@ int kfd_bind_processes_to_device(struct kfd_dev
>>> *dev)
>>> hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
>>> mutex_lock(&p->mutex);
>>> pdd = kfd_get_process_device_data(dev, p);
>>> +
>>> + if (!pdd) {
>>> + pr_err("Process device data doesn't exist\n");
>>> + mutex_unlock(&p->mutex);
>>> + return -EFAULT;
>>> + }
>>> +
>>> if (pdd->bound != PDD_BOUND_SUSPENDED) {
>>> mutex_unlock(&p->mutex);
>>> continue;
>>> @@ -501,6 +508,11 @@ void kfd_unbind_processes_from_device(struct
>>> kfd_dev *dev)
>>> mutex_lock(&p->mutex);
>>> pdd = kfd_get_process_device_data(dev, p);
>>>
>>> + if (!pdd) {
>>> + mutex_unlock(&p->mutex);
>>> + return;
>>> + }
>>> +
>>> if (pdd->bound == PDD_BOUND)
>>> pdd->bound = PDD_BOUND_SUSPENDED;
>>> mutex_unlock(&p->mutex);
>
>
>
>
>
>
___
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[PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
v2: fix register access Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..c73a476 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(0) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS | + PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amdkfd: Fix potential NULL pointer dereferences
In case kfd_get_process_device_data returns null, there are some
null pointer dereferences in functions kfd_bind_processes_to_device
and kfd_unbind_processes_from_device.
Fix this by printing a WARN_ON for PDDs that aren't found and skip
them with continue statements.
Addresses-Coverity-ID: 1463794 ("Dereference null return value")
Addresses-Coverity-ID: 1463772 ("Dereference null return value")
Suggested-by: Felix Kuehling
Signed-off-by: Gustavo A. R. Silva
---
Changes in v2:
Print a WARN_ON and skip PDDs that aren't found instead of returning
an error.
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index a22fb071..4ff5f0f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -461,7 +461,8 @@ int kfd_bind_processes_to_device(struct kfd_dev *dev)
hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
- if (pdd->bound != PDD_BOUND_SUSPENDED) {
+
+ if (WARN_ON(!pdd) || pdd->bound != PDD_BOUND_SUSPENDED) {
mutex_unlock(&p->mutex);
continue;
}
@@ -501,6 +502,11 @@ void kfd_unbind_processes_from_device(struct kfd_dev *dev)
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
+ if (WARN_ON(!pdd)) {
+ mutex_unlock(&p->mutex);
+ continue;
+ }
+
if (pdd->bound == PDD_BOUND)
pdd->bound = PDD_BOUND_SUSPENDED;
mutex_unlock(&p->mutex);
--
2.7.4
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Re: [PATCH] drm/amdkfd: Fix potential NULL pointer dereferences
Hi Felix,
Quoting Felix Kuehling :
Hi Gustavo,
Thanks for catching that. When returning a fault, I think you also need
to srcu_read_unlock(&kfd_processes_srcu, idx).
However, instead of returning an error, I think I'd prefer to skip PDDs
that can't be found with continue statements. That way others would
still suspend and resume successfully. Maybe just print a WARN_ON for
PDDs that aren't found, because that's an unexpected situation,
currently. Maybe in the future it could be normal thing if we ever
support GPU hotplug.
I got it. In that case, what do you think about the following patch instead?
index a22fb071..4ff5f0f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -461,7 +461,8 @@ int kfd_bind_processes_to_device(struct kfd_dev *dev)
hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
- if (pdd->bound != PDD_BOUND_SUSPENDED) {
+
+ if (WARN_ON(!pdd) || pdd->bound != PDD_BOUND_SUSPENDED) {
mutex_unlock(&p->mutex);
continue;
}
@@ -501,6 +502,11 @@ void kfd_unbind_processes_from_device(struct
kfd_dev *dev)
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
+ if (WARN_ON(!pdd)) {
+ mutex_unlock(&p->mutex);
+ continue;
+ }
+
if (pdd->bound == PDD_BOUND)
pdd->bound = PDD_BOUND_SUSPENDED;
mutex_unlock(&p->mutex);
Thank you for the feedback.
--
Gustavo
Regards,
Felix
On 2018-01-10 11:50 AM, Gustavo A. R. Silva wrote:
In case kfd_get_process_device_data returns null, there are some
null pointer dereferences in functions kfd_bind_processes_to_device
and kfd_unbind_processes_from_device.
Fix this by null checking pdd before dereferencing it.
Addresses-Coverity-ID: 1463794 ("Dereference null return value")
Addresses-Coverity-ID: 1463772 ("Dereference null return value")
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index a22fb071..29d51d5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -461,6 +461,13 @@ int kfd_bind_processes_to_device(struct kfd_dev *dev)
hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
+
+ if (!pdd) {
+ pr_err("Process device data doesn't exist\n");
+ mutex_unlock(&p->mutex);
+ return -EFAULT;
+ }
+
if (pdd->bound != PDD_BOUND_SUSPENDED) {
mutex_unlock(&p->mutex);
continue;
@@ -501,6 +508,11 @@ void kfd_unbind_processes_from_device(struct
kfd_dev *dev)
mutex_lock(&p->mutex);
pdd = kfd_get_process_device_data(dev, p);
+ if (!pdd) {
+ mutex_unlock(&p->mutex);
+ return;
+ }
+
if (pdd->bound == PDD_BOUND)
pdd->bound = PDD_BOUND_SUSPENDED;
mutex_unlock(&p->mutex);
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[PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
v2: fix register access Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..6db3645 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(1) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
Please ignore this one, a minor update is coming. Sorry for annoyance. Jerry On 01/11/2018 09:44 AM, Junwei Zhang wrote: v2: fix register access Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..c73a476 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(0) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS | + PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
Could I how to verify this is valid fix? Regards, David Zhou On 2018年01月11日 10:30, Junwei Zhang wrote: v2: fix register access Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..6db3645 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_DST_SEL(1) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | + adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
On 01/11/2018 10:50 AM, Chunming Zhou wrote: Could I how to verify this is valid fix? For now, check if there is no vm fault or any other side effect when loading amdgpu with ngg=1. Later development will be implemented with OGL team together. Jerry Regards, David Zhou On 2018年01月11日 10:30, Junwei Zhang wrote: v2: fix register access Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ae976e3..6db3645 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; -adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); -adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; +adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); +adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); /* Primitive Buffer */ r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], @@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | +PACKET3_DMA_DATA_DST_SEL(1) | PACKET3_DMA_DATA_SRC_SEL(2))); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); amdgpu_ring_write(ring, 0); -amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); - +amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | +adev->gfx.ngg.gds_reserve_size); gfx_v9_0_write_data_to_reg(ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 03/21] drm/amdgpu: add amdgpu_pasid_free_delayed
On 2018年01月10日 20:54, Christian König wrote:
Free up a pasid after all fences signaled.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 73 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 2 +
2 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 5248a3232aff..63c9fb0361c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -40,6 +40,12 @@
*/
static DEFINE_IDA(amdgpu_pasid_ida);
+/* Helper to free pasid from a fence callback */
+struct amdgpu_pasid_cb {
+ struct dma_fence_cb cb;
+ unsigned int pasid;
+};
+
/**
* amdgpu_pasid_alloc - Allocate a PASID
* @bits: Maximum width of the PASID in bits, must be at least 1
@@ -75,6 +81,73 @@ void amdgpu_pasid_free(unsigned int pasid)
ida_simple_remove(&amdgpu_pasid_ida, pasid);
}
+static void amdgpu_pasid_free_cb(struct dma_fence *fence,
+struct dma_fence_cb *_cb)
+{
+ struct amdgpu_pasid_cb *cb =
+ container_of(_cb, struct amdgpu_pasid_cb, cb);
+
+ amdgpu_pasid_free(cb->pasid);
+ dma_fence_put(fence);
+ kfree(cb);
+}
+
+/**
+ * amdgpu_pasid_free_delayed - free pasid when fences signal
+ *
+ * @resv: reservation object with the fences to wait for
+ * @pasid: pasid to free
+ *
+ * Free the pasid only after all the fences in resv are signaled.
+ */
+void amdgpu_pasid_free_delayed(struct reservation_object *resv,
+ unsigned int pasid)
+{
+ struct dma_fence *fence, **fences;
+ struct amdgpu_pasid_cb *cb;
+ unsigned count;
+ int r;
+
+ r = reservation_object_get_fences_rcu(resv, NULL, &count, &fences);
+ if (r) {
+ /* Not enough memory to grab the fence list, as last resort
+* block for all the fences to complete.
+*/
+ reservation_object_wait_timeout_rcu(resv, true, false,
+ MAX_SCHEDULE_TIMEOUT);
+ amdgpu_pasid_free(pasid);
+ return;
+ }
+
+ if (count == 0) {
+ amdgpu_pasid_free(pasid);
+ return;
+ }
+
+ if (count == 1) {
+ fence = fences[0];
+ kfree(fences);
+ } else {
+ uint64_t context = dma_fence_context_alloc(1);
+
+ fence = &dma_fence_array_create(count, fences, context,
+ 1, false)->base;
Here needs to check if fence is NULL.
Regards,
David Zhou
+ }
+
+ cb = kmalloc(sizeof(*cb), GFP_KERNEL);
+ if (!cb) {
+ /* Last resort when we are OOM */
+ dma_fence_wait(fence, false);
+ dma_fence_put(fence);
+ amdgpu_pasid_free(pasid);
+ } else {
+ cb->pasid = pasid;
+ if (dma_fence_add_callback(fence, &cb->cb,
+ amdgpu_pasid_free_cb))
+ amdgpu_pasid_free_cb(fence, &cb->cb);
+ }
+}
+
/*
* VMID manager
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
index ad931fa570b3..38f37c16fc5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -69,6 +69,8 @@ struct amdgpu_vmid_mgr {
int amdgpu_pasid_alloc(unsigned int bits);
void amdgpu_pasid_free(unsigned int pasid);
+void amdgpu_pasid_free_delayed(struct reservation_object *resv,
+ unsigned int pasid);
bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
struct amdgpu_vmid *id);
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Re: [PATCH 05/21] drm/amdgpu: trace allocated PASIDs
On 2018年01月10日 20:54, Christian König wrote:
Trace all allocated PASIDs.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 22 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 60e0f2dd87df..0948df366278 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -31,6 +31,7 @@
#include "amdgpu_sched.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
+#include "amdgpu_trace.h"
#include
#include
@@ -823,7 +824,10 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
if (pasid < 0) {
dev_info(adev->dev, "No more PASIDs available!");
pasid = 0;
+ } else {
+ trace_amdgpu_pasid_allocated(pasid);
How about moving to amdgpu_pasid_alloc?
}
+
r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
if (r)
goto error_pasid;
@@ -852,8 +856,10 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
amdgpu_vm_fini(adev, &fpriv->vm);
error_pasid:
- if (pasid)
+ if (pasid) {
amdgpu_pasid_free(pasid);
+ trace_amdgpu_pasid_freed(pasid);
How about moving to amdgpu_pasid_free?
+ }
kfree(fpriv);
@@ -908,8 +914,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
amdgpu_vm_fini(adev, &fpriv->vm);
- if (pasid)
+ if (pasid) {
amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
+ trace_amdgpu_pasid_freed(pasid);
How about moving to amdgpu_pasid_free?
Regards,
David Zhou
+ }
amdgpu_bo_unref(&pd);
idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index cace7a93fc94..9890c39ee810 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -378,6 +378,28 @@ TRACE_EVENT(amdgpu_vm_flush,
__entry->vm_hub,__entry->pd_addr)
);
+DECLARE_EVENT_CLASS(amdgpu_pasid,
+ TP_PROTO(unsigned pasid),
+ TP_ARGS(pasid),
+ TP_STRUCT__entry(
+__field(unsigned, pasid)
+),
+ TP_fast_assign(
+ __entry->pasid = pasid;
+ ),
+ TP_printk("pasid=%u", __entry->pasid)
+);
+
+DEFINE_EVENT(amdgpu_pasid, amdgpu_pasid_allocated,
+ TP_PROTO(unsigned pasid),
+ TP_ARGS(pasid)
+);
+
+DEFINE_EVENT(amdgpu_pasid, amdgpu_pasid_freed,
+ TP_PROTO(unsigned pasid),
+ TP_ARGS(pasid)
+);
+
TRACE_EVENT(amdgpu_bo_list_set,
TP_PROTO(struct amdgpu_bo_list *list, struct amdgpu_bo *bo),
TP_ARGS(list, bo),
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Re: [PATCH 04/21] drm/amdgpu: always allocate a pasid for each VM
On 2018年01月10日 20:54, Christian König wrote:
Start to always allocate a pasid for each VM.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 43 ++---
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5773a581761b..60e0f2dd87df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -805,7 +805,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
{
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_fpriv *fpriv;
- int r;
+ int r, pasid;
file_priv->driver_priv = NULL;
@@ -819,28 +819,25 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
goto out_suspend;
}
- r = amdgpu_vm_init(adev, &fpriv->vm,
- AMDGPU_VM_CONTEXT_GFX, 0);
- if (r) {
- kfree(fpriv);
- goto out_suspend;
+ pasid = amdgpu_pasid_alloc(16);
+ if (pasid < 0) {
+ dev_info(adev->dev, "No more PASIDs available!");
A WARN_ON seems be more appropriate, since the following patches relies
on vm->pasid.
Regards,
David Zhou
+ pasid = 0;
}
+ r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
+ if (r)
+ goto error_pasid;
fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
if (!fpriv->prt_va) {
r = -ENOMEM;
- amdgpu_vm_fini(adev, &fpriv->vm);
- kfree(fpriv);
- goto out_suspend;
+ goto error_vm;
}
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
- if (r) {
- amdgpu_vm_fini(adev, &fpriv->vm);
- kfree(fpriv);
- goto out_suspend;
- }
+ if (r)
+ goto error_vm;
}
mutex_init(&fpriv->bo_list_lock);
@@ -849,6 +846,16 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
file_priv->driver_priv = fpriv;
+ goto out_suspend;
+
+error_vm:
+ amdgpu_vm_fini(adev, &fpriv->vm);
+
+error_pasid:
+ if (pasid)
+ amdgpu_pasid_free(pasid);
+
+ kfree(fpriv);
out_suspend:
pm_runtime_mark_last_busy(dev->dev);
@@ -871,6 +878,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
struct amdgpu_bo_list *list;
+ struct amdgpu_bo *pd;
+ unsigned int pasid;
int handle;
if (!fpriv)
@@ -895,7 +904,13 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
amdgpu_bo_unreserve(adev->virt.csa_obj);
}
+ pasid = fpriv->vm.pasid;
+ pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
+
amdgpu_vm_fini(adev, &fpriv->vm);
+ if (pasid)
+ amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
+ amdgpu_bo_unref(&pd);
idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
amdgpu_bo_list_free(list);
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Re: [PATCH 21/21] drm/amdgpu: print the PASID with VM faults on GMC v8
Except some small nitpicks in patch #3, #4, #5, the series looks ok to
me, Reviewed-by: Chunming Zhou
Regards,
David Zhou
On 2018年01月10日 20:54, Christian König wrote:
Print that extra information on GMC v8.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 287228315b76..5b4f6c1f0993 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -962,21 +962,21 @@ static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
*
* Print human readable fault information (CIK).
*/
-static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
-u32 status, u32 addr, u32 mc_client)
+static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
+u32 addr, u32 mc_client, unsigned pasid)
{
- u32 mc_id;
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
VMID);
u32 protections = REG_GET_FIELD(status,
VM_CONTEXT1_PROTECTION_FAULT_STATUS,
PROTECTIONS);
char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
+ u32 mc_id;
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_ID);
- dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
- protections, vmid, addr,
+ dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from
'%s' (0x%08x) (%d)\n",
+ protections, vmid, pasid, addr,
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
MEMORY_CLIENT_RW) ?
"write" : "read", block, mc_client, mc_id);
@@ -1404,7 +1404,8 @@ static int gmc_v8_0_process_interrupt(struct
amdgpu_device *adev,
addr);
dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS
0x%08X\n",
status);
- gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
+ gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
+entry->pasid);
}
return 0;
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