From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Adjust assembler
times.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto.
---
.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 +-
.../gcc.target/riscv/rvv/vsetvl
Commited, thanks juzhe.
--
Li Xu
>OK.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-10-07 11:18
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH] RISC-V: Fix scan-assembler-times of RVV test case
>Fr
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Fix 'REQUIREMENT' for machine_mode
'MODE'.
* config/riscv/vector.md
(@pred_indexed_store): change
VNX16_QHSI to VNX16_QHSDI.
(@pred_indexed_store): Ditto.
---
gcc/config/riscv/vector-iterators.md | 26 +-
Consider this following case:
void test_vsoxseg3ei32_v_i32mf2x3(int32_t *base, vuint32mf2_t bindex,
vint32mf2x3_t v_tuple, size_t vl) {
return __riscv_vsoxseg3ei32_v_i32mf2x3(base, bindex, v_tuple, vl);
}
Compiler failed with:
test.c:19:1: internal compiler error: in vl_vtype_info, at
config/r
Consider this following case:
void test_vsoxseg3ei32_v_i32mf2x3(int32_t *base, vuint32mf2_t bindex,
vint32mf2x3_t v_tuple, size_t vl) {
return __riscv_vsoxseg3ei32_v_i32mf2x3(base, bindex, v_tuple, vl);
}
Compiler failed with:
test.c:19:1: internal compiler error: in vl_vtype_info, at
config/r
Consider this following case:
void test_vsoxseg3ei32_v_i32mf2x3(int32_t *base, vuint32mf2_t bindex,
vint32mf2x3_t v_tuple, size_t vl) {
return __riscv_vsoxseg3ei32_v_i32mf2x3(base, bindex, v_tuple, vl);
}
Compiler failed with:
test.c:19:1: internal compiler error: in vl_vtype_info, at
config/r
From: xuli
Computation of `vsadd`, `vsaddu`, `vssub`, and `vssubu` do not need the
rounding mode, therefore the intrinsics of these instructions do not have
the parameter for rounding mode control.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: remove rounding mode of
vs
From: xuli
Signed-off-by: Li Xu
ChangeLog:
* MAINTAINERS: Add myself.
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e9b11b43a0f..49aa6bae73b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -712,6 +712,7 @@ Jonathan Wright
From: xuli
This patch fixes this issue happens on GCC-13.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111074
This patch should be backported to GCC-13.
GCC-14 has rewritten propagate_avl function, so there is no issue.
PR target/111074
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (e
The test case is too complicated and I can't simplify it, so no test case is
added.
------
Li Xu
>From: xuli
>
>This patch fixes this issue happens on GCC-13.
>https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111074
>
>This patch should be backported to GCC-13
Committed, thanks all.
--
Li Xu
>The test case is too complicated and I can't simplify it, so no test case is
>added.
>
>------
>Li Xu
>>From: xuli
>>
>>This patch fixes this issue happens on GCC-13.
>>https://gcc.gnu.org/bug
VWF is defined under TARGET_MIN_VLEN >= 128.
VWEXTF: zvfh/zvfhmin depends on the Zve32f extension.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Fix requirement
---
gcc/config/riscv/vector-iterators.md | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
gcc/ChangeLog:
* config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the Zve32f
extension.
---
gcc/config/riscv/vector-iterators.md | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-itera
If reinterpret vnx2bi as vnx16bi, vnx16bi must occupy no more of the underlying
registers than vnx2bi.
Consider this following case:
void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out)
{
vbool64_t vmask = __riscv_vlm_v_b64 (in, 2);
vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1 (vma
If reinterpret vnx2bi as vnx16qi, vnx16qi must occupy no more of the underlying
registers than vnx2bi.
Consider this following case:
void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out)
{
vbool64_t vmask = __riscv_vlm_v_b64 (in, 2);
vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1 (vma
arg and target should be expanded to reg rtx during expand pass.
Consider this following case:
void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}
Compilation fails with:
test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4':
test.c:5:1: err
Consider this following case:
void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}
Compilation fails with:
test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4':
test.c:5:1: error: unrecognizable insn:
5 | }
| ^
(insn 30 29 0 2 (set
Hi, Jeff:
I have filled out the form. May I ask if you have received my application? Is
there anything else I need to do?
Thanks.
--
Li Xu
>
>
>On 6/25/23 03:13, juzhe.zh...@rivai.ai wrote:
>> LGTM.
>> Thanks for fixing it.
>Agreed. I didn't see t
If MAX_MACHINE_MODE exceeds 8bits, a warning will appear in the following code.
waring: writing 293 bytes into a region of size 256 overflows the destination
gcc/lto-streamer-out.cc
void
lto_output_init_mode_table (void)
{
memset (streamer_mode_table, '\0', MAX_MACHINE_MODE);
}
gcc/ChangeLog:
This patch fixes this issue happens on GCC-13.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110560
This patch should be backported to GCC-13.
GCC-14 has rewritten this function, so there is no issue.
PR target/110560
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_
Calling vget/vset intrinsic without receiving a return value will cause
a crash. Because in this case e.target is null.
This patch should be backported to releases/gcc-13.
PR target/111935
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Don't use the e.target directly.
gcc/testsuit
Calling vget/vset intrinsic without receiving a return value will cause
a crash. Because in this case e.target is null.
This patch should be backported to releases/gcc-13.
PR/target 111935
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: fix bug.
gcc/testsuite/Chan
Committed to trunk. Thanks juzhe.
--
Li Xu
>Ok for trunk (You can commit it to the trunk now).
>
>For GCC-13, I'd like to wait for kito's comment.
>
>Thanks.
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>
.
* gcc.target/riscv/rvv/base/overloaded_vget_vset.h: New test.
* gcc.target/riscv/rvv/base/overloaded_vloxseg2ei16.h: New test.
* gcc.target/riscv/rvv/base/overloaded_vmv.h: New test.
* gcc.target/riscv/rvv/base/overloaded_vreinterpret.h: New test.
Signed-off-by: Li Xu
Co
--
Li Xu
>Thanks.
>
>I like this 'HASH' solution which is much more reasonable to me.
>
>Some comments here:
>
>+bool
>+has_vxrm_or_frm_p (function_instance &instance, const vec
>&arglist)
>+{
&
OK, I will send patch v5.
--
Li Xu
>Ok. Understand.
>
>Could you add wrapper "maybe_require_vxrm_p" and "maybe_require_frm_p" ?
>
>static bool
>maybe_require_frm_p
>return instance.base == bases::vfwredu
/rvv/base/overloaded_vreinterpret.h: New test.
Signed-off-by: Li Xu
Co-Authored-By: Pan Li
---
gcc/config/riscv/riscv-c.cc | 36 ++-
gcc/config/riscv/riscv-protos.h | 1 +
.../riscv/riscv-vector-builtins-shapes.cc | 1 +
gcc/config/riscv/riscv-vector
Already backported to releases/gcc-13.
--
Li Xu
>Ok for gcc 13 but just wait one more week to make sure everything is fine
>as gcc convention :)
>
>Li Xu 於 2023年10月24日 週二，15:49寫道：
>
>> Committed t
const binop vfadd_frm_obj;
template
class binop : public function_base
{
public:
bool maybe_require_frm_p () const override { return true; }//vadd is true
...
}
--
Li Xu
>+static bool
>+maybe_require_frm_p (function_instance &instance)
>+{
>+ retu
.
* gcc.target/riscv/rvv/base/overloaded_vget_vset.h: New test.
* gcc.target/riscv/rvv/base/overloaded_vloxseg2ei16.h: New test.
* gcc.target/riscv/rvv/base/overloaded_vmv.h: New test.
* gcc.target/riscv/rvv/base/overloaded_vreinterpret.h: New test.
Signed-off-by: Li Xu
Co
All overload and non-overload intrinsics have been tested successfully on gcc
and g++.
Thanks.
> -原始邮件-发件人:"juzhe.zh...@rivai.ai"
> 发送时间:2023-10-31 17:07:11 (星期二)收件人:"Li Xu"
> , gcc-patches
> 抄送:"kito.cheng" , palmer
> , &
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (vundefined): Add
vundefine intrinsics for tuple types.
* config/riscv/riscv-vector-builtins.cc: Ditto.
* config/riscv/vector.md (@vu
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Expand non-tuple
intrinsics.
* config/riscv/riscv-vector-builtins-functions.def (vcreate): Define
non-tuple intrinsics.
* config/riscv/r
Committed, thanks juzhe.
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2023-11-02 09:00
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; Li Xu
Subject: Re: [PATCH] RISC-V: Support vcreate intrinsics for non-tuple types
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023
This issue happens is because the operand1 of scalar move can be
REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
not insert the vsetvl instruction correctly, and the compiler crashes.
Consider this following case:
int16_t foo1 (void *base, size_t vl)
{
int16_t maxVal = __ris
This issue happens is because the operand1 of scalar move can be
REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
not insert the vsetvl instruction correctly, and the compiler crashes.
Consider this following case:
int16_t foo1 (void *base, size_t vl)
{
int16_t maxVal = __ris
Ping.
xu...@eswincomputing.com
From: Li Xu
Date: 2024-02-27 09:17
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; zhengyu; xuli
Subject: [PATCH] RISC-V: Add riscv_vector_cc function attribute
From: xuli
Standard vector calling convention variant will only enabled when function
has
From: xuli
Standard vector calling convention variant will only enabled when function
has vector argument or returning value by default, however user may also
want to invoke function without that during a vectorized loop at some situation,
but it will cause a huge performance penalty due to vecto
From: xuli
Standard vector calling convention variant will only enabled when function
has vector argument or returning value by default, however user may also
want to invoke function without that during a vectorized loop at some situation,
but it will cause a huge performance penalty due to vecto
From: xuli
Change the hash value of overloaded intrinsic from considering
all parameter types to:
1. Encoding vector data type
2. In order to distinguish vle8_v_i8mf8_m(vbool64_t vm, const int8_t *rs1,
size_t vl)
and vle8_v_u8mf8_m(vbool64_t vm, const uint8_t *rs1, size_t vl), encode the
poi
you are right.
vint8mf8_t test_vle8_v_i8mf8_m(vbool64_t vm, const int32_t *rs1, size_t vl) {
return __riscv_vle8(vm, rs1, vl);
}
This will cause ICE. I tried clang and it will also cause ICE.
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2024-01-19 15:53
To: Li Xu; gcc-patches
From: xuli
v2:
Avoid internal ICE for the case below.
vint8mf8_t test_vle8_v_i8mf8_m(vbool64_t vm, const int32_t *rs1, size_t vl) {
return __riscv_vle8(vm, rs1, vl);
}
v1:
Change the hash value of overloaded intrinsic from considering
all parameter types to:
1. Encoding vector data type
2. In
Committed, thanks
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2024-01-22 14:40
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; Li Xu
Subject: Re: [PATCH v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-01-22 12:11
From: Juzhe-Zhong
This patch fixes the following FAIL when LMUL = 8:
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medany/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=scalable
FAIL: gcc.dg/vect/slp-multitypes-2.c execution test
The rootcause is we missed viota avl_type, so we
Committed, thanks juzhe.
xu...@eswincomputing.com
From: juzhe.zhong
Date: 2023-12-18 09:08
To: Li Xu
CC: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; pal...@dabbelt.com
Subject: Re: [PATCH] RISC-V: Add viota missed avl_type attribute
lgtm
Replied Message
FromLi Xu
Date12/18/2023
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks.
---
.../gcc.target/riscv/rvv/base/cpymem-1.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
b/gcc/te
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks.
---
.../gcc.target/riscv/rvv/base/cpymem-1.c | 29 +--
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
b/gcc/te
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-2.c: Fix checks.
---
.../gcc.target/riscv/rvv/base/cpymem-2.c | 44 ++-
1 file changed, 33 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
b/gcc/t
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks under medany.
* gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Fix checks.
* gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Ditto.
---
.../gcc.target/riscv/rvv/base/cpymem-1.c | 2
Committed, thanks juzhe.
xu...@eswincomputing.com
From: juzhe.zhong
Date: 2023-12-19 14:01
To: Li Xu
CC: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; pal...@dabbelt.com; xuli
Subject: Re: [PATCH] testsuite: Fix dump checks under different riscv-sim for
RVV.
ok
Replied Message
From: xuli
This patch fixs the issue of g++.dg/torture/vshuf-v2di.C
and g++.dg/torture/vshuf-v4di.C -Os execution failure with
-march=rv32gcv -mabi=ilp32d.
Consider the following code:
typedef unsigned long long V __attribute__((vector_size(16)));
.LC0: 0xc1c2c3c4c5c6c7c8
before this patch:
l
From: xuli
This patch fixs the issue of g++.dg/torture/vshuf-v2di.C
and g++.dg/torture/vshuf-v4di.C -Os execution failure with
-march=rv32gcv -mabi=ilp32d.
Consider the following code:
typedef unsigned long long V __attribute__((vector_size(16)));
.LC0: 0xc1c2c3c4c5c6c7c8
before this patch:
l
Committed, thanks juzhe.
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2023-12-05 16:41
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; Li Xu
Subject: Re: [PATCH v2] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os
(execution test) on RV32
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: xuli
gcc/ChangeLog:
* config/riscv/riscv.md: Remove.
---
gcc/config/riscv/riscv.md | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a98918dfd43..0db659acfbe 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/
Got it.
Committed, thanks juzhe and kito.
xu...@eswincomputing.com
From: Kito Cheng
Date: 2023-12-06 14:45
To: Li Xu
CC: gcc-patches; palmer; juzhe.zhong
Subject: Re: [PATCH] RISC-V: Remove useless modes
You could add [NFC] to the title for this kind of patch to declare its
clean up or
This patch should be backported to releases/gcc-13 to address
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111076
--
Li Xu
>This issue happens is because the operand1 of scalar move can be
>REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
>not insert t
From: xuli
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vcreate):
(BASE): New class.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vcreate): Add
vcreate support.
* config/ri
From: xuli
The parameter orig_fndecl is not used, use anonymous parameters instead.
../.././gcc/gcc/config/riscv/riscv-c.cc: In function ‘bool
riscv_check_builtin_call(location_t, vec, tree, tree, unsigned
int, tree_node**)’:
../.././gcc/gcc/config/riscv/riscv-c.cc:207:11: warning: unused para
From: xuli
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537
-mmemcpy-strategy=[auto|libcall|scalar|vector]
auto: Current status, use scalar or vector instructions.
libcall: Always use a library call.
scalar: Only use scalar instructions.
vector: Only use vector instructions.
PR targ
I've tested it and there are no issues with regression testing.
Thanks,
Li Xu
xu...@eswincomputing.com
From: Jeff Law
Date: 2023-11-20 05:42
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: Re: [PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537]
On 11/
Committed, thanks jeff and juzhe.
Thanks,
Li Xu
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2023-11-20 09:55
To: Li Xu; jeffreyalaw; gcc-patches
CC: kito.cheng; palmer; Robin Dapp
Subject: Re: Re: [PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537]
Jeff has approved
From: xuli
../.././gcc/gcc/config/riscv/riscv.cc: In function ‘void
riscv_option_override()’:
../.././gcc/gcc/config/riscv/riscv.cc:8673:6: warning: suggest explicit braces
to avoid ambiguous ‘else’ [-Wdangling-else]
if (TARGET_RVE)
^
gcc/ChangeLog:
* config/riscv/riscv.cc (r
Committed, thanks juzhe and kito.
--
Li Xu
>LGTM, thanks for implement this :)
>
>On Tue, Sep 12, 2023 at 10:16 AM juzhe.zh...@rivai.ai
> wrote:
>>
>> Thanks for support it.
>> LGTM from my side.
>> Wait for kito's more comments.
>>
From: xuli
./riscv-gcc/gcc/config/riscv/riscv-vector-builtins-bases.cc:1719:34:
warning: unused parameter 'e' [-Wunused-parameter]
rtx expand (function_expander &e) const override
^
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.
From: xuli
The following is the content of class vcreate:
class vcreate : public function_base
{
public:
gimple *fold (gimple_folder &f) const override
{
}
rtx expand (function_expander &e) const override
{
return NULL_RTX;
}
};
The warning caused is:
./riscv-gcc/gcc/co
From: xuli
The following is the content of class vcreate:
class vcreate : public function_base
{
public:
gimple *fold (gimple_folder &f) const override
{
}
rtx expand (function_expander &e) const override
{
return NULL_RTX;
}
};
The warning caused is:
./riscv-gcc/gcc/co
Committed, thanks juzhe.
--
Li Xu
>lgtm
> Replied Message
>FromLi Xu
>Date09/12/2023 14:20
>togcc-patc...@gcc.gnu.org
>cckito.ch...@gmail.com,
>pal...@dabbelt.com,
>juzhe.zh...@rivai.ai,
>xuli
>Subject[PATCH v3] RISC-V: Elimilate warning in class vcreate
From: xuli
vsetvl pass has been refactored in gcc14, and the optimization
is more reasonable than releases/gcc-13. This problem does not
exist in gcc14.
Phase 6 of gcc13 is an optimization patch. Due to lack of consideration,
there will be some hidden bugs, so we decided to remove phase 6.
Altho
commited, thanks kito and juzhe.
--
Li Xu
>I think it's not make too much sense to back port GCC14's change to
>GCC 13, removing phase 6 optimization is reasonable to me, so LGTM :)
>
>On Mon, Sep 18, 2023 at 2:44 PM juzhe.zh...@rivai.ai
> wrote:
>>
&
From: xuli
When stride == element width, vlsse should be optimized into vle.v.
vsse should be optimized into vse.v.
PR target/111450
gcc/ChangeLog:
*config/riscv/constraints.md (c01): const_int 1.
(c02): const_int 2.
(c04): const_int 4.
(c08): const_int
Committed, thanks Juzhe.
--
Li Xu
>Thanks a lot. LGTM.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-09-21 11:12
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH] RISC-V: Optimized for strided load/store with s
From: xuli
Consider this following case:
typedef int32_t vnx32si __attribute__ ((vector_size (128)));
__attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \
TYPE *out) \
{
From: xuli
Consider this following case:
typedef int32_t vnx32si __attribute__ ((vector_size (128)));
__attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \
TYPE *out) \
{
Committed, thanks Juzhe.
--
Li Xu
>LGTM. You can commit it after you pass the regression.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-09-22 10:37
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH V2] RISC-V:
From: xuli
Consider the flowing situation:
BB5: local_dem(RVV Insn 1, AVL(reg zero))
RVV Insn 1: vmv.s.x, AVL (const_int 1)
RVV Insn 2: vredsum.vs, AVL(reg zero)
vmv.s.x has vl operand, the following code will get
avl (cosnt_int) from RVV Insn 1.
rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn
From: xuli
Consider the flowing situation:
BB5: local_dem(RVV Insn 1, AVL(reg zero))
RVV Insn 1: vmv.s.x, AVL (const_int 1)
RVV Insn 2: vredsum.vs, AVL(reg zero)
vmv.s.x has vl operand, the following code will get
avl (cosnt_int) from RVV Insn 1.
rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn
Committed, thanks juzhe.
--
Li Xu
>LGTM. Thanks for fixing it.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-09-28 09:33
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
>
))
!= CODE_FOR_nothing)
|| targetm.slow_unaligned_access (mode, align))
misaligned vector access should be enabled by -mno-vector-strict-align option.
PR Target/115862
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable vector
misalign.
Signed-off-by: Li Xu
---
gcc
))
!= CODE_FOR_nothing)
|| targetm.slow_unaligned_access (mode, align))
misaligned vector access should be enabled by -mno-vector-strict-align option.
PR Target/115862
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable vector
misalign.
Signed-off-by: Li Xu
---
gcc
Sorry, I didn't understand.
>>but...this seems to have discovered another bug in the current trunk?
Isn't PR115862 the same bug as this one?
xu...@eswincomputing.com
From: Kito Cheng
Date: 2024-07-12 14:33
To: Li Xu
CC: gcc-patches; juzhe.zhong; rdapp.gcc
Subject: Re: [
Committed, thanks Kito.
xu...@eswincomputing.com
From: Kito Cheng
Date: 2024-07-12 15:57
To: Li Xu
CC: gcc-patches; juzhe.zhong; Robin Dapp
Subject: Re: Re: [PATCH v2] RISC-V: Disable misaligned vector access in hook
riscv_slow_unaligned_access[PR115862]
Oh, okay, my fault, I didn't rea
From: xuli
Because "targetm.slow_unaligned_access" is set to true by default
(aka -mtune=rocket) for RISC-V, it causes the __builtin_memcpy with
8 bytes failed to folded into int64 assignment during ccp1.
So adding "-mtune=generic-ooo" to the RISC-V target can vectorize
vect-early-break_124-pr11
Committed, thanks.
xu...@eswincomputing.com
From: Robin Dapp
Date: 2024-05-21 22:58
To: juzhe.zh...@rivai.ai; Li Xu; gcc-patches
CC: rdapp.gcc; kito.cheng; palmer; tamar.christina; Richard Biener;
richard.sandiford; zhengyu; pan2.li
Subject: Re: [PATCH] RISC-V: Enable vectorization for
vect
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo
(vfloat32m8_t): Likewise
---
gcc/config/riscv/riscv-vector-builtins.def | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def
b/gcc/config/
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def: Fix typo.
* config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Ditto.
* config/riscv/vector-iterators.md: Ditto.
---
gcc/config/riscv/riscv-vector-builtins.def | 3 +--
gcc/config/riscv/riscv.cc
-by: Li Xu
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_u_sub_imm-1_4.c: New test.
* gcc.target/riscv/sat_u_sub_imm-2_4.c: New test.
* gcc.target/riscv/sat_u_sub_imm-3_4.c: New test.
* gcc.target/riscv/sat_u_sub_imm-4_2.c: New test.
---
.../gcc.target/ri
0
Signed-off-by: Li Xu
gcc/ChangeLog:
* match.pd: Support IMM=1.
---
gcc/match.pd | 7 +++
1 file changed, 7 insertions(+)
diff --git a/gcc/match.pd b/gcc/match.pd
index 9aa2129814b..1cdb10a40b9 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3360,6 +3360,13 @@ DEFINE_INT_AND_FL
From: xuli
This patch would like to support .SAT_SUB when one of the op
is IMM = max - 1 of form1.
Form 1:
#define DEF_SAT_U_SUB_IMM_FMT_1(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \
{ \
return IMM >=
From: xuli
form 1:
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_1 (T y) \
{ \
return (T)IMM >= y ? (T)IMM - y : 0; \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_u_sub_imm-1_3
From: xuli
Example as follows:
int main()
{
unsigned long arraya[128], arrayb[128], arrayc[128];
for (int i = 0; i < 128; i++)
{
arraya[i] = arrayb[i] + arrayc[i];
}
return 0;
}
Compiled with -march=rv32imafc_zve32f -mabi=ilp32f, it will cause a compilation
issue:
riscv_vect
ode:
sat_u_sub_imm1_uint8_t_fmt_2:
sneza5,a0
subwa0,a0,a5
andia0,a0,0xff
ret
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
Signed-off-by: Li Xu
gcc/Change
ode:
sat_u_sub_imm1_uint8_t_fmt_2:
sneza5,a0
subwa0,a0,a5
andia0,a0,0xff
ret
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
Signed-off-by: Li Xu
gcc/Change
ode:
sat_u_sub_imm1_uint8_t_fmt_2:
sneza5,a0
subwa0,a0,a5
andia0,a0,0xff
ret
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
Signed-off-by: Li Xu
gcc/Change
From: xuli
form2:
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \
{ \
return x >= (T)IMM ? x - (T)IMM : 0; \
}
Passed the rv64gcv regression test.
Signed-off-by: Li Xu
gcc/testsuite/ChangeLog:
* gcc.tar
From: xuli
form2:
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \
{ \
return x >= (T)IMM ? x - (T)IMM : 0; \
}
Passed the rv64gcv regression test.
Signed-off-by: Li Xu
gcc/testsuite/ChangeLog:
* gcc.tar
x_6(D), -10); [tail call]
return _5;
}
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
Signed-off-by: Li Xu
gcc/ChangeLog:
* match.pd: Add the form1 of signed imm .SAT_ADD matching.
; 0 \
? sum\
: (sum ^ x) >= 0 \
? sum \
: x < 0 ? MIN : MAX; \
}
Passed the rv64gcv regression test.
Signed-off-by: Li Xu
gcc/testsuite/
se is that vlmul_trunc has a null return value.
gimple_call <__riscv_vlmul_trunc_v_f16m1_f16mf2, NULL, vb_13>
^^^
Passed the rv64gcv_zvfh regression test.
Singed-off-by: Li Xu
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 4
sts.
Signed-off-by: Li Xu
gcc/ChangeLog:
* match.pd: Simplify (x != 0 ? x + ~0 : 0) to (x - x != 0).
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/phi-opt-44.c: New test.
---
gcc/match.pd | 10 +
gcc/testsuite/gcc.dg/tree-ssa/phi-opt-44.c |
le function max_sew_overlap_and_next_ratio_valid_for_prev_sew_p.
Otherwise, the tail elements of next will be polluted.
DEF_SEW_LMUL_RULE (ge_sew, ratio_and_ge_sew, ratio_and_ge_sew,
max_sew_overlap_and_next_ratio_valid_for_prev_sew_p,
always_false, use_max_sew_and_lmul_with_next_ratio)
Passed the rv64gcv full regression test.
Signed-of
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