[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc created this revision. dnpetrov-sc added reviewers: craig.topper, anton-afanasyev, asi-sc. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Mart

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:637 +def : ProcessorModel<"scr1-min", SCR1Model, + [FeatureRV32E, FeatureStdExtC], + [TuneNoDefaultUnroll]>; craig.topper wrote: > Shouldn't this

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc updated this revision to Diff 480352. dnpetrov-sc edited the summary of this revision. dnpetrov-sc added a comment. - fixed new line at end-of-file in RISCVSchedSCR1.td; - dropped scr1-min (RV32E unsupported). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:/

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc updated this revision to Diff 482449. dnpetrov-sc marked an inline comment as done. dnpetrov-sc added a comment. - Added syntacore prefix Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302 Files:

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

dnpetrov-sc updated this revision to Diff 482455. dnpetrov-sc added a comment. - Fixes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302 Files: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-inva