dnpetrov-sc added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCV.td:637 +def : ProcessorModel<"scr1-min", SCR1Model, + [FeatureRV32E, FeatureStdExtC], + [TuneNoDefaultUnroll]>; ---------------- craig.topper wrote: > Shouldn't this also need Feature32Bit? Now, that's somewhat funny. Indeed, RISCVSubtarget has `HasRV32` field, but it is never queried. `IsRV32` predicate in RISCV.td is mapped to `!Subtarget->is64Bit()` in C++ code. Code generation for RV32E is not implemented yet, though (and would error out in `RISCVTargetLowering`). I'll drop scr1-min for now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
