[compiler-rt] [libcxx] [mlir] [flang] [llvm] [clang-tools-extra] [clang] [libc] [lldb] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

dwpan wrote: > Hello. Can you explain why this is needed, as opposed to using the equivalent > shift/and/ors? In Verilog/SystemVerilog language, the basic type is bit or bit vector, and length is arbitrary, insert/extract bits are common features in language. Introducing corresponding intrin

[libcxx] [flang] [clang-tools-extra] [compiler-rt] [mlir] [llvm] [lldb] [libc] [clang] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

dwpan wrote: > Hello. Can you explain why this is needed, as opposed to using the equivalent > shift/and/ors? In Verilog/SystemVerilog language, the basic type is bit or bit vector, and length is arbitrary, insert/extract bits are common features in language. Introducing corresponding intrins

[clang] [flang] [clang-tools-extra] [llvm] [compiler-rt] [llvm][AArch64] intrinsic to generate a ubfx instruction (PR #80103)

dwpan wrote: The feature will be very useful for hardware language like Verilog/SystemVerilog which insert/extract bits are parts of language reference manual. https://github.com/llvm/llvm-project/pull/80103 ___ cfe-commits mailing list cfe-commits