dwpan wrote: The feature will be very useful for hardware language like Verilog/SystemVerilog which insert/extract bits are parts of language reference manual.
https://github.com/llvm/llvm-project/pull/80103 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
