Am 11.10.2017 um 10:49 schrieb Philipp Klaus Krause:
> Am 14.05.2017 um 11:54 schrieb Maarten Brock:
>>
>> Hi Philipp,
>>
>> On the C8051F120 Dhrystone page you write:
>> The C8051F120 itself could run at up to 100 Mhz, but would require an
>> external crystal to do so.
>>
>> This is not true. You can also use the PLL on the internal 24.5MHz +/-2%
>> oscillator giving 98MHz +/-2%.
>>
>> Maarten
>
> Thanks.
> Do you have an example of how to set up the PLL for 98 Mhz on the
> C8051F120? Based on the datasheet I've tried:
>
> OSCICN = 0xc3; // Run internal oscillator at full 24.5 Mhz
>
> // Set PLL to get SYSCLK to 98 Mhz
> FLSCL = 0xb0;
> PLL0CN = 0x01;
> PLL0FLT = 0x01;
> PLL0MUL = 0x04;
> for (unsigned char i = 0; i < 31; i++) // Wait 5 µs
> {
> __asm
> nop
> nop
> nop
> nop
> __endasm;
> }
> PLL0CN = 0x03;
> while (!(PLL0CN & 0x10));
> CLKSEL = 0x02;
>
> but it doesn't seem to work for me.
>
> Philipp
In case anyone runs into the same problem:
FLSCL is in sfr page 0, unlike the other sfrs set here, which are in sfr
page 0xf. So to get the code to work, just replace
FLSCL = 0xb0;
by
SFRPAGE = 0x0;
FLSCL = 0xb0;
SFRPAGE = 0xf;
Philipp
P.S.: If it still doesn't work for you, check the decoupling capacitors
on the power pins. The requirements are different when using the PLL vs.
when not using it (apparently someone ran into that problem:
https://www.mikrocontroller.net/topic/189505).
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