ok - after figuring out that A is 8Bit wide (what i should have expected on an 8Bit arch) - i have two proposals for Peephole optimizations.
1.) ld a,(x) ld xl,a inc (direct) ld a,xl ret to ld a,(x) inc (direct) ret 2.) ld xl, a ld a, xh to rlwa (rotate word left through accumulator) (under the condition that the current content of xh is not used elsewhere) the same can be achived the other way round with RRWA Am 2014-10-02 um 16:29 schrieb Georg Ottinger: > hmm ... > > is ld a, (x) on stm8 a byte wise operation??? > > > > Am 2014-10-02 um 16:10 schrieb Georg Ottinger: >> I just figured out that >> s >> ld a,(x) >> ld xl, a >> ld a, xl >> >> acutally is usefull code - to zero the Upper Byte of A .... >> >> >> >> Am 2014-10-02 um 16:03 schrieb Georg Ottinger: >>> congrats to Ben Shi - his lastest patch - just shrunk my firmware from >>> 4210 Bytes to 4039 Bytes thanks to _mullong_stm8 >>> >>> I had a look at the asm code of my project and there more points where >>> optimization could be achived. - maybe I can convince someone to give it >>> a try - as I am not an expert to do this ;) >>> >>> for example an optimized _divulong routine - which should be >>> interessting as the STM8 has a hardware divder instruction. >>> >>> I also make use of _strncmp which could be optimzed but maybe that is >>> not so promising. >>> >>> I also noted some parts which could be optimized via peeps.def: >>> >>> >>> 000052 F6 [ 1] 126 ld a, (x) >>> 000053 97 [ 1] 127 ld xl, a >>> 128 ; rx_ringbuffer.c: 65: rx_tail++; >>> 000054 72 5Cu01u01 [ 1] 129 inc _rx_tail+0 >>> 130 ; rx_ringbuffer.c: 67: return temp; >>> 000058 9F [ 1] 131 ld a, xl >>> 000059 81 [ 4] 132 ret >>> >>> >>> => I think that the "131 ld a,xl" instruction could be omited - but I >>> have no Idea how to craft a peephole definition for this case. >>> >>> >>> best wishes, Georg >>> > > ------------------------------------------------------------------------------ > Meet PCI DSS 3.0 Compliance Requirements with EventLog Analyzer > Achieve PCI DSS 3.0 Compliant Status with Out-of-the-box PCI DSS Reports > Are you Audit-Ready for PCI DSS 3.0 Compliance? Download White paper > Comply to PCI DSS 3.0 Requirement 10 and 11.5 with EventLog Analyzer > http://pubads.g.doubleclick.net/gampad/clk?id=154622311&iu=/4140/ostg.clktrk > _______________________________________________ > Sdcc-user mailing list > Sdcc-user@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/sdcc-user ------------------------------------------------------------------------------ Meet PCI DSS 3.0 Compliance Requirements with EventLog Analyzer Achieve PCI DSS 3.0 Compliant Status with Out-of-the-box PCI DSS Reports Are you Audit-Ready for PCI DSS 3.0 Compliance? Download White paper Comply to PCI DSS 3.0 Requirement 10 and 11.5 with EventLog Analyzer http://pubads.g.doubleclick.net/gampad/clk?id=154622311&iu=/4140/ostg.clktrk _______________________________________________ Sdcc-user mailing list Sdcc-user@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sdcc-user
