Re: [PATCH 1/2] riscv: zicond: make non-experimental

[Vineet Gupta]

On 8/10/23 10:14, Alistair Francis wrote:

On Tue, Aug 8, 2023 at 2:18 PM Vineet Gupta <vine...@rivosinc.com> wrote:

zicond is now codegen supported in both llvm and gcc.

This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.

Signed-off-by: Vineet Gupta <vine...@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

Gentle ping to remind that this lands in some -next tree and not forgotten !

Thx,
-Vineet

---
  target/riscv/cpu.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b93b04453c8..022bd9d01223 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1816,6 +1816,7 @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
      DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
      DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),

      /* Vendor-specific custom extensions */
      DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
@@ -1832,7 +1833,6 @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, 
false),

      /* These are experimental so mark with 'x-' */
-    DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),

      /* ePMP 0.9.3 */
      DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.34.1