Hi, This series adds some checks before translating instructions
This includes: CPUCFG[1].IOCSR CPUCFG[2].FP CPUCFG[2].FP_SP CPUCFG[2].FP_DP CPUCFG[2].LSPW CPUCFG[2].LAM CPUCFG[2].LSX And this series adds [1] patches together. Patch 11,12,16 need review. V3: - Rebase; - The la32 instructions following Table 2 at [2]. V2: - Add a check parameter to the TRANS macro. - remove TRANS_64. - Add avail_ALL/64/FP/FP_SP/FP_DP/LSPW/LAM/LSX/IOCSR to check instructions. [1]: https://patchew.org/QEMU/20230809083258.1787464-...@jia.je/ [2]: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Please review. Thanks. Song Gao Jiajie Chen (10): target/loongarch: Add function to check current arch target/loongarch: Add new object class for loongarch32 cpus target/loongarch: Add GDB support for loongarch32 mode target/loongarch: Support LoongArch32 TLB entry target/loongarch: Support LoongArch32 DMW target/loongarch: Support LoongArch32 VPPN target/loongarch: Add LA64 & VA32 to DisasContext target/loongarch: Truncate high 32 bits of address in VA32 mode target/loongarch: Sign extend results in VA32 mode target/loongarch: Add loongarch32 cpu la132 Song Gao (8): target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW. target/loongarch: Add a check parameter to the TRANS macro target/loongarch: Add avail_64 to check la64-only instructions target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions target/loongarch: Add avail_LSPW to check LSPW instructions target/loongarch: Add avail_LAM to check atomic instructions target/loongarch: Add avail_LSX to check LSX instructions target/loongarch: Add avail_IOCSR to check iocsr instructions configs/targets/loongarch64-softmmu.mak | 2 +- gdb-xml/loongarch-base32.xml | 45 + hw/loongarch/virt.c | 5 - target/loongarch/cpu-csr.h | 22 +- target/loongarch/cpu.c | 75 +- target/loongarch/cpu.h | 33 + target/loongarch/gdbstub.c | 34 +- target/loongarch/insn_trans/trans_arith.c.inc | 98 +- .../loongarch/insn_trans/trans_atomic.c.inc | 85 +- target/loongarch/insn_trans/trans_bit.c.inc | 56 +- .../loongarch/insn_trans/trans_branch.c.inc | 27 +- target/loongarch/insn_trans/trans_extra.c.inc | 24 +- .../loongarch/insn_trans/trans_farith.c.inc | 96 +- target/loongarch/insn_trans/trans_fcmp.c.inc | 8 + target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +- .../loongarch/insn_trans/trans_fmemory.c.inc | 62 +- target/loongarch/insn_trans/trans_fmov.c.inc | 52 +- target/loongarch/insn_trans/trans_lsx.c.inc | 1520 +++++++++-------- .../loongarch/insn_trans/trans_memory.c.inc | 118 +- .../insn_trans/trans_privileged.c.inc | 24 +- target/loongarch/insn_trans/trans_shift.c.inc | 34 +- target/loongarch/op_helper.c | 4 +- target/loongarch/tlb_helper.c | 66 +- target/loongarch/translate.c | 46 + target/loongarch/translate.h | 19 +- 25 files changed, 1539 insertions(+), 1072 deletions(-) create mode 100644 gdb-xml/loongarch-base32.xml -- 2.39.1
