In v2, I rebased the patch on https://github.com/alistair23/qemu/tree/riscv-to-apply.next However, I forgot to add "Reviewed-by" in v2, so I add them in v3.
Jason Chien (1): target/riscv: Add Zihintntl extension ISA string to DTS target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) -- 2.17.1
