On 10/7/23 14:58, Jiaxun Yang wrote:
在 2023/6/30 15:28, Marcin Nowakowski 写道:GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Signed-off-by: Marcin Nowakowski <marcin.nowakow...@fungible.com>VZ is unimplemented in TCG so perhaps we should leave them as not supported?
GINVI and GINVT instr were implemented in commit 99029be1c2
("target/mips: Add implementation of GINVT instruction").
