The quad model implements the EC xscoms for the p9 machine, reusing the
same model for p10 which isn't quite correct. This series adds a PnvQuad
class and subclasses it for P9 and P10. Implement the core thread state
xscom as an example. I expect more function to be implemented in future
patches.
There's one outstanding question. Skiboot has this for the p10 scom:
#define P10_EC_CORE_THREAD_STATE 0x412
However the read that comes is for 0x28412. I suspect the upper 0x28000
are addressing bits, so we're really reporting the core thread state for
the given core. Should the model instead wired so one is created for
each chiplet? Or should we report the value for all possible cores, like
the P9 code does for P9X_EX_NCU_SPEC_BAR?
switch (offset) {
case P9X_EX_NCU_SPEC_BAR:
case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
Joel Stanley (4):
ppc/pnv: quad xscom callbacks are P9 specific
ppc/pnv: Subclass quad xscom callbacks
ppc/pnv: Add P10 quad ops
ppc/pnv: Return zero for core thread state xscom
include/hw/ppc/pnv_core.h | 12 +++-
hw/ppc/pnv.c | 11 ++--
hw/ppc/pnv_core.c | 114 +++++++++++++++++++++++++++++++-------
3 files changed, 113 insertions(+), 24 deletions(-)
--
2.40.1
