On Thu Jun 1, 2023 at 5:56 PM AEST, Cédric Le Goater wrote: > Hello Nick, > > On 5/31/23 03:23, Nicholas Piggin wrote: > > Hi, > > > > I'm posting this now just to get some first thoughts. I wouldn't say > > it's ready but it does actually work with some basic tests including > > pseries booting a Linux distro. I have powernv booting too, it just > > requires some more SPRs converted, nothing fundamentally different so > > for the purpose of this RFC I leave it out. > > > > A couple of things, I don't know the object model well enough to do > > something nice with topology. Iterating siblings I would have thought > > should be going to parent core then iterating its children CPUs. Should > > that be done with the object model, or is it better to add direct > > pointers in CPUs to core and core to CPUs? It is (semi) important for> > > performance so maybe that is better than object iterators. If we go that > > way, the PnvCore and SpaprCore have pointers to the SMT threads already, > > should those be abstracted go in the CPUCore? > > You should be able to move the thread array into the CPUCore. If you do > that, please check that migration compat is not impacted by the state > change. However, I am not sure you can use the CPUCore model under the > insn modeling. Something to check.
Okay. > Anyhow, the way you implemented the loop on the siblings is sufficiently > fast for a small numbers of CPU and safe, w.r.t to CPU hotplug. So > I would leave that part for now, if it runs decently with 4*4 vCPUs in > TCG it should be fine. Yeah you're right I'm overly paranoid about it but we don't do hundreds of CPUs in TCG so it should be fine. Maybe I will defer it for now then and just do the CPU iteration. Thanks, Nick
