On Wed May 31, 2023 at 5:25 PM AEST, Cédric Le Goater wrote:
> On 5/31/23 03:23, Nicholas Piggin wrote:
> > SMT TCG emulation needs to be able to iterate over siblings in a core,
> > and needs to serialise core access to shared SPRs and state.
> >
> > Signed-off-by: Nicholas Piggin <npig...@gmail.com>
> > ---
> > target/ppc/cpu.h | 9 +++++++++
> > target/ppc/cpu_init.c | 5 +++++
> > target/ppc/translate.c | 20 ++++++++++++++++++++
> > 3 files changed, 34 insertions(+)
> >
> > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > index 1f23b81e90..b594408a8d 100644
> > --- a/target/ppc/cpu.h
> > +++ b/target/ppc/cpu.h
> > @@ -672,6 +672,8 @@ enum {
> > POWERPC_FLAG_TM = 0x00100000,
> > /* Has SCV (ISA 3.00)
> > */
> > POWERPC_FLAG_SCV = 0x00200000,
> > + /* Has >1 thread per core
> > */
> > + POWERPC_FLAG_SMT = 0x00400000,
> > };
> >
> > /*
> > @@ -1266,6 +1268,13 @@ struct CPUArchState {
> > uint64_t pmu_base_time;
> > };
> >
> > +#define _CORE_ID(cs) \
> > + (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads
> > - 1))
> > +
> > +#define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
> > + CPU_FOREACH(cs_sibling) \
> > + if (_CORE_ID(cs) == _CORE_ID(cs_sibling))
> > +
>
>
> May be introduce these helpers when needed (and if needed).
Yeah that's a good idea, I tried to structure it so you could see
the main components first, but for a real patch it might indeed be
better add them as needed.
Thanks,
Nick
