On 5/5/23 14:19, Peter Maydell wrote:
On Wed, 3 May 2023 at 08:13, Richard Henderson <richard.hender...@linaro.org> wrote:Signed-off-by: Richard Henderson <richard.hender...@linaro.org> --- tcg/riscv/tcg-target.c.inc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 37870c89fc..4dd33c73e8 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -910,8 +910,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, { TCGLabelQemuLdst *ldst = NULL; MemOp opc = get_memop(oi); - unsigned a_bits = get_alignment_bits(opc); - unsigned a_mask = (1u << a_bits) - 1; + MemOp a_bits, atom_a, atom_u; + unsigned a_mask; + + a_bits = atom_and_align_for_opc(s, &atom_a, &atom_u, opc, + MO_ATOM_IFALIGN, false); + a_mask = (1u << a_bits) - 1; #ifdef CONFIG_SOFTMMU unsigned s_bits = opc & MO_SIZE;Same remark as for ppc.
Because the alignment was not required outside of prepare_host_addr. RISC-V does not have 128-bit memory operations of any kind. r~
