Signed-off-by: Andreas Färber <afaer...@suse.de>
Cc: Peter Maydell <peter.mayd...@linaro.org>
---
target-arm/cpu-core.h | 1 +
target-arm/cpu.c | 11 +++++++++++
target-arm/helper.c | 29 -----------------------------
3 files changed, 12 insertions(+), 29 deletions(-)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 0b2eb0a..53fac1a 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -50,6 +50,7 @@ typedef struct ARMCPUClass {
} cp15;
struct {
uint32_t fpsid;
+ uint32_t mvfr[2];
} vfp;
uint64_t jtag_id;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7893fa8..d004cfd 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -49,6 +49,8 @@ static void arm_cpu_reset(CPU *c)
env->cp15.c0_cachetype = cpu_class->cp15.c0_cachetype;
memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t));
+ env->vfp.xregs[ARM_VFP_MVFR0] = cpu_class->vfp.mvfr[0];
+ env->vfp.xregs[ARM_VFP_MVFR1] = cpu_class->vfp.mvfr[1];
/* Genuine reset */
env->cp15.c1_sys = cpu_class->cp15.c1_sys;
@@ -174,6 +176,7 @@ typedef struct ARMCPUInfo {
uint32_t cp15_c0_c2[8];
uint32_t cp15_c1_sys;
uint32_t vfp_fpsid;
+ uint32_t vfp_mvfr[2];
uint32_t features;
void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info);
} ARMCPUInfo;
@@ -307,6 +310,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00050078,
.vfp_fpsid = 0x410120b4,
+ .vfp_mvfr = { 0x11111111, 0x00000000 },
.features = ARM_FEATURE(V6) |
ARM_FEATURE(VFP),
},
@@ -324,6 +328,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00050078,
.vfp_fpsid = 0x410120b5,
+ .vfp_mvfr = { 0x11111111, 0x00000000 },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -341,6 +346,7 @@ static const ARMCPUInfo arm_cpus[] = {
0x141, 0, 0, 0
},
.vfp_fpsid = 0x410120b4,
+ .vfp_mvfr = { 0x11111111, 0x00000000 },
.features = ARM_FEATURE(V6K) |
ARM_FEATURE(VFP) |
ARM_FEATURE(VAPA),
@@ -365,6 +371,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00c50078,
.vfp_fpsid = 0x410330c0,
+ .vfp_mvfr = { 0x11110222, 0x00011100 },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(NEON) |
@@ -384,6 +391,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00c50078,
.vfp_fpsid = 0x41034000, /* Guess */
+ .vfp_mvfr = { 0x11110222, 0x01111111 },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP3) |
ARM_FEATURE(VFP_FP16) |
@@ -409,6 +417,7 @@ static const ARMCPUInfo arm_cpus[] = {
},
.cp15_c1_sys = 0x00c50078,
.vfp_fpsid = 0x410430f0,
+ .vfp_mvfr = { 0x10110222, 0x11111111 },
.features = ARM_FEATURE(V7) |
ARM_FEATURE(VFP4) |
ARM_FEATURE(VFP_FP16) |
@@ -533,6 +542,8 @@ static void arm_cpu_class_init(ObjectClass *klass, void
*data)
memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
k->cp15.c1_sys = info->cp15_c1_sys;
k->vfp.fpsid = info->vfp_fpsid;
+ k->vfp.mvfr[0] = info->vfp_mvfr[0];
+ k->vfp.mvfr[1] = info->vfp_mvfr[1];
k->features = info->features;
if (info->class_init != NULL) {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 466519a..4ec375c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -13,47 +13,18 @@
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
switch (id) {
- case ARM_CPUID_ARM1136:
- /* This is the 1136 r1, which is a v6K core */
- /* Fall through */
- case ARM_CPUID_ARM1136_R2:
- /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
- * older core than plain "arm1136". In particular this does not
- * have the v6K features.
- */
- /* These ID register values are correct for 1136 but may be wrong
- * for 1136_r2 (in particular r0p2 does not actually implement most
- * of the ID registers).
- */
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- break;
- case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- break;
- case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
- break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
env->cp15.c0_clid = 0x0a200023;
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
--
1.7.7
