Hi,
This new version was rebased on top of Alistair's riscv-to-apply.next @
9c60ca583cb ("hw/riscv: Add signature dump function ...").
No other changes made.
Changes from v3:
- rebased with riscv-to-apply.next @ 9c60ca583cb
- v3 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg06911.html
Daniel Henrique Barboza (20):
target/riscv: sync env->misa_ext* with cpu->cfg in realize()
target/riscv: remove MISA properties from isa_edata_arr[]
target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
target/riscv: introduce riscv_cpu_add_misa_properties()
target/riscv: remove cpu->cfg.ext_a
target/riscv: remove cpu->cfg.ext_c
target/riscv: remove cpu->cfg.ext_d
target/riscv: remove cpu->cfg.ext_f
target/riscv: remove cpu->cfg.ext_i
target/riscv: remove cpu->cfg.ext_e
target/riscv: remove cpu->cfg.ext_m
target/riscv: remove cpu->cfg.ext_s
target/riscv: remove cpu->cfg.ext_u
target/riscv: remove cpu->cfg.ext_h
target/riscv: remove cpu->cfg.ext_j
target/riscv: remove cpu->cfg.ext_v
target/riscv: remove riscv_cpu_sync_misa_cfg()
target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
target/riscv: add RVG and remove cpu->cfg.ext_g
target/riscv/cpu.c: redesign register_cpu_props()
target/riscv/cpu.c | 412 +++++++++++-----------
target/riscv/cpu.h | 19 +-
target/riscv/insn_trans/trans_rvzce.c.inc | 2 +-
3 files changed, 216 insertions(+), 217 deletions(-)
--
2.39.2
