Hi, In this version I simplified the logic used in write_misa() after reviews from Weiwei Li. The patch that handled RVV activation was removed, making RVV a regular MISA bit to activate/deactivate.
We're also checking whether one of the IMAFD extensions got disabled during write_misa() and, if that's the case, we'll clear RVG. Series is based on top of Alistair's riscv-to-apply.next. Patches acked: 1-5. Changes from v3: - patch 11: - remove c/u/s cpu->cfg assignment from rv64_thead_c906_cpu_init() - patch 14: - add RVG in set_misa() call inside rv64_thead_c906_cpu_init() - remove cpu->cfg.ext_g assignment from rv64_thead_c906_cpu_init() - patch 15: - remove ext_zfinx verification from riscv_cpu_enable_g() - patch 25: - do not call riscv_cpu_enable_g() in write_misa() - enable/disable RVG extensions manually in write_misa() - patch 26: removed - v3 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg05097.html Daniel Henrique Barboza (25): target/riscv/cpu.c: add riscv_cpu_validate_v() target/riscv/cpu.c: remove set_vext_version() target/riscv/cpu.c: remove set_priv_version() target/riscv: add PRIV_VERSION_LATEST target/riscv/cpu.c: add priv_spec validate/disable_exts helpers target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() target/riscv: move pmp and epmp validations to validate_set_extensions() target/riscv/cpu.c: validate extensions before riscv_timer_init() target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() target/riscv/cpu.c: set cpu config in set_misa() target/riscv/cpu.c: redesign register_cpu_props() target/riscv: put env->misa_ext <-> cpu->cfg code into helpers target/riscv: add RVG target/riscv/cpu.c: split RVG code from validate_set_extensions() target/riscv/cpu.c: add riscv_cpu_validate_misa_ext() target/riscv: move riscv_cpu_validate_v() to validate_misa_ext() target/riscv: error out on priv failure for RVH target/riscv: write env->misa_ext* in register_generic_cpu_props() target/riscv: make validate_misa_ext() use a misa_ext val target/riscv: split riscv_cpu_validate_set_extensions() target/riscv: use misa_ext val in riscv_cpu_validate_extensions() target/riscv: rework write_misa() target/riscv: update cpu->cfg misa bits in commit_cpu_cfg() target/riscv: handle RVG updates in write_misa() target/riscv/cpu.c | 654 ++++++++++++++++++++++++++++----------------- target/riscv/cpu.h | 14 +- target/riscv/csr.c | 72 +++-- 3 files changed, 463 insertions(+), 277 deletions(-) -- 2.39.2
