On Mon, 6 Mar 2023 at 15:12, Chen Baozi <chenba...@phytium.com.cn> wrote:
>
> Add implementation defined registers for neoverse-n1 which
> would be accessed by TF-A. Since there is no DSU in Qemu,
> CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
>
> Signed-off-by: Chen Baozi <chenba...@phytium.com.cn>
> Tested-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
> ---
> target/arm/cpu64.c | 2 ++
> target/arm/cpu_tcg.c | 62 ++++++++++++++++++++++++++++++++++++++++++
> target/arm/internals.h | 2 ++
> 3 files changed, 66 insertions(+)
We should add a comment here:
/*
* Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
* (and in particular its system registers).
*/
If that's the only issue with this version of the patch
I'll fix it up when I add this into target-arm.next.
> + { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
> + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
thanks
-- PMM
