在 2023/2/25 上午3:24, Richard Henderson 写道:
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_q_d,
.opt_opc = vecop_list,
.vece = MO_128
},
There are no 128-bit vector operations; you'll need to do this one
differently.
Presumably just load the two 64-bit elements, sign-extend into
128-bits, add with tcg_gen_add2_i64, and store the two 64-bit elements
as output. But that won't fit into the tcg_gen_gvec_3 interface.
'sign-extend into 128-bits,' Could you give a example?
I see a example at target/ppc/translate/vmx-impl.c.inc
static bool do_vx_vprtyb(DisasContext *ctx, arg_VX_tb *a, unsigned
vece)
{
...
{
.fno = gen_helper_VPRTYBQ,
.vece = MO_128
},
tcg_gen_gvec_2(avr_full_offset(a->vrt),
avr_full_offset(a->vrb),
16, 16, &op[vece - MO_32]);
return true;
}
TRANS(VPRTYBQ, do_vx_vprtyb, MO_128)
...
do_vx_vprtyb fit the fno into the tcg_gen_gvec_2.
I am not sure this example is right.
Thanks.
Song Gao
