This patch series adds stage-2 translation support for SMMUv3. It is controlled by a new system property “arm-smmuv3.stage”. - When set to “1”: Stage-1 only would be advertised and supported (default behavior) - When set to “2”: Stage-2 only would be advertised and supported. - Value “all” is reserved for nesting support. However it is not implemented in this patch series (more about this in the end)
Features implemented in stage-2 are mostly synonymous with stage-1 - VMID16. - Only AArch64 translation tables are supported. - 48 bits of IPA. - Stall is not supported. - HTTU is not supported, SW is expected to maintain the Access flag. To make it easy to support nesting, a new structure(SMMUS2Cfg) is embedded within SMMUTransCfg, to hold stage-2 configuration. TLBs were updated to support VMID, where when stage-2 is used ASID are set to -1 and ignored and when stage-1 is used VMID is set to -1 and ignored. As only one stage is supported at a time at the moment, TLB will represent IPA=>PA translation with proper attributes(granularity and t0sz) parsed from STEs for stage-2, and will represent VA=>PA translation with proper attributes parsed from the CDs for stage-1. New commands where added that are used with stage-2 - CMD_TLBI_S12_VMALL: Invalidate all translations for a VMID. - CMD_TLBI_S2_IPA: Invalidate stage-2 by VMID and IPA SMMUv3State.features has 2 new flags (SMMU_FEATURE_STAGE1 and SMMU_FEATURE_STAGE2): to indicate stage-1 and stage-2 support in HW. This patch series + GBPA patch https://lore.kernel.org/qemu-devel/20230126141120.448641-1-smost...@google.com/ Can be used to run Linux pKVM SMMUv3 patches (currently on the list) which controls stage-2 (from EL2) while providing a paravirtualized interface the host(EL1) https://lore.kernel.org/kvmarm/20230201125328.2186498-1-jean-phili...@linaro.org/ Looking forward, nesting is the next feature to go for, here are some thoughts about this: - TLB would require big changes for this, we can go either for a combined implementation or per stage one. This would affect returns from PTW and invalidation commands. - Stage-1 data structures should be translated by stage-2 if enabled (as context descriptors and ttb0/ttb1) - Translated addresses from stage-1 should be translated by stage-2 if enabled. - Record faults should be separated between stage-1 (CD_R) and stage-2 (S2R). - Some existing commands(as CMD_TLBI_S2_IPA, CMD_TLBI_NH_ASID …) would be modified and some of those would be based on the design of the TLBs. - Currently, VMID is ignored when stage-1 is used as it can’t be used with stage-2. However when nesting is advertised VMID shouldn’t be ignored even if stage-2 is bypassed. Mostafa Saleh (16): hw/arm/smmuv3: Add missing fields for IDR0 hw/arm/smmuv3: Update translation config to hold stage-2 hw/arm/smmuv3: Rename smmu_ptw_64 hw/arm/smmuv3: Add a system property to choose translation stage hw/arm/smmuv3: Add page table walk for stage-2 hw/arm/smmuv3: Parse STE config for stage-2 hw/arm/smmuv3: Check validity of stage-2 page table hw/arm/smmuv3: Support S2AFFD hw/arm/smmuv3: Don't touch CD if stage-1 is not supported. hw/arm/smmuv3: Make TLB lookup work for stage-2 hw/arm/smmuv3: Read VMID from STE hw/arm/smmuv3: Add VMID to tlb tagging hw/arm/smmuv3: Add CMDs related to stage 2 hw/arm/smmuv3: Add stage-2 support in iova notifier hw/arm/smmuv3: Add fault configuration for stage-2 hw/arm/smmuv3: Enable stage-2 support hw/arm/smmu-common.c | 168 +++++++++++++++++++++--- hw/arm/smmu-internal.h | 41 ++++++ hw/arm/smmuv3-internal.h | 10 ++ hw/arm/smmuv3.c | 247 ++++++++++++++++++++++++++++++----- hw/arm/trace-events | 4 +- include/hw/arm/smmu-common.h | 19 ++- include/hw/arm/smmuv3.h | 1 + 7 files changed, 433 insertions(+), 57 deletions(-) -- 2.39.1.519.gcb327c4b5f-goog
